arch/arm/mach-mx2/devices.c

   1 /*
   2  * Author: MontaVista Software, Inc.
   3  *       <source@mvista.com>
   4  *
   5  * Based on the OMAP devices.c
   6  *
   7  * 2005 (c) MontaVista Software, Inc. This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  *
  12  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27  * MA 02110-1301, USA.
  28  */
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/gpio.h>
  34 #include <linux/dma-mapping.h>
  35
  36 #include <mach/irqs.h>
  37 #include <mach/hardware.h>
  38 #include <mach/common.h>
  39 #include <mach/mmc.h>
  40
  41 #include "devices.h"
  42
  43 /*
  44  * SPI master controller
  45  *
  46  * - i.MX1: 2 channel (slighly different register setting)
  47  * - i.MX21: 2 channel
  48  * - i.MX27: 3 channel
  49  */
  50 static struct resource mxc_spi_resources0[] = {
  51         {
  52                .start = CSPI1_BASE_ADDR,
  53                .end = CSPI1_BASE_ADDR + SZ_4K - 1,
  54                .flags = IORESOURCE_MEM,
  55         }, {
  56                .start = MXC_INT_CSPI1,
  57                .end = MXC_INT_CSPI1,
  58                .flags = IORESOURCE_IRQ,
  59         },
  60 };
  61
  62 static struct resource mxc_spi_resources1[] = {
  63         {
  64                 .start = CSPI2_BASE_ADDR,
  65                 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
  66                 .flags = IORESOURCE_MEM,
  67         }, {
  68                 .start = MXC_INT_CSPI2,
  69                 .end = MXC_INT_CSPI2,
  70                 .flags = IORESOURCE_IRQ,
  71         },
  72 };
  73
  74 #ifdef CONFIG_MACH_MX27
  75 static struct resource mxc_spi_resources2[] = {
  76         {
  77                 .start = CSPI3_BASE_ADDR,
  78                 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
  79                 .flags = IORESOURCE_MEM,
  80         }, {
  81                 .start = MXC_INT_CSPI3,
  82                 .end = MXC_INT_CSPI3,
  83                 .flags = IORESOURCE_IRQ,
  84         },
  85 };
  86 #endif
  87
  88 struct platform_device mxc_spi_device0 = {
  89         .name = "spi_imx",
  90         .id = 0,
  91         .num_resources = ARRAY_SIZE(mxc_spi_resources0),
  92         .resource = mxc_spi_resources0,
  93 };
  94
  95 struct platform_device mxc_spi_device1 = {
  96         .name = "spi_imx",
  97         .id = 1,
  98         .num_resources = ARRAY_SIZE(mxc_spi_resources1),
  99         .resource = mxc_spi_resources1,
 100 };
 101
 102 #ifdef CONFIG_MACH_MX27
 103 struct platform_device mxc_spi_device2 = {
 104         .name = "spi_imx",
 105         .id = 2,
 106         .num_resources = ARRAY_SIZE(mxc_spi_resources2),
 107         .resource = mxc_spi_resources2,
 108 };
 109 #endif
 110
 111 /*
 112  * General Purpose Timer
 113  * - i.MX21: 3 timers
 114  * - i.MX27: 6 timers
 115  */
 116
 117 /* We use gpt0 as system timer, so do not add a device for this one */
 118
 119 static struct resource timer1_resources[] = {
 120         {
 121                 .start  = GPT2_BASE_ADDR,
 122                 .end    = GPT2_BASE_ADDR + 0x17,
 123                 .flags  = IORESOURCE_MEM,
 124         }, {
 125                 .start   = MXC_INT_GPT2,
 126                 .end     = MXC_INT_GPT2,
 127                 .flags   = IORESOURCE_IRQ,
 128         }
 129 };
 130
 131 struct platform_device mxc_gpt1 = {
 132         .name = "imx_gpt",
 133         .id = 1,
 134         .num_resources = ARRAY_SIZE(timer1_resources),
 135         .resource = timer1_resources,
 136 };
 137
 138 static struct resource timer2_resources[] = {
 139         {
 140                 .start  = GPT3_BASE_ADDR,
 141                 .end    = GPT3_BASE_ADDR + 0x17,
 142                 .flags  = IORESOURCE_MEM,
 143         }, {
 144                 .start   = MXC_INT_GPT3,
 145                 .end     = MXC_INT_GPT3,
 146                 .flags   = IORESOURCE_IRQ,
 147         }
 148 };
 149
 150 struct platform_device mxc_gpt2 = {
 151         .name = "imx_gpt",
 152         .id = 2,
 153         .num_resources = ARRAY_SIZE(timer2_resources),
 154         .resource = timer2_resources,
 155 };
 156
 157 #ifdef CONFIG_MACH_MX27
 158 static struct resource timer3_resources[] = {
 159         {
 160                 .start  = GPT4_BASE_ADDR,
 161                 .end    = GPT4_BASE_ADDR + 0x17,
 162                 .flags  = IORESOURCE_MEM,
 163         }, {
 164                 .start   = MXC_INT_GPT4,
 165                 .end     = MXC_INT_GPT4,
 166                 .flags   = IORESOURCE_IRQ,
 167         }
 168 };
 169
 170 struct platform_device mxc_gpt3 = {
 171         .name = "imx_gpt",
 172         .id = 3,
 173         .num_resources = ARRAY_SIZE(timer3_resources),
 174         .resource = timer3_resources,
 175 };
 176
 177 static struct resource timer4_resources[] = {
 178         {
 179                 .start  = GPT5_BASE_ADDR,
 180                 .end    = GPT5_BASE_ADDR + 0x17,
 181                 .flags  = IORESOURCE_MEM,
 182         }, {
 183                 .start   = MXC_INT_GPT5,
 184                 .end     = MXC_INT_GPT5,
 185                 .flags   = IORESOURCE_IRQ,
 186         }
 187 };
 188
 189 struct platform_device mxc_gpt4 = {
 190         .name = "imx_gpt",
 191         .id = 4,
 192         .num_resources = ARRAY_SIZE(timer4_resources),
 193         .resource = timer4_resources,
 194 };
 195
 196 static struct resource timer5_resources[] = {
 197         {
 198                 .start  = GPT6_BASE_ADDR,
 199                 .end    = GPT6_BASE_ADDR + 0x17,
 200                 .flags  = IORESOURCE_MEM,
 201         }, {
 202                 .start   = MXC_INT_GPT6,
 203                 .end     = MXC_INT_GPT6,
 204                 .flags   = IORESOURCE_IRQ,
 205         }
 206 };
 207
 208 struct platform_device mxc_gpt5 = {
 209         .name = "imx_gpt",
 210         .id = 5,
 211         .num_resources = ARRAY_SIZE(timer5_resources),
 212         .resource = timer5_resources,
 213 };
 214 #endif
 215
 216 /*
 217  * Watchdog:
 218  * - i.MX1
 219  * - i.MX21
 220  * - i.MX27
 221  */
 222 static struct resource mxc_wdt_resources[] = {
 223         {
 224                 .start  = WDOG_BASE_ADDR,
 225                 .end    = WDOG_BASE_ADDR + 0x30,
 226                 .flags  = IORESOURCE_MEM,
 227         },
 228 };
 229
 230 struct platform_device mxc_wdt = {
 231         .name = "mxc_wdt",
 232         .id = 0,
 233         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
 234         .resource = mxc_wdt_resources,
 235 };
 236
 237 static struct resource mxc_w1_master_resources[] = {
 238         {
 239                 .start = OWIRE_BASE_ADDR,
 240                 .end   = OWIRE_BASE_ADDR + SZ_4K - 1,
 241                 .flags = IORESOURCE_MEM,
 242         },
 243 };
 244
 245 struct platform_device mxc_w1_master_device = {
 246         .name = "mxc_w1",
 247         .id = 0,
 248         .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
 249         .resource = mxc_w1_master_resources,
 250 };
 251
 252 static struct resource mxc_nand_resources[] = {
 253         {
 254                 .start  = NFC_BASE_ADDR,
 255                 .end    = NFC_BASE_ADDR + 0xfff,
 256                 .flags  = IORESOURCE_MEM,
 257         }, {
 258                 .start  = MXC_INT_NANDFC,
 259                 .end    = MXC_INT_NANDFC,
 260                 .flags  = IORESOURCE_IRQ,
 261         },
 262 };
 263
 264 struct platform_device mxc_nand_device = {
 265         .name = "mxc_nand",
 266         .id = 0,
 267         .num_resources = ARRAY_SIZE(mxc_nand_resources),
 268         .resource = mxc_nand_resources,
 269 };
 270
 271 /*
 272  * lcdc:
 273  * - i.MX1: the basic controller
 274  * - i.MX21: to be checked
 275  * - i.MX27: like i.MX1, with slightly variations
 276  */
 277 static struct resource mxc_fb[] = {
 278         {
 279                 .start = LCDC_BASE_ADDR,
 280                 .end   = LCDC_BASE_ADDR + 0xFFF,
 281                 .flags = IORESOURCE_MEM,
 282         }, {
 283                 .start = MXC_INT_LCDC,
 284                 .end   = MXC_INT_LCDC,
 285                 .flags = IORESOURCE_IRQ,
 286         }
 287 };
 288
 289 /* mxc lcd driver */
 290 struct platform_device mxc_fb_device = {
 291         .name = "imx-fb",
 292         .id = 0,
 293         .num_resources = ARRAY_SIZE(mxc_fb),
 294         .resource = mxc_fb,
 295         .dev = {
 296                 .coherent_dma_mask = DMA_BIT_MASK(32),
 297         },
 298 };
 299
 300 #ifdef CONFIG_MACH_MX27
 301 static struct resource mxc_fec_resources[] = {
 302         {
 303                 .start  = FEC_BASE_ADDR,
 304                 .end    = FEC_BASE_ADDR + 0xfff,
 305                 .flags  = IORESOURCE_MEM,
 306         }, {
 307                 .start  = MXC_INT_FEC,
 308                 .end    = MXC_INT_FEC,
 309                 .flags  = IORESOURCE_IRQ,
 310         },
 311 };
 312
 313 struct platform_device mxc_fec_device = {
 314         .name = "fec",
 315         .id = 0,
 316         .num_resources = ARRAY_SIZE(mxc_fec_resources),
 317         .resource = mxc_fec_resources,
 318 };
 319 #endif
 320
 321 static struct resource mxc_i2c_1_resources[] = {
 322         {
 323                 .start  = I2C_BASE_ADDR,
 324                 .end    = I2C_BASE_ADDR + 0x0fff,
 325                 .flags  = IORESOURCE_MEM,
 326         }, {
 327                 .start  = MXC_INT_I2C,
 328                 .end    = MXC_INT_I2C,
 329                 .flags  = IORESOURCE_IRQ,
 330         }
 331 };
 332
 333 struct platform_device mxc_i2c_device0 = {
 334         .name = "imx-i2c",
 335         .id = 0,
 336         .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
 337         .resource = mxc_i2c_1_resources,
 338 };
 339
 340 #ifdef CONFIG_MACH_MX27
 341 static struct resource mxc_i2c_2_resources[] = {
 342         {
 343                 .start  = I2C2_BASE_ADDR,
 344                 .end    = I2C2_BASE_ADDR + 0x0fff,
 345                 .flags  = IORESOURCE_MEM,
 346         }, {
 347                 .start  = MXC_INT_I2C2,
 348                 .end    = MXC_INT_I2C2,
 349                 .flags  = IORESOURCE_IRQ,
 350         }
 351 };
 352
 353 struct platform_device mxc_i2c_device1 = {
 354         .name = "imx-i2c",
 355         .id = 1,
 356         .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
 357         .resource = mxc_i2c_2_resources,
 358 };
 359 #endif
 360
 361 static struct resource mxc_pwm_resources[] = {
 362         {
 363                 .start  = PWM_BASE_ADDR,
 364                 .end    = PWM_BASE_ADDR + 0x0fff,
 365                 .flags  = IORESOURCE_MEM,
 366         }, {
 367                 .start   = MXC_INT_PWM,
 368                 .end     = MXC_INT_PWM,
 369                 .flags   = IORESOURCE_IRQ,
 370         }
 371 };
 372
 373 struct platform_device mxc_pwm_device = {
 374         .name = "mxc_pwm",
 375         .id = 0,
 376         .num_resources = ARRAY_SIZE(mxc_pwm_resources),
 377         .resource = mxc_pwm_resources,
 378 };
 379
 380 /*
 381  * Resource definition for the MXC SDHC
 382  */
 383 static struct resource mxc_sdhc1_resources[] = {
 384         {
 385                 .start = SDHC1_BASE_ADDR,
 386                 .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
 387                 .flags = IORESOURCE_MEM,
 388         }, {
 389                 .start = MXC_INT_SDHC1,
 390                 .end   = MXC_INT_SDHC1,
 391                 .flags = IORESOURCE_IRQ,
 392         }, {
 393                 .start  = DMA_REQ_SDHC1,
 394                 .end    = DMA_REQ_SDHC1,
 395                 .flags  = IORESOURCE_DMA,
 396         },
 397 };
 398
 399 static u64 mxc_sdhc1_dmamask = DMA_BIT_MASK(32);
 400
 401 struct platform_device mxc_sdhc_device0 = {
 402         .name           = "mxc-mmc",
 403         .id             = 0,
 404         .dev            = {
 405                 .dma_mask = &mxc_sdhc1_dmamask,
 406                 .coherent_dma_mask = DMA_BIT_MASK(32),
 407         },
 408         .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
 409         .resource       = mxc_sdhc1_resources,
 410 };
 411
 412 static struct resource mxc_sdhc2_resources[] = {
 413         {
 414                 .start = SDHC2_BASE_ADDR,
 415                 .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
 416                 .flags = IORESOURCE_MEM,
 417         }, {
 418                 .start = MXC_INT_SDHC2,
 419                 .end   = MXC_INT_SDHC2,
 420                 .flags = IORESOURCE_IRQ,
 421         }, {
 422                 .start  = DMA_REQ_SDHC2,
 423                 .end    = DMA_REQ_SDHC2,
 424                 .flags  = IORESOURCE_DMA,
 425         },
 426 };
 427
 428 static u64 mxc_sdhc2_dmamask = DMA_BIT_MASK(32);
 429
 430 struct platform_device mxc_sdhc_device1 = {
 431         .name           = "mxc-mmc",
 432         .id             = 1,
 433         .dev            = {
 434                 .dma_mask = &mxc_sdhc2_dmamask,
 435                 .coherent_dma_mask = DMA_BIT_MASK(32),
 436         },
 437         .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
 438         .resource       = mxc_sdhc2_resources,
 439 };
 440
 441 #ifdef CONFIG_MACH_MX27
 442 static struct resource otg_resources[] = {
 443         {
 444                 .start  = OTG_BASE_ADDR,
 445                 .end    = OTG_BASE_ADDR + 0x1ff,
 446                 .flags  = IORESOURCE_MEM,
 447         }, {
 448                 .start  = MXC_INT_USB3,
 449                 .end    = MXC_INT_USB3,
 450                 .flags  = IORESOURCE_IRQ,
 451         },
 452 };
 453
 454 static u64 otg_dmamask = DMA_BIT_MASK(32);
 455
 456 /* OTG gadget device */
 457 struct platform_device mxc_otg_udc_device = {
 458         .name           = "fsl-usb2-udc",
 459         .id             = -1,
 460         .dev            = {
 461                 .dma_mask               = &otg_dmamask,
 462                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 463         },
 464         .resource       = otg_resources,
 465         .num_resources  = ARRAY_SIZE(otg_resources),
 466 };
 467
 468 /* OTG host */
 469 struct platform_device mxc_otg_host = {
 470         .name = "mxc-ehci",
 471         .id = 0,
 472         .dev = {
 473                 .coherent_dma_mask = DMA_BIT_MASK(32),
 474                 .dma_mask = &otg_dmamask,
 475         },
 476         .resource = otg_resources,
 477         .num_resources = ARRAY_SIZE(otg_resources),
 478 };
 479
 480 /* USB host 1 */
 481
 482 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
 483
 484 static struct resource mxc_usbh1_resources[] = {
 485         {
 486                 .start = OTG_BASE_ADDR + 0x200,
 487                 .end = OTG_BASE_ADDR + 0x3ff,
 488                 .flags = IORESOURCE_MEM,
 489         }, {
 490                 .start = MXC_INT_USB1,
 491                 .end = MXC_INT_USB1,
 492                 .flags = IORESOURCE_IRQ,
 493         },
 494 };
 495
 496 struct platform_device mxc_usbh1 = {
 497         .name = "mxc-ehci",
 498         .id = 1,
 499         .dev = {
 500                 .coherent_dma_mask = DMA_BIT_MASK(32),
 501                 .dma_mask = &usbh1_dmamask,
 502         },
 503         .resource = mxc_usbh1_resources,
 504         .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
 505 };
 506
 507 /* USB host 2 */
 508 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
 509
 510 static struct resource mxc_usbh2_resources[] = {
 511         {
 512                 .start = OTG_BASE_ADDR + 0x400,
 513                 .end = OTG_BASE_ADDR + 0x5ff,
 514                 .flags = IORESOURCE_MEM,
 515         }, {
 516                 .start = MXC_INT_USB2,
 517                 .end = MXC_INT_USB2,
 518                 .flags = IORESOURCE_IRQ,
 519         },
 520 };
 521
 522 struct platform_device mxc_usbh2 = {
 523         .name = "mxc-ehci",
 524         .id = 2,
 525         .dev = {
 526                 .coherent_dma_mask = DMA_BIT_MASK(32),
 527                 .dma_mask = &usbh2_dmamask,
 528         },
 529         .resource = mxc_usbh2_resources,
 530         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 531 };
 532 #endif
 533
 534 static struct resource imx_ssi_resources0[] = {
 535         {
 536                 .start  = SSI1_BASE_ADDR,
 537                 .end    = SSI1_BASE_ADDR + 0x6F,
 538                 .flags  = IORESOURCE_MEM,
 539         }, {
 540                 .start  = MXC_INT_SSI1,
 541                 .end    = MXC_INT_SSI1,
 542                 .flags  = IORESOURCE_IRQ,
 543         }, {
 544                 .name   = "tx0",
 545                 .start  = DMA_REQ_SSI1_TX0,
 546                 .end    = DMA_REQ_SSI1_TX0,
 547                 .flags  = IORESOURCE_DMA,
 548         }, {
 549                 .name   = "rx0",
 550                 .start  = DMA_REQ_SSI1_RX0,
 551                 .end    = DMA_REQ_SSI1_RX0,
 552                 .flags  = IORESOURCE_DMA,
 553         }, {
 554                 .name   = "tx1",
 555                 .start  = DMA_REQ_SSI1_TX1,
 556                 .end    = DMA_REQ_SSI1_TX1,
 557                 .flags  = IORESOURCE_DMA,
 558         }, {
 559                 .name   = "rx1",
 560                 .start  = DMA_REQ_SSI1_RX1,
 561                 .end    = DMA_REQ_SSI1_RX1,
 562                 .flags  = IORESOURCE_DMA,
 563         },
 564 };
 565
 566 static struct resource imx_ssi_resources1[] = {
 567         {
 568                 .start  = SSI2_BASE_ADDR,
 569                 .end    = SSI2_BASE_ADDR + 0x6F,
 570                 .flags  = IORESOURCE_MEM,
 571         }, {
 572                 .start  = MXC_INT_SSI2,
 573                 .end    = MXC_INT_SSI2,
 574                 .flags  = IORESOURCE_IRQ,
 575         }, {
 576                 .name   = "tx0",
 577                 .start  = DMA_REQ_SSI2_TX0,
 578                 .end    = DMA_REQ_SSI2_TX0,
 579                 .flags  = IORESOURCE_DMA,
 580         }, {
 581                 .name   = "rx0",
 582                 .start  = DMA_REQ_SSI2_RX0,
 583                 .end    = DMA_REQ_SSI2_RX0,
 584                 .flags  = IORESOURCE_DMA,
 585         }, {
 586                 .name   = "tx1",
 587                 .start  = DMA_REQ_SSI2_TX1,
 588                 .end    = DMA_REQ_SSI2_TX1,
 589                 .flags  = IORESOURCE_DMA,
 590         }, {
 591                 .name   = "rx1",
 592                 .start  = DMA_REQ_SSI2_RX1,
 593                 .end    = DMA_REQ_SSI2_RX1,
 594                 .flags  = IORESOURCE_DMA,
 595         },
 596 };
 597
 598 struct platform_device imx_ssi_device0 = {
 599         .name = "imx-ssi",
 600         .id = 0,
 601         .num_resources = ARRAY_SIZE(imx_ssi_resources0),
 602         .resource = imx_ssi_resources0,
 603 };
 604
 605 struct platform_device imx_ssi_device1 = {
 606         .name = "imx-ssi",
 607         .id = 1,
 608         .num_resources = ARRAY_SIZE(imx_ssi_resources1),
 609         .resource = imx_ssi_resources1,
 610 };
 611
 612 /* GPIO port description */
 613 static struct mxc_gpio_port imx_gpio_ports[] = {
 614         {
 615                 .chip.label = "gpio-0",
 616                 .irq = MXC_INT_GPIO,
 617                 .base = IO_ADDRESS(GPIO_BASE_ADDR),
 618                 .virtual_irq_start = MXC_GPIO_IRQ_START,
 619         }, {
 620                 .chip.label = "gpio-1",
 621                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
 622                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
 623         }, {
 624                 .chip.label = "gpio-2",
 625                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
 626                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
 627         }, {
 628                 .chip.label = "gpio-3",
 629                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
 630                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
 631         }, {
 632                 .chip.label = "gpio-4",
 633                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
 634                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
 635         }, {
 636                 .chip.label = "gpio-5",
 637                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
 638                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
 639         }
 640 };
 641
 642 int __init mxc_register_gpios(void)
 643 {
 644         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 645 }
 646
 647 #ifdef CONFIG_MACH_MX21
 648 static struct resource mx21_usbhc_resources[] = {
 649         {
 650                 .start  = USBOTG_BASE_ADDR,
 651                 .end    = USBOTG_BASE_ADDR + 0x1FFF,
 652                 .flags  = IORESOURCE_MEM,
 653         },
 654         {
 655                 .start          = MXC_INT_USBHOST,
 656                 .end            = MXC_INT_USBHOST,
 657                 .flags          = IORESOURCE_IRQ,
 658         },
 659 };
 660
 661 struct platform_device mx21_usbhc_device = {
 662         .name           = "imx21-hcd",
 663         .id             = 0,
 664         .dev            = {
 665                 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
 666                 .coherent_dma_mask = DMA_BIT_MASK(32),
 667         },
 668         .num_resources  = ARRAY_SIZE(mx21_usbhc_resources),
 669         .resource       = mx21_usbhc_resources,
 670 };
 671 #endif
 672