arch/arm/mach-kirkwood/common.c

   1 /*
   2  * arch/arm/mach-kirkwood/common.c
   3  *
   4  * Core functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/mbus.h>
  16 #include <linux/ata_platform.h>
  17 #include <linux/mtd/nand.h>
  18 #include <linux/spi/orion_spi.h>
  19 #include <net/dsa.h>
  20 #include <asm/page.h>
  21 #include <asm/timex.h>
  22 #include <asm/kexec.h>
  23 #include <asm/mach/map.h>
  24 #include <asm/mach/time.h>
  25 #include <mach/kirkwood.h>
  26 #include <mach/bridge-regs.h>
  27 #include <plat/audio.h>
  28 #include <plat/cache-feroceon-l2.h>
  29 #include <plat/ehci-orion.h>
  30 #include <plat/mvsdio.h>
  31 #include <plat/mv_xor.h>
  32 #include <plat/orion_nand.h>
  33 #include <plat/orion_wdt.h>
  34 #include <plat/common.h>
  35 #include <plat/time.h>
  36 #include "common.h"
  37
  38 /*****************************************************************************
  39  * I/O Address Mapping
  40  ****************************************************************************/
  41 static struct map_desc kirkwood_io_desc[] __initdata = {
  42         {
  43                 .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
  44                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
  45                 .length         = KIRKWOOD_PCIE_IO_SIZE,
  46                 .type           = MT_DEVICE,
  47         }, {
  48                 .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
  49                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
  50                 .length         = KIRKWOOD_PCIE1_IO_SIZE,
  51                 .type           = MT_DEVICE,
  52         }, {
  53                 .virtual        = KIRKWOOD_REGS_VIRT_BASE,
  54                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
  55                 .length         = KIRKWOOD_REGS_SIZE,
  56                 .type           = MT_DEVICE,
  57         },
  58 };
  59
  60 void __init kirkwood_map_io(void)
  61 {
  62         iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
  63 }
  64
  65 /*
  66  * Default clock control bits.  Any bit _not_ set in this variable
  67  * will be cleared from the hardware after platform devices have been
  68  * registered.  Some reserved bits must be set to 1.
  69  */
  70 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
  71
  72
  73 /*****************************************************************************
  74  * EHCI
  75  ****************************************************************************/
  76 static struct orion_ehci_data kirkwood_ehci_data = {
  77         .dram           = &kirkwood_mbus_dram_info,
  78         .phy_version    = EHCI_PHY_NA,
  79 };
  80
  81 static u64 ehci_dmamask = DMA_BIT_MASK(32);
  82
  83
  84 /*****************************************************************************
  85  * EHCI0
  86  ****************************************************************************/
  87 static struct resource kirkwood_ehci_resources[] = {
  88         {
  89                 .start  = USB_PHYS_BASE,
  90                 .end    = USB_PHYS_BASE + SZ_4K - 1,
  91                 .flags  = IORESOURCE_MEM,
  92         }, {
  93                 .start  = IRQ_KIRKWOOD_USB,
  94                 .end    = IRQ_KIRKWOOD_USB,
  95                 .flags  = IORESOURCE_IRQ,
  96         },
  97 };
  98
  99 static struct platform_device kirkwood_ehci = {
 100         .name           = "orion-ehci",
 101         .id             = 0,
 102         .dev            = {
 103                 .dma_mask               = &ehci_dmamask,
 104                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 105                 .platform_data          = &kirkwood_ehci_data,
 106         },
 107         .resource       = kirkwood_ehci_resources,
 108         .num_resources  = ARRAY_SIZE(kirkwood_ehci_resources),
 109 };
 110
 111 void __init kirkwood_ehci_init(void)
 112 {
 113         kirkwood_clk_ctrl |= CGC_USB0;
 114         platform_device_register(&kirkwood_ehci);
 115 }
 116
 117
 118 /*****************************************************************************
 119  * GE00
 120  ****************************************************************************/
 121 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 122 {
 123         kirkwood_clk_ctrl |= CGC_GE0;
 124
 125         orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
 126                         GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
 127                         IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
 128 }
 129
 130
 131 /*****************************************************************************
 132  * GE01
 133  ****************************************************************************/
 134 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 135 {
 136
 137         kirkwood_clk_ctrl |= CGC_GE1;
 138
 139         orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
 140                         GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
 141                         IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
 142 }
 143
 144
 145 /*****************************************************************************
 146  * Ethernet switch
 147  ****************************************************************************/
 148 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 149 {
 150         orion_ge00_switch_init(d, irq);
 151 }
 152
 153
 154 /*****************************************************************************
 155  * NAND flash
 156  ****************************************************************************/
 157 static struct resource kirkwood_nand_resource = {
 158         .flags          = IORESOURCE_MEM,
 159         .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
 160         .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
 161                                 KIRKWOOD_NAND_MEM_SIZE - 1,
 162 };
 163
 164 static struct orion_nand_data kirkwood_nand_data = {
 165         .cle            = 0,
 166         .ale            = 1,
 167         .width          = 8,
 168 };
 169
 170 static struct platform_device kirkwood_nand_flash = {
 171         .name           = "orion_nand",
 172         .id             = -1,
 173         .dev            = {
 174                 .platform_data  = &kirkwood_nand_data,
 175         },
 176         .resource       = &kirkwood_nand_resource,
 177         .num_resources  = 1,
 178 };
 179
 180 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
 181                                int chip_delay)
 182 {
 183         kirkwood_clk_ctrl |= CGC_RUNIT;
 184         kirkwood_nand_data.parts = parts;
 185         kirkwood_nand_data.nr_parts = nr_parts;
 186         kirkwood_nand_data.chip_delay = chip_delay;
 187         platform_device_register(&kirkwood_nand_flash);
 188 }
 189
 190 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 191                                    int (*dev_ready)(struct mtd_info *))
 192 {
 193         kirkwood_clk_ctrl |= CGC_RUNIT;
 194         kirkwood_nand_data.parts = parts;
 195         kirkwood_nand_data.nr_parts = nr_parts;
 196         kirkwood_nand_data.dev_ready = dev_ready;
 197         platform_device_register(&kirkwood_nand_flash);
 198 }
 199
 200 /*****************************************************************************
 201  * SoC RTC
 202  ****************************************************************************/
 203 static void __init kirkwood_rtc_init(void)
 204 {
 205         orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 206 }
 207
 208
 209 /*****************************************************************************
 210  * SATA
 211  ****************************************************************************/
 212 static struct resource kirkwood_sata_resources[] = {
 213         {
 214                 .name   = "sata base",
 215                 .start  = SATA_PHYS_BASE,
 216                 .end    = SATA_PHYS_BASE + 0x5000 - 1,
 217                 .flags  = IORESOURCE_MEM,
 218         }, {
 219                 .name   = "sata irq",
 220                 .start  = IRQ_KIRKWOOD_SATA,
 221                 .end    = IRQ_KIRKWOOD_SATA,
 222                 .flags  = IORESOURCE_IRQ,
 223         },
 224 };
 225
 226 static struct platform_device kirkwood_sata = {
 227         .name           = "sata_mv",
 228         .id             = 0,
 229         .dev            = {
 230                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 231         },
 232         .num_resources  = ARRAY_SIZE(kirkwood_sata_resources),
 233         .resource       = kirkwood_sata_resources,
 234 };
 235
 236 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 237 {
 238         kirkwood_clk_ctrl |= CGC_SATA0;
 239         if (sata_data->n_ports > 1)
 240                 kirkwood_clk_ctrl |= CGC_SATA1;
 241         sata_data->dram = &kirkwood_mbus_dram_info;
 242         kirkwood_sata.dev.platform_data = sata_data;
 243         platform_device_register(&kirkwood_sata);
 244 }
 245
 246
 247 /*****************************************************************************
 248  * SD/SDIO/MMC
 249  ****************************************************************************/
 250 static struct resource mvsdio_resources[] = {
 251         [0] = {
 252                 .start  = SDIO_PHYS_BASE,
 253                 .end    = SDIO_PHYS_BASE + SZ_1K - 1,
 254                 .flags  = IORESOURCE_MEM,
 255         },
 256         [1] = {
 257                 .start  = IRQ_KIRKWOOD_SDIO,
 258                 .end    = IRQ_KIRKWOOD_SDIO,
 259                 .flags  = IORESOURCE_IRQ,
 260         },
 261 };
 262
 263 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
 264
 265 static struct platform_device kirkwood_sdio = {
 266         .name           = "mvsdio",
 267         .id             = -1,
 268         .dev            = {
 269                 .dma_mask = &mvsdio_dmamask,
 270                 .coherent_dma_mask = DMA_BIT_MASK(32),
 271         },
 272         .num_resources  = ARRAY_SIZE(mvsdio_resources),
 273         .resource       = mvsdio_resources,
 274 };
 275
 276 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 277 {
 278         u32 dev, rev;
 279
 280         kirkwood_pcie_id(&dev, &rev);
 281         if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
 282                 mvsdio_data->clock = 100000000;
 283         else
 284                 mvsdio_data->clock = 200000000;
 285         mvsdio_data->dram = &kirkwood_mbus_dram_info;
 286         kirkwood_clk_ctrl |= CGC_SDIO;
 287         kirkwood_sdio.dev.platform_data = mvsdio_data;
 288         platform_device_register(&kirkwood_sdio);
 289 }
 290
 291
 292 /*****************************************************************************
 293  * SPI
 294  ****************************************************************************/
 295 static struct orion_spi_info kirkwood_spi_plat_data = {
 296 };
 297
 298 static struct resource kirkwood_spi_resources[] = {
 299         {
 300                 .start  = SPI_PHYS_BASE,
 301                 .end    = SPI_PHYS_BASE + SZ_512 - 1,
 302                 .flags  = IORESOURCE_MEM,
 303         },
 304 };
 305
 306 static struct platform_device kirkwood_spi = {
 307         .name           = "orion_spi",
 308         .id             = 0,
 309         .resource       = kirkwood_spi_resources,
 310         .dev            = {
 311                 .platform_data  = &kirkwood_spi_plat_data,
 312         },
 313         .num_resources  = ARRAY_SIZE(kirkwood_spi_resources),
 314 };
 315
 316 void __init kirkwood_spi_init()
 317 {
 318         kirkwood_clk_ctrl |= CGC_RUNIT;
 319         platform_device_register(&kirkwood_spi);
 320 }
 321
 322
 323 /*****************************************************************************
 324  * I2C
 325  ****************************************************************************/
 326 void __init kirkwood_i2c_init(void)
 327 {
 328         orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
 329 }
 330
 331
 332 /*****************************************************************************
 333  * UART0
 334  ****************************************************************************/
 335
 336 void __init kirkwood_uart0_init(void)
 337 {
 338         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 339                          IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
 340 }
 341
 342
 343 /*****************************************************************************
 344  * UART1
 345  ****************************************************************************/
 346 void __init kirkwood_uart1_init(void)
 347 {
 348         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 349                          IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
 350 }
 351
 352 /*****************************************************************************
 353  * Cryptographic Engines and Security Accelerator (CESA)
 354  ****************************************************************************/
 355
 356 static struct resource kirkwood_crypto_res[] = {
 357         {
 358                 .name   = "regs",
 359                 .start  = CRYPTO_PHYS_BASE,
 360                 .end    = CRYPTO_PHYS_BASE + 0xffff,
 361                 .flags  = IORESOURCE_MEM,
 362         }, {
 363                 .name   = "sram",
 364                 .start  = KIRKWOOD_SRAM_PHYS_BASE,
 365                 .end    = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
 366                 .flags  = IORESOURCE_MEM,
 367         }, {
 368                 .name   = "crypto interrupt",
 369                 .start  = IRQ_KIRKWOOD_CRYPTO,
 370                 .end    = IRQ_KIRKWOOD_CRYPTO,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373 };
 374
 375 static struct platform_device kirkwood_crypto_device = {
 376         .name           = "mv_crypto",
 377         .id             = -1,
 378         .num_resources  = ARRAY_SIZE(kirkwood_crypto_res),
 379         .resource       = kirkwood_crypto_res,
 380 };
 381
 382 void __init kirkwood_crypto_init(void)
 383 {
 384         kirkwood_clk_ctrl |= CGC_CRYPTO;
 385         platform_device_register(&kirkwood_crypto_device);
 386 }
 387
 388
 389 /*****************************************************************************
 390  * XOR
 391  ****************************************************************************/
 392 static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
 393         .dram           = &kirkwood_mbus_dram_info,
 394 };
 395
 396
 397 /*****************************************************************************
 398  * XOR0
 399  ****************************************************************************/
 400 static struct resource kirkwood_xor0_shared_resources[] = {
 401         {
 402                 .name   = "xor 0 low",
 403                 .start  = XOR0_PHYS_BASE,
 404                 .end    = XOR0_PHYS_BASE + 0xff,
 405                 .flags  = IORESOURCE_MEM,
 406         }, {
 407                 .name   = "xor 0 high",
 408                 .start  = XOR0_HIGH_PHYS_BASE,
 409                 .end    = XOR0_HIGH_PHYS_BASE + 0xff,
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412 };
 413
 414 static struct platform_device kirkwood_xor0_shared = {
 415         .name           = MV_XOR_SHARED_NAME,
 416         .id             = 0,
 417         .dev            = {
 418                 .platform_data = &kirkwood_xor_shared_data,
 419         },
 420         .num_resources  = ARRAY_SIZE(kirkwood_xor0_shared_resources),
 421         .resource       = kirkwood_xor0_shared_resources,
 422 };
 423
 424 static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
 425
 426 static struct resource kirkwood_xor00_resources[] = {
 427         [0] = {
 428                 .start  = IRQ_KIRKWOOD_XOR_00,
 429                 .end    = IRQ_KIRKWOOD_XOR_00,
 430                 .flags  = IORESOURCE_IRQ,
 431         },
 432 };
 433
 434 static struct mv_xor_platform_data kirkwood_xor00_data = {
 435         .shared         = &kirkwood_xor0_shared,
 436         .hw_id          = 0,
 437         .pool_size      = PAGE_SIZE,
 438 };
 439
 440 static struct platform_device kirkwood_xor00_channel = {
 441         .name           = MV_XOR_NAME,
 442         .id             = 0,
 443         .num_resources  = ARRAY_SIZE(kirkwood_xor00_resources),
 444         .resource       = kirkwood_xor00_resources,
 445         .dev            = {
 446                 .dma_mask               = &kirkwood_xor_dmamask,
 447                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 448                 .platform_data          = &kirkwood_xor00_data,
 449         },
 450 };
 451
 452 static struct resource kirkwood_xor01_resources[] = {
 453         [0] = {
 454                 .start  = IRQ_KIRKWOOD_XOR_01,
 455                 .end    = IRQ_KIRKWOOD_XOR_01,
 456                 .flags  = IORESOURCE_IRQ,
 457         },
 458 };
 459
 460 static struct mv_xor_platform_data kirkwood_xor01_data = {
 461         .shared         = &kirkwood_xor0_shared,
 462         .hw_id          = 1,
 463         .pool_size      = PAGE_SIZE,
 464 };
 465
 466 static struct platform_device kirkwood_xor01_channel = {
 467         .name           = MV_XOR_NAME,
 468         .id             = 1,
 469         .num_resources  = ARRAY_SIZE(kirkwood_xor01_resources),
 470         .resource       = kirkwood_xor01_resources,
 471         .dev            = {
 472                 .dma_mask               = &kirkwood_xor_dmamask,
 473                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 474                 .platform_data          = &kirkwood_xor01_data,
 475         },
 476 };
 477
 478 static void __init kirkwood_xor0_init(void)
 479 {
 480         kirkwood_clk_ctrl |= CGC_XOR0;
 481         platform_device_register(&kirkwood_xor0_shared);
 482
 483         /*
 484          * two engines can't do memset simultaneously, this limitation
 485          * satisfied by removing memset support from one of the engines.
 486          */
 487         dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
 488         dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
 489         platform_device_register(&kirkwood_xor00_channel);
 490
 491         dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
 492         dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
 493         dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
 494         platform_device_register(&kirkwood_xor01_channel);
 495 }
 496
 497
 498 /*****************************************************************************
 499  * XOR1
 500  ****************************************************************************/
 501 static struct resource kirkwood_xor1_shared_resources[] = {
 502         {
 503                 .name   = "xor 1 low",
 504                 .start  = XOR1_PHYS_BASE,
 505                 .end    = XOR1_PHYS_BASE + 0xff,
 506                 .flags  = IORESOURCE_MEM,
 507         }, {
 508                 .name   = "xor 1 high",
 509                 .start  = XOR1_HIGH_PHYS_BASE,
 510                 .end    = XOR1_HIGH_PHYS_BASE + 0xff,
 511                 .flags  = IORESOURCE_MEM,
 512         },
 513 };
 514
 515 static struct platform_device kirkwood_xor1_shared = {
 516         .name           = MV_XOR_SHARED_NAME,
 517         .id             = 1,
 518         .dev            = {
 519                 .platform_data = &kirkwood_xor_shared_data,
 520         },
 521         .num_resources  = ARRAY_SIZE(kirkwood_xor1_shared_resources),
 522         .resource       = kirkwood_xor1_shared_resources,
 523 };
 524
 525 static struct resource kirkwood_xor10_resources[] = {
 526         [0] = {
 527                 .start  = IRQ_KIRKWOOD_XOR_10,
 528                 .end    = IRQ_KIRKWOOD_XOR_10,
 529                 .flags  = IORESOURCE_IRQ,
 530         },
 531 };
 532
 533 static struct mv_xor_platform_data kirkwood_xor10_data = {
 534         .shared         = &kirkwood_xor1_shared,
 535         .hw_id          = 0,
 536         .pool_size      = PAGE_SIZE,
 537 };
 538
 539 static struct platform_device kirkwood_xor10_channel = {
 540         .name           = MV_XOR_NAME,
 541         .id             = 2,
 542         .num_resources  = ARRAY_SIZE(kirkwood_xor10_resources),
 543         .resource       = kirkwood_xor10_resources,
 544         .dev            = {
 545                 .dma_mask               = &kirkwood_xor_dmamask,
 546                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 547                 .platform_data          = &kirkwood_xor10_data,
 548         },
 549 };
 550
 551 static struct resource kirkwood_xor11_resources[] = {
 552         [0] = {
 553                 .start  = IRQ_KIRKWOOD_XOR_11,
 554                 .end    = IRQ_KIRKWOOD_XOR_11,
 555                 .flags  = IORESOURCE_IRQ,
 556         },
 557 };
 558
 559 static struct mv_xor_platform_data kirkwood_xor11_data = {
 560         .shared         = &kirkwood_xor1_shared,
 561         .hw_id          = 1,
 562         .pool_size      = PAGE_SIZE,
 563 };
 564
 565 static struct platform_device kirkwood_xor11_channel = {
 566         .name           = MV_XOR_NAME,
 567         .id             = 3,
 568         .num_resources  = ARRAY_SIZE(kirkwood_xor11_resources),
 569         .resource       = kirkwood_xor11_resources,
 570         .dev            = {
 571                 .dma_mask               = &kirkwood_xor_dmamask,
 572                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 573                 .platform_data          = &kirkwood_xor11_data,
 574         },
 575 };
 576
 577 static void __init kirkwood_xor1_init(void)
 578 {
 579         kirkwood_clk_ctrl |= CGC_XOR1;
 580         platform_device_register(&kirkwood_xor1_shared);
 581
 582         /*
 583          * two engines can't do memset simultaneously, this limitation
 584          * satisfied by removing memset support from one of the engines.
 585          */
 586         dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
 587         dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
 588         platform_device_register(&kirkwood_xor10_channel);
 589
 590         dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
 591         dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
 592         dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
 593         platform_device_register(&kirkwood_xor11_channel);
 594 }
 595
 596
 597 /*****************************************************************************
 598  * Watchdog
 599  ****************************************************************************/
 600 static struct orion_wdt_platform_data kirkwood_wdt_data = {
 601         .tclk           = 0,
 602 };
 603
 604 static struct platform_device kirkwood_wdt_device = {
 605         .name           = "orion_wdt",
 606         .id             = -1,
 607         .dev            = {
 608                 .platform_data  = &kirkwood_wdt_data,
 609         },
 610         .num_resources  = 0,
 611 };
 612
 613 static void __init kirkwood_wdt_init(void)
 614 {
 615         kirkwood_wdt_data.tclk = kirkwood_tclk;
 616         platform_device_register(&kirkwood_wdt_device);
 617 }
 618
 619
 620 /*****************************************************************************
 621  * Time handling
 622  ****************************************************************************/
 623 void __init kirkwood_init_early(void)
 624 {
 625         orion_time_set_base(TIMER_VIRT_BASE);
 626 }
 627
 628 int kirkwood_tclk;
 629
 630 static int __init kirkwood_find_tclk(void)
 631 {
 632         u32 dev, rev;
 633
 634         kirkwood_pcie_id(&dev, &rev);
 635
 636         if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
 637                 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
 638                         return 200000000;
 639
 640         return 166666667;
 641 }
 642
 643 static void __init kirkwood_timer_init(void)
 644 {
 645         kirkwood_tclk = kirkwood_find_tclk();
 646
 647         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 648                         IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 649 }
 650
 651 struct sys_timer kirkwood_timer = {
 652         .init = kirkwood_timer_init,
 653 };
 654
 655 /*****************************************************************************
 656  * Audio
 657  ****************************************************************************/
 658 static struct resource kirkwood_i2s_resources[] = {
 659         [0] = {
 660                 .start  = AUDIO_PHYS_BASE,
 661                 .end    = AUDIO_PHYS_BASE + SZ_16K - 1,
 662                 .flags  = IORESOURCE_MEM,
 663         },
 664         [1] = {
 665                 .start  = IRQ_KIRKWOOD_I2S,
 666                 .end    = IRQ_KIRKWOOD_I2S,
 667                 .flags  = IORESOURCE_IRQ,
 668         },
 669 };
 670
 671 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
 672         .dram        = &kirkwood_mbus_dram_info,
 673         .burst       = 128,
 674 };
 675
 676 static struct platform_device kirkwood_i2s_device = {
 677         .name           = "kirkwood-i2s",
 678         .id             = -1,
 679         .num_resources  = ARRAY_SIZE(kirkwood_i2s_resources),
 680         .resource       = kirkwood_i2s_resources,
 681         .dev            = {
 682                 .platform_data  = &kirkwood_i2s_data,
 683         },
 684 };
 685
 686 static struct platform_device kirkwood_pcm_device = {
 687         .name           = "kirkwood-pcm-audio",
 688         .id             = -1,
 689 };
 690
 691 void __init kirkwood_audio_init(void)
 692 {
 693         kirkwood_clk_ctrl |= CGC_AUDIO;
 694         platform_device_register(&kirkwood_i2s_device);
 695         platform_device_register(&kirkwood_pcm_device);
 696 }
 697
 698 /*****************************************************************************
 699  * General
 700  ****************************************************************************/
 701 /*
 702  * Identify device ID and revision.
 703  */
 704 static char * __init kirkwood_id(void)
 705 {
 706         u32 dev, rev;
 707
 708         kirkwood_pcie_id(&dev, &rev);
 709
 710         if (dev == MV88F6281_DEV_ID) {
 711                 if (rev == MV88F6281_REV_Z0)
 712                         return "MV88F6281-Z0";
 713                 else if (rev == MV88F6281_REV_A0)
 714                         return "MV88F6281-A0";
 715                 else if (rev == MV88F6281_REV_A1)
 716                         return "MV88F6281-A1";
 717                 else
 718                         return "MV88F6281-Rev-Unsupported";
 719         } else if (dev == MV88F6192_DEV_ID) {
 720                 if (rev == MV88F6192_REV_Z0)
 721                         return "MV88F6192-Z0";
 722                 else if (rev == MV88F6192_REV_A0)
 723                         return "MV88F6192-A0";
 724                 else if (rev == MV88F6192_REV_A1)
 725                         return "MV88F6192-A1";
 726                 else
 727                         return "MV88F6192-Rev-Unsupported";
 728         } else if (dev == MV88F6180_DEV_ID) {
 729                 if (rev == MV88F6180_REV_A0)
 730                         return "MV88F6180-Rev-A0";
 731                 else if (rev == MV88F6180_REV_A1)
 732                         return "MV88F6180-Rev-A1";
 733                 else
 734                         return "MV88F6180-Rev-Unsupported";
 735         } else if (dev == MV88F6282_DEV_ID) {
 736                 if (rev == MV88F6282_REV_A0)
 737                         return "MV88F6282-Rev-A0";
 738                 else
 739                         return "MV88F6282-Rev-Unsupported";
 740         } else {
 741                 return "Device-Unknown";
 742         }
 743 }
 744
 745 static void __init kirkwood_l2_init(void)
 746 {
 747 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 748         writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
 749         feroceon_l2_init(1);
 750 #else
 751         writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
 752         feroceon_l2_init(0);
 753 #endif
 754 }
 755
 756 void __init kirkwood_init(void)
 757 {
 758         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 759                 kirkwood_id(), kirkwood_tclk);
 760         kirkwood_spi_plat_data.tclk = kirkwood_tclk;
 761         kirkwood_i2s_data.tclk = kirkwood_tclk;
 762
 763         /*
 764          * Disable propagation of mbus errors to the CPU local bus,
 765          * as this causes mbus errors (which can occur for example
 766          * for PCI aborts) to throw CPU aborts, which we're not set
 767          * up to deal with.
 768          */
 769         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 770
 771         kirkwood_setup_cpu_mbus();
 772
 773 #ifdef CONFIG_CACHE_FEROCEON_L2
 774         kirkwood_l2_init();
 775 #endif
 776
 777         /* internal devices that every board has */
 778         kirkwood_rtc_init();
 779         kirkwood_wdt_init();
 780         kirkwood_xor0_init();
 781         kirkwood_xor1_init();
 782         kirkwood_crypto_init();
 783
 784 #ifdef CONFIG_KEXEC
 785         kexec_reinit = kirkwood_enable_pcie;
 786 #endif
 787 }
 788
 789 static int __init kirkwood_clock_gate(void)
 790 {
 791         unsigned int curr = readl(CLOCK_GATING_CTRL);
 792         u32 dev, rev;
 793
 794         kirkwood_pcie_id(&dev, &rev);
 795         printk(KERN_DEBUG "Gating clock of unused units\n");
 796         printk(KERN_DEBUG "before: 0x%08x\n", curr);
 797
 798         /* Make sure those units are accessible */
 799         writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 800
 801         /* For SATA: first shutdown the phy */
 802         if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 803                 /* Disable PLL and IVREF */
 804                 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
 805                 /* Disable PHY */
 806                 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
 807         }
 808         if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
 809                 /* Disable PLL and IVREF */
 810                 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
 811                 /* Disable PHY */
 812                 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 813         }
 814
 815         /* For PCIe: first shutdown the phy */
 816         if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 817                 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
 818                 while (1)
 819                         if (readl(PCIE_STATUS) & 0x1)
 820                                 break;
 821                 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 822         }
 823
 824         /* For PCIe 1: first shutdown the phy */
 825         if (dev == MV88F6282_DEV_ID) {
 826                 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
 827                         writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
 828                         while (1)
 829                                 if (readl(PCIE1_STATUS) & 0x1)
 830                                         break;
 831                         writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
 832                 }
 833         } else  /* keep this bit set for devices that don't have PCIe1 */
 834                 kirkwood_clk_ctrl |= CGC_PEX1;
 835
 836         /* Now gate clock the required units */
 837         writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 838         printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
 839
 840         return 0;
 841 }
 842 late_initcall(kirkwood_clock_gate);