arch/arm/mach-kirkwood/addr-map.c

   1 /*
   2  * arch/arm/mach-kirkwood/addr-map.c
   3  *
   4  * Address map functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/mbus.h>
  14 #include <linux/io.h>
  15 #include <mach/hardware.h>
  16 #include "common.h"
  17
  18 /*
  19  * Generic Address Decode Windows bit settings
  20  */
  21 #define TARGET_DDR              0
  22 #define TARGET_DEV_BUS          1
  23 #define TARGET_SRAM             3
  24 #define TARGET_PCIE             4
  25 #define ATTR_DEV_SPI_ROM        0x1e
  26 #define ATTR_DEV_BOOT           0x1d
  27 #define ATTR_DEV_NAND           0x2f
  28 #define ATTR_DEV_CS3            0x37
  29 #define ATTR_DEV_CS2            0x3b
  30 #define ATTR_DEV_CS1            0x3d
  31 #define ATTR_DEV_CS0            0x3e
  32 #define ATTR_PCIE_IO            0xe0
  33 #define ATTR_PCIE_MEM           0xe8
  34 #define ATTR_PCIE1_IO           0xd0
  35 #define ATTR_PCIE1_MEM          0xd8
  36 #define ATTR_SRAM               0x01
  37
  38 /*
  39  * Helpers to get DDR bank info
  40  */
  41 #define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  42 #define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  43
  44 /*
  45  * CPU Address Decode Windows registers
  46  */
  47 #define WIN_OFF(n)              (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
  48 #define WIN_CTRL_OFF            0x0000
  49 #define WIN_BASE_OFF            0x0004
  50 #define WIN_REMAP_LO_OFF        0x0008
  51 #define WIN_REMAP_HI_OFF        0x000c
  52
  53
  54 struct mbus_dram_target_info kirkwood_mbus_dram_info;
  55
  56 static int __init cpu_win_can_remap(int win)
  57 {
  58         if (win < 4)
  59                 return 1;
  60
  61         return 0;
  62 }
  63
  64 static void __init setup_cpu_win(int win, u32 base, u32 size,
  65                                  u8 target, u8 attr, int remap)
  66 {
  67         void __iomem *addr = (void __iomem *)WIN_OFF(win);
  68         u32 ctrl;
  69
  70         base &= 0xffff0000;
  71         ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
  72
  73         writel(base, addr + WIN_BASE_OFF);
  74         writel(ctrl, addr + WIN_CTRL_OFF);
  75         if (cpu_win_can_remap(win)) {
  76                 if (remap < 0)
  77                         remap = base;
  78
  79                 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
  80                 writel(0, addr + WIN_REMAP_HI_OFF);
  81         }
  82 }
  83
  84 void __init kirkwood_setup_cpu_mbus(void)
  85 {
  86         void __iomem *addr;
  87         int i;
  88         int cs;
  89
  90         /*
  91          * First, disable and clear windows.
  92          */
  93         for (i = 0; i < 8; i++) {
  94                 addr = (void __iomem *)WIN_OFF(i);
  95
  96                 writel(0, addr + WIN_BASE_OFF);
  97                 writel(0, addr + WIN_CTRL_OFF);
  98                 if (cpu_win_can_remap(i)) {
  99                         writel(0, addr + WIN_REMAP_LO_OFF);
 100                         writel(0, addr + WIN_REMAP_HI_OFF);
 101                 }
 102         }
 103
 104         /*
 105          * Setup windows for PCIe IO+MEM space.
 106          */
 107         setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
 108                       TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
 109         setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 110                       TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
 111         setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
 112                       TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
 113         setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
 114                       TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 115
 116         /*
 117          * Setup window for NAND controller.
 118          */
 119         setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 120                       TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 121
 122         /*
 123          * Setup window for SRAM.
 124          */
 125         setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 126                       TARGET_SRAM, ATTR_SRAM, -1);
 127
 128         /*
 129          * Setup MBUS dram target info.
 130          */
 131         kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 132
 133         addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
 134
 135         for (i = 0, cs = 0; i < 4; i++) {
 136                 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
 137                 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
 138
 139                 /*
 140                  * Chip select enabled?
 141                  */
 142                 if (size & 1) {
 143                         struct mbus_dram_window *w;
 144
 145                         w = &kirkwood_mbus_dram_info.cs[cs++];
 146                         w->cs_index = i;
 147                         w->mbus_attr = 0xf & ~(1 << i);
 148                         w->base = base & 0xffff0000;
 149                         w->size = (size | 0x0000ffff) + 1;
 150                 }
 151         }
 152         kirkwood_mbus_dram_info.num_cs = cs;
 153 }