arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/string.h>
  17 #include <linux/sysdev.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/kmi.h>
  20 #include <linux/amba/clcd.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/io.h>
  23 #include <linux/gfp.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/platform.h>
  28 #include <asm/irq.h>
  29 #include <asm/setup.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/hardware/arm_timer.h>
  32 #include <asm/hardware/icst.h>
  33
  34 #include <mach/cm.h>
  35 #include <mach/lm.h>
  36
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/flash.h>
  39 #include <asm/mach/irq.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/time.h>
  42
  43 #include <asm/hardware/timer-sp.h>
  44
  45 #include "common.h"
  46
  47 #define INTCP_PA_FLASH_BASE             0x24000000
  48 #define INTCP_FLASH_SIZE                SZ_32M
  49
  50 #define INTCP_PA_CLCD_BASE              0xc0000000
  51
  52 #define INTCP_VA_CIC_BASE               IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
  53 #define INTCP_VA_PIC_BASE               IO_ADDRESS(INTEGRATOR_IC_BASE)
  54 #define INTCP_VA_SIC_BASE               IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
  55
  56 #define INTCP_ETH_SIZE                  0x10
  57
  58 #define INTCP_VA_CTRL_BASE              IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
  59 #define INTCP_FLASHPROG                 0x04
  60 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  61 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  62
  63 /*
  64  * Logical      Physical
  65  * f1000000     10000000        Core module registers
  66  * f1100000     11000000        System controller registers
  67  * f1200000     12000000        EBI registers
  68  * f1300000     13000000        Counter/Timer
  69  * f1400000     14000000        Interrupt controller
  70  * f1600000     16000000        UART 0
  71  * f1700000     17000000        UART 1
  72  * f1a00000     1a000000        Debug LEDs
  73  * fc900000     c9000000        GPIO
  74  * fca00000     ca000000        SIC
  75  * fcb00000     cb000000        CP system control
  76  */
  77
  78 static struct map_desc intcp_io_desc[] __initdata = {
  79         {
  80                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  81                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  82                 .length         = SZ_4K,
  83                 .type           = MT_DEVICE
  84         }, {
  85                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  86                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  87                 .length         = SZ_4K,
  88                 .type           = MT_DEVICE
  89         }, {
  90                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  91                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  92                 .length         = SZ_4K,
  93                 .type           = MT_DEVICE
  94         }, {
  95                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  96                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE
  99         }, {
 100                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 101                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE
 104         }, {
 105                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 106                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE
 109         }, {
 110                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 111                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE
 114         }, {
 115                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 116                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE
 119         }, {
 120                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
 121                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE
 124         }, {
 125                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 126                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE
 129         }, {
 130                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
 131                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE
 134         }
 135 };
 136
 137 static void __init intcp_map_io(void)
 138 {
 139         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 140 }
 141
 142 #define cic_writel      __raw_writel
 143 #define cic_readl       __raw_readl
 144 #define pic_writel      __raw_writel
 145 #define pic_readl       __raw_readl
 146 #define sic_writel      __raw_writel
 147 #define sic_readl       __raw_readl
 148
 149 static void cic_mask_irq(struct irq_data *d)
 150 {
 151         unsigned int irq = d->irq - IRQ_CIC_START;
 152         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 153 }
 154
 155 static void cic_unmask_irq(struct irq_data *d)
 156 {
 157         unsigned int irq = d->irq - IRQ_CIC_START;
 158         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 159 }
 160
 161 static struct irq_chip cic_chip = {
 162         .name           = "CIC",
 163         .irq_ack        = cic_mask_irq,
 164         .irq_mask       = cic_mask_irq,
 165         .irq_unmask     = cic_unmask_irq,
 166 };
 167
 168 static void pic_mask_irq(struct irq_data *d)
 169 {
 170         unsigned int irq = d->irq - IRQ_PIC_START;
 171         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 172 }
 173
 174 static void pic_unmask_irq(struct irq_data *d)
 175 {
 176         unsigned int irq = d->irq - IRQ_PIC_START;
 177         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 178 }
 179
 180 static struct irq_chip pic_chip = {
 181         .name           = "PIC",
 182         .irq_ack        = pic_mask_irq,
 183         .irq_mask       = pic_mask_irq,
 184         .irq_unmask     = pic_unmask_irq,
 185 };
 186
 187 static void sic_mask_irq(struct irq_data *d)
 188 {
 189         unsigned int irq = d->irq - IRQ_SIC_START;
 190         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 191 }
 192
 193 static void sic_unmask_irq(struct irq_data *d)
 194 {
 195         unsigned int irq = d->irq - IRQ_SIC_START;
 196         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 197 }
 198
 199 static struct irq_chip sic_chip = {
 200         .name           = "SIC",
 201         .irq_ack        = sic_mask_irq,
 202         .irq_mask       = sic_mask_irq,
 203         .irq_unmask     = sic_unmask_irq,
 204 };
 205
 206 static void
 207 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 208 {
 209         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 210
 211         if (status == 0) {
 212                 do_bad_IRQ(irq, desc);
 213                 return;
 214         }
 215
 216         do {
 217                 irq = ffs(status) - 1;
 218                 status &= ~(1 << irq);
 219
 220                 irq += IRQ_SIC_START;
 221
 222                 generic_handle_irq(irq);
 223         } while (status);
 224 }
 225
 226 static void __init intcp_init_irq(void)
 227 {
 228         unsigned int i;
 229
 230         /*
 231          * Disable all interrupt sources
 232          */
 233         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 234         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 235
 236         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
 237                 if (i == 11)
 238                         i = 22;
 239                 if (i == 29)
 240                         break;
 241                 set_irq_chip(i, &pic_chip);
 242                 set_irq_handler(i, handle_level_irq);
 243                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 244         }
 245
 246         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 247         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 248
 249         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
 250                 set_irq_chip(i, &cic_chip);
 251                 set_irq_handler(i, handle_level_irq);
 252                 set_irq_flags(i, IRQF_VALID);
 253         }
 254
 255         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 256         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 257
 258         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 259                 set_irq_chip(i, &sic_chip);
 260                 set_irq_handler(i, handle_level_irq);
 261                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 262         }
 263
 264         set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 265 }
 266
 267 /*
 268  * Clock handling
 269  */
 270 #define CM_LOCK         (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
 271 #define CM_AUXOSC       (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
 272
 273 static const struct icst_params cp_auxvco_params = {
 274         .ref            = 24000000,
 275         .vco_max        = ICST525_VCO_MAX_5V,
 276         .vco_min        = ICST525_VCO_MIN,
 277         .vd_min         = 8,
 278         .vd_max         = 263,
 279         .rd_min         = 3,
 280         .rd_max         = 65,
 281         .s2div          = icst525_s2div,
 282         .idx2s          = icst525_idx2s,
 283 };
 284
 285 static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
 286 {
 287         u32 val;
 288
 289         val = readl(clk->vcoreg) & ~0x7ffff;
 290         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 291
 292         writel(0xa05f, CM_LOCK);
 293         writel(val, clk->vcoreg);
 294         writel(0, CM_LOCK);
 295 }
 296
 297 static const struct clk_ops cp_auxclk_ops = {
 298         .round  = icst_clk_round,
 299         .set    = icst_clk_set,
 300         .setvco = cp_auxvco_set,
 301 };
 302
 303 static struct clk cp_auxclk = {
 304         .ops    = &cp_auxclk_ops,
 305         .params = &cp_auxvco_params,
 306         .vcoreg = CM_AUXOSC,
 307 };
 308
 309 static struct clk_lookup cp_lookups[] = {
 310         {       /* CLCD */
 311                 .dev_id         = "mb:c0",
 312                 .clk            = &cp_auxclk,
 313         },
 314 };
 315
 316 /*
 317  * Flash handling.
 318  */
 319 static int intcp_flash_init(void)
 320 {
 321         u32 val;
 322
 323         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 324         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 325         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 326
 327         return 0;
 328 }
 329
 330 static void intcp_flash_exit(void)
 331 {
 332         u32 val;
 333
 334         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 335         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 336         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 337 }
 338
 339 static void intcp_flash_set_vpp(int on)
 340 {
 341         u32 val;
 342
 343         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 344         if (on)
 345                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 346         else
 347                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 348         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 349 }
 350
 351 static struct flash_platform_data intcp_flash_data = {
 352         .map_name       = "cfi_probe",
 353         .width          = 4,
 354         .init           = intcp_flash_init,
 355         .exit           = intcp_flash_exit,
 356         .set_vpp        = intcp_flash_set_vpp,
 357 };
 358
 359 static struct resource intcp_flash_resource = {
 360         .start          = INTCP_PA_FLASH_BASE,
 361         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 362         .flags          = IORESOURCE_MEM,
 363 };
 364
 365 static struct platform_device intcp_flash_device = {
 366         .name           = "armflash",
 367         .id             = 0,
 368         .dev            = {
 369                 .platform_data  = &intcp_flash_data,
 370         },
 371         .num_resources  = 1,
 372         .resource       = &intcp_flash_resource,
 373 };
 374
 375 static struct resource smc91x_resources[] = {
 376         [0] = {
 377                 .start  = INTEGRATOR_CP_ETH_BASE,
 378                 .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
 379                 .flags  = IORESOURCE_MEM,
 380         },
 381         [1] = {
 382                 .start  = IRQ_CP_ETHINT,
 383                 .end    = IRQ_CP_ETHINT,
 384                 .flags  = IORESOURCE_IRQ,
 385         },
 386 };
 387
 388 static struct platform_device smc91x_device = {
 389         .name           = "smc91x",
 390         .id             = 0,
 391         .num_resources  = ARRAY_SIZE(smc91x_resources),
 392         .resource       = smc91x_resources,
 393 };
 394
 395 static struct platform_device *intcp_devs[] __initdata = {
 396         &intcp_flash_device,
 397         &smc91x_device,
 398 };
 399
 400 /*
 401  * It seems that the card insertion interrupt remains active after
 402  * we've acknowledged it.  We therefore ignore the interrupt, and
 403  * rely on reading it from the SIC.  This also means that we must
 404  * clear the latched interrupt.
 405  */
 406 static unsigned int mmc_status(struct device *dev)
 407 {
 408         unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
 409         writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
 410
 411         return status & 8;
 412 }
 413
 414 static struct mmci_platform_data mmc_data = {
 415         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 416         .status         = mmc_status,
 417         .gpio_wp        = -1,
 418         .gpio_cd        = -1,
 419 };
 420
 421 static struct amba_device mmc_device = {
 422         .dev            = {
 423                 .init_name = "mb:1c",
 424                 .platform_data = &mmc_data,
 425         },
 426         .res            = {
 427                 .start  = INTEGRATOR_CP_MMC_BASE,
 428                 .end    = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
 429                 .flags  = IORESOURCE_MEM,
 430         },
 431         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
 432         .periphid       = 0,
 433 };
 434
 435 static struct amba_device aaci_device = {
 436         .dev            = {
 437                 .init_name = "mb:1d",
 438         },
 439         .res            = {
 440                 .start  = INTEGRATOR_CP_AACI_BASE,
 441                 .end    = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
 442                 .flags  = IORESOURCE_MEM,
 443         },
 444         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
 445         .periphid       = 0,
 446 };
 447
 448
 449 /*
 450  * CLCD support
 451  */
 452 static struct clcd_panel vga = {
 453         .mode           = {
 454                 .name           = "VGA",
 455                 .refresh        = 60,
 456                 .xres           = 640,
 457                 .yres           = 480,
 458                 .pixclock       = 39721,
 459                 .left_margin    = 40,
 460                 .right_margin   = 24,
 461                 .upper_margin   = 32,
 462                 .lower_margin   = 11,
 463                 .hsync_len      = 96,
 464                 .vsync_len      = 2,
 465                 .sync           = 0,
 466                 .vmode          = FB_VMODE_NONINTERLACED,
 467         },
 468         .width          = -1,
 469         .height         = -1,
 470         .tim2           = TIM2_BCD | TIM2_IPC,
 471         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 472         .bpp            = 16,
 473         .grayscale      = 0,
 474 };
 475
 476 /*
 477  * Ensure VGA is selected.
 478  */
 479 static void cp_clcd_enable(struct clcd_fb *fb)
 480 {
 481         u32 val;
 482
 483         if (fb->fb.var.bits_per_pixel <= 8)
 484                 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
 485         else if (fb->fb.var.bits_per_pixel <= 16)
 486                 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
 487                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
 488                         | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
 489         else
 490                 val = 0; /* no idea for this, don't trust the docs */
 491
 492         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 493                    CM_CTRL_LCDEN0|
 494                    CM_CTRL_LCDEN1|
 495                    CM_CTRL_STATIC1|
 496                    CM_CTRL_STATIC2|
 497                    CM_CTRL_STATIC|
 498                    CM_CTRL_n24BITEN, val);
 499 }
 500
 501 static unsigned long framesize = SZ_1M;
 502
 503 static int cp_clcd_setup(struct clcd_fb *fb)
 504 {
 505         dma_addr_t dma;
 506
 507         fb->panel = &vga;
 508
 509         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 510                                                     &dma, GFP_KERNEL);
 511         if (!fb->fb.screen_base) {
 512                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 513                 return -ENOMEM;
 514         }
 515
 516         fb->fb.fix.smem_start   = dma;
 517         fb->fb.fix.smem_len     = framesize;
 518
 519         return 0;
 520 }
 521
 522 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 523 {
 524         return dma_mmap_writecombine(&fb->dev->dev, vma,
 525                                      fb->fb.screen_base,
 526                                      fb->fb.fix.smem_start,
 527                                      fb->fb.fix.smem_len);
 528 }
 529
 530 static void cp_clcd_remove(struct clcd_fb *fb)
 531 {
 532         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 533                               fb->fb.screen_base, fb->fb.fix.smem_start);
 534 }
 535
 536 static struct clcd_board clcd_data = {
 537         .name           = "Integrator/CP",
 538         .check          = clcdfb_check,
 539         .decode         = clcdfb_decode,
 540         .enable         = cp_clcd_enable,
 541         .setup          = cp_clcd_setup,
 542         .mmap           = cp_clcd_mmap,
 543         .remove         = cp_clcd_remove,
 544 };
 545
 546 static struct amba_device clcd_device = {
 547         .dev            = {
 548                 .init_name = "mb:c0",
 549                 .coherent_dma_mask = ~0,
 550                 .platform_data = &clcd_data,
 551         },
 552         .res            = {
 553                 .start  = INTCP_PA_CLCD_BASE,
 554                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
 555                 .flags  = IORESOURCE_MEM,
 556         },
 557         .dma_mask       = ~0,
 558         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
 559         .periphid       = 0,
 560 };
 561
 562 static struct amba_device *amba_devs[] __initdata = {
 563         &mmc_device,
 564         &aaci_device,
 565         &clcd_device,
 566 };
 567
 568 static void __init intcp_init(void)
 569 {
 570         int i;
 571
 572         clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
 573         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 574
 575         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 576                 struct amba_device *d = amba_devs[i];
 577                 amba_device_register(d, &iomem_resource);
 578         }
 579 }
 580
 581 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
 582 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
 583 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 584
 585 static void __init intcp_timer_init(void)
 586 {
 587         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 588         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 589         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 590
 591         sp804_clocksource_init(TIMER2_VA_BASE);
 592         sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
 593 }
 594
 595 static struct sys_timer cp_timer = {
 596         .init           = intcp_timer_init,
 597 };
 598
 599 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 600         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 601         .boot_params    = 0x00000100,
 602         .map_io         = intcp_map_io,
 603         .reserve        = integrator_reserve,
 604         .init_irq       = intcp_init_irq,
 605         .timer          = &cp_timer,
 606         .init_machine   = intcp_init,
 607 MACHINE_END