arch/arm/mach-exynos4/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/sysmmu.h>
  27
  28 static struct clk clk_sclk_hdmi27m = {
  29         .name           = "sclk_hdmi27m",
  30         .rate           = 27000000,
  31 };
  32
  33 static struct clk clk_sclk_hdmiphy = {
  34         .name           = "sclk_hdmiphy",
  35 };
  36
  37 static struct clk clk_sclk_usbphy0 = {
  38         .name           = "sclk_usbphy0",
  39         .rate           = 27000000,
  40 };
  41
  42 static struct clk clk_sclk_usbphy1 = {
  43         .name           = "sclk_usbphy1",
  44 };
  45
  46 static struct clk dummy_apb_pclk = {
  47         .name           = "apb_pclk",
  48         .id             = -1,
  49 };
  50
  51 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  52 {
  53         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
  54 }
  55
  56 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
  57 {
  58         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
  59 }
  60
  61 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
  62 {
  63         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
  64 }
  65
  66 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  67 {
  68         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  69 }
  70
  71 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
  72 {
  73         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
  74 }
  75
  76 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
  77 {
  78         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
  79 }
  80
  81 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
  82 {
  83         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
  84 }
  85
  86 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
  87 {
  88         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
  89 }
  90
  91 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
  92 {
  93         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
  94 }
  95
  96 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
  97 {
  98         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
  99 }
 100
 101 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 102 {
 103         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 104 }
 105
 106 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 107 {
 108         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 109 }
 110
 111 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 112 {
 113         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 114 }
 115
 116 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 117 {
 118         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 119 }
 120
 121 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 124 }
 125
 126 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 127 {
 128         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 129 }
 130
 131 /* Core list of CMU_CPU side */
 132
 133 static struct clksrc_clk clk_mout_apll = {
 134         .clk    = {
 135                 .name           = "mout_apll",
 136         },
 137         .sources        = &clk_src_apll,
 138         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 139 };
 140
 141 static struct clksrc_clk clk_sclk_apll = {
 142         .clk    = {
 143                 .name           = "sclk_apll",
 144                 .parent         = &clk_mout_apll.clk,
 145         },
 146         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 147 };
 148
 149 static struct clksrc_clk clk_mout_epll = {
 150         .clk    = {
 151                 .name           = "mout_epll",
 152         },
 153         .sources        = &clk_src_epll,
 154         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 155 };
 156
 157 static struct clksrc_clk clk_mout_mpll = {
 158         .clk = {
 159                 .name           = "mout_mpll",
 160         },
 161         .sources        = &clk_src_mpll,
 162         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
 163 };
 164
 165 static struct clk *clkset_moutcore_list[] = {
 166         [0] = &clk_mout_apll.clk,
 167         [1] = &clk_mout_mpll.clk,
 168 };
 169
 170 static struct clksrc_sources clkset_moutcore = {
 171         .sources        = clkset_moutcore_list,
 172         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 173 };
 174
 175 static struct clksrc_clk clk_moutcore = {
 176         .clk    = {
 177                 .name           = "moutcore",
 178         },
 179         .sources        = &clkset_moutcore,
 180         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 181 };
 182
 183 static struct clksrc_clk clk_coreclk = {
 184         .clk    = {
 185                 .name           = "core_clk",
 186                 .parent         = &clk_moutcore.clk,
 187         },
 188         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 189 };
 190
 191 static struct clksrc_clk clk_armclk = {
 192         .clk    = {
 193                 .name           = "armclk",
 194                 .parent         = &clk_coreclk.clk,
 195         },
 196 };
 197
 198 static struct clksrc_clk clk_aclk_corem0 = {
 199         .clk    = {
 200                 .name           = "aclk_corem0",
 201                 .parent         = &clk_coreclk.clk,
 202         },
 203         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 204 };
 205
 206 static struct clksrc_clk clk_aclk_cores = {
 207         .clk    = {
 208                 .name           = "aclk_cores",
 209                 .parent         = &clk_coreclk.clk,
 210         },
 211         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 212 };
 213
 214 static struct clksrc_clk clk_aclk_corem1 = {
 215         .clk    = {
 216                 .name           = "aclk_corem1",
 217                 .parent         = &clk_coreclk.clk,
 218         },
 219         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 220 };
 221
 222 static struct clksrc_clk clk_periphclk = {
 223         .clk    = {
 224                 .name           = "periphclk",
 225                 .parent         = &clk_coreclk.clk,
 226         },
 227         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 228 };
 229
 230 /* Core list of CMU_CORE side */
 231
 232 static struct clk *clkset_corebus_list[] = {
 233         [0] = &clk_mout_mpll.clk,
 234         [1] = &clk_sclk_apll.clk,
 235 };
 236
 237 static struct clksrc_sources clkset_mout_corebus = {
 238         .sources        = clkset_corebus_list,
 239         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 240 };
 241
 242 static struct clksrc_clk clk_mout_corebus = {
 243         .clk    = {
 244                 .name           = "mout_corebus",
 245         },
 246         .sources        = &clkset_mout_corebus,
 247         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 248 };
 249
 250 static struct clksrc_clk clk_sclk_dmc = {
 251         .clk    = {
 252                 .name           = "sclk_dmc",
 253                 .parent         = &clk_mout_corebus.clk,
 254         },
 255         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 256 };
 257
 258 static struct clksrc_clk clk_aclk_cored = {
 259         .clk    = {
 260                 .name           = "aclk_cored",
 261                 .parent         = &clk_sclk_dmc.clk,
 262         },
 263         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 264 };
 265
 266 static struct clksrc_clk clk_aclk_corep = {
 267         .clk    = {
 268                 .name           = "aclk_corep",
 269                 .parent         = &clk_aclk_cored.clk,
 270         },
 271         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 272 };
 273
 274 static struct clksrc_clk clk_aclk_acp = {
 275         .clk    = {
 276                 .name           = "aclk_acp",
 277                 .parent         = &clk_mout_corebus.clk,
 278         },
 279         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 280 };
 281
 282 static struct clksrc_clk clk_pclk_acp = {
 283         .clk    = {
 284                 .name           = "pclk_acp",
 285                 .parent         = &clk_aclk_acp.clk,
 286         },
 287         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 288 };
 289
 290 /* Core list of CMU_TOP side */
 291
 292 static struct clk *clkset_aclk_top_list[] = {
 293         [0] = &clk_mout_mpll.clk,
 294         [1] = &clk_sclk_apll.clk,
 295 };
 296
 297 static struct clksrc_sources clkset_aclk = {
 298         .sources        = clkset_aclk_top_list,
 299         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 300 };
 301
 302 static struct clksrc_clk clk_aclk_200 = {
 303         .clk    = {
 304                 .name           = "aclk_200",
 305         },
 306         .sources        = &clkset_aclk,
 307         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 308         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 309 };
 310
 311 static struct clksrc_clk clk_aclk_100 = {
 312         .clk    = {
 313                 .name           = "aclk_100",
 314         },
 315         .sources        = &clkset_aclk,
 316         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 317         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 318 };
 319
 320 static struct clksrc_clk clk_aclk_160 = {
 321         .clk    = {
 322                 .name           = "aclk_160",
 323         },
 324         .sources        = &clkset_aclk,
 325         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 326         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 327 };
 328
 329 static struct clksrc_clk clk_aclk_133 = {
 330         .clk    = {
 331                 .name           = "aclk_133",
 332         },
 333         .sources        = &clkset_aclk,
 334         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 335         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 336 };
 337
 338 static struct clk *clkset_vpllsrc_list[] = {
 339         [0] = &clk_fin_vpll,
 340         [1] = &clk_sclk_hdmi27m,
 341 };
 342
 343 static struct clksrc_sources clkset_vpllsrc = {
 344         .sources        = clkset_vpllsrc_list,
 345         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 346 };
 347
 348 static struct clksrc_clk clk_vpllsrc = {
 349         .clk    = {
 350                 .name           = "vpll_src",
 351                 .enable         = exynos4_clksrc_mask_top_ctrl,
 352                 .ctrlbit        = (1 << 0),
 353         },
 354         .sources        = &clkset_vpllsrc,
 355         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 356 };
 357
 358 static struct clk *clkset_sclk_vpll_list[] = {
 359         [0] = &clk_vpllsrc.clk,
 360         [1] = &clk_fout_vpll,
 361 };
 362
 363 static struct clksrc_sources clkset_sclk_vpll = {
 364         .sources        = clkset_sclk_vpll_list,
 365         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 366 };
 367
 368 static struct clksrc_clk clk_sclk_vpll = {
 369         .clk    = {
 370                 .name           = "sclk_vpll",
 371         },
 372         .sources        = &clkset_sclk_vpll,
 373         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 374 };
 375
 376 static struct clk init_clocks_off[] = {
 377         {
 378                 .name           = "timers",
 379                 .parent         = &clk_aclk_100.clk,
 380                 .enable         = exynos4_clk_ip_peril_ctrl,
 381                 .ctrlbit        = (1<<24),
 382         }, {
 383                 .name           = "csis",
 384                 .devname        = "s5p-mipi-csis.0",
 385                 .enable         = exynos4_clk_ip_cam_ctrl,
 386                 .ctrlbit        = (1 << 4),
 387         }, {
 388                 .name           = "csis",
 389                 .devname        = "s5p-mipi-csis.1",
 390                 .enable         = exynos4_clk_ip_cam_ctrl,
 391                 .ctrlbit        = (1 << 5),
 392         }, {
 393                 .name           = "fimc",
 394                 .devname        = "exynos4-fimc.0",
 395                 .enable         = exynos4_clk_ip_cam_ctrl,
 396                 .ctrlbit        = (1 << 0),
 397         }, {
 398                 .name           = "fimc",
 399                 .devname        = "exynos4-fimc.1",
 400                 .enable         = exynos4_clk_ip_cam_ctrl,
 401                 .ctrlbit        = (1 << 1),
 402         }, {
 403                 .name           = "fimc",
 404                 .devname        = "exynos4-fimc.2",
 405                 .enable         = exynos4_clk_ip_cam_ctrl,
 406                 .ctrlbit        = (1 << 2),
 407         }, {
 408                 .name           = "fimc",
 409                 .devname        = "exynos4-fimc.3",
 410                 .enable         = exynos4_clk_ip_cam_ctrl,
 411                 .ctrlbit        = (1 << 3),
 412         }, {
 413                 .name           = "fimd",
 414                 .devname        = "exynos4-fb.0",
 415                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 416                 .ctrlbit        = (1 << 0),
 417         }, {
 418                 .name           = "fimd",
 419                 .devname        = "exynos4-fb.1",
 420                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 421                 .ctrlbit        = (1 << 0),
 422         }, {
 423                 .name           = "sataphy",
 424                 .parent         = &clk_aclk_133.clk,
 425                 .enable         = exynos4_clk_ip_fsys_ctrl,
 426                 .ctrlbit        = (1 << 3),
 427         }, {
 428                 .name           = "hsmmc",
 429                 .devname        = "s3c-sdhci.0",
 430                 .parent         = &clk_aclk_133.clk,
 431                 .enable         = exynos4_clk_ip_fsys_ctrl,
 432                 .ctrlbit        = (1 << 5),
 433         }, {
 434                 .name           = "hsmmc",
 435                 .devname        = "s3c-sdhci.1",
 436                 .parent         = &clk_aclk_133.clk,
 437                 .enable         = exynos4_clk_ip_fsys_ctrl,
 438                 .ctrlbit        = (1 << 6),
 439         }, {
 440                 .name           = "hsmmc",
 441                 .devname        = "s3c-sdhci.2",
 442                 .parent         = &clk_aclk_133.clk,
 443                 .enable         = exynos4_clk_ip_fsys_ctrl,
 444                 .ctrlbit        = (1 << 7),
 445         }, {
 446                 .name           = "hsmmc",
 447                 .devname        = "s3c-sdhci.3",
 448                 .parent         = &clk_aclk_133.clk,
 449                 .enable         = exynos4_clk_ip_fsys_ctrl,
 450                 .ctrlbit        = (1 << 8),
 451         }, {
 452                 .name           = "dwmmc",
 453                 .parent         = &clk_aclk_133.clk,
 454                 .enable         = exynos4_clk_ip_fsys_ctrl,
 455                 .ctrlbit        = (1 << 9),
 456         }, {
 457                 .name           = "sata",
 458                 .parent         = &clk_aclk_133.clk,
 459                 .enable         = exynos4_clk_ip_fsys_ctrl,
 460                 .ctrlbit        = (1 << 10),
 461         }, {
 462                 .name           = "dma",
 463                 .devname        = "s3c-pl330.0",
 464                 .enable         = exynos4_clk_ip_fsys_ctrl,
 465                 .ctrlbit        = (1 << 0),
 466         }, {
 467                 .name           = "dma",
 468                 .devname        = "s3c-pl330.1",
 469                 .enable         = exynos4_clk_ip_fsys_ctrl,
 470                 .ctrlbit        = (1 << 1),
 471         }, {
 472                 .name           = "adc",
 473                 .enable         = exynos4_clk_ip_peril_ctrl,
 474                 .ctrlbit        = (1 << 15),
 475         }, {
 476                 .name           = "keypad",
 477                 .enable         = exynos4_clk_ip_perir_ctrl,
 478                 .ctrlbit        = (1 << 16),
 479         }, {
 480                 .name           = "rtc",
 481                 .enable         = exynos4_clk_ip_perir_ctrl,
 482                 .ctrlbit        = (1 << 15),
 483         }, {
 484                 .name           = "watchdog",
 485                 .parent         = &clk_aclk_100.clk,
 486                 .enable         = exynos4_clk_ip_perir_ctrl,
 487                 .ctrlbit        = (1 << 14),
 488         }, {
 489                 .name           = "usbhost",
 490                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 491                 .ctrlbit        = (1 << 12),
 492         }, {
 493                 .name           = "otg",
 494                 .enable         = exynos4_clk_ip_fsys_ctrl,
 495                 .ctrlbit        = (1 << 13),
 496         }, {
 497                 .name           = "spi",
 498                 .devname        = "s3c64xx-spi.0",
 499                 .enable         = exynos4_clk_ip_peril_ctrl,
 500                 .ctrlbit        = (1 << 16),
 501         }, {
 502                 .name           = "spi",
 503                 .devname        = "s3c64xx-spi.1",
 504                 .enable         = exynos4_clk_ip_peril_ctrl,
 505                 .ctrlbit        = (1 << 17),
 506         }, {
 507                 .name           = "spi",
 508                 .devname        = "s3c64xx-spi.2",
 509                 .enable         = exynos4_clk_ip_peril_ctrl,
 510                 .ctrlbit        = (1 << 18),
 511         }, {
 512                 .name           = "iis",
 513                 .devname        = "samsung-i2s.0",
 514                 .enable         = exynos4_clk_ip_peril_ctrl,
 515                 .ctrlbit        = (1 << 19),
 516         }, {
 517                 .name           = "iis",
 518                 .devname        = "samsung-i2s.1",
 519                 .enable         = exynos4_clk_ip_peril_ctrl,
 520                 .ctrlbit        = (1 << 20),
 521         }, {
 522                 .name           = "iis",
 523                 .devname        = "samsung-i2s.2",
 524                 .enable         = exynos4_clk_ip_peril_ctrl,
 525                 .ctrlbit        = (1 << 21),
 526         }, {
 527                 .name           = "ac97",
 528                 .id             = -1,
 529                 .enable         = exynos4_clk_ip_peril_ctrl,
 530                 .ctrlbit        = (1 << 27),
 531         }, {
 532                 .name           = "fimg2d",
 533                 .enable         = exynos4_clk_ip_image_ctrl,
 534                 .ctrlbit        = (1 << 0),
 535         }, {
 536                 .name           = "mfc",
 537                 .devname        = "s5p-mfc",
 538                 .enable         = exynos4_clk_ip_mfc_ctrl,
 539                 .ctrlbit        = (1 << 0),
 540         }, {
 541                 .name           = "i2c",
 542                 .devname        = "s3c2440-i2c.0",
 543                 .parent         = &clk_aclk_100.clk,
 544                 .enable         = exynos4_clk_ip_peril_ctrl,
 545                 .ctrlbit        = (1 << 6),
 546         }, {
 547                 .name           = "i2c",
 548                 .devname        = "s3c2440-i2c.1",
 549                 .parent         = &clk_aclk_100.clk,
 550                 .enable         = exynos4_clk_ip_peril_ctrl,
 551                 .ctrlbit        = (1 << 7),
 552         }, {
 553                 .name           = "i2c",
 554                 .devname        = "s3c2440-i2c.2",
 555                 .parent         = &clk_aclk_100.clk,
 556                 .enable         = exynos4_clk_ip_peril_ctrl,
 557                 .ctrlbit        = (1 << 8),
 558         }, {
 559                 .name           = "i2c",
 560                 .devname        = "s3c2440-i2c.3",
 561                 .parent         = &clk_aclk_100.clk,
 562                 .enable         = exynos4_clk_ip_peril_ctrl,
 563                 .ctrlbit        = (1 << 9),
 564         }, {
 565                 .name           = "i2c",
 566                 .devname        = "s3c2440-i2c.4",
 567                 .parent         = &clk_aclk_100.clk,
 568                 .enable         = exynos4_clk_ip_peril_ctrl,
 569                 .ctrlbit        = (1 << 10),
 570         }, {
 571                 .name           = "i2c",
 572                 .devname        = "s3c2440-i2c.5",
 573                 .parent         = &clk_aclk_100.clk,
 574                 .enable         = exynos4_clk_ip_peril_ctrl,
 575                 .ctrlbit        = (1 << 11),
 576         }, {
 577                 .name           = "i2c",
 578                 .devname        = "s3c2440-i2c.6",
 579                 .parent         = &clk_aclk_100.clk,
 580                 .enable         = exynos4_clk_ip_peril_ctrl,
 581                 .ctrlbit        = (1 << 12),
 582         }, {
 583                 .name           = "i2c",
 584                 .devname        = "s3c2440-i2c.7",
 585                 .parent         = &clk_aclk_100.clk,
 586                 .enable         = exynos4_clk_ip_peril_ctrl,
 587                 .ctrlbit        = (1 << 13),
 588         }, {
 589                 .name           = "SYSMMU_MDMA",
 590                 .enable         = exynos4_clk_ip_image_ctrl,
 591                 .ctrlbit        = (1 << 5),
 592         }, {
 593                 .name           = "SYSMMU_FIMC0",
 594                 .enable         = exynos4_clk_ip_cam_ctrl,
 595                 .ctrlbit        = (1 << 7),
 596         }, {
 597                 .name           = "SYSMMU_FIMC1",
 598                 .enable         = exynos4_clk_ip_cam_ctrl,
 599                 .ctrlbit        = (1 << 8),
 600         }, {
 601                 .name           = "SYSMMU_FIMC2",
 602                 .enable         = exynos4_clk_ip_cam_ctrl,
 603                 .ctrlbit        = (1 << 9),
 604         }, {
 605                 .name           = "SYSMMU_FIMC3",
 606                 .enable         = exynos4_clk_ip_cam_ctrl,
 607                 .ctrlbit        = (1 << 10),
 608         }, {
 609                 .name           = "SYSMMU_JPEG",
 610                 .enable         = exynos4_clk_ip_cam_ctrl,
 611                 .ctrlbit        = (1 << 11),
 612         }, {
 613                 .name           = "SYSMMU_FIMD0",
 614                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 615                 .ctrlbit        = (1 << 4),
 616         }, {
 617                 .name           = "SYSMMU_FIMD1",
 618                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 619                 .ctrlbit        = (1 << 4),
 620         }, {
 621                 .name           = "SYSMMU_PCIe",
 622                 .enable         = exynos4_clk_ip_fsys_ctrl,
 623                 .ctrlbit        = (1 << 18),
 624         }, {
 625                 .name           = "SYSMMU_G2D",
 626                 .enable         = exynos4_clk_ip_image_ctrl,
 627                 .ctrlbit        = (1 << 3),
 628         }, {
 629                 .name           = "SYSMMU_ROTATOR",
 630                 .enable         = exynos4_clk_ip_image_ctrl,
 631                 .ctrlbit        = (1 << 4),
 632         }, {
 633                 .name           = "SYSMMU_TV",
 634                 .enable         = exynos4_clk_ip_tv_ctrl,
 635                 .ctrlbit        = (1 << 4),
 636         }, {
 637                 .name           = "SYSMMU_MFC_L",
 638                 .enable         = exynos4_clk_ip_mfc_ctrl,
 639                 .ctrlbit        = (1 << 1),
 640         }, {
 641                 .name           = "SYSMMU_MFC_R",
 642                 .enable         = exynos4_clk_ip_mfc_ctrl,
 643                 .ctrlbit        = (1 << 2),
 644         }
 645 };
 646
 647 static struct clk init_clocks[] = {
 648         {
 649                 .name           = "uart",
 650                 .devname        = "s5pv210-uart.0",
 651                 .enable         = exynos4_clk_ip_peril_ctrl,
 652                 .ctrlbit        = (1 << 0),
 653         }, {
 654                 .name           = "uart",
 655                 .devname        = "s5pv210-uart.1",
 656                 .enable         = exynos4_clk_ip_peril_ctrl,
 657                 .ctrlbit        = (1 << 1),
 658         }, {
 659                 .name           = "uart",
 660                 .devname        = "s5pv210-uart.2",
 661                 .enable         = exynos4_clk_ip_peril_ctrl,
 662                 .ctrlbit        = (1 << 2),
 663         }, {
 664                 .name           = "uart",
 665                 .devname        = "s5pv210-uart.3",
 666                 .enable         = exynos4_clk_ip_peril_ctrl,
 667                 .ctrlbit        = (1 << 3),
 668         }, {
 669                 .name           = "uart",
 670                 .devname        = "s5pv210-uart.4",
 671                 .enable         = exynos4_clk_ip_peril_ctrl,
 672                 .ctrlbit        = (1 << 4),
 673         }, {
 674                 .name           = "uart",
 675                 .devname        = "s5pv210-uart.5",
 676                 .enable         = exynos4_clk_ip_peril_ctrl,
 677                 .ctrlbit        = (1 << 5),
 678         }
 679 };
 680
 681 static struct clk *clkset_group_list[] = {
 682         [0] = &clk_ext_xtal_mux,
 683         [1] = &clk_xusbxti,
 684         [2] = &clk_sclk_hdmi27m,
 685         [3] = &clk_sclk_usbphy0,
 686         [4] = &clk_sclk_usbphy1,
 687         [5] = &clk_sclk_hdmiphy,
 688         [6] = &clk_mout_mpll.clk,
 689         [7] = &clk_mout_epll.clk,
 690         [8] = &clk_sclk_vpll.clk,
 691 };
 692
 693 static struct clksrc_sources clkset_group = {
 694         .sources        = clkset_group_list,
 695         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 696 };
 697
 698 static struct clk *clkset_mout_g2d0_list[] = {
 699         [0] = &clk_mout_mpll.clk,
 700         [1] = &clk_sclk_apll.clk,
 701 };
 702
 703 static struct clksrc_sources clkset_mout_g2d0 = {
 704         .sources        = clkset_mout_g2d0_list,
 705         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 706 };
 707
 708 static struct clksrc_clk clk_mout_g2d0 = {
 709         .clk    = {
 710                 .name           = "mout_g2d0",
 711         },
 712         .sources        = &clkset_mout_g2d0,
 713         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 714 };
 715
 716 static struct clk *clkset_mout_g2d1_list[] = {
 717         [0] = &clk_mout_epll.clk,
 718         [1] = &clk_sclk_vpll.clk,
 719 };
 720
 721 static struct clksrc_sources clkset_mout_g2d1 = {
 722         .sources        = clkset_mout_g2d1_list,
 723         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 724 };
 725
 726 static struct clksrc_clk clk_mout_g2d1 = {
 727         .clk    = {
 728                 .name           = "mout_g2d1",
 729         },
 730         .sources        = &clkset_mout_g2d1,
 731         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 732 };
 733
 734 static struct clk *clkset_mout_g2d_list[] = {
 735         [0] = &clk_mout_g2d0.clk,
 736         [1] = &clk_mout_g2d1.clk,
 737 };
 738
 739 static struct clksrc_sources clkset_mout_g2d = {
 740         .sources        = clkset_mout_g2d_list,
 741         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 742 };
 743
 744 static struct clk *clkset_mout_mfc0_list[] = {
 745         [0] = &clk_mout_mpll.clk,
 746         [1] = &clk_sclk_apll.clk,
 747 };
 748
 749 static struct clksrc_sources clkset_mout_mfc0 = {
 750         .sources        = clkset_mout_mfc0_list,
 751         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
 752 };
 753
 754 static struct clksrc_clk clk_mout_mfc0 = {
 755         .clk    = {
 756                 .name           = "mout_mfc0",
 757         },
 758         .sources        = &clkset_mout_mfc0,
 759         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
 760 };
 761
 762 static struct clk *clkset_mout_mfc1_list[] = {
 763         [0] = &clk_mout_epll.clk,
 764         [1] = &clk_sclk_vpll.clk,
 765 };
 766
 767 static struct clksrc_sources clkset_mout_mfc1 = {
 768         .sources        = clkset_mout_mfc1_list,
 769         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
 770 };
 771
 772 static struct clksrc_clk clk_mout_mfc1 = {
 773         .clk    = {
 774                 .name           = "mout_mfc1",
 775         },
 776         .sources        = &clkset_mout_mfc1,
 777         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
 778 };
 779
 780 static struct clk *clkset_mout_mfc_list[] = {
 781         [0] = &clk_mout_mfc0.clk,
 782         [1] = &clk_mout_mfc1.clk,
 783 };
 784
 785 static struct clksrc_sources clkset_mout_mfc = {
 786         .sources        = clkset_mout_mfc_list,
 787         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 788 };
 789
 790 static struct clksrc_clk clk_dout_mmc0 = {
 791         .clk            = {
 792                 .name           = "dout_mmc0",
 793         },
 794         .sources = &clkset_group,
 795         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 796         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 797 };
 798
 799 static struct clksrc_clk clk_dout_mmc1 = {
 800         .clk            = {
 801                 .name           = "dout_mmc1",
 802         },
 803         .sources = &clkset_group,
 804         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 805         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 806 };
 807
 808 static struct clksrc_clk clk_dout_mmc2 = {
 809         .clk            = {
 810                 .name           = "dout_mmc2",
 811         },
 812         .sources = &clkset_group,
 813         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 814         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 815 };
 816
 817 static struct clksrc_clk clk_dout_mmc3 = {
 818         .clk            = {
 819                 .name           = "dout_mmc3",
 820         },
 821         .sources = &clkset_group,
 822         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
 823         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 824 };
 825
 826 static struct clksrc_clk clk_dout_mmc4 = {
 827         .clk            = {
 828                 .name           = "dout_mmc4",
 829         },
 830         .sources = &clkset_group,
 831         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
 832         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 833 };
 834
 835 static struct clksrc_clk clksrcs[] = {
 836         {
 837                 .clk    = {
 838                         .name           = "uclk1",
 839                         .devname        = "s5pv210-uart.0",
 840                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 841                         .ctrlbit        = (1 << 0),
 842                 },
 843                 .sources = &clkset_group,
 844                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
 845                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
 846         }, {
 847                 .clk            = {
 848                         .name           = "uclk1",
 849                         .devname        = "s5pv210-uart.1",
 850                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 851                         .ctrlbit        = (1 << 4),
 852                 },
 853                 .sources = &clkset_group,
 854                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
 855                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
 856         }, {
 857                 .clk            = {
 858                         .name           = "uclk1",
 859                         .devname        = "s5pv210-uart.2",
 860                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 861                         .ctrlbit        = (1 << 8),
 862                 },
 863                 .sources = &clkset_group,
 864                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
 865                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
 866         }, {
 867                 .clk            = {
 868                         .name           = "uclk1",
 869                         .devname        = "s5pv210-uart.3",
 870                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 871                         .ctrlbit        = (1 << 12),
 872                 },
 873                 .sources = &clkset_group,
 874                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
 875                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 876         }, {
 877                 .clk            = {
 878                         .name           = "sclk_pwm",
 879                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 880                         .ctrlbit        = (1 << 24),
 881                 },
 882                 .sources = &clkset_group,
 883                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
 884                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 885         }, {
 886                 .clk            = {
 887                         .name           = "sclk_csis",
 888                         .devname        = "s5p-mipi-csis.0",
 889                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 890                         .ctrlbit        = (1 << 24),
 891                 },
 892                 .sources = &clkset_group,
 893                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
 894                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
 895         }, {
 896                 .clk            = {
 897                         .name           = "sclk_csis",
 898                         .devname        = "s5p-mipi-csis.1",
 899                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 900                         .ctrlbit        = (1 << 28),
 901                 },
 902                 .sources = &clkset_group,
 903                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
 904                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
 905         }, {
 906                 .clk            = {
 907                         .name           = "sclk_cam",
 908                         .devname        = "exynos4-fimc.0",
 909                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 910                         .ctrlbit        = (1 << 16),
 911                 },
 912                 .sources = &clkset_group,
 913                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
 914                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
 915         }, {
 916                 .clk            = {
 917                         .name           = "sclk_cam",
 918                         .devname        = "exynos4-fimc.1",
 919                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 920                         .ctrlbit        = (1 << 20),
 921                 },
 922                 .sources = &clkset_group,
 923                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
 924                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
 925         }, {
 926                 .clk            = {
 927                         .name           = "sclk_fimc",
 928                         .devname        = "exynos4-fimc.0",
 929                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 930                         .ctrlbit        = (1 << 0),
 931                 },
 932                 .sources = &clkset_group,
 933                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
 934                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
 935         }, {
 936                 .clk            = {
 937                         .name           = "sclk_fimc",
 938                         .devname        = "exynos4-fimc.1",
 939                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 940                         .ctrlbit        = (1 << 4),
 941                 },
 942                 .sources = &clkset_group,
 943                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
 944                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
 945         }, {
 946                 .clk            = {
 947                         .name           = "sclk_fimc",
 948                         .devname        = "exynos4-fimc.2",
 949                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 950                         .ctrlbit        = (1 << 8),
 951                 },
 952                 .sources = &clkset_group,
 953                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
 954                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
 955         }, {
 956                 .clk            = {
 957                         .name           = "sclk_fimc",
 958                         .devname        = "exynos4-fimc.3",
 959                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 960                         .ctrlbit        = (1 << 12),
 961                 },
 962                 .sources = &clkset_group,
 963                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
 964                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
 965         }, {
 966                 .clk            = {
 967                         .name           = "sclk_fimd",
 968                         .devname        = "exynos4-fb.0",
 969                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
 970                         .ctrlbit        = (1 << 0),
 971                 },
 972                 .sources = &clkset_group,
 973                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
 974                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
 975         }, {
 976                 .clk            = {
 977                         .name           = "sclk_fimd",
 978                         .devname        = "exynos4-fb.1",
 979                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
 980                         .ctrlbit        = (1 << 0),
 981                 },
 982                 .sources = &clkset_group,
 983                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
 984                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
 985         }, {
 986                 .clk            = {
 987                         .name           = "sclk_sata",
 988                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 989                         .ctrlbit        = (1 << 24),
 990                 },
 991                 .sources = &clkset_mout_corebus,
 992                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
 993                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
 994         }, {
 995                 .clk            = {
 996                         .name           = "sclk_spi",
 997                         .devname        = "s3c64xx-spi.0",
 998                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 999                         .ctrlbit        = (1 << 16),
1000                 },
1001                 .sources = &clkset_group,
1002                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1003                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1004         }, {
1005                 .clk            = {
1006                         .name           = "sclk_spi",
1007                         .devname        = "s3c64xx-spi.1",
1008                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1009                         .ctrlbit        = (1 << 20),
1010                 },
1011                 .sources = &clkset_group,
1012                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1013                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1014         }, {
1015                 .clk            = {
1016                         .name           = "sclk_spi",
1017                         .devname        = "s3c64xx-spi.2",
1018                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1019                         .ctrlbit        = (1 << 24),
1020                 },
1021                 .sources = &clkset_group,
1022                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1023                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1024         }, {
1025                 .clk            = {
1026                         .name           = "sclk_fimg2d",
1027                 },
1028                 .sources = &clkset_mout_g2d,
1029                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1030                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1031         }, {
1032                 .clk            = {
1033                         .name           = "sclk_mfc",
1034                         .devname        = "s5p-mfc",
1035                 },
1036                 .sources = &clkset_mout_mfc,
1037                 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1038                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1039         }, {
1040                 .clk            = {
1041                         .name           = "sclk_mmc",
1042                         .devname        = "s3c-sdhci.0",
1043                         .parent         = &clk_dout_mmc0.clk,
1044                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1045                         .ctrlbit        = (1 << 0),
1046                 },
1047                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1048         }, {
1049                 .clk            = {
1050                         .name           = "sclk_mmc",
1051                         .devname        = "s3c-sdhci.1",
1052                         .parent         = &clk_dout_mmc1.clk,
1053                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1054                         .ctrlbit        = (1 << 4),
1055                 },
1056                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1057         }, {
1058                 .clk            = {
1059                         .name           = "sclk_mmc",
1060                         .devname        = "s3c-sdhci.2",
1061                         .parent         = &clk_dout_mmc2.clk,
1062                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1063                         .ctrlbit        = (1 << 8),
1064                 },
1065                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1066         }, {
1067                 .clk            = {
1068                         .name           = "sclk_mmc",
1069                         .devname        = "s3c-sdhci.3",
1070                         .parent         = &clk_dout_mmc3.clk,
1071                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1072                         .ctrlbit        = (1 << 12),
1073                 },
1074                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1075         }, {
1076                 .clk            = {
1077                         .name           = "sclk_dwmmc",
1078                         .parent         = &clk_dout_mmc4.clk,
1079                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1080                         .ctrlbit        = (1 << 16),
1081                 },
1082                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1083         }
1084 };
1085
1086 /* Clock initialization code */
1087 static struct clksrc_clk *sysclks[] = {
1088         &clk_mout_apll,
1089         &clk_sclk_apll,
1090         &clk_mout_epll,
1091         &clk_mout_mpll,
1092         &clk_moutcore,
1093         &clk_coreclk,
1094         &clk_armclk,
1095         &clk_aclk_corem0,
1096         &clk_aclk_cores,
1097         &clk_aclk_corem1,
1098         &clk_periphclk,
1099         &clk_mout_corebus,
1100         &clk_sclk_dmc,
1101         &clk_aclk_cored,
1102         &clk_aclk_corep,
1103         &clk_aclk_acp,
1104         &clk_pclk_acp,
1105         &clk_vpllsrc,
1106         &clk_sclk_vpll,
1107         &clk_aclk_200,
1108         &clk_aclk_100,
1109         &clk_aclk_160,
1110         &clk_aclk_133,
1111         &clk_dout_mmc0,
1112         &clk_dout_mmc1,
1113         &clk_dout_mmc2,
1114         &clk_dout_mmc3,
1115         &clk_dout_mmc4,
1116         &clk_mout_mfc0,
1117         &clk_mout_mfc1,
1118 };
1119
1120 static int xtal_rate;
1121
1122 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1123 {
1124         return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1125 }
1126
1127 static struct clk_ops exynos4_fout_apll_ops = {
1128         .get_rate = exynos4_fout_apll_get_rate,
1129 };
1130
1131 void __init_or_cpufreq exynos4_setup_clocks(void)
1132 {
1133         struct clk *xtal_clk;
1134         unsigned long apll;
1135         unsigned long mpll;
1136         unsigned long epll;
1137         unsigned long vpll;
1138         unsigned long vpllsrc;
1139         unsigned long xtal;
1140         unsigned long armclk;
1141         unsigned long sclk_dmc;
1142         unsigned long aclk_200;
1143         unsigned long aclk_100;
1144         unsigned long aclk_160;
1145         unsigned long aclk_133;
1146         unsigned int ptr;
1147
1148         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1149
1150         xtal_clk = clk_get(NULL, "xtal");
1151         BUG_ON(IS_ERR(xtal_clk));
1152
1153         xtal = clk_get_rate(xtal_clk);
1154
1155         xtal_rate = xtal;
1156
1157         clk_put(xtal_clk);
1158
1159         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1160
1161         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1162         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1163         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1164                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1165
1166         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1167         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1168                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
1169
1170         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1171         clk_fout_mpll.rate = mpll;
1172         clk_fout_epll.rate = epll;
1173         clk_fout_vpll.rate = vpll;
1174
1175         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1176                         apll, mpll, epll, vpll);
1177
1178         armclk = clk_get_rate(&clk_armclk.clk);
1179         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1180
1181         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1182         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1183         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1184         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1185
1186         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1187                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1188                         armclk, sclk_dmc, aclk_200,
1189                         aclk_100, aclk_160, aclk_133);
1190
1191         clk_f.rate = armclk;
1192         clk_h.rate = sclk_dmc;
1193         clk_p.rate = aclk_100;
1194
1195         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1196                 s3c_set_clksrc(&clksrcs[ptr], true);
1197 }
1198
1199 static struct clk *clks[] __initdata = {
1200         /* Nothing here yet */
1201 };
1202
1203 void __init exynos4_register_clocks(void)
1204 {
1205         int ptr;
1206
1207         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1208
1209         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1210                 s3c_register_clksrc(sysclks[ptr], 1);
1211
1212         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1213         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1214
1215         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1216         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1217
1218         s3c24xx_register_clock(&dummy_apb_pclk);
1219
1220         s3c_pwmclk_init();
1221 }