arch/arm/mach-exynos4/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/sysmmu.h>
  27
  28 static struct clk clk_sclk_hdmi27m = {
  29         .name           = "sclk_hdmi27m",
  30         .rate           = 27000000,
  31 };
  32
  33 static struct clk clk_sclk_hdmiphy = {
  34         .name           = "sclk_hdmiphy",
  35 };
  36
  37 static struct clk clk_sclk_usbphy0 = {
  38         .name           = "sclk_usbphy0",
  39         .rate           = 27000000,
  40 };
  41
  42 static struct clk clk_sclk_usbphy1 = {
  43         .name           = "sclk_usbphy1",
  44 };
  45
  46 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  47 {
  48         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
  49 }
  50
  51 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
  52 {
  53         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
  54 }
  55
  56 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
  57 {
  58         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
  59 }
  60
  61 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  62 {
  63         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  64 }
  65
  66 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
  67 {
  68         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
  69 }
  70
  71 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
  72 {
  73         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
  74 }
  75
  76 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
  77 {
  78         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
  79 }
  80
  81 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
  82 {
  83         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
  84 }
  85
  86 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
  87 {
  88         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
  89 }
  90
  91 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
  92 {
  93         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
  94 }
  95
  96 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
  97 {
  98         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
  99 }
 100
 101 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 102 {
 103         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 104 }
 105
 106 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 107 {
 108         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 109 }
 110
 111 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 112 {
 113         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 114 }
 115
 116 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 117 {
 118         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 119 }
 120
 121 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 124 }
 125
 126 /* Core list of CMU_CPU side */
 127
 128 static struct clksrc_clk clk_mout_apll = {
 129         .clk    = {
 130                 .name           = "mout_apll",
 131         },
 132         .sources        = &clk_src_apll,
 133         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 134 };
 135
 136 static struct clksrc_clk clk_sclk_apll = {
 137         .clk    = {
 138                 .name           = "sclk_apll",
 139                 .parent         = &clk_mout_apll.clk,
 140         },
 141         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 142 };
 143
 144 static struct clksrc_clk clk_mout_epll = {
 145         .clk    = {
 146                 .name           = "mout_epll",
 147         },
 148         .sources        = &clk_src_epll,
 149         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 150 };
 151
 152 static struct clksrc_clk clk_mout_mpll = {
 153         .clk = {
 154                 .name           = "mout_mpll",
 155         },
 156         .sources        = &clk_src_mpll,
 157         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
 158 };
 159
 160 static struct clk *clkset_moutcore_list[] = {
 161         [0] = &clk_mout_apll.clk,
 162         [1] = &clk_mout_mpll.clk,
 163 };
 164
 165 static struct clksrc_sources clkset_moutcore = {
 166         .sources        = clkset_moutcore_list,
 167         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 168 };
 169
 170 static struct clksrc_clk clk_moutcore = {
 171         .clk    = {
 172                 .name           = "moutcore",
 173         },
 174         .sources        = &clkset_moutcore,
 175         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 176 };
 177
 178 static struct clksrc_clk clk_coreclk = {
 179         .clk    = {
 180                 .name           = "core_clk",
 181                 .parent         = &clk_moutcore.clk,
 182         },
 183         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 184 };
 185
 186 static struct clksrc_clk clk_armclk = {
 187         .clk    = {
 188                 .name           = "armclk",
 189                 .parent         = &clk_coreclk.clk,
 190         },
 191 };
 192
 193 static struct clksrc_clk clk_aclk_corem0 = {
 194         .clk    = {
 195                 .name           = "aclk_corem0",
 196                 .parent         = &clk_coreclk.clk,
 197         },
 198         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 199 };
 200
 201 static struct clksrc_clk clk_aclk_cores = {
 202         .clk    = {
 203                 .name           = "aclk_cores",
 204                 .parent         = &clk_coreclk.clk,
 205         },
 206         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 207 };
 208
 209 static struct clksrc_clk clk_aclk_corem1 = {
 210         .clk    = {
 211                 .name           = "aclk_corem1",
 212                 .parent         = &clk_coreclk.clk,
 213         },
 214         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 215 };
 216
 217 static struct clksrc_clk clk_periphclk = {
 218         .clk    = {
 219                 .name           = "periphclk",
 220                 .parent         = &clk_coreclk.clk,
 221         },
 222         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 223 };
 224
 225 /* Core list of CMU_CORE side */
 226
 227 static struct clk *clkset_corebus_list[] = {
 228         [0] = &clk_mout_mpll.clk,
 229         [1] = &clk_sclk_apll.clk,
 230 };
 231
 232 static struct clksrc_sources clkset_mout_corebus = {
 233         .sources        = clkset_corebus_list,
 234         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 235 };
 236
 237 static struct clksrc_clk clk_mout_corebus = {
 238         .clk    = {
 239                 .name           = "mout_corebus",
 240         },
 241         .sources        = &clkset_mout_corebus,
 242         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 243 };
 244
 245 static struct clksrc_clk clk_sclk_dmc = {
 246         .clk    = {
 247                 .name           = "sclk_dmc",
 248                 .parent         = &clk_mout_corebus.clk,
 249         },
 250         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 251 };
 252
 253 static struct clksrc_clk clk_aclk_cored = {
 254         .clk    = {
 255                 .name           = "aclk_cored",
 256                 .parent         = &clk_sclk_dmc.clk,
 257         },
 258         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 259 };
 260
 261 static struct clksrc_clk clk_aclk_corep = {
 262         .clk    = {
 263                 .name           = "aclk_corep",
 264                 .parent         = &clk_aclk_cored.clk,
 265         },
 266         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 267 };
 268
 269 static struct clksrc_clk clk_aclk_acp = {
 270         .clk    = {
 271                 .name           = "aclk_acp",
 272                 .parent         = &clk_mout_corebus.clk,
 273         },
 274         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 275 };
 276
 277 static struct clksrc_clk clk_pclk_acp = {
 278         .clk    = {
 279                 .name           = "pclk_acp",
 280                 .parent         = &clk_aclk_acp.clk,
 281         },
 282         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 283 };
 284
 285 /* Core list of CMU_TOP side */
 286
 287 static struct clk *clkset_aclk_top_list[] = {
 288         [0] = &clk_mout_mpll.clk,
 289         [1] = &clk_sclk_apll.clk,
 290 };
 291
 292 static struct clksrc_sources clkset_aclk = {
 293         .sources        = clkset_aclk_top_list,
 294         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 295 };
 296
 297 static struct clksrc_clk clk_aclk_200 = {
 298         .clk    = {
 299                 .name           = "aclk_200",
 300         },
 301         .sources        = &clkset_aclk,
 302         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 303         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 304 };
 305
 306 static struct clksrc_clk clk_aclk_100 = {
 307         .clk    = {
 308                 .name           = "aclk_100",
 309         },
 310         .sources        = &clkset_aclk,
 311         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 312         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 313 };
 314
 315 static struct clksrc_clk clk_aclk_160 = {
 316         .clk    = {
 317                 .name           = "aclk_160",
 318         },
 319         .sources        = &clkset_aclk,
 320         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 321         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 322 };
 323
 324 static struct clksrc_clk clk_aclk_133 = {
 325         .clk    = {
 326                 .name           = "aclk_133",
 327         },
 328         .sources        = &clkset_aclk,
 329         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 330         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 331 };
 332
 333 static struct clk *clkset_vpllsrc_list[] = {
 334         [0] = &clk_fin_vpll,
 335         [1] = &clk_sclk_hdmi27m,
 336 };
 337
 338 static struct clksrc_sources clkset_vpllsrc = {
 339         .sources        = clkset_vpllsrc_list,
 340         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 341 };
 342
 343 static struct clksrc_clk clk_vpllsrc = {
 344         .clk    = {
 345                 .name           = "vpll_src",
 346                 .enable         = exynos4_clksrc_mask_top_ctrl,
 347                 .ctrlbit        = (1 << 0),
 348         },
 349         .sources        = &clkset_vpllsrc,
 350         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 351 };
 352
 353 static struct clk *clkset_sclk_vpll_list[] = {
 354         [0] = &clk_vpllsrc.clk,
 355         [1] = &clk_fout_vpll,
 356 };
 357
 358 static struct clksrc_sources clkset_sclk_vpll = {
 359         .sources        = clkset_sclk_vpll_list,
 360         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 361 };
 362
 363 static struct clksrc_clk clk_sclk_vpll = {
 364         .clk    = {
 365                 .name           = "sclk_vpll",
 366         },
 367         .sources        = &clkset_sclk_vpll,
 368         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 369 };
 370
 371 static struct clk init_clocks_off[] = {
 372         {
 373                 .name           = "timers",
 374                 .parent         = &clk_aclk_100.clk,
 375                 .enable         = exynos4_clk_ip_peril_ctrl,
 376                 .ctrlbit        = (1<<24),
 377         }, {
 378                 .name           = "csis",
 379                 .devname        = "s5p-mipi-csis.0",
 380                 .enable         = exynos4_clk_ip_cam_ctrl,
 381                 .ctrlbit        = (1 << 4),
 382         }, {
 383                 .name           = "csis",
 384                 .devname        = "s5p-mipi-csis.1",
 385                 .enable         = exynos4_clk_ip_cam_ctrl,
 386                 .ctrlbit        = (1 << 5),
 387         }, {
 388                 .name           = "fimc",
 389                 .devname        = "exynos4-fimc.0",
 390                 .enable         = exynos4_clk_ip_cam_ctrl,
 391                 .ctrlbit        = (1 << 0),
 392         }, {
 393                 .name           = "fimc",
 394                 .devname        = "exynos4-fimc.1",
 395                 .enable         = exynos4_clk_ip_cam_ctrl,
 396                 .ctrlbit        = (1 << 1),
 397         }, {
 398                 .name           = "fimc",
 399                 .devname        = "exynos4-fimc.2",
 400                 .enable         = exynos4_clk_ip_cam_ctrl,
 401                 .ctrlbit        = (1 << 2),
 402         }, {
 403                 .name           = "fimc",
 404                 .devname        = "exynos4-fimc.3",
 405                 .enable         = exynos4_clk_ip_cam_ctrl,
 406                 .ctrlbit        = (1 << 3),
 407         }, {
 408                 .name           = "fimd",
 409                 .devname        = "exynos4-fb.0",
 410                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 411                 .ctrlbit        = (1 << 0),
 412         }, {
 413                 .name           = "fimd",
 414                 .devname        = "exynos4-fb.1",
 415                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 416                 .ctrlbit        = (1 << 0),
 417         }, {
 418                 .name           = "sataphy",
 419                 .parent         = &clk_aclk_133.clk,
 420                 .enable         = exynos4_clk_ip_fsys_ctrl,
 421                 .ctrlbit        = (1 << 3),
 422         }, {
 423                 .name           = "hsmmc",
 424                 .devname        = "s3c-sdhci.0",
 425                 .parent         = &clk_aclk_133.clk,
 426                 .enable         = exynos4_clk_ip_fsys_ctrl,
 427                 .ctrlbit        = (1 << 5),
 428         }, {
 429                 .name           = "hsmmc",
 430                 .devname        = "s3c-sdhci.1",
 431                 .parent         = &clk_aclk_133.clk,
 432                 .enable         = exynos4_clk_ip_fsys_ctrl,
 433                 .ctrlbit        = (1 << 6),
 434         }, {
 435                 .name           = "hsmmc",
 436                 .devname        = "s3c-sdhci.2",
 437                 .parent         = &clk_aclk_133.clk,
 438                 .enable         = exynos4_clk_ip_fsys_ctrl,
 439                 .ctrlbit        = (1 << 7),
 440         }, {
 441                 .name           = "hsmmc",
 442                 .devname        = "s3c-sdhci.3",
 443                 .parent         = &clk_aclk_133.clk,
 444                 .enable         = exynos4_clk_ip_fsys_ctrl,
 445                 .ctrlbit        = (1 << 8),
 446         }, {
 447                 .name           = "dwmmc",
 448                 .parent         = &clk_aclk_133.clk,
 449                 .enable         = exynos4_clk_ip_fsys_ctrl,
 450                 .ctrlbit        = (1 << 9),
 451         }, {
 452                 .name           = "sata",
 453                 .parent         = &clk_aclk_133.clk,
 454                 .enable         = exynos4_clk_ip_fsys_ctrl,
 455                 .ctrlbit        = (1 << 10),
 456         }, {
 457                 .name           = "pdma",
 458                 .devname        = "s3c-pl330.0",
 459                 .enable         = exynos4_clk_ip_fsys_ctrl,
 460                 .ctrlbit        = (1 << 0),
 461         }, {
 462                 .name           = "pdma",
 463                 .devname        = "s3c-pl330.1",
 464                 .enable         = exynos4_clk_ip_fsys_ctrl,
 465                 .ctrlbit        = (1 << 1),
 466         }, {
 467                 .name           = "adc",
 468                 .enable         = exynos4_clk_ip_peril_ctrl,
 469                 .ctrlbit        = (1 << 15),
 470         }, {
 471                 .name           = "keypad",
 472                 .enable         = exynos4_clk_ip_perir_ctrl,
 473                 .ctrlbit        = (1 << 16),
 474         }, {
 475                 .name           = "rtc",
 476                 .enable         = exynos4_clk_ip_perir_ctrl,
 477                 .ctrlbit        = (1 << 15),
 478         }, {
 479                 .name           = "watchdog",
 480                 .parent         = &clk_aclk_100.clk,
 481                 .enable         = exynos4_clk_ip_perir_ctrl,
 482                 .ctrlbit        = (1 << 14),
 483         }, {
 484                 .name           = "usbhost",
 485                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 486                 .ctrlbit        = (1 << 12),
 487         }, {
 488                 .name           = "otg",
 489                 .enable         = exynos4_clk_ip_fsys_ctrl,
 490                 .ctrlbit        = (1 << 13),
 491         }, {
 492                 .name           = "spi",
 493                 .devname        = "s3c64xx-spi.0",
 494                 .enable         = exynos4_clk_ip_peril_ctrl,
 495                 .ctrlbit        = (1 << 16),
 496         }, {
 497                 .name           = "spi",
 498                 .devname        = "s3c64xx-spi.1",
 499                 .enable         = exynos4_clk_ip_peril_ctrl,
 500                 .ctrlbit        = (1 << 17),
 501         }, {
 502                 .name           = "spi",
 503                 .devname        = "s3c64xx-spi.2",
 504                 .enable         = exynos4_clk_ip_peril_ctrl,
 505                 .ctrlbit        = (1 << 18),
 506         }, {
 507                 .name           = "iis",
 508                 .devname        = "samsung-i2s.0",
 509                 .enable         = exynos4_clk_ip_peril_ctrl,
 510                 .ctrlbit        = (1 << 19),
 511         }, {
 512                 .name           = "iis",
 513                 .devname        = "samsung-i2s.1",
 514                 .enable         = exynos4_clk_ip_peril_ctrl,
 515                 .ctrlbit        = (1 << 20),
 516         }, {
 517                 .name           = "iis",
 518                 .devname        = "samsung-i2s.2",
 519                 .enable         = exynos4_clk_ip_peril_ctrl,
 520                 .ctrlbit        = (1 << 21),
 521         }, {
 522                 .name           = "ac97",
 523                 .id             = -1,
 524                 .enable         = exynos4_clk_ip_peril_ctrl,
 525                 .ctrlbit        = (1 << 27),
 526         }, {
 527                 .name           = "fimg2d",
 528                 .enable         = exynos4_clk_ip_image_ctrl,
 529                 .ctrlbit        = (1 << 0),
 530         }, {
 531                 .name           = "i2c",
 532                 .devname        = "s3c2440-i2c.0",
 533                 .parent         = &clk_aclk_100.clk,
 534                 .enable         = exynos4_clk_ip_peril_ctrl,
 535                 .ctrlbit        = (1 << 6),
 536         }, {
 537                 .name           = "i2c",
 538                 .devname        = "s3c2440-i2c.1",
 539                 .parent         = &clk_aclk_100.clk,
 540                 .enable         = exynos4_clk_ip_peril_ctrl,
 541                 .ctrlbit        = (1 << 7),
 542         }, {
 543                 .name           = "i2c",
 544                 .devname        = "s3c2440-i2c.2",
 545                 .parent         = &clk_aclk_100.clk,
 546                 .enable         = exynos4_clk_ip_peril_ctrl,
 547                 .ctrlbit        = (1 << 8),
 548         }, {
 549                 .name           = "i2c",
 550                 .devname        = "s3c2440-i2c.3",
 551                 .parent         = &clk_aclk_100.clk,
 552                 .enable         = exynos4_clk_ip_peril_ctrl,
 553                 .ctrlbit        = (1 << 9),
 554         }, {
 555                 .name           = "i2c",
 556                 .devname        = "s3c2440-i2c.4",
 557                 .parent         = &clk_aclk_100.clk,
 558                 .enable         = exynos4_clk_ip_peril_ctrl,
 559                 .ctrlbit        = (1 << 10),
 560         }, {
 561                 .name           = "i2c",
 562                 .devname        = "s3c2440-i2c.5",
 563                 .parent         = &clk_aclk_100.clk,
 564                 .enable         = exynos4_clk_ip_peril_ctrl,
 565                 .ctrlbit        = (1 << 11),
 566         }, {
 567                 .name           = "i2c",
 568                 .devname        = "s3c2440-i2c.6",
 569                 .parent         = &clk_aclk_100.clk,
 570                 .enable         = exynos4_clk_ip_peril_ctrl,
 571                 .ctrlbit        = (1 << 12),
 572         }, {
 573                 .name           = "i2c",
 574                 .devname        = "s3c2440-i2c.7",
 575                 .parent         = &clk_aclk_100.clk,
 576                 .enable         = exynos4_clk_ip_peril_ctrl,
 577                 .ctrlbit        = (1 << 13),
 578         }, {
 579                 .name           = "SYSMMU_MDMA",
 580                 .enable         = exynos4_clk_ip_image_ctrl,
 581                 .ctrlbit        = (1 << 5),
 582         }, {
 583                 .name           = "SYSMMU_FIMC0",
 584                 .enable         = exynos4_clk_ip_cam_ctrl,
 585                 .ctrlbit        = (1 << 7),
 586         }, {
 587                 .name           = "SYSMMU_FIMC1",
 588                 .enable         = exynos4_clk_ip_cam_ctrl,
 589                 .ctrlbit        = (1 << 8),
 590         }, {
 591                 .name           = "SYSMMU_FIMC2",
 592                 .enable         = exynos4_clk_ip_cam_ctrl,
 593                 .ctrlbit        = (1 << 9),
 594         }, {
 595                 .name           = "SYSMMU_FIMC3",
 596                 .enable         = exynos4_clk_ip_cam_ctrl,
 597                 .ctrlbit        = (1 << 10),
 598         }, {
 599                 .name           = "SYSMMU_JPEG",
 600                 .enable         = exynos4_clk_ip_cam_ctrl,
 601                 .ctrlbit        = (1 << 11),
 602         }, {
 603                 .name           = "SYSMMU_FIMD0",
 604                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 605                 .ctrlbit        = (1 << 4),
 606         }, {
 607                 .name           = "SYSMMU_FIMD1",
 608                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 609                 .ctrlbit        = (1 << 4),
 610         }, {
 611                 .name           = "SYSMMU_PCIe",
 612                 .enable         = exynos4_clk_ip_fsys_ctrl,
 613                 .ctrlbit        = (1 << 18),
 614         }, {
 615                 .name           = "SYSMMU_G2D",
 616                 .enable         = exynos4_clk_ip_image_ctrl,
 617                 .ctrlbit        = (1 << 3),
 618         }, {
 619                 .name           = "SYSMMU_ROTATOR",
 620                 .enable         = exynos4_clk_ip_image_ctrl,
 621                 .ctrlbit        = (1 << 4),
 622         }, {
 623                 .name           = "SYSMMU_TV",
 624                 .enable         = exynos4_clk_ip_tv_ctrl,
 625                 .ctrlbit        = (1 << 4),
 626         }, {
 627                 .name           = "SYSMMU_MFC_L",
 628                 .enable         = exynos4_clk_ip_mfc_ctrl,
 629                 .ctrlbit        = (1 << 1),
 630         }, {
 631                 .name           = "SYSMMU_MFC_R",
 632                 .enable         = exynos4_clk_ip_mfc_ctrl,
 633                 .ctrlbit        = (1 << 2),
 634         }
 635 };
 636
 637 static struct clk init_clocks[] = {
 638         {
 639                 .name           = "uart",
 640                 .devname        = "s5pv210-uart.0",
 641                 .enable         = exynos4_clk_ip_peril_ctrl,
 642                 .ctrlbit        = (1 << 0),
 643         }, {
 644                 .name           = "uart",
 645                 .devname        = "s5pv210-uart.1",
 646                 .enable         = exynos4_clk_ip_peril_ctrl,
 647                 .ctrlbit        = (1 << 1),
 648         }, {
 649                 .name           = "uart",
 650                 .devname        = "s5pv210-uart.2",
 651                 .enable         = exynos4_clk_ip_peril_ctrl,
 652                 .ctrlbit        = (1 << 2),
 653         }, {
 654                 .name           = "uart",
 655                 .devname        = "s5pv210-uart.3",
 656                 .enable         = exynos4_clk_ip_peril_ctrl,
 657                 .ctrlbit        = (1 << 3),
 658         }, {
 659                 .name           = "uart",
 660                 .devname        = "s5pv210-uart.4",
 661                 .enable         = exynos4_clk_ip_peril_ctrl,
 662                 .ctrlbit        = (1 << 4),
 663         }, {
 664                 .name           = "uart",
 665                 .devname        = "s5pv210-uart.5",
 666                 .enable         = exynos4_clk_ip_peril_ctrl,
 667                 .ctrlbit        = (1 << 5),
 668         }
 669 };
 670
 671 static struct clk *clkset_group_list[] = {
 672         [0] = &clk_ext_xtal_mux,
 673         [1] = &clk_xusbxti,
 674         [2] = &clk_sclk_hdmi27m,
 675         [3] = &clk_sclk_usbphy0,
 676         [4] = &clk_sclk_usbphy1,
 677         [5] = &clk_sclk_hdmiphy,
 678         [6] = &clk_mout_mpll.clk,
 679         [7] = &clk_mout_epll.clk,
 680         [8] = &clk_sclk_vpll.clk,
 681 };
 682
 683 static struct clksrc_sources clkset_group = {
 684         .sources        = clkset_group_list,
 685         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 686 };
 687
 688 static struct clk *clkset_mout_g2d0_list[] = {
 689         [0] = &clk_mout_mpll.clk,
 690         [1] = &clk_sclk_apll.clk,
 691 };
 692
 693 static struct clksrc_sources clkset_mout_g2d0 = {
 694         .sources        = clkset_mout_g2d0_list,
 695         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 696 };
 697
 698 static struct clksrc_clk clk_mout_g2d0 = {
 699         .clk    = {
 700                 .name           = "mout_g2d0",
 701         },
 702         .sources        = &clkset_mout_g2d0,
 703         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 704 };
 705
 706 static struct clk *clkset_mout_g2d1_list[] = {
 707         [0] = &clk_mout_epll.clk,
 708         [1] = &clk_sclk_vpll.clk,
 709 };
 710
 711 static struct clksrc_sources clkset_mout_g2d1 = {
 712         .sources        = clkset_mout_g2d1_list,
 713         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 714 };
 715
 716 static struct clksrc_clk clk_mout_g2d1 = {
 717         .clk    = {
 718                 .name           = "mout_g2d1",
 719         },
 720         .sources        = &clkset_mout_g2d1,
 721         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 722 };
 723
 724 static struct clk *clkset_mout_g2d_list[] = {
 725         [0] = &clk_mout_g2d0.clk,
 726         [1] = &clk_mout_g2d1.clk,
 727 };
 728
 729 static struct clksrc_sources clkset_mout_g2d = {
 730         .sources        = clkset_mout_g2d_list,
 731         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 732 };
 733
 734 static struct clksrc_clk clk_dout_mmc0 = {
 735         .clk            = {
 736                 .name           = "dout_mmc0",
 737         },
 738         .sources = &clkset_group,
 739         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 740         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 741 };
 742
 743 static struct clksrc_clk clk_dout_mmc1 = {
 744         .clk            = {
 745                 .name           = "dout_mmc1",
 746         },
 747         .sources = &clkset_group,
 748         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 749         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 750 };
 751
 752 static struct clksrc_clk clk_dout_mmc2 = {
 753         .clk            = {
 754                 .name           = "dout_mmc2",
 755         },
 756         .sources = &clkset_group,
 757         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 758         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 759 };
 760
 761 static struct clksrc_clk clk_dout_mmc3 = {
 762         .clk            = {
 763                 .name           = "dout_mmc3",
 764         },
 765         .sources = &clkset_group,
 766         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
 767         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 768 };
 769
 770 static struct clksrc_clk clk_dout_mmc4 = {
 771         .clk            = {
 772                 .name           = "dout_mmc4",
 773         },
 774         .sources = &clkset_group,
 775         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
 776         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 777 };
 778
 779 static struct clksrc_clk clksrcs[] = {
 780         {
 781                 .clk    = {
 782                         .name           = "uclk1",
 783                         .devname        = "s5pv210-uart.0",
 784                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 785                         .ctrlbit        = (1 << 0),
 786                 },
 787                 .sources = &clkset_group,
 788                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
 789                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
 790         }, {
 791                 .clk            = {
 792                         .name           = "uclk1",
 793                         .devname        = "s5pv210-uart.1",
 794                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 795                         .ctrlbit        = (1 << 4),
 796                 },
 797                 .sources = &clkset_group,
 798                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
 799                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
 800         }, {
 801                 .clk            = {
 802                         .name           = "uclk1",
 803                         .devname        = "s5pv210-uart.2",
 804                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 805                         .ctrlbit        = (1 << 8),
 806                 },
 807                 .sources = &clkset_group,
 808                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
 809                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
 810         }, {
 811                 .clk            = {
 812                         .name           = "uclk1",
 813                         .devname        = "s5pv210-uart.3",
 814                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 815                         .ctrlbit        = (1 << 12),
 816                 },
 817                 .sources = &clkset_group,
 818                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
 819                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 820         }, {
 821                 .clk            = {
 822                         .name           = "sclk_pwm",
 823                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 824                         .ctrlbit        = (1 << 24),
 825                 },
 826                 .sources = &clkset_group,
 827                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
 828                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 829         }, {
 830                 .clk            = {
 831                         .name           = "sclk_csis",
 832                         .devname        = "s5p-mipi-csis.0",
 833                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 834                         .ctrlbit        = (1 << 24),
 835                 },
 836                 .sources = &clkset_group,
 837                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
 838                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
 839         }, {
 840                 .clk            = {
 841                         .name           = "sclk_csis",
 842                         .devname        = "s5p-mipi-csis.1",
 843                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 844                         .ctrlbit        = (1 << 28),
 845                 },
 846                 .sources = &clkset_group,
 847                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
 848                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
 849         }, {
 850                 .clk            = {
 851                         .name           = "sclk_cam",
 852                         .devname        = "exynos4-fimc.0",
 853                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 854                         .ctrlbit        = (1 << 16),
 855                 },
 856                 .sources = &clkset_group,
 857                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
 858                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
 859         }, {
 860                 .clk            = {
 861                         .name           = "sclk_cam",
 862                         .devname        = "exynos4-fimc.1",
 863                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 864                         .ctrlbit        = (1 << 20),
 865                 },
 866                 .sources = &clkset_group,
 867                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
 868                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
 869         }, {
 870                 .clk            = {
 871                         .name           = "sclk_fimc",
 872                         .devname        = "exynos4-fimc.0",
 873                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 874                         .ctrlbit        = (1 << 0),
 875                 },
 876                 .sources = &clkset_group,
 877                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
 878                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
 879         }, {
 880                 .clk            = {
 881                         .name           = "sclk_fimc",
 882                         .devname        = "exynos4-fimc.1",
 883                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 884                         .ctrlbit        = (1 << 4),
 885                 },
 886                 .sources = &clkset_group,
 887                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
 888                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
 889         }, {
 890                 .clk            = {
 891                         .name           = "sclk_fimc",
 892                         .devname        = "exynos4-fimc.2",
 893                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 894                         .ctrlbit        = (1 << 8),
 895                 },
 896                 .sources = &clkset_group,
 897                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
 898                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
 899         }, {
 900                 .clk            = {
 901                         .name           = "sclk_fimc",
 902                         .devname        = "exynos4-fimc.3",
 903                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 904                         .ctrlbit        = (1 << 12),
 905                 },
 906                 .sources = &clkset_group,
 907                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
 908                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
 909         }, {
 910                 .clk            = {
 911                         .name           = "sclk_fimd",
 912                         .devname        = "exynos4-fb.0",
 913                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
 914                         .ctrlbit        = (1 << 0),
 915                 },
 916                 .sources = &clkset_group,
 917                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
 918                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
 919         }, {
 920                 .clk            = {
 921                         .name           = "sclk_fimd",
 922                         .devname        = "exynos4-fb.1",
 923                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
 924                         .ctrlbit        = (1 << 0),
 925                 },
 926                 .sources = &clkset_group,
 927                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
 928                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
 929         }, {
 930                 .clk            = {
 931                         .name           = "sclk_sata",
 932                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 933                         .ctrlbit        = (1 << 24),
 934                 },
 935                 .sources = &clkset_mout_corebus,
 936                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
 937                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
 938         }, {
 939                 .clk            = {
 940                         .name           = "sclk_spi",
 941                         .devname        = "s3c64xx-spi.0",
 942                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 943                         .ctrlbit        = (1 << 16),
 944                 },
 945                 .sources = &clkset_group,
 946                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
 947                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
 948         }, {
 949                 .clk            = {
 950                         .name           = "sclk_spi",
 951                         .devname        = "s3c64xx-spi.1",
 952                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 953                         .ctrlbit        = (1 << 20),
 954                 },
 955                 .sources = &clkset_group,
 956                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
 957                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
 958         }, {
 959                 .clk            = {
 960                         .name           = "sclk_spi",
 961                         .devname        = "s3c64xx-spi.2",
 962                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 963                         .ctrlbit        = (1 << 24),
 964                 },
 965                 .sources = &clkset_group,
 966                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
 967                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
 968         }, {
 969                 .clk            = {
 970                         .name           = "sclk_fimg2d",
 971                 },
 972                 .sources = &clkset_mout_g2d,
 973                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
 974                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
 975         }, {
 976                 .clk            = {
 977                         .name           = "sclk_mmc",
 978                         .devname        = "s3c-sdhci.0",
 979                         .parent         = &clk_dout_mmc0.clk,
 980                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 981                         .ctrlbit        = (1 << 0),
 982                 },
 983                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
 984         }, {
 985                 .clk            = {
 986                         .name           = "sclk_mmc",
 987                         .devname        = "s3c-sdhci.1",
 988                         .parent         = &clk_dout_mmc1.clk,
 989                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 990                         .ctrlbit        = (1 << 4),
 991                 },
 992                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
 993         }, {
 994                 .clk            = {
 995                         .name           = "sclk_mmc",
 996                         .devname        = "s3c-sdhci.2",
 997                         .parent         = &clk_dout_mmc2.clk,
 998                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 999                         .ctrlbit        = (1 << 8),
1000                 },
1001                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1002         }, {
1003                 .clk            = {
1004                         .name           = "sclk_mmc",
1005                         .devname        = "s3c-sdhci.3",
1006                         .parent         = &clk_dout_mmc3.clk,
1007                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1008                         .ctrlbit        = (1 << 12),
1009                 },
1010                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1011         }, {
1012                 .clk            = {
1013                         .name           = "sclk_dwmmc",
1014                         .parent         = &clk_dout_mmc4.clk,
1015                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1016                         .ctrlbit        = (1 << 16),
1017                 },
1018                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1019         }
1020 };
1021
1022 /* Clock initialization code */
1023 static struct clksrc_clk *sysclks[] = {
1024         &clk_mout_apll,
1025         &clk_sclk_apll,
1026         &clk_mout_epll,
1027         &clk_mout_mpll,
1028         &clk_moutcore,
1029         &clk_coreclk,
1030         &clk_armclk,
1031         &clk_aclk_corem0,
1032         &clk_aclk_cores,
1033         &clk_aclk_corem1,
1034         &clk_periphclk,
1035         &clk_mout_corebus,
1036         &clk_sclk_dmc,
1037         &clk_aclk_cored,
1038         &clk_aclk_corep,
1039         &clk_aclk_acp,
1040         &clk_pclk_acp,
1041         &clk_vpllsrc,
1042         &clk_sclk_vpll,
1043         &clk_aclk_200,
1044         &clk_aclk_100,
1045         &clk_aclk_160,
1046         &clk_aclk_133,
1047         &clk_dout_mmc0,
1048         &clk_dout_mmc1,
1049         &clk_dout_mmc2,
1050         &clk_dout_mmc3,
1051         &clk_dout_mmc4,
1052 };
1053
1054 static int xtal_rate;
1055
1056 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1057 {
1058         return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1059 }
1060
1061 static struct clk_ops exynos4_fout_apll_ops = {
1062         .get_rate = exynos4_fout_apll_get_rate,
1063 };
1064
1065 void __init_or_cpufreq exynos4_setup_clocks(void)
1066 {
1067         struct clk *xtal_clk;
1068         unsigned long apll;
1069         unsigned long mpll;
1070         unsigned long epll;
1071         unsigned long vpll;
1072         unsigned long vpllsrc;
1073         unsigned long xtal;
1074         unsigned long armclk;
1075         unsigned long sclk_dmc;
1076         unsigned long aclk_200;
1077         unsigned long aclk_100;
1078         unsigned long aclk_160;
1079         unsigned long aclk_133;
1080         unsigned int ptr;
1081
1082         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1083
1084         xtal_clk = clk_get(NULL, "xtal");
1085         BUG_ON(IS_ERR(xtal_clk));
1086
1087         xtal = clk_get_rate(xtal_clk);
1088
1089         xtal_rate = xtal;
1090
1091         clk_put(xtal_clk);
1092
1093         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1094
1095         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1096         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1097         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1098                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1099
1100         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1101         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1102                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
1103
1104         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1105         clk_fout_mpll.rate = mpll;
1106         clk_fout_epll.rate = epll;
1107         clk_fout_vpll.rate = vpll;
1108
1109         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1110                         apll, mpll, epll, vpll);
1111
1112         armclk = clk_get_rate(&clk_armclk.clk);
1113         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1114
1115         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1116         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1117         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1118         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1119
1120         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1121                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1122                         armclk, sclk_dmc, aclk_200,
1123                         aclk_100, aclk_160, aclk_133);
1124
1125         clk_f.rate = armclk;
1126         clk_h.rate = sclk_dmc;
1127         clk_p.rate = aclk_100;
1128
1129         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1130                 s3c_set_clksrc(&clksrcs[ptr], true);
1131 }
1132
1133 static struct clk *clks[] __initdata = {
1134         /* Nothing here yet */
1135 };
1136
1137 void __init exynos4_register_clocks(void)
1138 {
1139         int ptr;
1140
1141         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1142
1143         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1144                 s3c_register_clksrc(sysclks[ptr], 1);
1145
1146         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1147         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1148
1149         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1150         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1151
1152         s3c_pwmclk_init();
1153 }