arch/arm/mach-exynos/clock-exynos4.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30 #include "clock-exynos4.h"
  31
  32 #ifdef CONFIG_PM_SLEEP
  33 static struct sleep_save exynos4_clock_save[] = {
  34         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
  35         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
  36         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
  37         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
  38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
  39         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
  40         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
  41         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
  42         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
  43         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
  44         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
  45         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
  46         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
  47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
  48         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
  49         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
  50         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
  51         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
  52         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
  53         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
  54         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
  60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
  61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
  62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
  63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
  64         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
  65         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
  66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
  67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
  68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
  69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
  70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
  71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
  72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
  73         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
  74         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
  75         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
  76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
  77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
  78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
  79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
  80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
  81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
  82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
  83         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
  84         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
  85         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
  86         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
  87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
  88         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
  89         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
  90         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
  91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
  92         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
  93         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
  94         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
  95 };
  96 #endif
  97
  98 static struct clk exynos4_clk_sclk_hdmi27m = {
  99         .name           = "sclk_hdmi27m",
 100         .rate           = 27000000,
 101 };
 102
 103 static struct clk exynos4_clk_sclk_hdmiphy = {
 104         .name           = "sclk_hdmiphy",
 105 };
 106
 107 static struct clk exynos4_clk_sclk_usbphy0 = {
 108         .name           = "sclk_usbphy0",
 109         .rate           = 27000000,
 110 };
 111
 112 static struct clk exynos4_clk_sclk_usbphy1 = {
 113         .name           = "sclk_usbphy1",
 114 };
 115
 116 static struct clk dummy_apb_pclk = {
 117         .name           = "apb_pclk",
 118         .id             = -1,
 119 };
 120
 121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 124 }
 125
 126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 127 {
 128         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 129 }
 130
 131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 132 {
 133         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 134 }
 135
 136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 137 {
 138         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 139 }
 140
 141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 142 {
 143         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 144 }
 145
 146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 147 {
 148         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 149 }
 150
 151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 152 {
 153         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 154 }
 155
 156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 159 }
 160
 161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 164 }
 165
 166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 169 }
 170
 171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 174 }
 175
 176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 179 }
 180
 181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 182 {
 183         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 184 }
 185
 186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 187 {
 188         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 189 }
 190
 191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 192 {
 193         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 194 }
 195
 196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 197 {
 198         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 199 }
 200
 201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
 202 {
 203         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
 204 }
 205
 206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 207 {
 208         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 209 }
 210
 211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 212 {
 213         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 214 }
 215
 216 /* Core list of CMU_CPU side */
 217
 218 static struct clksrc_clk exynos4_clk_mout_apll = {
 219         .clk    = {
 220                 .name           = "mout_apll",
 221         },
 222         .sources = &clk_src_apll,
 223         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 224 };
 225
 226 static struct clksrc_clk exynos4_clk_sclk_apll = {
 227         .clk    = {
 228                 .name           = "sclk_apll",
 229                 .parent         = &exynos4_clk_mout_apll.clk,
 230         },
 231         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 232 };
 233
 234 static struct clksrc_clk exynos4_clk_mout_epll = {
 235         .clk    = {
 236                 .name           = "mout_epll",
 237         },
 238         .sources = &clk_src_epll,
 239         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 240 };
 241
 242 struct clksrc_clk exynos4_clk_mout_mpll = {
 243         .clk    = {
 244                 .name           = "mout_mpll",
 245         },
 246         .sources = &clk_src_mpll,
 247
 248         /* reg_src will be added in each SoCs' clock */
 249 };
 250
 251 static struct clk *exynos4_clkset_moutcore_list[] = {
 252         [0] = &exynos4_clk_mout_apll.clk,
 253         [1] = &exynos4_clk_mout_mpll.clk,
 254 };
 255
 256 static struct clksrc_sources exynos4_clkset_moutcore = {
 257         .sources        = exynos4_clkset_moutcore_list,
 258         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
 259 };
 260
 261 static struct clksrc_clk exynos4_clk_moutcore = {
 262         .clk    = {
 263                 .name           = "moutcore",
 264         },
 265         .sources = &exynos4_clkset_moutcore,
 266         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 267 };
 268
 269 static struct clksrc_clk exynos4_clk_coreclk = {
 270         .clk    = {
 271                 .name           = "core_clk",
 272                 .parent         = &exynos4_clk_moutcore.clk,
 273         },
 274         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 275 };
 276
 277 static struct clksrc_clk exynos4_clk_armclk = {
 278         .clk    = {
 279                 .name           = "armclk",
 280                 .parent         = &exynos4_clk_coreclk.clk,
 281         },
 282 };
 283
 284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 285         .clk    = {
 286                 .name           = "aclk_corem0",
 287                 .parent         = &exynos4_clk_coreclk.clk,
 288         },
 289         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 290 };
 291
 292 static struct clksrc_clk exynos4_clk_aclk_cores = {
 293         .clk    = {
 294                 .name           = "aclk_cores",
 295                 .parent         = &exynos4_clk_coreclk.clk,
 296         },
 297         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 298 };
 299
 300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 301         .clk    = {
 302                 .name           = "aclk_corem1",
 303                 .parent         = &exynos4_clk_coreclk.clk,
 304         },
 305         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 306 };
 307
 308 static struct clksrc_clk exynos4_clk_periphclk = {
 309         .clk    = {
 310                 .name           = "periphclk",
 311                 .parent         = &exynos4_clk_coreclk.clk,
 312         },
 313         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 314 };
 315
 316 /* Core list of CMU_CORE side */
 317
 318 static struct clk *exynos4_clkset_corebus_list[] = {
 319         [0] = &exynos4_clk_mout_mpll.clk,
 320         [1] = &exynos4_clk_sclk_apll.clk,
 321 };
 322
 323 struct clksrc_sources exynos4_clkset_mout_corebus = {
 324         .sources        = exynos4_clkset_corebus_list,
 325         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
 326 };
 327
 328 static struct clksrc_clk exynos4_clk_mout_corebus = {
 329         .clk    = {
 330                 .name           = "mout_corebus",
 331         },
 332         .sources = &exynos4_clkset_mout_corebus,
 333         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 334 };
 335
 336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
 337         .clk    = {
 338                 .name           = "sclk_dmc",
 339                 .parent         = &exynos4_clk_mout_corebus.clk,
 340         },
 341         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 342 };
 343
 344 static struct clksrc_clk exynos4_clk_aclk_cored = {
 345         .clk    = {
 346                 .name           = "aclk_cored",
 347                 .parent         = &exynos4_clk_sclk_dmc.clk,
 348         },
 349         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 350 };
 351
 352 static struct clksrc_clk exynos4_clk_aclk_corep = {
 353         .clk    = {
 354                 .name           = "aclk_corep",
 355                 .parent         = &exynos4_clk_aclk_cored.clk,
 356         },
 357         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 358 };
 359
 360 static struct clksrc_clk exynos4_clk_aclk_acp = {
 361         .clk    = {
 362                 .name           = "aclk_acp",
 363                 .parent         = &exynos4_clk_mout_corebus.clk,
 364         },
 365         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 366 };
 367
 368 static struct clksrc_clk exynos4_clk_pclk_acp = {
 369         .clk    = {
 370                 .name           = "pclk_acp",
 371                 .parent         = &exynos4_clk_aclk_acp.clk,
 372         },
 373         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 374 };
 375
 376 /* Core list of CMU_TOP side */
 377
 378 struct clk *exynos4_clkset_aclk_top_list[] = {
 379         [0] = &exynos4_clk_mout_mpll.clk,
 380         [1] = &exynos4_clk_sclk_apll.clk,
 381 };
 382
 383 static struct clksrc_sources exynos4_clkset_aclk = {
 384         .sources        = exynos4_clkset_aclk_top_list,
 385         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 386 };
 387
 388 static struct clksrc_clk exynos4_clk_aclk_200 = {
 389         .clk    = {
 390                 .name           = "aclk_200",
 391         },
 392         .sources = &exynos4_clkset_aclk,
 393         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
 394         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 395 };
 396
 397 static struct clksrc_clk exynos4_clk_aclk_100 = {
 398         .clk    = {
 399                 .name           = "aclk_100",
 400         },
 401         .sources = &exynos4_clkset_aclk,
 402         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
 403         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 404 };
 405
 406 static struct clksrc_clk exynos4_clk_aclk_160 = {
 407         .clk    = {
 408                 .name           = "aclk_160",
 409         },
 410         .sources = &exynos4_clkset_aclk,
 411         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
 412         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 413 };
 414
 415 struct clksrc_clk exynos4_clk_aclk_133 = {
 416         .clk    = {
 417                 .name           = "aclk_133",
 418         },
 419         .sources = &exynos4_clkset_aclk,
 420         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
 421         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 422 };
 423
 424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
 425         [0] = &clk_fin_vpll,
 426         [1] = &exynos4_clk_sclk_hdmi27m,
 427 };
 428
 429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
 430         .sources        = exynos4_clkset_vpllsrc_list,
 431         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 432 };
 433
 434 static struct clksrc_clk exynos4_clk_vpllsrc = {
 435         .clk    = {
 436                 .name           = "vpll_src",
 437                 .enable         = exynos4_clksrc_mask_top_ctrl,
 438                 .ctrlbit        = (1 << 0),
 439         },
 440         .sources = &exynos4_clkset_vpllsrc,
 441         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 442 };
 443
 444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
 445         [0] = &exynos4_clk_vpllsrc.clk,
 446         [1] = &clk_fout_vpll,
 447 };
 448
 449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
 450         .sources        = exynos4_clkset_sclk_vpll_list,
 451         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 452 };
 453
 454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
 455         .clk    = {
 456                 .name           = "sclk_vpll",
 457         },
 458         .sources = &exynos4_clkset_sclk_vpll,
 459         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 460 };
 461
 462 static struct clk exynos4_init_clocks_off[] = {
 463         {
 464                 .name           = "timers",
 465                 .parent         = &exynos4_clk_aclk_100.clk,
 466                 .enable         = exynos4_clk_ip_peril_ctrl,
 467                 .ctrlbit        = (1<<24),
 468         }, {
 469                 .name           = "csis",
 470                 .devname        = "s5p-mipi-csis.0",
 471                 .enable         = exynos4_clk_ip_cam_ctrl,
 472                 .ctrlbit        = (1 << 4),
 473         }, {
 474                 .name           = "csis",
 475                 .devname        = "s5p-mipi-csis.1",
 476                 .enable         = exynos4_clk_ip_cam_ctrl,
 477                 .ctrlbit        = (1 << 5),
 478         }, {
 479                 .name           = "jpeg",
 480                 .id             = 0,
 481                 .enable         = exynos4_clk_ip_cam_ctrl,
 482                 .ctrlbit        = (1 << 6),
 483         }, {
 484                 .name           = "fimc",
 485                 .devname        = "exynos4-fimc.0",
 486                 .enable         = exynos4_clk_ip_cam_ctrl,
 487                 .ctrlbit        = (1 << 0),
 488         }, {
 489                 .name           = "fimc",
 490                 .devname        = "exynos4-fimc.1",
 491                 .enable         = exynos4_clk_ip_cam_ctrl,
 492                 .ctrlbit        = (1 << 1),
 493         }, {
 494                 .name           = "fimc",
 495                 .devname        = "exynos4-fimc.2",
 496                 .enable         = exynos4_clk_ip_cam_ctrl,
 497                 .ctrlbit        = (1 << 2),
 498         }, {
 499                 .name           = "fimc",
 500                 .devname        = "exynos4-fimc.3",
 501                 .enable         = exynos4_clk_ip_cam_ctrl,
 502                 .ctrlbit        = (1 << 3),
 503         }, {
 504                 .name           = "tsi",
 505                 .enable         = exynos4_clk_ip_fsys_ctrl,
 506                 .ctrlbit        = (1 << 4),
 507         }, {
 508                 .name           = "hsmmc",
 509                 .devname        = "exynos4-sdhci.0",
 510                 .parent         = &exynos4_clk_aclk_133.clk,
 511                 .enable         = exynos4_clk_ip_fsys_ctrl,
 512                 .ctrlbit        = (1 << 5),
 513         }, {
 514                 .name           = "hsmmc",
 515                 .devname        = "exynos4-sdhci.1",
 516                 .parent         = &exynos4_clk_aclk_133.clk,
 517                 .enable         = exynos4_clk_ip_fsys_ctrl,
 518                 .ctrlbit        = (1 << 6),
 519         }, {
 520                 .name           = "hsmmc",
 521                 .devname        = "exynos4-sdhci.2",
 522                 .parent         = &exynos4_clk_aclk_133.clk,
 523                 .enable         = exynos4_clk_ip_fsys_ctrl,
 524                 .ctrlbit        = (1 << 7),
 525         }, {
 526                 .name           = "hsmmc",
 527                 .devname        = "exynos4-sdhci.3",
 528                 .parent         = &exynos4_clk_aclk_133.clk,
 529                 .enable         = exynos4_clk_ip_fsys_ctrl,
 530                 .ctrlbit        = (1 << 8),
 531         }, {
 532                 .name           = "dwmmc",
 533                 .parent         = &exynos4_clk_aclk_133.clk,
 534                 .enable         = exynos4_clk_ip_fsys_ctrl,
 535                 .ctrlbit        = (1 << 9),
 536         }, {
 537                 .name           = "onenand",
 538                 .enable         = exynos4_clk_ip_fsys_ctrl,
 539                 .ctrlbit        = (1 << 15),
 540         }, {
 541                 .name           = "nfcon",
 542                 .enable         = exynos4_clk_ip_fsys_ctrl,
 543                 .ctrlbit        = (1 << 16),
 544         }, {
 545                 .name           = "dac",
 546                 .devname        = "s5p-sdo",
 547                 .enable         = exynos4_clk_ip_tv_ctrl,
 548                 .ctrlbit        = (1 << 2),
 549         }, {
 550                 .name           = "mixer",
 551                 .devname        = "s5p-mixer",
 552                 .enable         = exynos4_clk_ip_tv_ctrl,
 553                 .ctrlbit        = (1 << 1),
 554         }, {
 555                 .name           = "vp",
 556                 .devname        = "s5p-mixer",
 557                 .enable         = exynos4_clk_ip_tv_ctrl,
 558                 .ctrlbit        = (1 << 0),
 559         }, {
 560                 .name           = "hdmi",
 561                 .devname        = "exynos4-hdmi",
 562                 .enable         = exynos4_clk_ip_tv_ctrl,
 563                 .ctrlbit        = (1 << 3),
 564         }, {
 565                 .name           = "hdmiphy",
 566                 .devname        = "exynos4-hdmi",
 567                 .enable         = exynos4_clk_hdmiphy_ctrl,
 568                 .ctrlbit        = (1 << 0),
 569         }, {
 570                 .name           = "dacphy",
 571                 .devname        = "s5p-sdo",
 572                 .enable         = exynos4_clk_dac_ctrl,
 573                 .ctrlbit        = (1 << 0),
 574         }, {
 575                 .name           = "adc",
 576                 .enable         = exynos4_clk_ip_peril_ctrl,
 577                 .ctrlbit        = (1 << 15),
 578         }, {
 579                 .name           = "keypad",
 580                 .enable         = exynos4_clk_ip_perir_ctrl,
 581                 .ctrlbit        = (1 << 16),
 582         }, {
 583                 .name           = "rtc",
 584                 .enable         = exynos4_clk_ip_perir_ctrl,
 585                 .ctrlbit        = (1 << 15),
 586         }, {
 587                 .name           = "watchdog",
 588                 .parent         = &exynos4_clk_aclk_100.clk,
 589                 .enable         = exynos4_clk_ip_perir_ctrl,
 590                 .ctrlbit        = (1 << 14),
 591         }, {
 592                 .name           = "usbhost",
 593                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 594                 .ctrlbit        = (1 << 12),
 595         }, {
 596                 .name           = "otg",
 597                 .enable         = exynos4_clk_ip_fsys_ctrl,
 598                 .ctrlbit        = (1 << 13),
 599         }, {
 600                 .name           = "spi",
 601                 .devname        = "exynos4210-spi.0",
 602                 .enable         = exynos4_clk_ip_peril_ctrl,
 603                 .ctrlbit        = (1 << 16),
 604         }, {
 605                 .name           = "spi",
 606                 .devname        = "exynos4210-spi.1",
 607                 .enable         = exynos4_clk_ip_peril_ctrl,
 608                 .ctrlbit        = (1 << 17),
 609         }, {
 610                 .name           = "spi",
 611                 .devname        = "exynos4210-spi.2",
 612                 .enable         = exynos4_clk_ip_peril_ctrl,
 613                 .ctrlbit        = (1 << 18),
 614         }, {
 615                 .name           = "iis",
 616                 .devname        = "samsung-i2s.1",
 617                 .enable         = exynos4_clk_ip_peril_ctrl,
 618                 .ctrlbit        = (1 << 20),
 619         }, {
 620                 .name           = "iis",
 621                 .devname        = "samsung-i2s.2",
 622                 .enable         = exynos4_clk_ip_peril_ctrl,
 623                 .ctrlbit        = (1 << 21),
 624         }, {
 625                 .name           = "pcm",
 626                 .devname        = "samsung-pcm.1",
 627                 .enable         = exynos4_clk_ip_peril_ctrl,
 628                 .ctrlbit        = (1 << 22),
 629         }, {
 630                 .name           = "pcm",
 631                 .devname        = "samsung-pcm.2",
 632                 .enable         = exynos4_clk_ip_peril_ctrl,
 633                 .ctrlbit        = (1 << 23),
 634         }, {
 635                 .name           = "slimbus",
 636                 .enable         = exynos4_clk_ip_peril_ctrl,
 637                 .ctrlbit        = (1 << 25),
 638         }, {
 639                 .name           = "spdif",
 640                 .devname        = "samsung-spdif",
 641                 .enable         = exynos4_clk_ip_peril_ctrl,
 642                 .ctrlbit        = (1 << 26),
 643         }, {
 644                 .name           = "ac97",
 645                 .devname        = "samsung-ac97",
 646                 .enable         = exynos4_clk_ip_peril_ctrl,
 647                 .ctrlbit        = (1 << 27),
 648         }, {
 649                 .name           = "mfc",
 650                 .devname        = "s5p-mfc",
 651                 .enable         = exynos4_clk_ip_mfc_ctrl,
 652                 .ctrlbit        = (1 << 0),
 653         }, {
 654                 .name           = "i2c",
 655                 .devname        = "s3c2440-i2c.0",
 656                 .parent         = &exynos4_clk_aclk_100.clk,
 657                 .enable         = exynos4_clk_ip_peril_ctrl,
 658                 .ctrlbit        = (1 << 6),
 659         }, {
 660                 .name           = "i2c",
 661                 .devname        = "s3c2440-i2c.1",
 662                 .parent         = &exynos4_clk_aclk_100.clk,
 663                 .enable         = exynos4_clk_ip_peril_ctrl,
 664                 .ctrlbit        = (1 << 7),
 665         }, {
 666                 .name           = "i2c",
 667                 .devname        = "s3c2440-i2c.2",
 668                 .parent         = &exynos4_clk_aclk_100.clk,
 669                 .enable         = exynos4_clk_ip_peril_ctrl,
 670                 .ctrlbit        = (1 << 8),
 671         }, {
 672                 .name           = "i2c",
 673                 .devname        = "s3c2440-i2c.3",
 674                 .parent         = &exynos4_clk_aclk_100.clk,
 675                 .enable         = exynos4_clk_ip_peril_ctrl,
 676                 .ctrlbit        = (1 << 9),
 677         }, {
 678                 .name           = "i2c",
 679                 .devname        = "s3c2440-i2c.4",
 680                 .parent         = &exynos4_clk_aclk_100.clk,
 681                 .enable         = exynos4_clk_ip_peril_ctrl,
 682                 .ctrlbit        = (1 << 10),
 683         }, {
 684                 .name           = "i2c",
 685                 .devname        = "s3c2440-i2c.5",
 686                 .parent         = &exynos4_clk_aclk_100.clk,
 687                 .enable         = exynos4_clk_ip_peril_ctrl,
 688                 .ctrlbit        = (1 << 11),
 689         }, {
 690                 .name           = "i2c",
 691                 .devname        = "s3c2440-i2c.6",
 692                 .parent         = &exynos4_clk_aclk_100.clk,
 693                 .enable         = exynos4_clk_ip_peril_ctrl,
 694                 .ctrlbit        = (1 << 12),
 695         }, {
 696                 .name           = "i2c",
 697                 .devname        = "s3c2440-i2c.7",
 698                 .parent         = &exynos4_clk_aclk_100.clk,
 699                 .enable         = exynos4_clk_ip_peril_ctrl,
 700                 .ctrlbit        = (1 << 13),
 701         }, {
 702                 .name           = "i2c",
 703                 .devname        = "s3c2440-hdmiphy-i2c",
 704                 .parent         = &exynos4_clk_aclk_100.clk,
 705                 .enable         = exynos4_clk_ip_peril_ctrl,
 706                 .ctrlbit        = (1 << 14),
 707         }, {
 708                 .name           = SYSMMU_CLOCK_NAME,
 709                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 710                 .enable         = exynos4_clk_ip_mfc_ctrl,
 711                 .ctrlbit        = (1 << 1),
 712         }, {
 713                 .name           = SYSMMU_CLOCK_NAME,
 714                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 715                 .enable         = exynos4_clk_ip_mfc_ctrl,
 716                 .ctrlbit        = (1 << 2),
 717         }, {
 718                 .name           = SYSMMU_CLOCK_NAME,
 719                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 720                 .enable         = exynos4_clk_ip_tv_ctrl,
 721                 .ctrlbit        = (1 << 4),
 722         }, {
 723                 .name           = SYSMMU_CLOCK_NAME,
 724                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 725                 .enable         = exynos4_clk_ip_cam_ctrl,
 726                 .ctrlbit        = (1 << 11),
 727         }, {
 728                 .name           = SYSMMU_CLOCK_NAME,
 729                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 730                 .enable         = exynos4_clk_ip_image_ctrl,
 731                 .ctrlbit        = (1 << 4),
 732         }, {
 733                 .name           = SYSMMU_CLOCK_NAME,
 734                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
 735                 .enable         = exynos4_clk_ip_cam_ctrl,
 736                 .ctrlbit        = (1 << 7),
 737         }, {
 738                 .name           = SYSMMU_CLOCK_NAME,
 739                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
 740                 .enable         = exynos4_clk_ip_cam_ctrl,
 741                 .ctrlbit        = (1 << 8),
 742         }, {
 743                 .name           = SYSMMU_CLOCK_NAME,
 744                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
 745                 .enable         = exynos4_clk_ip_cam_ctrl,
 746                 .ctrlbit        = (1 << 9),
 747         }, {
 748                 .name           = SYSMMU_CLOCK_NAME,
 749                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
 750                 .enable         = exynos4_clk_ip_cam_ctrl,
 751                 .ctrlbit        = (1 << 10),
 752         }, {
 753                 .name           = SYSMMU_CLOCK_NAME,
 754                 .devname        = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 755                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 756                 .ctrlbit        = (1 << 4),
 757         }
 758 };
 759
 760 static struct clk exynos4_init_clocks_on[] = {
 761         {
 762                 .name           = "uart",
 763                 .devname        = "s5pv210-uart.0",
 764                 .enable         = exynos4_clk_ip_peril_ctrl,
 765                 .ctrlbit        = (1 << 0),
 766         }, {
 767                 .name           = "uart",
 768                 .devname        = "s5pv210-uart.1",
 769                 .enable         = exynos4_clk_ip_peril_ctrl,
 770                 .ctrlbit        = (1 << 1),
 771         }, {
 772                 .name           = "uart",
 773                 .devname        = "s5pv210-uart.2",
 774                 .enable         = exynos4_clk_ip_peril_ctrl,
 775                 .ctrlbit        = (1 << 2),
 776         }, {
 777                 .name           = "uart",
 778                 .devname        = "s5pv210-uart.3",
 779                 .enable         = exynos4_clk_ip_peril_ctrl,
 780                 .ctrlbit        = (1 << 3),
 781         }, {
 782                 .name           = "uart",
 783                 .devname        = "s5pv210-uart.4",
 784                 .enable         = exynos4_clk_ip_peril_ctrl,
 785                 .ctrlbit        = (1 << 4),
 786         }, {
 787                 .name           = "uart",
 788                 .devname        = "s5pv210-uart.5",
 789                 .enable         = exynos4_clk_ip_peril_ctrl,
 790                 .ctrlbit        = (1 << 5),
 791         }
 792 };
 793
 794 static struct clk exynos4_clk_pdma0 = {
 795         .name           = "dma",
 796         .devname        = "dma-pl330.0",
 797         .enable         = exynos4_clk_ip_fsys_ctrl,
 798         .ctrlbit        = (1 << 0),
 799 };
 800
 801 static struct clk exynos4_clk_pdma1 = {
 802         .name           = "dma",
 803         .devname        = "dma-pl330.1",
 804         .enable         = exynos4_clk_ip_fsys_ctrl,
 805         .ctrlbit        = (1 << 1),
 806 };
 807
 808 static struct clk exynos4_clk_mdma1 = {
 809         .name           = "dma",
 810         .devname        = "dma-pl330.2",
 811         .enable         = exynos4_clk_ip_image_ctrl,
 812         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
 813 };
 814
 815 static struct clk exynos4_clk_fimd0 = {
 816         .name           = "fimd",
 817         .devname        = "exynos4-fb.0",
 818         .enable         = exynos4_clk_ip_lcd0_ctrl,
 819         .ctrlbit        = (1 << 0),
 820 };
 821
 822 struct clk *exynos4_clkset_group_list[] = {
 823         [0] = &clk_ext_xtal_mux,
 824         [1] = &clk_xusbxti,
 825         [2] = &exynos4_clk_sclk_hdmi27m,
 826         [3] = &exynos4_clk_sclk_usbphy0,
 827         [4] = &exynos4_clk_sclk_usbphy1,
 828         [5] = &exynos4_clk_sclk_hdmiphy,
 829         [6] = &exynos4_clk_mout_mpll.clk,
 830         [7] = &exynos4_clk_mout_epll.clk,
 831         [8] = &exynos4_clk_sclk_vpll.clk,
 832 };
 833
 834 struct clksrc_sources exynos4_clkset_group = {
 835         .sources        = exynos4_clkset_group_list,
 836         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
 837 };
 838
 839 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
 840         [0] = &exynos4_clk_mout_mpll.clk,
 841         [1] = &exynos4_clk_sclk_apll.clk,
 842 };
 843
 844 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
 845         .sources        = exynos4_clkset_mout_g2d0_list,
 846         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 847 };
 848
 849 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
 850         [0] = &exynos4_clk_mout_epll.clk,
 851         [1] = &exynos4_clk_sclk_vpll.clk,
 852 };
 853
 854 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
 855         .sources        = exynos4_clkset_mout_g2d1_list,
 856         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 857 };
 858
 859 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
 860         [0] = &exynos4_clk_mout_mpll.clk,
 861         [1] = &exynos4_clk_sclk_apll.clk,
 862 };
 863
 864 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
 865         .sources        = exynos4_clkset_mout_mfc0_list,
 866         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 867 };
 868
 869 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 870         .clk    = {
 871                 .name           = "mout_mfc0",
 872         },
 873         .sources = &exynos4_clkset_mout_mfc0,
 874         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 875 };
 876
 877 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
 878         [0] = &exynos4_clk_mout_epll.clk,
 879         [1] = &exynos4_clk_sclk_vpll.clk,
 880 };
 881
 882 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
 883         .sources        = exynos4_clkset_mout_mfc1_list,
 884         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 885 };
 886
 887 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 888         .clk    = {
 889                 .name           = "mout_mfc1",
 890         },
 891         .sources = &exynos4_clkset_mout_mfc1,
 892         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 893 };
 894
 895 static struct clk *exynos4_clkset_mout_mfc_list[] = {
 896         [0] = &exynos4_clk_mout_mfc0.clk,
 897         [1] = &exynos4_clk_mout_mfc1.clk,
 898 };
 899
 900 static struct clksrc_sources exynos4_clkset_mout_mfc = {
 901         .sources        = exynos4_clkset_mout_mfc_list,
 902         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 903 };
 904
 905 static struct clk *exynos4_clkset_sclk_dac_list[] = {
 906         [0] = &exynos4_clk_sclk_vpll.clk,
 907         [1] = &exynos4_clk_sclk_hdmiphy,
 908 };
 909
 910 static struct clksrc_sources exynos4_clkset_sclk_dac = {
 911         .sources        = exynos4_clkset_sclk_dac_list,
 912         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 913 };
 914
 915 static struct clksrc_clk exynos4_clk_sclk_dac = {
 916         .clk            = {
 917                 .name           = "sclk_dac",
 918                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 919                 .ctrlbit        = (1 << 8),
 920         },
 921         .sources = &exynos4_clkset_sclk_dac,
 922         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 923 };
 924
 925 static struct clksrc_clk exynos4_clk_sclk_pixel = {
 926         .clk            = {
 927                 .name           = "sclk_pixel",
 928                 .parent         = &exynos4_clk_sclk_vpll.clk,
 929         },
 930         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 931 };
 932
 933 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
 934         [0] = &exynos4_clk_sclk_pixel.clk,
 935         [1] = &exynos4_clk_sclk_hdmiphy,
 936 };
 937
 938 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
 939         .sources        = exynos4_clkset_sclk_hdmi_list,
 940         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 941 };
 942
 943 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 944         .clk            = {
 945                 .name           = "sclk_hdmi",
 946                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 947                 .ctrlbit        = (1 << 0),
 948         },
 949         .sources = &exynos4_clkset_sclk_hdmi,
 950         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 951 };
 952
 953 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
 954         [0] = &exynos4_clk_sclk_dac.clk,
 955         [1] = &exynos4_clk_sclk_hdmi.clk,
 956 };
 957
 958 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
 959         .sources        = exynos4_clkset_sclk_mixer_list,
 960         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 961 };
 962
 963 static struct clksrc_clk exynos4_clk_sclk_mixer = {
 964         .clk    = {
 965                 .name           = "sclk_mixer",
 966                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 967                 .ctrlbit        = (1 << 4),
 968         },
 969         .sources = &exynos4_clkset_sclk_mixer,
 970         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 971 };
 972
 973 static struct clksrc_clk *exynos4_sclk_tv[] = {
 974         &exynos4_clk_sclk_dac,
 975         &exynos4_clk_sclk_pixel,
 976         &exynos4_clk_sclk_hdmi,
 977         &exynos4_clk_sclk_mixer,
 978 };
 979
 980 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 981         .clk    = {
 982                 .name           = "dout_mmc0",
 983         },
 984         .sources = &exynos4_clkset_group,
 985         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
 986         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 987 };
 988
 989 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
 990         .clk    = {
 991                 .name           = "dout_mmc1",
 992         },
 993         .sources = &exynos4_clkset_group,
 994         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
 995         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 996 };
 997
 998 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
 999         .clk    = {
1000                 .name           = "dout_mmc2",
1001         },
1002         .sources = &exynos4_clkset_group,
1003         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1004         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1005 };
1006
1007 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1008         .clk    = {
1009                 .name           = "dout_mmc3",
1010         },
1011         .sources = &exynos4_clkset_group,
1012         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1013         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1014 };
1015
1016 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1017         .clk            = {
1018                 .name           = "dout_mmc4",
1019         },
1020         .sources = &exynos4_clkset_group,
1021         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1022         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1023 };
1024
1025 static struct clksrc_clk exynos4_clksrcs[] = {
1026         {
1027                 .clk    = {
1028                         .name           = "sclk_pwm",
1029                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1030                         .ctrlbit        = (1 << 24),
1031                 },
1032                 .sources = &exynos4_clkset_group,
1033                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1034                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1035         }, {
1036                 .clk    = {
1037                         .name           = "sclk_csis",
1038                         .devname        = "s5p-mipi-csis.0",
1039                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1040                         .ctrlbit        = (1 << 24),
1041                 },
1042                 .sources = &exynos4_clkset_group,
1043                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1044                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1045         }, {
1046                 .clk    = {
1047                         .name           = "sclk_csis",
1048                         .devname        = "s5p-mipi-csis.1",
1049                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1050                         .ctrlbit        = (1 << 28),
1051                 },
1052                 .sources = &exynos4_clkset_group,
1053                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1054                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1055         }, {
1056                 .clk    = {
1057                         .name           = "sclk_cam0",
1058                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1059                         .ctrlbit        = (1 << 16),
1060                 },
1061                 .sources = &exynos4_clkset_group,
1062                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1063                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1064         }, {
1065                 .clk    = {
1066                         .name           = "sclk_cam1",
1067                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1068                         .ctrlbit        = (1 << 20),
1069                 },
1070                 .sources = &exynos4_clkset_group,
1071                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1072                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1073         }, {
1074                 .clk    = {
1075                         .name           = "sclk_fimc",
1076                         .devname        = "exynos4-fimc.0",
1077                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1078                         .ctrlbit        = (1 << 0),
1079                 },
1080                 .sources = &exynos4_clkset_group,
1081                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1082                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1083         }, {
1084                 .clk    = {
1085                         .name           = "sclk_fimc",
1086                         .devname        = "exynos4-fimc.1",
1087                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1088                         .ctrlbit        = (1 << 4),
1089                 },
1090                 .sources = &exynos4_clkset_group,
1091                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1092                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1093         }, {
1094                 .clk    = {
1095                         .name           = "sclk_fimc",
1096                         .devname        = "exynos4-fimc.2",
1097                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1098                         .ctrlbit        = (1 << 8),
1099                 },
1100                 .sources = &exynos4_clkset_group,
1101                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1102                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1103         }, {
1104                 .clk    = {
1105                         .name           = "sclk_fimc",
1106                         .devname        = "exynos4-fimc.3",
1107                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1108                         .ctrlbit        = (1 << 12),
1109                 },
1110                 .sources = &exynos4_clkset_group,
1111                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1112                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1113         }, {
1114                 .clk    = {
1115                         .name           = "sclk_fimd",
1116                         .devname        = "exynos4-fb.0",
1117                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1118                         .ctrlbit        = (1 << 0),
1119                 },
1120                 .sources = &exynos4_clkset_group,
1121                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1122                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1123         }, {
1124                 .clk    = {
1125                         .name           = "sclk_mfc",
1126                         .devname        = "s5p-mfc",
1127                 },
1128                 .sources = &exynos4_clkset_mout_mfc,
1129                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1130                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1131         }, {
1132                 .clk    = {
1133                         .name           = "sclk_dwmmc",
1134                         .parent         = &exynos4_clk_dout_mmc4.clk,
1135                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1136                         .ctrlbit        = (1 << 16),
1137                 },
1138                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1139         }
1140 };
1141
1142 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1143         .clk    = {
1144                 .name           = "uclk1",
1145                 .devname        = "exynos4210-uart.0",
1146                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1147                 .ctrlbit        = (1 << 0),
1148         },
1149         .sources = &exynos4_clkset_group,
1150         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1151         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1152 };
1153
1154 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1155         .clk    = {
1156                 .name           = "uclk1",
1157                 .devname        = "exynos4210-uart.1",
1158                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1159                 .ctrlbit        = (1 << 4),
1160         },
1161         .sources = &exynos4_clkset_group,
1162         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1163         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1164 };
1165
1166 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1167         .clk    = {
1168                 .name           = "uclk1",
1169                 .devname        = "exynos4210-uart.2",
1170                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1171                 .ctrlbit        = (1 << 8),
1172         },
1173         .sources = &exynos4_clkset_group,
1174         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1175         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1176 };
1177
1178 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1179         .clk    = {
1180                 .name           = "uclk1",
1181                 .devname        = "exynos4210-uart.3",
1182                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1183                 .ctrlbit        = (1 << 12),
1184         },
1185         .sources = &exynos4_clkset_group,
1186         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1187         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1188 };
1189
1190 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1191         .clk    = {
1192                 .name           = "sclk_mmc",
1193                 .devname        = "exynos4-sdhci.0",
1194                 .parent         = &exynos4_clk_dout_mmc0.clk,
1195                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1196                 .ctrlbit        = (1 << 0),
1197         },
1198         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1199 };
1200
1201 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1202         .clk    = {
1203                 .name           = "sclk_mmc",
1204                 .devname        = "exynos4-sdhci.1",
1205                 .parent         = &exynos4_clk_dout_mmc1.clk,
1206                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1207                 .ctrlbit        = (1 << 4),
1208         },
1209         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1210 };
1211
1212 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1213         .clk    = {
1214                 .name           = "sclk_mmc",
1215                 .devname        = "exynos4-sdhci.2",
1216                 .parent         = &exynos4_clk_dout_mmc2.clk,
1217                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1218                 .ctrlbit        = (1 << 8),
1219         },
1220         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1221 };
1222
1223 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1224         .clk    = {
1225                 .name           = "sclk_mmc",
1226                 .devname        = "exynos4-sdhci.3",
1227                 .parent         = &exynos4_clk_dout_mmc3.clk,
1228                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1229                 .ctrlbit        = (1 << 12),
1230         },
1231         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1232 };
1233
1234 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1235         .clk    = {
1236                 .name           = "mdout_spi",
1237                 .devname        = "exynos4210-spi.0",
1238         },
1239         .sources = &exynos4_clkset_group,
1240         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1241         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1242 };
1243
1244 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1245         .clk    = {
1246                 .name           = "mdout_spi",
1247                 .devname        = "exynos4210-spi.1",
1248         },
1249         .sources = &exynos4_clkset_group,
1250         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1251         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1252 };
1253
1254 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1255         .clk    = {
1256                 .name           = "mdout_spi",
1257                 .devname        = "exynos4210-spi.2",
1258         },
1259         .sources = &exynos4_clkset_group,
1260         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1261         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1262 };
1263
1264 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1265         .clk    = {
1266                 .name           = "sclk_spi",
1267                 .devname        = "exynos4210-spi.0",
1268                 .parent         = &exynos4_clk_mdout_spi0.clk,
1269                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1270                 .ctrlbit        = (1 << 16),
1271         },
1272         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1273 };
1274
1275 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1276         .clk    = {
1277                 .name           = "sclk_spi",
1278                 .devname        = "exynos4210-spi.1",
1279                 .parent         = &exynos4_clk_mdout_spi1.clk,
1280                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1281                 .ctrlbit        = (1 << 20),
1282         },
1283         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1284 };
1285
1286 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1287         .clk    = {
1288                 .name           = "sclk_spi",
1289                 .devname        = "exynos4210-spi.2",
1290                 .parent         = &exynos4_clk_mdout_spi2.clk,
1291                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1292                 .ctrlbit        = (1 << 24),
1293         },
1294         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1295 };
1296
1297 /* Clock initialization code */
1298 static struct clksrc_clk *exynos4_sysclks[] = {
1299         &exynos4_clk_mout_apll,
1300         &exynos4_clk_sclk_apll,
1301         &exynos4_clk_mout_epll,
1302         &exynos4_clk_mout_mpll,
1303         &exynos4_clk_moutcore,
1304         &exynos4_clk_coreclk,
1305         &exynos4_clk_armclk,
1306         &exynos4_clk_aclk_corem0,
1307         &exynos4_clk_aclk_cores,
1308         &exynos4_clk_aclk_corem1,
1309         &exynos4_clk_periphclk,
1310         &exynos4_clk_mout_corebus,
1311         &exynos4_clk_sclk_dmc,
1312         &exynos4_clk_aclk_cored,
1313         &exynos4_clk_aclk_corep,
1314         &exynos4_clk_aclk_acp,
1315         &exynos4_clk_pclk_acp,
1316         &exynos4_clk_vpllsrc,
1317         &exynos4_clk_sclk_vpll,
1318         &exynos4_clk_aclk_200,
1319         &exynos4_clk_aclk_100,
1320         &exynos4_clk_aclk_160,
1321         &exynos4_clk_aclk_133,
1322         &exynos4_clk_dout_mmc0,
1323         &exynos4_clk_dout_mmc1,
1324         &exynos4_clk_dout_mmc2,
1325         &exynos4_clk_dout_mmc3,
1326         &exynos4_clk_dout_mmc4,
1327         &exynos4_clk_mout_mfc0,
1328         &exynos4_clk_mout_mfc1,
1329 };
1330
1331 static struct clk *exynos4_clk_cdev[] = {
1332         &exynos4_clk_pdma0,
1333         &exynos4_clk_pdma1,
1334         &exynos4_clk_mdma1,
1335         &exynos4_clk_fimd0,
1336 };
1337
1338 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1339         &exynos4_clk_sclk_uart0,
1340         &exynos4_clk_sclk_uart1,
1341         &exynos4_clk_sclk_uart2,
1342         &exynos4_clk_sclk_uart3,
1343         &exynos4_clk_sclk_mmc0,
1344         &exynos4_clk_sclk_mmc1,
1345         &exynos4_clk_sclk_mmc2,
1346         &exynos4_clk_sclk_mmc3,
1347         &exynos4_clk_sclk_spi0,
1348         &exynos4_clk_sclk_spi1,
1349         &exynos4_clk_sclk_spi2,
1350         &exynos4_clk_mdout_spi0,
1351         &exynos4_clk_mdout_spi1,
1352         &exynos4_clk_mdout_spi2,
1353 };
1354
1355 static struct clk_lookup exynos4_clk_lookup[] = {
1356         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1357         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1358         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1359         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1360         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1361         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1362         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1363         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1364         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1365         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1366         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1367         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1368         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1369         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1370         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1371 };
1372
1373 static int xtal_rate;
1374
1375 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1376 {
1377         if (soc_is_exynos4210())
1378                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1379                                         pll_4508);
1380         else if (soc_is_exynos4212() || soc_is_exynos4412())
1381                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1382         else
1383                 return 0;
1384 }
1385
1386 static struct clk_ops exynos4_fout_apll_ops = {
1387         .get_rate = exynos4_fout_apll_get_rate,
1388 };
1389
1390 static u32 exynos4_vpll_div[][8] = {
1391         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1392         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1393 };
1394
1395 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1396 {
1397         return clk->rate;
1398 }
1399
1400 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1401 {
1402         unsigned int vpll_con0, vpll_con1 = 0;
1403         unsigned int i;
1404
1405         /* Return if nothing changed */
1406         if (clk->rate == rate)
1407                 return 0;
1408
1409         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1410         vpll_con0 &= ~(0x1 << 27 |                                      \
1411                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1412                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1413                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1414
1415         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1416         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1417                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1418                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1419
1420         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1421                 if (exynos4_vpll_div[i][0] == rate) {
1422                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1423                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1424                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1425                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1426                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1427                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1428                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1429                         break;
1430                 }
1431         }
1432
1433         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1434                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1435                                 __func__);
1436                 return -EINVAL;
1437         }
1438
1439         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1440         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1441
1442         /* Wait for VPLL lock */
1443         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1444                 continue;
1445
1446         clk->rate = rate;
1447         return 0;
1448 }
1449
1450 static struct clk_ops exynos4_vpll_ops = {
1451         .get_rate = exynos4_vpll_get_rate,
1452         .set_rate = exynos4_vpll_set_rate,
1453 };
1454
1455 void __init_or_cpufreq exynos4_setup_clocks(void)
1456 {
1457         struct clk *xtal_clk;
1458         unsigned long apll = 0;
1459         unsigned long mpll = 0;
1460         unsigned long epll = 0;
1461         unsigned long vpll = 0;
1462         unsigned long vpllsrc;
1463         unsigned long xtal;
1464         unsigned long armclk;
1465         unsigned long sclk_dmc;
1466         unsigned long aclk_200;
1467         unsigned long aclk_100;
1468         unsigned long aclk_160;
1469         unsigned long aclk_133;
1470         unsigned int ptr;
1471
1472         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1473
1474         xtal_clk = clk_get(NULL, "xtal");
1475         BUG_ON(IS_ERR(xtal_clk));
1476
1477         xtal = clk_get_rate(xtal_clk);
1478
1479         xtal_rate = xtal;
1480
1481         clk_put(xtal_clk);
1482
1483         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1484
1485         if (soc_is_exynos4210()) {
1486                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1487                                         pll_4508);
1488                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1489                                         pll_4508);
1490                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1491                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1492
1493                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1494                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1495                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1496         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1497                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1498                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1499                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1500                                         __raw_readl(EXYNOS4_EPLL_CON1));
1501
1502                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1503                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1504                                         __raw_readl(EXYNOS4_VPLL_CON1));
1505         } else {
1506                 /* nothing */
1507         }
1508
1509         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1510         clk_fout_mpll.rate = mpll;
1511         clk_fout_epll.rate = epll;
1512         clk_fout_vpll.ops = &exynos4_vpll_ops;
1513         clk_fout_vpll.rate = vpll;
1514
1515         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1516                         apll, mpll, epll, vpll);
1517
1518         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1519         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1520
1521         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1522         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1523         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1524         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1525
1526         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1527                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1528                         armclk, sclk_dmc, aclk_200,
1529                         aclk_100, aclk_160, aclk_133);
1530
1531         clk_f.rate = armclk;
1532         clk_h.rate = sclk_dmc;
1533         clk_p.rate = aclk_100;
1534
1535         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1536                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1537 }
1538
1539 static struct clk *exynos4_clks[] __initdata = {
1540         &exynos4_clk_sclk_hdmi27m,
1541         &exynos4_clk_sclk_hdmiphy,
1542         &exynos4_clk_sclk_usbphy0,
1543         &exynos4_clk_sclk_usbphy1,
1544 };
1545
1546 #ifdef CONFIG_PM_SLEEP
1547 static int exynos4_clock_suspend(void)
1548 {
1549         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1550         return 0;
1551 }
1552
1553 static void exynos4_clock_resume(void)
1554 {
1555         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1556 }
1557
1558 #else
1559 #define exynos4_clock_suspend NULL
1560 #define exynos4_clock_resume NULL
1561 #endif
1562
1563 static struct syscore_ops exynos4_clock_syscore_ops = {
1564         .suspend        = exynos4_clock_suspend,
1565         .resume         = exynos4_clock_resume,
1566 };
1567
1568 void __init exynos4_register_clocks(void)
1569 {
1570         int ptr;
1571
1572         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1573
1574         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1575                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1576
1577         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1578                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1579
1580         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1581                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1582
1583         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1584         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1585
1586         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1587         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1588                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1589
1590         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1591         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1592         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1593
1594         register_syscore_ops(&exynos4_clock_syscore_ops);
1595         s3c24xx_register_clock(&dummy_apb_pclk);
1596
1597         s3c_pwmclk_init();
1598 }