2 * Low-level IRQ helper macros for Cavium Networks platforms
4 * Copyright 2008 Cavium Networks
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
11 #include <mach/hardware.h>
12 #include <asm/hardware/gic.h>
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
22 .macro arch_ret_to_user, tmp1, tmp2
26 * The interrupt numbering scheme is defined in the
27 * interrupt controller spec. To wit:
29 * Interrupts 0-15 are IPI
31 * 29-31 are local. We allow 30 to be used for the watchdog.
33 * 1021-1022 are reserved
34 * 1023 is "spurious" (no interrupt)
36 * For now, we ignore all local interrupts so only return an interrupt if it's
37 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
39 * A simple read from the controller will tell us the number of the highest
40 * priority enabled interrupt. We then just need to check whether it is in the
41 * valid range for an IRQ (30-1020 inclusive).
44 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
46 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
50 bic \irqnr, \irqstat, #0x1c00
59 /* We assume that irqstat (the raw value of the IRQ acknowledge
60 * register) is preserved from the macro above.
61 * If there is an IPI, we immediately signal end of interrupt on the
62 * controller, since this requires the original irqstat value which
63 * we won't easily be able to recreate later.
66 .macro test_for_ipi, irqnr, irqstat, base, tmp
67 bic \irqnr, \irqstat, #0x1c00
69 strcc \irqstat, [\base, #GIC_CPU_EOI]
73 /* As above, this assumes that irqstat and base are preserved.. */
75 .macro test_for_ltirq, irqnr, irqstat, base, tmp
76 bic \irqnr, \irqstat, #0x1c00
80 streq \irqstat, [\base, #GIC_CPU_EOI]