arch/arm/mach-at91/at91sam9rl_devices.c

   1 /*
   2  *  Copyright (C) 2007 Atmel Corporation
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file COPYING in the main directory of this archive for
   6  * more details.
   7  */
   8
   9 #include <asm/mach/arch.h>
  10 #include <asm/mach/map.h>
  11
  12 #include <linux/dma-mapping.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/i2c-gpio.h>
  15
  16 #include <linux/fb.h>
  17 #include <video/atmel_lcdc.h>
  18
  19 #include <asm/arch/board.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/at91sam9rl.h>
  22 #include <asm/arch/at91sam9rl_matrix.h>
  23 #include <asm/arch/at91sam9_smc.h>
  24
  25 #include "generic.h"
  26
  27
  28 /* --------------------------------------------------------------------
  29  *  MMC / SD
  30  * -------------------------------------------------------------------- */
  31
  32 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
  33 static u64 mmc_dmamask = DMA_BIT_MASK(32);
  34 static struct at91_mmc_data mmc_data;
  35
  36 static struct resource mmc_resources[] = {
  37         [0] = {
  38                 .start  = AT91SAM9RL_BASE_MCI,
  39                 .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
  40                 .flags  = IORESOURCE_MEM,
  41         },
  42         [1] = {
  43                 .start  = AT91SAM9RL_ID_MCI,
  44                 .end    = AT91SAM9RL_ID_MCI,
  45                 .flags  = IORESOURCE_IRQ,
  46         },
  47 };
  48
  49 static struct platform_device at91sam9rl_mmc_device = {
  50         .name           = "at91_mci",
  51         .id             = -1,
  52         .dev            = {
  53                                 .dma_mask               = &mmc_dmamask,
  54                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  55                                 .platform_data          = &mmc_data,
  56         },
  57         .resource       = mmc_resources,
  58         .num_resources  = ARRAY_SIZE(mmc_resources),
  59 };
  60
  61 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
  62 {
  63         if (!data)
  64                 return;
  65
  66         /* input/irq */
  67         if (data->det_pin) {
  68                 at91_set_gpio_input(data->det_pin, 1);
  69                 at91_set_deglitch(data->det_pin, 1);
  70         }
  71         if (data->wp_pin)
  72                 at91_set_gpio_input(data->wp_pin, 1);
  73         if (data->vcc_pin)
  74                 at91_set_gpio_output(data->vcc_pin, 0);
  75
  76         /* CLK */
  77         at91_set_A_periph(AT91_PIN_PA2, 0);
  78
  79         /* CMD */
  80         at91_set_A_periph(AT91_PIN_PA1, 1);
  81
  82         /* DAT0, maybe DAT1..DAT3 */
  83         at91_set_A_periph(AT91_PIN_PA0, 1);
  84         if (data->wire4) {
  85                 at91_set_A_periph(AT91_PIN_PA3, 1);
  86                 at91_set_A_periph(AT91_PIN_PA4, 1);
  87                 at91_set_A_periph(AT91_PIN_PA5, 1);
  88         }
  89
  90         mmc_data = *data;
  91         platform_device_register(&at91sam9rl_mmc_device);
  92 }
  93 #else
  94 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  95 #endif
  96
  97
  98 /* --------------------------------------------------------------------
  99  *  NAND / SmartMedia
 100  * -------------------------------------------------------------------- */
 101
 102 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
 103 static struct at91_nand_data nand_data;
 104
 105 #define NAND_BASE       AT91_CHIPSELECT_3
 106
 107 static struct resource nand_resources[] = {
 108         [0] = {
 109                 .start  = NAND_BASE,
 110                 .end    = NAND_BASE + SZ_256M - 1,
 111                 .flags  = IORESOURCE_MEM,
 112         },
 113         [1] = {
 114                 .start  = AT91_BASE_SYS + AT91_ECC,
 115                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
 116                 .flags  = IORESOURCE_MEM,
 117         }
 118 };
 119
 120 static struct platform_device at91_nand_device = {
 121         .name           = "at91_nand",
 122         .id             = -1,
 123         .dev            = {
 124                                 .platform_data  = &nand_data,
 125         },
 126         .resource       = nand_resources,
 127         .num_resources  = ARRAY_SIZE(nand_resources),
 128 };
 129
 130 void __init at91_add_device_nand(struct at91_nand_data *data)
 131 {
 132         unsigned long csa;
 133
 134         if (!data)
 135                 return;
 136
 137         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 138         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 139
 140         /* set the bus interface characteristics */
 141         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
 142                         | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
 143
 144         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
 145                         | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
 146
 147         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
 148
 149         at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
 150
 151         /* enable pin */
 152         if (data->enable_pin)
 153                 at91_set_gpio_output(data->enable_pin, 1);
 154
 155         /* ready/busy pin */
 156         if (data->rdy_pin)
 157                 at91_set_gpio_input(data->rdy_pin, 1);
 158
 159         /* card detect pin */
 160         if (data->det_pin)
 161                 at91_set_gpio_input(data->det_pin, 1);
 162
 163         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
 164         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
 165
 166         nand_data = *data;
 167         platform_device_register(&at91_nand_device);
 168 }
 169
 170 #else
 171 void __init at91_add_device_nand(struct at91_nand_data *data) {}
 172 #endif
 173
 174
 175 /* --------------------------------------------------------------------
 176  *  TWI (i2c)
 177  * -------------------------------------------------------------------- */
 178
 179 /*
 180  * Prefer the GPIO code since the TWI controller isn't robust
 181  * (gets overruns and underruns under load) and can only issue
 182  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 183  */
 184 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 185
 186 static struct i2c_gpio_platform_data pdata = {
 187         .sda_pin                = AT91_PIN_PA23,
 188         .sda_is_open_drain      = 1,
 189         .scl_pin                = AT91_PIN_PA24,
 190         .scl_is_open_drain      = 1,
 191         .udelay                 = 2,            /* ~100 kHz */
 192 };
 193
 194 static struct platform_device at91sam9rl_twi_device = {
 195         .name                   = "i2c-gpio",
 196         .id                     = -1,
 197         .dev.platform_data      = &pdata,
 198 };
 199
 200 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 201 {
 202         at91_set_GPIO_periph(AT91_PIN_PA23, 1);         /* TWD (SDA) */
 203         at91_set_multi_drive(AT91_PIN_PA23, 1);
 204
 205         at91_set_GPIO_periph(AT91_PIN_PA24, 1);         /* TWCK (SCL) */
 206         at91_set_multi_drive(AT91_PIN_PA24, 1);
 207
 208         i2c_register_board_info(0, devices, nr_devices);
 209         platform_device_register(&at91sam9rl_twi_device);
 210 }
 211
 212 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 213
 214 static struct resource twi_resources[] = {
 215         [0] = {
 216                 .start  = AT91SAM9RL_BASE_TWI0,
 217                 .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
 218                 .flags  = IORESOURCE_MEM,
 219         },
 220         [1] = {
 221                 .start  = AT91SAM9RL_ID_TWI0,
 222                 .end    = AT91SAM9RL_ID_TWI0,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct platform_device at91sam9rl_twi_device = {
 228         .name           = "at91_i2c",
 229         .id             = -1,
 230         .resource       = twi_resources,
 231         .num_resources  = ARRAY_SIZE(twi_resources),
 232 };
 233
 234 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 235 {
 236         /* pins used for TWI interface */
 237         at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
 238         at91_set_multi_drive(AT91_PIN_PA23, 1);
 239
 240         at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
 241         at91_set_multi_drive(AT91_PIN_PA24, 1);
 242
 243         i2c_register_board_info(0, devices, nr_devices);
 244         platform_device_register(&at91sam9rl_twi_device);
 245 }
 246 #else
 247 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
 248 #endif
 249
 250
 251 /* --------------------------------------------------------------------
 252  *  SPI
 253  * -------------------------------------------------------------------- */
 254
 255 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 256 static u64 spi_dmamask = DMA_BIT_MASK(32);
 257
 258 static struct resource spi_resources[] = {
 259         [0] = {
 260                 .start  = AT91SAM9RL_BASE_SPI,
 261                 .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
 262                 .flags  = IORESOURCE_MEM,
 263         },
 264         [1] = {
 265                 .start  = AT91SAM9RL_ID_SPI,
 266                 .end    = AT91SAM9RL_ID_SPI,
 267                 .flags  = IORESOURCE_IRQ,
 268         },
 269 };
 270
 271 static struct platform_device at91sam9rl_spi_device = {
 272         .name           = "atmel_spi",
 273         .id             = 0,
 274         .dev            = {
 275                                 .dma_mask               = &spi_dmamask,
 276                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 277         },
 278         .resource       = spi_resources,
 279         .num_resources  = ARRAY_SIZE(spi_resources),
 280 };
 281
 282 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
 283
 284
 285 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 286 {
 287         int i;
 288         unsigned long cs_pin;
 289
 290         at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
 291         at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
 292         at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
 293
 294         /* Enable SPI chip-selects */
 295         for (i = 0; i < nr_devices; i++) {
 296                 if (devices[i].controller_data)
 297                         cs_pin = (unsigned long) devices[i].controller_data;
 298                 else
 299                         cs_pin = spi_standard_cs[devices[i].chip_select];
 300
 301                 /* enable chip-select pin */
 302                 at91_set_gpio_output(cs_pin, 1);
 303
 304                 /* pass chip-select pin to driver */
 305                 devices[i].controller_data = (void *) cs_pin;
 306         }
 307
 308         spi_register_board_info(devices, nr_devices);
 309         platform_device_register(&at91sam9rl_spi_device);
 310 }
 311 #else
 312 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 313 #endif
 314
 315
 316 /* --------------------------------------------------------------------
 317  *  LCD Controller
 318  * -------------------------------------------------------------------- */
 319
 320 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 321 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 322 static struct atmel_lcdfb_info lcdc_data;
 323
 324 static struct resource lcdc_resources[] = {
 325         [0] = {
 326                 .start  = AT91SAM9RL_LCDC_BASE,
 327                 .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
 328                 .flags  = IORESOURCE_MEM,
 329         },
 330         [1] = {
 331                 .start  = AT91SAM9RL_ID_LCDC,
 332                 .end    = AT91SAM9RL_ID_LCDC,
 333                 .flags  = IORESOURCE_IRQ,
 334         },
 335 };
 336
 337 static struct platform_device at91_lcdc_device = {
 338         .name           = "atmel_lcdfb",
 339         .id             = 0,
 340         .dev            = {
 341                                 .dma_mask               = &lcdc_dmamask,
 342                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 343                                 .platform_data          = &lcdc_data,
 344         },
 345         .resource       = lcdc_resources,
 346         .num_resources  = ARRAY_SIZE(lcdc_resources),
 347 };
 348
 349 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 350 {
 351         if (!data) {
 352                 return;
 353         }
 354
 355         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 356         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 357         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 358         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 359         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 360         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 361         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 362         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 363         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 364         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 365         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 366         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 367         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 368         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 369         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 370         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 371         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 372         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 373         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 374         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 375         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 376
 377         lcdc_data = *data;
 378         platform_device_register(&at91_lcdc_device);
 379 }
 380 #else
 381 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 382 #endif
 383
 384
 385 /* --------------------------------------------------------------------
 386  *  Timer/Counter block
 387  * -------------------------------------------------------------------- */
 388
 389 #ifdef CONFIG_ATMEL_TCLIB
 390
 391 static struct resource tcb_resources[] = {
 392         [0] = {
 393                 .start  = AT91SAM9RL_BASE_TCB0,
 394                 .end    = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
 395                 .flags  = IORESOURCE_MEM,
 396         },
 397         [1] = {
 398                 .start  = AT91SAM9RL_ID_TC0,
 399                 .end    = AT91SAM9RL_ID_TC0,
 400                 .flags  = IORESOURCE_IRQ,
 401         },
 402         [2] = {
 403                 .start  = AT91SAM9RL_ID_TC1,
 404                 .end    = AT91SAM9RL_ID_TC1,
 405                 .flags  = IORESOURCE_IRQ,
 406         },
 407         [3] = {
 408                 .start  = AT91SAM9RL_ID_TC2,
 409                 .end    = AT91SAM9RL_ID_TC2,
 410                 .flags  = IORESOURCE_IRQ,
 411         },
 412 };
 413
 414 static struct platform_device at91sam9rl_tcb_device = {
 415         .name           = "atmel_tcb",
 416         .id             = 0,
 417         .resource       = tcb_resources,
 418         .num_resources  = ARRAY_SIZE(tcb_resources),
 419 };
 420
 421 static void __init at91_add_device_tc(void)
 422 {
 423         /* this chip has a separate clock and irq for each TC channel */
 424         at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
 425         at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
 426         at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
 427         platform_device_register(&at91sam9rl_tcb_device);
 428 }
 429 #else
 430 static void __init at91_add_device_tc(void) { }
 431 #endif
 432
 433
 434 /* --------------------------------------------------------------------
 435  *  RTC
 436  * -------------------------------------------------------------------- */
 437
 438 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
 439 static struct platform_device at91sam9rl_rtc_device = {
 440         .name           = "at91_rtc",
 441         .id             = -1,
 442         .num_resources  = 0,
 443 };
 444
 445 static void __init at91_add_device_rtc(void)
 446 {
 447         platform_device_register(&at91sam9rl_rtc_device);
 448 }
 449 #else
 450 static void __init at91_add_device_rtc(void) {}
 451 #endif
 452
 453
 454 /* --------------------------------------------------------------------
 455  *  RTT
 456  * -------------------------------------------------------------------- */
 457
 458 static struct resource rtt_resources[] = {
 459         {
 460                 .start  = AT91_BASE_SYS + AT91_RTT,
 461                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
 462                 .flags  = IORESOURCE_MEM,
 463         }
 464 };
 465
 466 static struct platform_device at91sam9rl_rtt_device = {
 467         .name           = "at91_rtt",
 468         .id             = 0,
 469         .resource       = rtt_resources,
 470         .num_resources  = ARRAY_SIZE(rtt_resources),
 471 };
 472
 473 static void __init at91_add_device_rtt(void)
 474 {
 475         platform_device_register(&at91sam9rl_rtt_device);
 476 }
 477
 478
 479 /* --------------------------------------------------------------------
 480  *  Watchdog
 481  * -------------------------------------------------------------------- */
 482
 483 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
 484 static struct platform_device at91sam9rl_wdt_device = {
 485         .name           = "at91_wdt",
 486         .id             = -1,
 487         .num_resources  = 0,
 488 };
 489
 490 static void __init at91_add_device_watchdog(void)
 491 {
 492         platform_device_register(&at91sam9rl_wdt_device);
 493 }
 494 #else
 495 static void __init at91_add_device_watchdog(void) {}
 496 #endif
 497
 498
 499 /* --------------------------------------------------------------------
 500  *  SSC -- Synchronous Serial Controller
 501  * -------------------------------------------------------------------- */
 502
 503 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
 504 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
 505
 506 static struct resource ssc0_resources[] = {
 507         [0] = {
 508                 .start  = AT91SAM9RL_BASE_SSC0,
 509                 .end    = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
 510                 .flags  = IORESOURCE_MEM,
 511         },
 512         [1] = {
 513                 .start  = AT91SAM9RL_ID_SSC0,
 514                 .end    = AT91SAM9RL_ID_SSC0,
 515                 .flags  = IORESOURCE_IRQ,
 516         },
 517 };
 518
 519 static struct platform_device at91sam9rl_ssc0_device = {
 520         .name   = "ssc",
 521         .id     = 0,
 522         .dev    = {
 523                 .dma_mask               = &ssc0_dmamask,
 524                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 525         },
 526         .resource       = ssc0_resources,
 527         .num_resources  = ARRAY_SIZE(ssc0_resources),
 528 };
 529
 530 static inline void configure_ssc0_pins(unsigned pins)
 531 {
 532         if (pins & ATMEL_SSC_TF)
 533                 at91_set_A_periph(AT91_PIN_PC0, 1);
 534         if (pins & ATMEL_SSC_TK)
 535                 at91_set_A_periph(AT91_PIN_PC1, 1);
 536         if (pins & ATMEL_SSC_TD)
 537                 at91_set_A_periph(AT91_PIN_PA15, 1);
 538         if (pins & ATMEL_SSC_RD)
 539                 at91_set_A_periph(AT91_PIN_PA16, 1);
 540         if (pins & ATMEL_SSC_RK)
 541                 at91_set_B_periph(AT91_PIN_PA10, 1);
 542         if (pins & ATMEL_SSC_RF)
 543                 at91_set_B_periph(AT91_PIN_PA22, 1);
 544 }
 545
 546 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
 547
 548 static struct resource ssc1_resources[] = {
 549         [0] = {
 550                 .start  = AT91SAM9RL_BASE_SSC1,
 551                 .end    = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
 552                 .flags  = IORESOURCE_MEM,
 553         },
 554         [1] = {
 555                 .start  = AT91SAM9RL_ID_SSC1,
 556                 .end    = AT91SAM9RL_ID_SSC1,
 557                 .flags  = IORESOURCE_IRQ,
 558         },
 559 };
 560
 561 static struct platform_device at91sam9rl_ssc1_device = {
 562         .name   = "ssc",
 563         .id     = 1,
 564         .dev    = {
 565                 .dma_mask               = &ssc1_dmamask,
 566                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 567         },
 568         .resource       = ssc1_resources,
 569         .num_resources  = ARRAY_SIZE(ssc1_resources),
 570 };
 571
 572 static inline void configure_ssc1_pins(unsigned pins)
 573 {
 574         if (pins & ATMEL_SSC_TF)
 575                 at91_set_B_periph(AT91_PIN_PA29, 1);
 576         if (pins & ATMEL_SSC_TK)
 577                 at91_set_B_periph(AT91_PIN_PA30, 1);
 578         if (pins & ATMEL_SSC_TD)
 579                 at91_set_B_periph(AT91_PIN_PA13, 1);
 580         if (pins & ATMEL_SSC_RD)
 581                 at91_set_B_periph(AT91_PIN_PA14, 1);
 582         if (pins & ATMEL_SSC_RK)
 583                 at91_set_B_periph(AT91_PIN_PA9, 1);
 584         if (pins & ATMEL_SSC_RF)
 585                 at91_set_B_periph(AT91_PIN_PA8, 1);
 586 }
 587
 588 /*
 589  * SSC controllers are accessed through library code, instead of any
 590  * kind of all-singing/all-dancing driver.  For example one could be
 591  * used by a particular I2S audio codec's driver, while another one
 592  * on the same system might be used by a custom data capture driver.
 593  */
 594 void __init at91_add_device_ssc(unsigned id, unsigned pins)
 595 {
 596         struct platform_device *pdev;
 597
 598         /*
 599          * NOTE: caller is responsible for passing information matching
 600          * "pins" to whatever will be using each particular controller.
 601          */
 602         switch (id) {
 603         case AT91SAM9RL_ID_SSC0:
 604                 pdev = &at91sam9rl_ssc0_device;
 605                 configure_ssc0_pins(pins);
 606                 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
 607                 break;
 608         case AT91SAM9RL_ID_SSC1:
 609                 pdev = &at91sam9rl_ssc1_device;
 610                 configure_ssc1_pins(pins);
 611                 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
 612                 break;
 613         default:
 614                 return;
 615         }
 616
 617         platform_device_register(pdev);
 618 }
 619
 620 #else
 621 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 622 #endif
 623
 624
 625 /* --------------------------------------------------------------------
 626  *  UART
 627  * -------------------------------------------------------------------- */
 628
 629 #if defined(CONFIG_SERIAL_ATMEL)
 630 static struct resource dbgu_resources[] = {
 631         [0] = {
 632                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
 633                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
 634                 .flags  = IORESOURCE_MEM,
 635         },
 636         [1] = {
 637                 .start  = AT91_ID_SYS,
 638                 .end    = AT91_ID_SYS,
 639                 .flags  = IORESOURCE_IRQ,
 640         },
 641 };
 642
 643 static struct atmel_uart_data dbgu_data = {
 644         .use_dma_tx     = 0,
 645         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
 646         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
 647 };
 648
 649 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
 650
 651 static struct platform_device at91sam9rl_dbgu_device = {
 652         .name           = "atmel_usart",
 653         .id             = 0,
 654         .dev            = {
 655                                 .dma_mask               = &dbgu_dmamask,
 656                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 657                                 .platform_data          = &dbgu_data,
 658         },
 659         .resource       = dbgu_resources,
 660         .num_resources  = ARRAY_SIZE(dbgu_resources),
 661 };
 662
 663 static inline void configure_dbgu_pins(void)
 664 {
 665         at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
 666         at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
 667 }
 668
 669 static struct resource uart0_resources[] = {
 670         [0] = {
 671                 .start  = AT91SAM9RL_BASE_US0,
 672                 .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
 673                 .flags  = IORESOURCE_MEM,
 674         },
 675         [1] = {
 676                 .start  = AT91SAM9RL_ID_US0,
 677                 .end    = AT91SAM9RL_ID_US0,
 678                 .flags  = IORESOURCE_IRQ,
 679         },
 680 };
 681
 682 static struct atmel_uart_data uart0_data = {
 683         .use_dma_tx     = 1,
 684         .use_dma_rx     = 1,
 685 };
 686
 687 static u64 uart0_dmamask = DMA_BIT_MASK(32);
 688
 689 static struct platform_device at91sam9rl_uart0_device = {
 690         .name           = "atmel_usart",
 691         .id             = 1,
 692         .dev            = {
 693                                 .dma_mask               = &uart0_dmamask,
 694                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 695                                 .platform_data          = &uart0_data,
 696         },
 697         .resource       = uart0_resources,
 698         .num_resources  = ARRAY_SIZE(uart0_resources),
 699 };
 700
 701 static inline void configure_usart0_pins(unsigned pins)
 702 {
 703         at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
 704         at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
 705
 706         if (pins & ATMEL_UART_RTS)
 707                 at91_set_A_periph(AT91_PIN_PA9, 0);     /* RTS0 */
 708         if (pins & ATMEL_UART_CTS)
 709                 at91_set_A_periph(AT91_PIN_PA10, 0);    /* CTS0 */
 710         if (pins & ATMEL_UART_DSR)
 711                 at91_set_A_periph(AT91_PIN_PD14, 0);    /* DSR0 */
 712         if (pins & ATMEL_UART_DTR)
 713                 at91_set_A_periph(AT91_PIN_PD15, 0);    /* DTR0 */
 714         if (pins & ATMEL_UART_DCD)
 715                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* DCD0 */
 716         if (pins & ATMEL_UART_RI)
 717                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* RI0 */
 718 }
 719
 720 static struct resource uart1_resources[] = {
 721         [0] = {
 722                 .start  = AT91SAM9RL_BASE_US1,
 723                 .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
 724                 .flags  = IORESOURCE_MEM,
 725         },
 726         [1] = {
 727                 .start  = AT91SAM9RL_ID_US1,
 728                 .end    = AT91SAM9RL_ID_US1,
 729                 .flags  = IORESOURCE_IRQ,
 730         },
 731 };
 732
 733 static struct atmel_uart_data uart1_data = {
 734         .use_dma_tx     = 1,
 735         .use_dma_rx     = 1,
 736 };
 737
 738 static u64 uart1_dmamask = DMA_BIT_MASK(32);
 739
 740 static struct platform_device at91sam9rl_uart1_device = {
 741         .name           = "atmel_usart",
 742         .id             = 2,
 743         .dev            = {
 744                                 .dma_mask               = &uart1_dmamask,
 745                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 746                                 .platform_data          = &uart1_data,
 747         },
 748         .resource       = uart1_resources,
 749         .num_resources  = ARRAY_SIZE(uart1_resources),
 750 };
 751
 752 static inline void configure_usart1_pins(unsigned pins)
 753 {
 754         at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
 755         at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
 756
 757         if (pins & ATMEL_UART_RTS)
 758                 at91_set_B_periph(AT91_PIN_PA18, 0);    /* RTS1 */
 759         if (pins & ATMEL_UART_CTS)
 760                 at91_set_B_periph(AT91_PIN_PA19, 0);    /* CTS1 */
 761 }
 762
 763 static struct resource uart2_resources[] = {
 764         [0] = {
 765                 .start  = AT91SAM9RL_BASE_US2,
 766                 .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
 767                 .flags  = IORESOURCE_MEM,
 768         },
 769         [1] = {
 770                 .start  = AT91SAM9RL_ID_US2,
 771                 .end    = AT91SAM9RL_ID_US2,
 772                 .flags  = IORESOURCE_IRQ,
 773         },
 774 };
 775
 776 static struct atmel_uart_data uart2_data = {
 777         .use_dma_tx     = 1,
 778         .use_dma_rx     = 1,
 779 };
 780
 781 static u64 uart2_dmamask = DMA_BIT_MASK(32);
 782
 783 static struct platform_device at91sam9rl_uart2_device = {
 784         .name           = "atmel_usart",
 785         .id             = 3,
 786         .dev            = {
 787                                 .dma_mask               = &uart2_dmamask,
 788                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 789                                 .platform_data          = &uart2_data,
 790         },
 791         .resource       = uart2_resources,
 792         .num_resources  = ARRAY_SIZE(uart2_resources),
 793 };
 794
 795 static inline void configure_usart2_pins(unsigned pins)
 796 {
 797         at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
 798         at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
 799
 800         if (pins & ATMEL_UART_RTS)
 801                 at91_set_A_periph(AT91_PIN_PA29, 0);    /* RTS2 */
 802         if (pins & ATMEL_UART_CTS)
 803                 at91_set_A_periph(AT91_PIN_PA30, 0);    /* CTS2 */
 804 }
 805
 806 static struct resource uart3_resources[] = {
 807         [0] = {
 808                 .start  = AT91SAM9RL_BASE_US3,
 809                 .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
 810                 .flags  = IORESOURCE_MEM,
 811         },
 812         [1] = {
 813                 .start  = AT91SAM9RL_ID_US3,
 814                 .end    = AT91SAM9RL_ID_US3,
 815                 .flags  = IORESOURCE_IRQ,
 816         },
 817 };
 818
 819 static struct atmel_uart_data uart3_data = {
 820         .use_dma_tx     = 1,
 821         .use_dma_rx     = 1,
 822 };
 823
 824 static u64 uart3_dmamask = DMA_BIT_MASK(32);
 825
 826 static struct platform_device at91sam9rl_uart3_device = {
 827         .name           = "atmel_usart",
 828         .id             = 4,
 829         .dev            = {
 830                                 .dma_mask               = &uart3_dmamask,
 831                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 832                                 .platform_data          = &uart3_data,
 833         },
 834         .resource       = uart3_resources,
 835         .num_resources  = ARRAY_SIZE(uart3_resources),
 836 };
 837
 838 static inline void configure_usart3_pins(unsigned pins)
 839 {
 840         at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
 841         at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
 842
 843         if (pins & ATMEL_UART_RTS)
 844                 at91_set_B_periph(AT91_PIN_PD4, 0);     /* RTS3 */
 845         if (pins & ATMEL_UART_CTS)
 846                 at91_set_B_periph(AT91_PIN_PD3, 0);     /* CTS3 */
 847 }
 848
 849 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 850 struct platform_device *atmel_default_console_device;   /* the serial console device */
 851
 852 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 853 {
 854         struct platform_device *pdev;
 855
 856         switch (id) {
 857                 case 0:         /* DBGU */
 858                         pdev = &at91sam9rl_dbgu_device;
 859                         configure_dbgu_pins();
 860                         at91_clock_associate("mck", &pdev->dev, "usart");
 861                         break;
 862                 case AT91SAM9RL_ID_US0:
 863                         pdev = &at91sam9rl_uart0_device;
 864                         configure_usart0_pins(pins);
 865                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
 866                         break;
 867                 case AT91SAM9RL_ID_US1:
 868                         pdev = &at91sam9rl_uart1_device;
 869                         configure_usart1_pins(pins);
 870                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
 871                         break;
 872                 case AT91SAM9RL_ID_US2:
 873                         pdev = &at91sam9rl_uart2_device;
 874                         configure_usart2_pins(pins);
 875                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
 876                         break;
 877                 case AT91SAM9RL_ID_US3:
 878                         pdev = &at91sam9rl_uart3_device;
 879                         configure_usart3_pins(pins);
 880                         at91_clock_associate("usart3_clk", &pdev->dev, "usart");
 881                         break;
 882                 default:
 883                         return;
 884         }
 885         pdev->id = portnr;              /* update to mapped ID */
 886
 887         if (portnr < ATMEL_MAX_UART)
 888                 at91_uarts[portnr] = pdev;
 889 }
 890
 891 void __init at91_set_serial_console(unsigned portnr)
 892 {
 893         if (portnr < ATMEL_MAX_UART)
 894                 atmel_default_console_device = at91_uarts[portnr];
 895 }
 896
 897 void __init at91_add_device_serial(void)
 898 {
 899         int i;
 900
 901         for (i = 0; i < ATMEL_MAX_UART; i++) {
 902                 if (at91_uarts[i])
 903                         platform_device_register(at91_uarts[i]);
 904         }
 905
 906         if (!atmel_default_console_device)
 907                 printk(KERN_INFO "AT91: No default serial console defined.\n");
 908 }
 909 #else
 910 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 911 void __init at91_set_serial_console(unsigned portnr) {}
 912 void __init at91_add_device_serial(void) {}
 913 #endif
 914
 915
 916 /* -------------------------------------------------------------------- */
 917
 918 /*
 919  * These devices are always present and don't need any board-specific
 920  * setup.
 921  */
 922 static int __init at91_add_standard_devices(void)
 923 {
 924         at91_add_device_rtc();
 925         at91_add_device_rtt();
 926         at91_add_device_watchdog();
 927         at91_add_device_tc();
 928         return 0;
 929 }
 930
 931 arch_initcall(at91_add_standard_devices);