arch/arm/mach-at91/at91sam9g45_devices.c

   1 /*
   2  *  On-Chip devices setup code for the AT91SAM9G45 family
   3  *
   4  *  Copyright (C) 2009 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12 #include <asm/mach/arch.h>
  13 #include <asm/mach/map.h>
  14
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/i2c-gpio.h>
  19 #include <linux/atmel-mci.h>
  20
  21 #include <linux/fb.h>
  22 #include <video/atmel_lcdc.h>
  23
  24 #include <mach/board.h>
  25 #include <mach/at91sam9g45.h>
  26 #include <mach/at91sam9g45_matrix.h>
  27 #include <mach/at91sam9_smc.h>
  28 #include <mach/at_hdmac.h>
  29 #include <mach/atmel-mci.h>
  30
  31 #include "generic.h"
  32
  33
  34 /* --------------------------------------------------------------------
  35  *  HDMAC - AHB DMA Controller
  36  * -------------------------------------------------------------------- */
  37
  38 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
  39 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
  40
  41 static struct at_dma_platform_data atdma_pdata = {
  42         .nr_channels    = 8,
  43 };
  44
  45 static struct resource hdmac_resources[] = {
  46         [0] = {
  47                 .start  = AT91_BASE_SYS + AT91_DMA,
  48                 .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
  49                 .flags  = IORESOURCE_MEM,
  50         },
  51         [1] = {
  52                 .start  = AT91SAM9G45_ID_DMA,
  53                 .end    = AT91SAM9G45_ID_DMA,
  54                 .flags  = IORESOURCE_IRQ,
  55         },
  56 };
  57
  58 static struct platform_device at_hdmac_device = {
  59         .name           = "at_hdmac",
  60         .id             = -1,
  61         .dev            = {
  62                                 .dma_mask               = &hdmac_dmamask,
  63                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  64                                 .platform_data          = &atdma_pdata,
  65         },
  66         .resource       = hdmac_resources,
  67         .num_resources  = ARRAY_SIZE(hdmac_resources),
  68 };
  69
  70 void __init at91_add_device_hdmac(void)
  71 {
  72         dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
  73         dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
  74         platform_device_register(&at_hdmac_device);
  75 }
  76 #else
  77 void __init at91_add_device_hdmac(void) {}
  78 #endif
  79
  80
  81 /* --------------------------------------------------------------------
  82  *  USB Host (OHCI)
  83  * -------------------------------------------------------------------- */
  84
  85 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  86 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  87 static struct at91_usbh_data usbh_ohci_data;
  88
  89 static struct resource usbh_ohci_resources[] = {
  90         [0] = {
  91                 .start  = AT91SAM9G45_OHCI_BASE,
  92                 .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = AT91SAM9G45_ID_UHPHS,
  97                 .end    = AT91SAM9G45_ID_UHPHS,
  98                 .flags  = IORESOURCE_IRQ,
  99         },
 100 };
 101
 102 static struct platform_device at91_usbh_ohci_device = {
 103         .name           = "at91_ohci",
 104         .id             = -1,
 105         .dev            = {
 106                                 .dma_mask               = &ohci_dmamask,
 107                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 108                                 .platform_data          = &usbh_ohci_data,
 109         },
 110         .resource       = usbh_ohci_resources,
 111         .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
 112 };
 113
 114 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 115 {
 116         int i;
 117
 118         if (!data)
 119                 return;
 120
 121         /* Enable VBus control for UHP ports */
 122         for (i = 0; i < data->ports; i++) {
 123                 if (data->vbus_pin[i])
 124                         at91_set_gpio_output(data->vbus_pin[i], 0);
 125         }
 126
 127         /* Enable overcurrent notification */
 128         for (i = 0; i < data->ports; i++) {
 129                 if (data->overcurrent_pin[i])
 130                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
 131         }
 132
 133         usbh_ohci_data = *data;
 134         platform_device_register(&at91_usbh_ohci_device);
 135 }
 136 #else
 137 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
 138 #endif
 139
 140
 141 /* --------------------------------------------------------------------
 142  *  USB Host HS (EHCI)
 143  *  Needs an OHCI host for low and full speed management
 144  * -------------------------------------------------------------------- */
 145
 146 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
 147 static u64 ehci_dmamask = DMA_BIT_MASK(32);
 148 static struct at91_usbh_data usbh_ehci_data;
 149
 150 static struct resource usbh_ehci_resources[] = {
 151         [0] = {
 152                 .start  = AT91SAM9G45_EHCI_BASE,
 153                 .end    = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
 154                 .flags  = IORESOURCE_MEM,
 155         },
 156         [1] = {
 157                 .start  = AT91SAM9G45_ID_UHPHS,
 158                 .end    = AT91SAM9G45_ID_UHPHS,
 159                 .flags  = IORESOURCE_IRQ,
 160         },
 161 };
 162
 163 static struct platform_device at91_usbh_ehci_device = {
 164         .name           = "atmel-ehci",
 165         .id             = -1,
 166         .dev            = {
 167                                 .dma_mask               = &ehci_dmamask,
 168                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 169                                 .platform_data          = &usbh_ehci_data,
 170         },
 171         .resource       = usbh_ehci_resources,
 172         .num_resources  = ARRAY_SIZE(usbh_ehci_resources),
 173 };
 174
 175 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
 176 {
 177         int i;
 178
 179         if (!data)
 180                 return;
 181
 182         /* Enable VBus control for UHP ports */
 183         for (i = 0; i < data->ports; i++) {
 184                 if (data->vbus_pin[i])
 185                         at91_set_gpio_output(data->vbus_pin[i], 0);
 186         }
 187
 188         usbh_ehci_data = *data;
 189         platform_device_register(&at91_usbh_ehci_device);
 190 }
 191 #else
 192 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
 193 #endif
 194
 195
 196 /* --------------------------------------------------------------------
 197  *  USB HS Device (Gadget)
 198  * -------------------------------------------------------------------- */
 199
 200 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
 201 static struct resource usba_udc_resources[] = {
 202         [0] = {
 203                 .start  = AT91SAM9G45_UDPHS_FIFO,
 204                 .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
 205                 .flags  = IORESOURCE_MEM,
 206         },
 207         [1] = {
 208                 .start  = AT91SAM9G45_BASE_UDPHS,
 209                 .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
 210                 .flags  = IORESOURCE_MEM,
 211         },
 212         [2] = {
 213                 .start  = AT91SAM9G45_ID_UDPHS,
 214                 .end    = AT91SAM9G45_ID_UDPHS,
 215                 .flags  = IORESOURCE_IRQ,
 216         },
 217 };
 218
 219 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
 220         [idx] = {                                               \
 221                 .name           = nam,                          \
 222                 .index          = idx,                          \
 223                 .fifo_size      = maxpkt,                       \
 224                 .nr_banks       = maxbk,                        \
 225                 .can_dma        = dma,                          \
 226                 .can_isoc       = isoc,                         \
 227         }
 228
 229 static struct usba_ep_data usba_udc_ep[] __initdata = {
 230         EP("ep0", 0, 64, 1, 0, 0),
 231         EP("ep1", 1, 1024, 2, 1, 1),
 232         EP("ep2", 2, 1024, 2, 1, 1),
 233         EP("ep3", 3, 1024, 3, 1, 0),
 234         EP("ep4", 4, 1024, 3, 1, 0),
 235         EP("ep5", 5, 1024, 3, 1, 1),
 236         EP("ep6", 6, 1024, 3, 1, 1),
 237 };
 238
 239 #undef EP
 240
 241 /*
 242  * pdata doesn't have room for any endpoints, so we need to
 243  * append room for the ones we need right after it.
 244  */
 245 static struct {
 246         struct usba_platform_data pdata;
 247         struct usba_ep_data ep[7];
 248 } usba_udc_data;
 249
 250 static struct platform_device at91_usba_udc_device = {
 251         .name           = "atmel_usba_udc",
 252         .id             = -1,
 253         .dev            = {
 254                                 .platform_data  = &usba_udc_data.pdata,
 255         },
 256         .resource       = usba_udc_resources,
 257         .num_resources  = ARRAY_SIZE(usba_udc_resources),
 258 };
 259
 260 void __init at91_add_device_usba(struct usba_platform_data *data)
 261 {
 262         usba_udc_data.pdata.vbus_pin = -EINVAL;
 263         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
 264         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 265
 266         if (data && data->vbus_pin > 0) {
 267                 at91_set_gpio_input(data->vbus_pin, 0);
 268                 at91_set_deglitch(data->vbus_pin, 1);
 269                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
 270         }
 271
 272         /* Pullup pin is handled internally by USB device peripheral */
 273
 274         platform_device_register(&at91_usba_udc_device);
 275 }
 276 #else
 277 void __init at91_add_device_usba(struct usba_platform_data *data) {}
 278 #endif
 279
 280
 281 /* --------------------------------------------------------------------
 282  *  Ethernet
 283  * -------------------------------------------------------------------- */
 284
 285 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 286 static u64 eth_dmamask = DMA_BIT_MASK(32);
 287 static struct at91_eth_data eth_data;
 288
 289 static struct resource eth_resources[] = {
 290         [0] = {
 291                 .start  = AT91SAM9G45_BASE_EMAC,
 292                 .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
 293                 .flags  = IORESOURCE_MEM,
 294         },
 295         [1] = {
 296                 .start  = AT91SAM9G45_ID_EMAC,
 297                 .end    = AT91SAM9G45_ID_EMAC,
 298                 .flags  = IORESOURCE_IRQ,
 299         },
 300 };
 301
 302 static struct platform_device at91sam9g45_eth_device = {
 303         .name           = "macb",
 304         .id             = -1,
 305         .dev            = {
 306                                 .dma_mask               = &eth_dmamask,
 307                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 308                                 .platform_data          = &eth_data,
 309         },
 310         .resource       = eth_resources,
 311         .num_resources  = ARRAY_SIZE(eth_resources),
 312 };
 313
 314 void __init at91_add_device_eth(struct at91_eth_data *data)
 315 {
 316         if (!data)
 317                 return;
 318
 319         if (data->phy_irq_pin) {
 320                 at91_set_gpio_input(data->phy_irq_pin, 0);
 321                 at91_set_deglitch(data->phy_irq_pin, 1);
 322         }
 323
 324         /* Pins used for MII and RMII */
 325         at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
 326         at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
 327         at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
 328         at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
 329         at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
 330         at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
 331         at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
 332         at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
 333         at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
 334         at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
 335
 336         if (!data->is_rmii) {
 337                 at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
 338                 at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
 339                 at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
 340                 at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
 341                 at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
 342                 at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
 343                 at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
 344                 at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
 345         }
 346
 347         eth_data = *data;
 348         platform_device_register(&at91sam9g45_eth_device);
 349 }
 350 #else
 351 void __init at91_add_device_eth(struct at91_eth_data *data) {}
 352 #endif
 353
 354
 355 /* --------------------------------------------------------------------
 356  *  MMC / SD
 357  * -------------------------------------------------------------------- */
 358
 359 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 360 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 361 static struct mci_platform_data mmc0_data, mmc1_data;
 362
 363 static struct resource mmc0_resources[] = {
 364         [0] = {
 365                 .start  = AT91SAM9G45_BASE_MCI0,
 366                 .end    = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
 367                 .flags  = IORESOURCE_MEM,
 368         },
 369         [1] = {
 370                 .start  = AT91SAM9G45_ID_MCI0,
 371                 .end    = AT91SAM9G45_ID_MCI0,
 372                 .flags  = IORESOURCE_IRQ,
 373         },
 374 };
 375
 376 static struct platform_device at91sam9g45_mmc0_device = {
 377         .name           = "atmel_mci",
 378         .id             = 0,
 379         .dev            = {
 380                                 .dma_mask               = &mmc_dmamask,
 381                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 382                                 .platform_data          = &mmc0_data,
 383         },
 384         .resource       = mmc0_resources,
 385         .num_resources  = ARRAY_SIZE(mmc0_resources),
 386 };
 387
 388 static struct resource mmc1_resources[] = {
 389         [0] = {
 390                 .start  = AT91SAM9G45_BASE_MCI1,
 391                 .end    = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
 392                 .flags  = IORESOURCE_MEM,
 393         },
 394         [1] = {
 395                 .start  = AT91SAM9G45_ID_MCI1,
 396                 .end    = AT91SAM9G45_ID_MCI1,
 397                 .flags  = IORESOURCE_IRQ,
 398         },
 399 };
 400
 401 static struct platform_device at91sam9g45_mmc1_device = {
 402         .name           = "atmel_mci",
 403         .id             = 1,
 404         .dev            = {
 405                                 .dma_mask               = &mmc_dmamask,
 406                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 407                                 .platform_data          = &mmc1_data,
 408         },
 409         .resource       = mmc1_resources,
 410         .num_resources  = ARRAY_SIZE(mmc1_resources),
 411 };
 412
 413 /* Consider only one slot : slot 0 */
 414 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 415 {
 416
 417         if (!data)
 418                 return;
 419
 420         /* Must have at least one usable slot */
 421         if (!data->slot[0].bus_width)
 422                 return;
 423
 424 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
 425         {
 426         struct at_dma_slave     *atslave;
 427         struct mci_dma_data     *alt_atslave;
 428
 429         alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
 430         atslave = &alt_atslave->sdata;
 431
 432         /* DMA slave channel configuration */
 433         atslave->dma_dev = &at_hdmac_device.dev;
 434         atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
 435         atslave->cfg = ATC_FIFOCFG_HALFFIFO
 436                         | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
 437         atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
 438         if (mmc_id == 0)        /* MCI0 */
 439                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
 440                               | ATC_DST_PER(AT_DMA_ID_MCI0);
 441
 442         else                    /* MCI1 */
 443                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
 444                               | ATC_DST_PER(AT_DMA_ID_MCI1);
 445
 446         data->dma_slave = alt_atslave;
 447         }
 448 #endif
 449
 450
 451         /* input/irq */
 452         if (data->slot[0].detect_pin) {
 453                 at91_set_gpio_input(data->slot[0].detect_pin, 1);
 454                 at91_set_deglitch(data->slot[0].detect_pin, 1);
 455         }
 456         if (data->slot[0].wp_pin)
 457                 at91_set_gpio_input(data->slot[0].wp_pin, 1);
 458
 459         if (mmc_id == 0) {              /* MCI0 */
 460
 461                 /* CLK */
 462                 at91_set_A_periph(AT91_PIN_PA0, 0);
 463
 464                 /* CMD */
 465                 at91_set_A_periph(AT91_PIN_PA1, 1);
 466
 467                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 468                 at91_set_A_periph(AT91_PIN_PA2, 1);
 469                 if (data->slot[0].bus_width == 4) {
 470                         at91_set_A_periph(AT91_PIN_PA3, 1);
 471                         at91_set_A_periph(AT91_PIN_PA4, 1);
 472                         at91_set_A_periph(AT91_PIN_PA5, 1);
 473                         if (data->slot[0].bus_width == 8) {
 474                                 at91_set_A_periph(AT91_PIN_PA6, 1);
 475                                 at91_set_A_periph(AT91_PIN_PA7, 1);
 476                                 at91_set_A_periph(AT91_PIN_PA8, 1);
 477                                 at91_set_A_periph(AT91_PIN_PA9, 1);
 478                         }
 479                 }
 480
 481                 mmc0_data = *data;
 482                 platform_device_register(&at91sam9g45_mmc0_device);
 483
 484         } else {                        /* MCI1 */
 485
 486                 /* CLK */
 487                 at91_set_A_periph(AT91_PIN_PA31, 0);
 488
 489                 /* CMD */
 490                 at91_set_A_periph(AT91_PIN_PA22, 1);
 491
 492                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 493                 at91_set_A_periph(AT91_PIN_PA23, 1);
 494                 if (data->slot[0].bus_width == 4) {
 495                         at91_set_A_periph(AT91_PIN_PA24, 1);
 496                         at91_set_A_periph(AT91_PIN_PA25, 1);
 497                         at91_set_A_periph(AT91_PIN_PA26, 1);
 498                         if (data->slot[0].bus_width == 8) {
 499                                 at91_set_A_periph(AT91_PIN_PA27, 1);
 500                                 at91_set_A_periph(AT91_PIN_PA28, 1);
 501                                 at91_set_A_periph(AT91_PIN_PA29, 1);
 502                                 at91_set_A_periph(AT91_PIN_PA30, 1);
 503                         }
 504                 }
 505
 506                 mmc1_data = *data;
 507                 platform_device_register(&at91sam9g45_mmc1_device);
 508
 509         }
 510 }
 511 #else
 512 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 513 #endif
 514
 515
 516 /* --------------------------------------------------------------------
 517  *  NAND / SmartMedia
 518  * -------------------------------------------------------------------- */
 519
 520 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 521 static struct atmel_nand_data nand_data;
 522
 523 #define NAND_BASE       AT91_CHIPSELECT_3
 524
 525 static struct resource nand_resources[] = {
 526         [0] = {
 527                 .start  = NAND_BASE,
 528                 .end    = NAND_BASE + SZ_256M - 1,
 529                 .flags  = IORESOURCE_MEM,
 530         },
 531         [1] = {
 532                 .start  = AT91_BASE_SYS + AT91_ECC,
 533                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
 534                 .flags  = IORESOURCE_MEM,
 535         }
 536 };
 537
 538 static struct platform_device at91sam9g45_nand_device = {
 539         .name           = "atmel_nand",
 540         .id             = -1,
 541         .dev            = {
 542                                 .platform_data  = &nand_data,
 543         },
 544         .resource       = nand_resources,
 545         .num_resources  = ARRAY_SIZE(nand_resources),
 546 };
 547
 548 void __init at91_add_device_nand(struct atmel_nand_data *data)
 549 {
 550         unsigned long csa;
 551
 552         if (!data)
 553                 return;
 554
 555         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 556         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 557
 558         /* enable pin */
 559         if (data->enable_pin)
 560                 at91_set_gpio_output(data->enable_pin, 1);
 561
 562         /* ready/busy pin */
 563         if (data->rdy_pin)
 564                 at91_set_gpio_input(data->rdy_pin, 1);
 565
 566         /* card detect pin */
 567         if (data->det_pin)
 568                 at91_set_gpio_input(data->det_pin, 1);
 569
 570         nand_data = *data;
 571         platform_device_register(&at91sam9g45_nand_device);
 572 }
 573 #else
 574 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 575 #endif
 576
 577
 578 /* --------------------------------------------------------------------
 579  *  TWI (i2c)
 580  * -------------------------------------------------------------------- */
 581
 582 /*
 583  * Prefer the GPIO code since the TWI controller isn't robust
 584  * (gets overruns and underruns under load) and can only issue
 585  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 586  */
 587 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 588 static struct i2c_gpio_platform_data pdata_i2c0 = {
 589         .sda_pin                = AT91_PIN_PA20,
 590         .sda_is_open_drain      = 1,
 591         .scl_pin                = AT91_PIN_PA21,
 592         .scl_is_open_drain      = 1,
 593         .udelay                 = 5,            /* ~100 kHz */
 594 };
 595
 596 static struct platform_device at91sam9g45_twi0_device = {
 597         .name                   = "i2c-gpio",
 598         .id                     = 0,
 599         .dev.platform_data      = &pdata_i2c0,
 600 };
 601
 602 static struct i2c_gpio_platform_data pdata_i2c1 = {
 603         .sda_pin                = AT91_PIN_PB10,
 604         .sda_is_open_drain      = 1,
 605         .scl_pin                = AT91_PIN_PB11,
 606         .scl_is_open_drain      = 1,
 607         .udelay                 = 5,            /* ~100 kHz */
 608 };
 609
 610 static struct platform_device at91sam9g45_twi1_device = {
 611         .name                   = "i2c-gpio",
 612         .id                     = 1,
 613         .dev.platform_data      = &pdata_i2c1,
 614 };
 615
 616 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 617 {
 618         i2c_register_board_info(i2c_id, devices, nr_devices);
 619
 620         if (i2c_id == 0) {
 621                 at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
 622                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 623
 624                 at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
 625                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 626
 627                 platform_device_register(&at91sam9g45_twi0_device);
 628         } else {
 629                 at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
 630                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 631
 632                 at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
 633                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 634
 635                 platform_device_register(&at91sam9g45_twi1_device);
 636         }
 637 }
 638
 639 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 640 static struct resource twi0_resources[] = {
 641         [0] = {
 642                 .start  = AT91SAM9G45_BASE_TWI0,
 643                 .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
 644                 .flags  = IORESOURCE_MEM,
 645         },
 646         [1] = {
 647                 .start  = AT91SAM9G45_ID_TWI0,
 648                 .end    = AT91SAM9G45_ID_TWI0,
 649                 .flags  = IORESOURCE_IRQ,
 650         },
 651 };
 652
 653 static struct platform_device at91sam9g45_twi0_device = {
 654         .name           = "at91_i2c",
 655         .id             = 0,
 656         .resource       = twi0_resources,
 657         .num_resources  = ARRAY_SIZE(twi0_resources),
 658 };
 659
 660 static struct resource twi1_resources[] = {
 661         [0] = {
 662                 .start  = AT91SAM9G45_BASE_TWI1,
 663                 .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
 664                 .flags  = IORESOURCE_MEM,
 665         },
 666         [1] = {
 667                 .start  = AT91SAM9G45_ID_TWI1,
 668                 .end    = AT91SAM9G45_ID_TWI1,
 669                 .flags  = IORESOURCE_IRQ,
 670         },
 671 };
 672
 673 static struct platform_device at91sam9g45_twi1_device = {
 674         .name           = "at91_i2c",
 675         .id             = 1,
 676         .resource       = twi1_resources,
 677         .num_resources  = ARRAY_SIZE(twi1_resources),
 678 };
 679
 680 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 681 {
 682         i2c_register_board_info(i2c_id, devices, nr_devices);
 683
 684         /* pins used for TWI interface */
 685         if (i2c_id == 0) {
 686                 at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
 687                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 688
 689                 at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
 690                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 691
 692                 platform_device_register(&at91sam9g45_twi0_device);
 693         } else {
 694                 at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
 695                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 696
 697                 at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
 698                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 699
 700                 platform_device_register(&at91sam9g45_twi1_device);
 701         }
 702 }
 703 #else
 704 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
 705 #endif
 706
 707
 708 /* --------------------------------------------------------------------
 709  *  SPI
 710  * -------------------------------------------------------------------- */
 711
 712 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 713 static u64 spi_dmamask = DMA_BIT_MASK(32);
 714
 715 static struct resource spi0_resources[] = {
 716         [0] = {
 717                 .start  = AT91SAM9G45_BASE_SPI0,
 718                 .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
 719                 .flags  = IORESOURCE_MEM,
 720         },
 721         [1] = {
 722                 .start  = AT91SAM9G45_ID_SPI0,
 723                 .end    = AT91SAM9G45_ID_SPI0,
 724                 .flags  = IORESOURCE_IRQ,
 725         },
 726 };
 727
 728 static struct platform_device at91sam9g45_spi0_device = {
 729         .name           = "atmel_spi",
 730         .id             = 0,
 731         .dev            = {
 732                                 .dma_mask               = &spi_dmamask,
 733                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 734         },
 735         .resource       = spi0_resources,
 736         .num_resources  = ARRAY_SIZE(spi0_resources),
 737 };
 738
 739 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
 740
 741 static struct resource spi1_resources[] = {
 742         [0] = {
 743                 .start  = AT91SAM9G45_BASE_SPI1,
 744                 .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
 745                 .flags  = IORESOURCE_MEM,
 746         },
 747         [1] = {
 748                 .start  = AT91SAM9G45_ID_SPI1,
 749                 .end    = AT91SAM9G45_ID_SPI1,
 750                 .flags  = IORESOURCE_IRQ,
 751         },
 752 };
 753
 754 static struct platform_device at91sam9g45_spi1_device = {
 755         .name           = "atmel_spi",
 756         .id             = 1,
 757         .dev            = {
 758                                 .dma_mask               = &spi_dmamask,
 759                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 760         },
 761         .resource       = spi1_resources,
 762         .num_resources  = ARRAY_SIZE(spi1_resources),
 763 };
 764
 765 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
 766
 767 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 768 {
 769         int i;
 770         unsigned long cs_pin;
 771         short enable_spi0 = 0;
 772         short enable_spi1 = 0;
 773
 774         /* Choose SPI chip-selects */
 775         for (i = 0; i < nr_devices; i++) {
 776                 if (devices[i].controller_data)
 777                         cs_pin = (unsigned long) devices[i].controller_data;
 778                 else if (devices[i].bus_num == 0)
 779                         cs_pin = spi0_standard_cs[devices[i].chip_select];
 780                 else
 781                         cs_pin = spi1_standard_cs[devices[i].chip_select];
 782
 783                 if (devices[i].bus_num == 0)
 784                         enable_spi0 = 1;
 785                 else
 786                         enable_spi1 = 1;
 787
 788                 /* enable chip-select pin */
 789                 at91_set_gpio_output(cs_pin, 1);
 790
 791                 /* pass chip-select pin to driver */
 792                 devices[i].controller_data = (void *) cs_pin;
 793         }
 794
 795         spi_register_board_info(devices, nr_devices);
 796
 797         /* Configure SPI bus(es) */
 798         if (enable_spi0) {
 799                 at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
 800                 at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
 801                 at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
 802
 803                 platform_device_register(&at91sam9g45_spi0_device);
 804         }
 805         if (enable_spi1) {
 806                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
 807                 at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
 808                 at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
 809
 810                 platform_device_register(&at91sam9g45_spi1_device);
 811         }
 812 }
 813 #else
 814 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 815 #endif
 816
 817
 818 /* --------------------------------------------------------------------
 819  *  AC97
 820  * -------------------------------------------------------------------- */
 821
 822 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 823 static u64 ac97_dmamask = DMA_BIT_MASK(32);
 824 static struct ac97c_platform_data ac97_data;
 825
 826 static struct resource ac97_resources[] = {
 827         [0] = {
 828                 .start  = AT91SAM9G45_BASE_AC97C,
 829                 .end    = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
 830                 .flags  = IORESOURCE_MEM,
 831         },
 832         [1] = {
 833                 .start  = AT91SAM9G45_ID_AC97C,
 834                 .end    = AT91SAM9G45_ID_AC97C,
 835                 .flags  = IORESOURCE_IRQ,
 836         },
 837 };
 838
 839 static struct platform_device at91sam9g45_ac97_device = {
 840         .name           = "atmel_ac97c",
 841         .id             = 0,
 842         .dev            = {
 843                                 .dma_mask               = &ac97_dmamask,
 844                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 845                                 .platform_data          = &ac97_data,
 846         },
 847         .resource       = ac97_resources,
 848         .num_resources  = ARRAY_SIZE(ac97_resources),
 849 };
 850
 851 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 852 {
 853         if (!data)
 854                 return;
 855
 856         at91_set_A_periph(AT91_PIN_PD8, 0);     /* AC97FS */
 857         at91_set_A_periph(AT91_PIN_PD9, 0);     /* AC97CK */
 858         at91_set_A_periph(AT91_PIN_PD7, 0);     /* AC97TX */
 859         at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
 860
 861         /* reset */
 862         if (data->reset_pin)
 863                 at91_set_gpio_output(data->reset_pin, 0);
 864
 865         ac97_data = *data;
 866         platform_device_register(&at91sam9g45_ac97_device);
 867 }
 868 #else
 869 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 870 #endif
 871
 872
 873 /* --------------------------------------------------------------------
 874  *  LCD Controller
 875  * -------------------------------------------------------------------- */
 876
 877 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 878 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 879 static struct atmel_lcdfb_info lcdc_data;
 880
 881 static struct resource lcdc_resources[] = {
 882         [0] = {
 883                 .start  = AT91SAM9G45_LCDC_BASE,
 884                 .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
 885                 .flags  = IORESOURCE_MEM,
 886         },
 887         [1] = {
 888                 .start  = AT91SAM9G45_ID_LCDC,
 889                 .end    = AT91SAM9G45_ID_LCDC,
 890                 .flags  = IORESOURCE_IRQ,
 891         },
 892 };
 893
 894 static struct platform_device at91_lcdc_device = {
 895         .name           = "atmel_lcdfb",
 896         .id             = 0,
 897         .dev            = {
 898                                 .dma_mask               = &lcdc_dmamask,
 899                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 900                                 .platform_data          = &lcdc_data,
 901         },
 902         .resource       = lcdc_resources,
 903         .num_resources  = ARRAY_SIZE(lcdc_resources),
 904 };
 905
 906 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 907 {
 908         if (!data)
 909                 return;
 910
 911         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 912
 913         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 914         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 915         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 916         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 917         at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
 918         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 919         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 920         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 921         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 922         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 923         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 924         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 925         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 926         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 927         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 928         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 929         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 930         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 931         at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 932         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 933         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 934         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 935         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 936         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 937         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 938         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 939         at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 940         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 941         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 942
 943         lcdc_data = *data;
 944         platform_device_register(&at91_lcdc_device);
 945 }
 946 #else
 947 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 948 #endif
 949
 950
 951 /* --------------------------------------------------------------------
 952  *  Timer/Counter block
 953  * -------------------------------------------------------------------- */
 954
 955 #ifdef CONFIG_ATMEL_TCLIB
 956 static struct resource tcb0_resources[] = {
 957         [0] = {
 958                 .start  = AT91SAM9G45_BASE_TCB0,
 959                 .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
 960                 .flags  = IORESOURCE_MEM,
 961         },
 962         [1] = {
 963                 .start  = AT91SAM9G45_ID_TCB,
 964                 .end    = AT91SAM9G45_ID_TCB,
 965                 .flags  = IORESOURCE_IRQ,
 966         },
 967 };
 968
 969 static struct platform_device at91sam9g45_tcb0_device = {
 970         .name           = "atmel_tcb",
 971         .id             = 0,
 972         .resource       = tcb0_resources,
 973         .num_resources  = ARRAY_SIZE(tcb0_resources),
 974 };
 975
 976 /* TCB1 begins with TC3 */
 977 static struct resource tcb1_resources[] = {
 978         [0] = {
 979                 .start  = AT91SAM9G45_BASE_TCB1,
 980                 .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
 981                 .flags  = IORESOURCE_MEM,
 982         },
 983         [1] = {
 984                 .start  = AT91SAM9G45_ID_TCB,
 985                 .end    = AT91SAM9G45_ID_TCB,
 986                 .flags  = IORESOURCE_IRQ,
 987         },
 988 };
 989
 990 static struct platform_device at91sam9g45_tcb1_device = {
 991         .name           = "atmel_tcb",
 992         .id             = 1,
 993         .resource       = tcb1_resources,
 994         .num_resources  = ARRAY_SIZE(tcb1_resources),
 995 };
 996
 997 static void __init at91_add_device_tc(void)
 998 {
 999         platform_device_register(&at91sam9g45_tcb0_device);
1000         platform_device_register(&at91sam9g45_tcb1_device);
1001 }
1002 #else
1003 static void __init at91_add_device_tc(void) { }
1004 #endif
1005
1006
1007 /* --------------------------------------------------------------------
1008  *  RTC
1009  * -------------------------------------------------------------------- */
1010
1011 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1012 static struct platform_device at91sam9g45_rtc_device = {
1013         .name           = "at91_rtc",
1014         .id             = -1,
1015         .num_resources  = 0,
1016 };
1017
1018 static void __init at91_add_device_rtc(void)
1019 {
1020         platform_device_register(&at91sam9g45_rtc_device);
1021 }
1022 #else
1023 static void __init at91_add_device_rtc(void) {}
1024 #endif
1025
1026
1027 /* --------------------------------------------------------------------
1028  *  Touchscreen
1029  * -------------------------------------------------------------------- */
1030
1031 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1032 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1033 static struct at91_tsadcc_data tsadcc_data;
1034
1035 static struct resource tsadcc_resources[] = {
1036         [0] = {
1037                 .start  = AT91SAM9G45_BASE_TSC,
1038                 .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1039                 .flags  = IORESOURCE_MEM,
1040         },
1041         [1] = {
1042                 .start  = AT91SAM9G45_ID_TSC,
1043                 .end    = AT91SAM9G45_ID_TSC,
1044                 .flags  = IORESOURCE_IRQ,
1045         }
1046 };
1047
1048 static struct platform_device at91sam9g45_tsadcc_device = {
1049         .name           = "atmel_tsadcc",
1050         .id             = -1,
1051         .dev            = {
1052                                 .dma_mask               = &tsadcc_dmamask,
1053                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1054                                 .platform_data          = &tsadcc_data,
1055         },
1056         .resource       = tsadcc_resources,
1057         .num_resources  = ARRAY_SIZE(tsadcc_resources),
1058 };
1059
1060 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1061 {
1062         if (!data)
1063                 return;
1064
1065         at91_set_gpio_input(AT91_PIN_PD20, 0);  /* AD0_XR */
1066         at91_set_gpio_input(AT91_PIN_PD21, 0);  /* AD1_XL */
1067         at91_set_gpio_input(AT91_PIN_PD22, 0);  /* AD2_YT */
1068         at91_set_gpio_input(AT91_PIN_PD23, 0);  /* AD3_TB */
1069
1070         tsadcc_data = *data;
1071         platform_device_register(&at91sam9g45_tsadcc_device);
1072 }
1073 #else
1074 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1075 #endif
1076
1077
1078 /* --------------------------------------------------------------------
1079  *  RTT
1080  * -------------------------------------------------------------------- */
1081
1082 static struct resource rtt_resources[] = {
1083         {
1084                 .start  = AT91_BASE_SYS + AT91_RTT,
1085                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
1086                 .flags  = IORESOURCE_MEM,
1087         }
1088 };
1089
1090 static struct platform_device at91sam9g45_rtt_device = {
1091         .name           = "at91_rtt",
1092         .id             = 0,
1093         .resource       = rtt_resources,
1094         .num_resources  = ARRAY_SIZE(rtt_resources),
1095 };
1096
1097 static void __init at91_add_device_rtt(void)
1098 {
1099         platform_device_register(&at91sam9g45_rtt_device);
1100 }
1101
1102
1103 /* --------------------------------------------------------------------
1104  *  TRNG
1105  * -------------------------------------------------------------------- */
1106
1107 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1108 static struct resource trng_resources[] = {
1109         {
1110                 .start  = AT91SAM9G45_BASE_TRNG,
1111                 .end    = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1112                 .flags  = IORESOURCE_MEM,
1113         },
1114 };
1115
1116 static struct platform_device at91sam9g45_trng_device = {
1117         .name           = "atmel-trng",
1118         .id             = -1,
1119         .resource       = trng_resources,
1120         .num_resources  = ARRAY_SIZE(trng_resources),
1121 };
1122
1123 static void __init at91_add_device_trng(void)
1124 {
1125         platform_device_register(&at91sam9g45_trng_device);
1126 }
1127 #else
1128 static void __init at91_add_device_trng(void) {}
1129 #endif
1130
1131 /* --------------------------------------------------------------------
1132  *  Watchdog
1133  * -------------------------------------------------------------------- */
1134
1135 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1136 static struct platform_device at91sam9g45_wdt_device = {
1137         .name           = "at91_wdt",
1138         .id             = -1,
1139         .num_resources  = 0,
1140 };
1141
1142 static void __init at91_add_device_watchdog(void)
1143 {
1144         platform_device_register(&at91sam9g45_wdt_device);
1145 }
1146 #else
1147 static void __init at91_add_device_watchdog(void) {}
1148 #endif
1149
1150
1151 /* --------------------------------------------------------------------
1152  *  PWM
1153  * --------------------------------------------------------------------*/
1154
1155 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1156 static u32 pwm_mask;
1157
1158 static struct resource pwm_resources[] = {
1159         [0] = {
1160                 .start  = AT91SAM9G45_BASE_PWMC,
1161                 .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1162                 .flags  = IORESOURCE_MEM,
1163         },
1164         [1] = {
1165                 .start  = AT91SAM9G45_ID_PWMC,
1166                 .end    = AT91SAM9G45_ID_PWMC,
1167                 .flags  = IORESOURCE_IRQ,
1168         },
1169 };
1170
1171 static struct platform_device at91sam9g45_pwm0_device = {
1172         .name   = "atmel_pwm",
1173         .id     = -1,
1174         .dev    = {
1175                 .platform_data          = &pwm_mask,
1176         },
1177         .resource       = pwm_resources,
1178         .num_resources  = ARRAY_SIZE(pwm_resources),
1179 };
1180
1181 void __init at91_add_device_pwm(u32 mask)
1182 {
1183         if (mask & (1 << AT91_PWM0))
1184                 at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
1185
1186         if (mask & (1 << AT91_PWM1))
1187                 at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
1188
1189         if (mask & (1 << AT91_PWM2))
1190                 at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
1191
1192         if (mask & (1 << AT91_PWM3))
1193                 at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
1194
1195         pwm_mask = mask;
1196
1197         platform_device_register(&at91sam9g45_pwm0_device);
1198 }
1199 #else
1200 void __init at91_add_device_pwm(u32 mask) {}
1201 #endif
1202
1203
1204 /* --------------------------------------------------------------------
1205  *  SSC -- Synchronous Serial Controller
1206  * -------------------------------------------------------------------- */
1207
1208 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1209 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1210
1211 static struct resource ssc0_resources[] = {
1212         [0] = {
1213                 .start  = AT91SAM9G45_BASE_SSC0,
1214                 .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1215                 .flags  = IORESOURCE_MEM,
1216         },
1217         [1] = {
1218                 .start  = AT91SAM9G45_ID_SSC0,
1219                 .end    = AT91SAM9G45_ID_SSC0,
1220                 .flags  = IORESOURCE_IRQ,
1221         },
1222 };
1223
1224 static struct platform_device at91sam9g45_ssc0_device = {
1225         .name   = "ssc",
1226         .id     = 0,
1227         .dev    = {
1228                 .dma_mask               = &ssc0_dmamask,
1229                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1230         },
1231         .resource       = ssc0_resources,
1232         .num_resources  = ARRAY_SIZE(ssc0_resources),
1233 };
1234
1235 static inline void configure_ssc0_pins(unsigned pins)
1236 {
1237         if (pins & ATMEL_SSC_TF)
1238                 at91_set_A_periph(AT91_PIN_PD1, 1);
1239         if (pins & ATMEL_SSC_TK)
1240                 at91_set_A_periph(AT91_PIN_PD0, 1);
1241         if (pins & ATMEL_SSC_TD)
1242                 at91_set_A_periph(AT91_PIN_PD2, 1);
1243         if (pins & ATMEL_SSC_RD)
1244                 at91_set_A_periph(AT91_PIN_PD3, 1);
1245         if (pins & ATMEL_SSC_RK)
1246                 at91_set_A_periph(AT91_PIN_PD4, 1);
1247         if (pins & ATMEL_SSC_RF)
1248                 at91_set_A_periph(AT91_PIN_PD5, 1);
1249 }
1250
1251 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1252
1253 static struct resource ssc1_resources[] = {
1254         [0] = {
1255                 .start  = AT91SAM9G45_BASE_SSC1,
1256                 .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1257                 .flags  = IORESOURCE_MEM,
1258         },
1259         [1] = {
1260                 .start  = AT91SAM9G45_ID_SSC1,
1261                 .end    = AT91SAM9G45_ID_SSC1,
1262                 .flags  = IORESOURCE_IRQ,
1263         },
1264 };
1265
1266 static struct platform_device at91sam9g45_ssc1_device = {
1267         .name   = "ssc",
1268         .id     = 1,
1269         .dev    = {
1270                 .dma_mask               = &ssc1_dmamask,
1271                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1272         },
1273         .resource       = ssc1_resources,
1274         .num_resources  = ARRAY_SIZE(ssc1_resources),
1275 };
1276
1277 static inline void configure_ssc1_pins(unsigned pins)
1278 {
1279         if (pins & ATMEL_SSC_TF)
1280                 at91_set_A_periph(AT91_PIN_PD14, 1);
1281         if (pins & ATMEL_SSC_TK)
1282                 at91_set_A_periph(AT91_PIN_PD12, 1);
1283         if (pins & ATMEL_SSC_TD)
1284                 at91_set_A_periph(AT91_PIN_PD10, 1);
1285         if (pins & ATMEL_SSC_RD)
1286                 at91_set_A_periph(AT91_PIN_PD11, 1);
1287         if (pins & ATMEL_SSC_RK)
1288                 at91_set_A_periph(AT91_PIN_PD13, 1);
1289         if (pins & ATMEL_SSC_RF)
1290                 at91_set_A_periph(AT91_PIN_PD15, 1);
1291 }
1292
1293 /*
1294  * SSC controllers are accessed through library code, instead of any
1295  * kind of all-singing/all-dancing driver.  For example one could be
1296  * used by a particular I2S audio codec's driver, while another one
1297  * on the same system might be used by a custom data capture driver.
1298  */
1299 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1300 {
1301         struct platform_device *pdev;
1302
1303         /*
1304          * NOTE: caller is responsible for passing information matching
1305          * "pins" to whatever will be using each particular controller.
1306          */
1307         switch (id) {
1308         case AT91SAM9G45_ID_SSC0:
1309                 pdev = &at91sam9g45_ssc0_device;
1310                 configure_ssc0_pins(pins);
1311                 break;
1312         case AT91SAM9G45_ID_SSC1:
1313                 pdev = &at91sam9g45_ssc1_device;
1314                 configure_ssc1_pins(pins);
1315                 break;
1316         default:
1317                 return;
1318         }
1319
1320         platform_device_register(pdev);
1321 }
1322
1323 #else
1324 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1325 #endif
1326
1327
1328 /* --------------------------------------------------------------------
1329  *  UART
1330  * -------------------------------------------------------------------- */
1331
1332 #if defined(CONFIG_SERIAL_ATMEL)
1333 static struct resource dbgu_resources[] = {
1334         [0] = {
1335                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
1336                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1337                 .flags  = IORESOURCE_MEM,
1338         },
1339         [1] = {
1340                 .start  = AT91_ID_SYS,
1341                 .end    = AT91_ID_SYS,
1342                 .flags  = IORESOURCE_IRQ,
1343         },
1344 };
1345
1346 static struct atmel_uart_data dbgu_data = {
1347         .use_dma_tx     = 0,
1348         .use_dma_rx     = 0,
1349         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1350 };
1351
1352 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1353
1354 static struct platform_device at91sam9g45_dbgu_device = {
1355         .name           = "atmel_usart",
1356         .id             = 0,
1357         .dev            = {
1358                                 .dma_mask               = &dbgu_dmamask,
1359                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1360                                 .platform_data          = &dbgu_data,
1361         },
1362         .resource       = dbgu_resources,
1363         .num_resources  = ARRAY_SIZE(dbgu_resources),
1364 };
1365
1366 static inline void configure_dbgu_pins(void)
1367 {
1368         at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
1369         at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
1370 }
1371
1372 static struct resource uart0_resources[] = {
1373         [0] = {
1374                 .start  = AT91SAM9G45_BASE_US0,
1375                 .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1376                 .flags  = IORESOURCE_MEM,
1377         },
1378         [1] = {
1379                 .start  = AT91SAM9G45_ID_US0,
1380                 .end    = AT91SAM9G45_ID_US0,
1381                 .flags  = IORESOURCE_IRQ,
1382         },
1383 };
1384
1385 static struct atmel_uart_data uart0_data = {
1386         .use_dma_tx     = 1,
1387         .use_dma_rx     = 1,
1388 };
1389
1390 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1391
1392 static struct platform_device at91sam9g45_uart0_device = {
1393         .name           = "atmel_usart",
1394         .id             = 1,
1395         .dev            = {
1396                                 .dma_mask               = &uart0_dmamask,
1397                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1398                                 .platform_data          = &uart0_data,
1399         },
1400         .resource       = uart0_resources,
1401         .num_resources  = ARRAY_SIZE(uart0_resources),
1402 };
1403
1404 static inline void configure_usart0_pins(unsigned pins)
1405 {
1406         at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
1407         at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
1408
1409         if (pins & ATMEL_UART_RTS)
1410                 at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
1411         if (pins & ATMEL_UART_CTS)
1412                 at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
1413 }
1414
1415 static struct resource uart1_resources[] = {
1416         [0] = {
1417                 .start  = AT91SAM9G45_BASE_US1,
1418                 .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1419                 .flags  = IORESOURCE_MEM,
1420         },
1421         [1] = {
1422                 .start  = AT91SAM9G45_ID_US1,
1423                 .end    = AT91SAM9G45_ID_US1,
1424                 .flags  = IORESOURCE_IRQ,
1425         },
1426 };
1427
1428 static struct atmel_uart_data uart1_data = {
1429         .use_dma_tx     = 1,
1430         .use_dma_rx     = 1,
1431 };
1432
1433 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1434
1435 static struct platform_device at91sam9g45_uart1_device = {
1436         .name           = "atmel_usart",
1437         .id             = 2,
1438         .dev            = {
1439                                 .dma_mask               = &uart1_dmamask,
1440                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1441                                 .platform_data          = &uart1_data,
1442         },
1443         .resource       = uart1_resources,
1444         .num_resources  = ARRAY_SIZE(uart1_resources),
1445 };
1446
1447 static inline void configure_usart1_pins(unsigned pins)
1448 {
1449         at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
1450         at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
1451
1452         if (pins & ATMEL_UART_RTS)
1453                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
1454         if (pins & ATMEL_UART_CTS)
1455                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
1456 }
1457
1458 static struct resource uart2_resources[] = {
1459         [0] = {
1460                 .start  = AT91SAM9G45_BASE_US2,
1461                 .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1462                 .flags  = IORESOURCE_MEM,
1463         },
1464         [1] = {
1465                 .start  = AT91SAM9G45_ID_US2,
1466                 .end    = AT91SAM9G45_ID_US2,
1467                 .flags  = IORESOURCE_IRQ,
1468         },
1469 };
1470
1471 static struct atmel_uart_data uart2_data = {
1472         .use_dma_tx     = 1,
1473         .use_dma_rx     = 1,
1474 };
1475
1476 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1477
1478 static struct platform_device at91sam9g45_uart2_device = {
1479         .name           = "atmel_usart",
1480         .id             = 3,
1481         .dev            = {
1482                                 .dma_mask               = &uart2_dmamask,
1483                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1484                                 .platform_data          = &uart2_data,
1485         },
1486         .resource       = uart2_resources,
1487         .num_resources  = ARRAY_SIZE(uart2_resources),
1488 };
1489
1490 static inline void configure_usart2_pins(unsigned pins)
1491 {
1492         at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
1493         at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
1494
1495         if (pins & ATMEL_UART_RTS)
1496                 at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
1497         if (pins & ATMEL_UART_CTS)
1498                 at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
1499 }
1500
1501 static struct resource uart3_resources[] = {
1502         [0] = {
1503                 .start  = AT91SAM9G45_BASE_US3,
1504                 .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1505                 .flags  = IORESOURCE_MEM,
1506         },
1507         [1] = {
1508                 .start  = AT91SAM9G45_ID_US3,
1509                 .end    = AT91SAM9G45_ID_US3,
1510                 .flags  = IORESOURCE_IRQ,
1511         },
1512 };
1513
1514 static struct atmel_uart_data uart3_data = {
1515         .use_dma_tx     = 1,
1516         .use_dma_rx     = 1,
1517 };
1518
1519 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1520
1521 static struct platform_device at91sam9g45_uart3_device = {
1522         .name           = "atmel_usart",
1523         .id             = 4,
1524         .dev            = {
1525                                 .dma_mask               = &uart3_dmamask,
1526                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1527                                 .platform_data          = &uart3_data,
1528         },
1529         .resource       = uart3_resources,
1530         .num_resources  = ARRAY_SIZE(uart3_resources),
1531 };
1532
1533 static inline void configure_usart3_pins(unsigned pins)
1534 {
1535         at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
1536         at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
1537
1538         if (pins & ATMEL_UART_RTS)
1539                 at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
1540         if (pins & ATMEL_UART_CTS)
1541                 at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
1542 }
1543
1544 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1545 struct platform_device *atmel_default_console_device;   /* the serial console device */
1546
1547 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1548 {
1549         struct platform_device *pdev;
1550         struct atmel_uart_data *pdata;
1551
1552         switch (id) {
1553                 case 0:         /* DBGU */
1554                         pdev = &at91sam9g45_dbgu_device;
1555                         configure_dbgu_pins();
1556                         break;
1557                 case AT91SAM9G45_ID_US0:
1558                         pdev = &at91sam9g45_uart0_device;
1559                         configure_usart0_pins(pins);
1560                         break;
1561                 case AT91SAM9G45_ID_US1:
1562                         pdev = &at91sam9g45_uart1_device;
1563                         configure_usart1_pins(pins);
1564                         break;
1565                 case AT91SAM9G45_ID_US2:
1566                         pdev = &at91sam9g45_uart2_device;
1567                         configure_usart2_pins(pins);
1568                         break;
1569                 case AT91SAM9G45_ID_US3:
1570                         pdev = &at91sam9g45_uart3_device;
1571                         configure_usart3_pins(pins);
1572                         break;
1573                 default:
1574                         return;
1575         }
1576         pdata = pdev->dev.platform_data;
1577         pdata->num = portnr;            /* update to mapped ID */
1578
1579         if (portnr < ATMEL_MAX_UART)
1580                 at91_uarts[portnr] = pdev;
1581 }
1582
1583 void __init at91_set_serial_console(unsigned portnr)
1584 {
1585         if (portnr < ATMEL_MAX_UART) {
1586                 atmel_default_console_device = at91_uarts[portnr];
1587                 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1588         }
1589 }
1590
1591 void __init at91_add_device_serial(void)
1592 {
1593         int i;
1594
1595         for (i = 0; i < ATMEL_MAX_UART; i++) {
1596                 if (at91_uarts[i])
1597                         platform_device_register(at91_uarts[i]);
1598         }
1599
1600         if (!atmel_default_console_device)
1601                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1602 }
1603 #else
1604 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1605 void __init at91_set_serial_console(unsigned portnr) {}
1606 void __init at91_add_device_serial(void) {}
1607 #endif
1608
1609
1610 /* -------------------------------------------------------------------- */
1611 /*
1612  * These devices are always present and don't need any board-specific
1613  * setup.
1614  */
1615 static int __init at91_add_standard_devices(void)
1616 {
1617         at91_add_device_hdmac();
1618         at91_add_device_rtc();
1619         at91_add_device_rtt();
1620         at91_add_device_trng();
1621         at91_add_device_watchdog();
1622         at91_add_device_tc();
1623         return 0;
1624 }
1625
1626 arch_initcall(at91_add_standard_devices);