arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91sam9260.h>
  21 #include <mach/at91_pmc.h>
  22 #include <mach/at91_rstc.h>
  23 #include <mach/at91_shdwc.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "clock.h"
  28
  29 static struct map_desc at91sam9260_sram_desc[] __initdata = {
  30         {
  31                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
  32                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
  33                 .length         = AT91SAM9260_SRAM0_SIZE,
  34                 .type           = MT_DEVICE,
  35         }, {
  36                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
  37                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
  38                 .length         = AT91SAM9260_SRAM1_SIZE,
  39                 .type           = MT_DEVICE,
  40         }
  41 };
  42
  43 static struct map_desc at91sam9g20_sram_desc[] __initdata = {
  44         {
  45                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
  46                 .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
  47                 .length         = AT91SAM9G20_SRAM0_SIZE,
  48                 .type           = MT_DEVICE,
  49         }, {
  50                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
  51                 .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
  52                 .length         = AT91SAM9G20_SRAM1_SIZE,
  53                 .type           = MT_DEVICE,
  54         }
  55 };
  56
  57 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
  58         {
  59                 .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
  60                 .type           = MT_DEVICE,
  61         }
  62 };
  63
  64 /* --------------------------------------------------------------------
  65  *  Clocks
  66  * -------------------------------------------------------------------- */
  67
  68 /*
  69  * The peripheral clocks.
  70  */
  71 static struct clk pioA_clk = {
  72         .name           = "pioA_clk",
  73         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  74         .type           = CLK_TYPE_PERIPHERAL,
  75 };
  76 static struct clk pioB_clk = {
  77         .name           = "pioB_clk",
  78         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  79         .type           = CLK_TYPE_PERIPHERAL,
  80 };
  81 static struct clk pioC_clk = {
  82         .name           = "pioC_clk",
  83         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk adc_clk = {
  87         .name           = "adc_clk",
  88         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk usart0_clk = {
  92         .name           = "usart0_clk",
  93         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk usart1_clk = {
  97         .name           = "usart1_clk",
  98         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk usart2_clk = {
 102         .name           = "usart2_clk",
 103         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk mmc_clk = {
 107         .name           = "mci_clk",
 108         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk udc_clk = {
 112         .name           = "udc_clk",
 113         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk twi_clk = {
 117         .name           = "twi_clk",
 118         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk spi0_clk = {
 122         .name           = "spi0_clk",
 123         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk spi1_clk = {
 127         .name           = "spi1_clk",
 128         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131 static struct clk ssc_clk = {
 132         .name           = "ssc_clk",
 133         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 134         .type           = CLK_TYPE_PERIPHERAL,
 135 };
 136 static struct clk tc0_clk = {
 137         .name           = "tc0_clk",
 138         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 139         .type           = CLK_TYPE_PERIPHERAL,
 140 };
 141 static struct clk tc1_clk = {
 142         .name           = "tc1_clk",
 143         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 144         .type           = CLK_TYPE_PERIPHERAL,
 145 };
 146 static struct clk tc2_clk = {
 147         .name           = "tc2_clk",
 148         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 149         .type           = CLK_TYPE_PERIPHERAL,
 150 };
 151 static struct clk ohci_clk = {
 152         .name           = "ohci_clk",
 153         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 154         .type           = CLK_TYPE_PERIPHERAL,
 155 };
 156 static struct clk macb_clk = {
 157         .name           = "macb_clk",
 158         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 159         .type           = CLK_TYPE_PERIPHERAL,
 160 };
 161 static struct clk isi_clk = {
 162         .name           = "isi_clk",
 163         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 164         .type           = CLK_TYPE_PERIPHERAL,
 165 };
 166 static struct clk usart3_clk = {
 167         .name           = "usart3_clk",
 168         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 169         .type           = CLK_TYPE_PERIPHERAL,
 170 };
 171 static struct clk usart4_clk = {
 172         .name           = "usart4_clk",
 173         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 174         .type           = CLK_TYPE_PERIPHERAL,
 175 };
 176 static struct clk usart5_clk = {
 177         .name           = "usart5_clk",
 178         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 179         .type           = CLK_TYPE_PERIPHERAL,
 180 };
 181 static struct clk tc3_clk = {
 182         .name           = "tc3_clk",
 183         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 184         .type           = CLK_TYPE_PERIPHERAL,
 185 };
 186 static struct clk tc4_clk = {
 187         .name           = "tc4_clk",
 188         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 189         .type           = CLK_TYPE_PERIPHERAL,
 190 };
 191 static struct clk tc5_clk = {
 192         .name           = "tc5_clk",
 193         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 194         .type           = CLK_TYPE_PERIPHERAL,
 195 };
 196
 197 static struct clk *periph_clocks[] __initdata = {
 198         &pioA_clk,
 199         &pioB_clk,
 200         &pioC_clk,
 201         &adc_clk,
 202         &usart0_clk,
 203         &usart1_clk,
 204         &usart2_clk,
 205         &mmc_clk,
 206         &udc_clk,
 207         &twi_clk,
 208         &spi0_clk,
 209         &spi1_clk,
 210         &ssc_clk,
 211         &tc0_clk,
 212         &tc1_clk,
 213         &tc2_clk,
 214         &ohci_clk,
 215         &macb_clk,
 216         &isi_clk,
 217         &usart3_clk,
 218         &usart4_clk,
 219         &usart5_clk,
 220         &tc3_clk,
 221         &tc4_clk,
 222         &tc5_clk,
 223         // irq0 .. irq2
 224 };
 225
 226 static struct clk_lookup periph_clocks_lookups[] = {
 227         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 228         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 229         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 230         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 231         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 232         CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
 233         CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
 234         CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
 235         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
 236 };
 237
 238 static struct clk_lookup usart_clocks_lookups[] = {
 239         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 240         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 241         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 242         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 243         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 244         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 245         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 246 };
 247
 248 /*
 249  * The two programmable clocks.
 250  * You must configure pin multiplexing to bring these signals out.
 251  */
 252 static struct clk pck0 = {
 253         .name           = "pck0",
 254         .pmc_mask       = AT91_PMC_PCK0,
 255         .type           = CLK_TYPE_PROGRAMMABLE,
 256         .id             = 0,
 257 };
 258 static struct clk pck1 = {
 259         .name           = "pck1",
 260         .pmc_mask       = AT91_PMC_PCK1,
 261         .type           = CLK_TYPE_PROGRAMMABLE,
 262         .id             = 1,
 263 };
 264
 265 static void __init at91sam9260_register_clocks(void)
 266 {
 267         int i;
 268
 269         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 270                 clk_register(periph_clocks[i]);
 271
 272         clkdev_add_table(periph_clocks_lookups,
 273                          ARRAY_SIZE(periph_clocks_lookups));
 274         clkdev_add_table(usart_clocks_lookups,
 275                          ARRAY_SIZE(usart_clocks_lookups));
 276
 277         clk_register(&pck0);
 278         clk_register(&pck1);
 279 }
 280
 281 static struct clk_lookup console_clock_lookup;
 282
 283 void __init at91sam9260_set_console_clock(int id)
 284 {
 285         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 286                 return;
 287
 288         console_clock_lookup.con_id = "usart";
 289         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 290         clkdev_add(&console_clock_lookup);
 291 }
 292
 293 /* --------------------------------------------------------------------
 294  *  GPIO
 295  * -------------------------------------------------------------------- */
 296
 297 static struct at91_gpio_bank at91sam9260_gpio[] = {
 298         {
 299                 .id             = AT91SAM9260_ID_PIOA,
 300                 .offset         = AT91_PIOA,
 301                 .clock          = &pioA_clk,
 302         }, {
 303                 .id             = AT91SAM9260_ID_PIOB,
 304                 .offset         = AT91_PIOB,
 305                 .clock          = &pioB_clk,
 306         }, {
 307                 .id             = AT91SAM9260_ID_PIOC,
 308                 .offset         = AT91_PIOC,
 309                 .clock          = &pioC_clk,
 310         }
 311 };
 312
 313 static void at91sam9260_poweroff(void)
 314 {
 315         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 316 }
 317
 318
 319 /* --------------------------------------------------------------------
 320  *  AT91SAM9260 processor initialization
 321  * -------------------------------------------------------------------- */
 322
 323 static void __init at91sam9xe_map_io(void)
 324 {
 325         unsigned long cidr, sram_size;
 326
 327         cidr = at91_sys_read(AT91_DBGU_CIDR);
 328
 329         switch (cidr & AT91_CIDR_SRAMSIZ) {
 330                 case AT91_CIDR_SRAMSIZ_32K:
 331                         sram_size = 2 * SZ_16K;
 332                         break;
 333                 case AT91_CIDR_SRAMSIZ_16K:
 334                 default:
 335                         sram_size = SZ_16K;
 336         }
 337
 338         at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
 339         at91sam9xe_sram_desc->length = sram_size;
 340
 341         iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
 342 }
 343
 344 static void __init at91sam9260_map_io(void)
 345 {
 346         if (cpu_is_at91sam9xe())
 347                 at91sam9xe_map_io();
 348         else if (cpu_is_at91sam9g20())
 349                 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
 350         else
 351                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 352 }
 353
 354 static void __init at91sam9260_initialize(unsigned long main_clock)
 355 {
 356         at91_arch_reset = at91sam9_alt_reset;
 357         pm_power_off = at91sam9260_poweroff;
 358         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 359                         | (1 << AT91SAM9260_ID_IRQ2);
 360
 361         /* Init clock subsystem */
 362         at91_clock_init(main_clock);
 363
 364         /* Register the processor-specific clocks */
 365         at91sam9260_register_clocks();
 366
 367         /* Register GPIO subsystem */
 368         at91_gpio_init(at91sam9260_gpio, 3);
 369 }
 370
 371 /* --------------------------------------------------------------------
 372  *  Interrupt initialization
 373  * -------------------------------------------------------------------- */
 374
 375 /*
 376  * The default interrupt priority levels (0 = lowest, 7 = highest).
 377  */
 378 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 379         7,      /* Advanced Interrupt Controller */
 380         7,      /* System Peripherals */
 381         1,      /* Parallel IO Controller A */
 382         1,      /* Parallel IO Controller B */
 383         1,      /* Parallel IO Controller C */
 384         0,      /* Analog-to-Digital Converter */
 385         5,      /* USART 0 */
 386         5,      /* USART 1 */
 387         5,      /* USART 2 */
 388         0,      /* Multimedia Card Interface */
 389         2,      /* USB Device Port */
 390         6,      /* Two-Wire Interface */
 391         5,      /* Serial Peripheral Interface 0 */
 392         5,      /* Serial Peripheral Interface 1 */
 393         5,      /* Serial Synchronous Controller */
 394         0,
 395         0,
 396         0,      /* Timer Counter 0 */
 397         0,      /* Timer Counter 1 */
 398         0,      /* Timer Counter 2 */
 399         2,      /* USB Host port */
 400         3,      /* Ethernet */
 401         0,      /* Image Sensor Interface */
 402         5,      /* USART 3 */
 403         5,      /* USART 4 */
 404         5,      /* USART 5 */
 405         0,      /* Timer Counter 3 */
 406         0,      /* Timer Counter 4 */
 407         0,      /* Timer Counter 5 */
 408         0,      /* Advanced Interrupt Controller */
 409         0,      /* Advanced Interrupt Controller */
 410         0,      /* Advanced Interrupt Controller */
 411 };
 412
 413 void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 414 {
 415         if (!priority)
 416                 priority = at91sam9260_default_irq_priority;
 417
 418         /* Initialize the AIC interrupt controller */
 419         at91_aic_init(priority);
 420
 421         /* Enable GPIO interrupts */
 422         at91_gpio_irq_setup();
 423 }
 424
 425 struct at91_soc __initdata at91sam9260_soc = {
 426         .map_io = at91sam9260_map_io,
 427         .init = at91sam9260_initialize,
 428 };