2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
25 #ifdef CONFIG_DEBUG_LL
26 #include <mach/debug-macro.S>
29 #if (PHYS_OFFSET & 0x001fffff)
30 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
33 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
34 #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
38 * swapper_pg_dir is the virtual address of the initial page table.
39 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
40 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
41 * the least significant 16 bits to be 0x8000, but we could probably
42 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
44 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
45 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
49 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
52 ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
55 #ifdef CONFIG_XIP_KERNEL
56 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
57 #define KERNEL_END _edata_loc
59 #define KERNEL_START KERNEL_RAM_VADDR
60 #define KERNEL_END _end
64 * Kernel startup entry point.
65 * ---------------------------
67 * This is normally called from the decompressor code. The requirements
68 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
69 * r1 = machine nr, r2 = atags pointer.
71 * This code is mostly position independent, so if you link the kernel at
72 * 0xc0008000, you call this at __pa(0xc0008000).
74 * See linux/arch/arm/tools/mach-types for the complete list of machine
77 * We're trying to keep crap to a minimum; DO NOT add any machine specific
78 * crap here - that's what the boot loader (or in extreme, well justified
79 * circumstances, zImage) is for.
83 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
85 mrc p15, 0, r9, c0, c0 @ get processor id
86 bl __lookup_processor_type @ r5=procinfo r9=cpuid
87 movs r10, r5 @ invalid processor (r5=0)?
88 beq __error_p @ yes, error 'p'
89 bl __lookup_machine_type @ r5=machinfo
90 movs r8, r5 @ invalid machine (r5=0)?
91 beq __error_a @ yes, error 'a'
94 * r1 = machine no, r2 = atags,
95 * r8 = machinfo, r9 = cpuid, r10 = procinfo
98 #ifdef CONFIG_SMP_ON_UP
101 bl __create_page_tables
104 * The following calls CPU specific code in a position independent
105 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
106 * xxx_proc_info structure selected by __lookup_machine_type
107 * above. On return, the CPU will be ready for the MMU to be
108 * turned on, and r0 will hold the CPU control register value.
110 ldr r13, =__mmap_switched @ address to jump to after
111 @ mmu has been enabled
112 adr lr, BSYM(1f) @ return (PIC) address
113 ARM( add pc, r10, #PROCINFO_INITFUNC )
114 THUMB( add r12, r10, #PROCINFO_INITFUNC )
121 * Setup the initial page tables. We only setup the barest
122 * amount which are required to get the kernel running, which
123 * generally means mapping in the kernel code.
130 * r0, r3, r5-r7 corrupted
131 * r4 = physical page table address
133 __create_page_tables:
134 pgtbl r4 @ page table address
137 * Clear the 16K level 1 swapper page table
149 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
152 * Create identity mapping to cater for __enable_mmu.
153 * This identity mapping will be removed by paging_init().
155 adr r0, __enable_mmu_loc
156 ldmia r0, {r3, r5, r6}
157 sub r0, r0, r3 @ virt->phys offset
158 add r5, r5, r0 @ phys __enable_mmu
159 add r6, r6, r0 @ phys __enable_mmu_end
163 1: orr r3, r7, r5, lsl #20 @ flags + kernel base
164 str r3, [r4, r5, lsl #2] @ identity mapping
166 addne r5, r5, #1 @ next section
170 * Now setup the pagetables for our kernel direct
175 orr r3, r7, r3, lsl #20
176 add r0, r4, #(KERNEL_START & 0xff000000) >> 18
177 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
178 ldr r6, =(KERNEL_END - 1)
180 add r6, r4, r6, lsr #18
186 #ifdef CONFIG_XIP_KERNEL
188 * Map some ram to cover our .data and .bss areas.
190 orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
191 .if (KERNEL_RAM_PADDR & 0x00f00000)
192 orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
194 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
195 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
198 add r6, r4, r6, lsr #18
206 * Then map first 1MB of ram in case it contains our boot params.
208 add r0, r4, #PAGE_OFFSET >> 18
209 orr r6, r7, #(PHYS_OFFSET & 0xff000000)
210 .if (PHYS_OFFSET & 0x00f00000)
211 orr r6, r6, #(PHYS_OFFSET & 0x00f00000)
215 #ifdef CONFIG_DEBUG_LL
216 #ifndef CONFIG_DEBUG_ICEDCC
218 * Map in IO space for serial debugging.
219 * This allows debug messages to be output
220 * via a serial console before paging_init.
228 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
229 cmp r3, #0x0800 @ limit to 512MB
233 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
234 orr r3, r7, r3, lsl #20
240 #else /* CONFIG_DEBUG_ICEDCC */
241 /* we don't need any serial debugging mappings for ICEDCC */
242 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
243 #endif /* !CONFIG_DEBUG_ICEDCC */
245 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
247 * If we're using the NetWinder or CATS, we also need to map
248 * in the 16550-type serial port for the debug messages
250 add r0, r4, #0xff000000 >> 18
251 orr r3, r7, #0x7c000000
254 #ifdef CONFIG_ARCH_RPC
256 * Map in screen at 0x02000000 & SCREEN2_BASE
257 * Similar reasons here - for debug. This is
258 * only for Acorn RiscPC architectures.
260 add r0, r4, #0x02000000 >> 18
261 orr r3, r7, #0x02000000
263 add r0, r4, #0xd8000000 >> 18
268 ENDPROC(__create_page_tables)
273 .long __enable_mmu_end
275 #if defined(CONFIG_SMP)
277 ENTRY(secondary_startup)
279 * Common entry point for secondary CPUs.
281 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
282 * the processor type - there is no need to check the machine type
283 * as it has already been validated by the primary processor.
285 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
286 mrc p15, 0, r9, c0, c0 @ get processor id
287 bl __lookup_processor_type
288 movs r10, r5 @ invalid processor?
289 moveq r0, #'p' @ yes, error 'p'
293 * Use the page tables supplied from __cpu_up.
295 adr r4, __secondary_data
296 ldmia r4, {r5, r7, r12} @ address to jump to after
297 sub r4, r4, r5 @ mmu has been enabled
298 ldr r4, [r7, r4] @ get secondary_data.pgdir
299 adr lr, BSYM(__enable_mmu) @ return address
300 mov r13, r12 @ __secondary_switched address
301 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
302 @ (return control reg)
303 THUMB( add r12, r10, #PROCINFO_INITFUNC )
305 ENDPROC(secondary_startup)
308 * r6 = &secondary_data
310 ENTRY(__secondary_switched)
311 ldr sp, [r7, #4] @ get secondary_data.stack
313 b secondary_start_kernel
314 ENDPROC(__secondary_switched)
316 .type __secondary_data, %object
320 .long __secondary_switched
321 #endif /* defined(CONFIG_SMP) */
326 * Setup common bits before finally enabling the MMU. Essentially
327 * this is just loading the page table pointer and domain access
330 * r0 = cp#15 control register
333 * r4 = page table pointer
335 * r13 = *virtual* address to jump to upon completion
338 #ifdef CONFIG_ALIGNMENT_TRAP
343 #ifdef CONFIG_CPU_DCACHE_DISABLE
346 #ifdef CONFIG_CPU_BPREDICT_DISABLE
349 #ifdef CONFIG_CPU_ICACHE_DISABLE
352 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
353 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
354 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
355 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
356 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
357 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
359 ENDPROC(__enable_mmu)
362 * Enable the MMU. This completely changes the structure of the visible
363 * memory space. You will not be able to trace execution through this.
364 * If you have an enquiry about this, *please* check the linux-arm-kernel
365 * mailing list archives BEFORE sending another post to the list.
367 * r0 = cp#15 control register
371 * r13 = *virtual* address to jump to upon completion
373 * other registers depend on the function called upon completion
378 mcr p15, 0, r0, c1, c0, 0 @ write control reg
379 mrc p15, 0, r3, c0, c0, 0 @ read id reg
384 ENDPROC(__turn_mmu_on)
387 #ifdef CONFIG_SMP_ON_UP
390 orr r3, r4, #0xff000000 @ mask 0xff070000
391 orr r4, r4, #0x41000000 @ val 0x41070000
393 teq r0, r4 @ ARM CPU and ARMv6/v7?
394 bne __fixup_smp_on_up @ no, assume UP
396 orr r3, r3, #0x0000ff00
397 orr r3, r3, #0x000000f0 @ mask 0xff07fff0
398 orr r4, r4, #0x0000b000
399 orr r4, r4, #0x00000020 @ val 0x4107b020
401 teq r0, r4 @ ARM 11MPCore?
402 moveq pc, lr @ yes, assume SMP
404 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
406 movne pc, lr @ bit 31 => SMP
417 ARM( str r6, [r0, r3] )
418 THUMB( add r0, r0, r3 )
420 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
422 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
423 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
424 THUMB( strh r6, [r0] )
441 #include "head-common.S"