2 * arch/arm/include/asm/cacheflush.h
4 * Copyright (C) 1999-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
16 #include <asm/shmparam.h>
17 #include <asm/cachetype.h>
18 #include <asm/outercache.h>
20 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
29 #if defined(CONFIG_CPU_CACHE_V3)
31 # define MULTI_CACHE 1
37 #if defined(CONFIG_CPU_CACHE_V4)
39 # define MULTI_CACHE 1
45 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
46 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
47 defined(CONFIG_CPU_ARM1026)
48 # define MULTI_CACHE 1
51 #if defined(CONFIG_CPU_FA526)
53 # define MULTI_CACHE 1
59 #if defined(CONFIG_CPU_ARM926T)
61 # define MULTI_CACHE 1
63 # define _CACHE arm926
67 #if defined(CONFIG_CPU_ARM940T)
69 # define MULTI_CACHE 1
71 # define _CACHE arm940
75 #if defined(CONFIG_CPU_ARM946E)
77 # define MULTI_CACHE 1
79 # define _CACHE arm946
83 #if defined(CONFIG_CPU_CACHE_V4WB)
85 # define MULTI_CACHE 1
91 #if defined(CONFIG_CPU_XSCALE)
93 # define MULTI_CACHE 1
95 # define _CACHE xscale
99 #if defined(CONFIG_CPU_XSC3)
101 # define MULTI_CACHE 1
107 #if defined(CONFIG_CPU_MOHAWK)
109 # define MULTI_CACHE 1
111 # define _CACHE mohawk
115 #if defined(CONFIG_CPU_FEROCEON)
116 # define MULTI_CACHE 1
119 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
121 # define MULTI_CACHE 1
127 #if defined(CONFIG_CPU_V7)
129 # define MULTI_CACHE 1
135 #if !defined(_CACHE) && !defined(MULTI_CACHE)
136 #error Unknown cache maintainence model
140 * This flag is used to indicate that the page pointed to by a pte is clean
141 * and does not require cleaning before returning it to the user.
143 #define PG_dcache_clean PG_arch_1
146 * MM Cache Management
147 * ===================
149 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
150 * implement these methods.
152 * Start addresses are inclusive and end addresses are exclusive;
153 * start addresses should be rounded down, end addresses up.
155 * See Documentation/cachetlb.txt for more information.
156 * Please note that the implementation of these, and the required
157 * effects are cache-type (VIVT/VIPT/PIPT) specific.
161 * Unconditionally clean and invalidate the entire icache.
162 * Currently only needed for cache-v6.S and cache-v7.S, see
163 * __flush_icache_all for the generic implementation.
167 * Unconditionally clean and invalidate the entire cache.
171 * Clean and invalidate all user space cache entries
172 * before a change of page tables.
174 * flush_user_range(start, end, flags)
176 * Clean and invalidate a range of cache entries in the
177 * specified address space before a change of page tables.
178 * - start - user start address (inclusive, page aligned)
179 * - end - user end address (exclusive, page aligned)
180 * - flags - vma->vm_flags field
182 * coherent_kern_range(start, end)
184 * Ensure coherency between the Icache and the Dcache in the
185 * region described by start, end. If you have non-snooping
186 * Harvard caches, you need to implement this function.
187 * - start - virtual start address
188 * - end - virtual end address
190 * coherent_user_range(start, end)
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start, end. If you have non-snooping
194 * Harvard caches, you need to implement this function.
195 * - start - virtual start address
196 * - end - virtual end address
198 * flush_kern_dcache_area(kaddr, size)
200 * Ensure that the data held in page is written back.
201 * - kaddr - page address
202 * - size - region size
204 * DMA Cache Coherency
205 * ===================
207 * dma_flush_range(start, end)
209 * Clean and invalidate the specified virtual address range.
210 * - start - virtual start address
211 * - end - virtual end address
214 struct cpu_cache_fns {
215 void (*flush_icache_all)(void);
216 void (*flush_kern_all)(void);
217 void (*flush_user_all)(void);
218 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
220 void (*coherent_kern_range)(unsigned long, unsigned long);
221 void (*coherent_user_range)(unsigned long, unsigned long);
222 void (*flush_kern_dcache_area)(void *, size_t);
224 void (*dma_map_area)(const void *, size_t, int);
225 void (*dma_unmap_area)(const void *, size_t, int);
227 void (*dma_flush_range)(const void *, const void *);
231 * Select the calling method
235 extern struct cpu_cache_fns cpu_cache;
237 #define __cpuc_flush_icache_all cpu_cache.flush_icache_all
238 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
239 #define __cpuc_flush_user_all cpu_cache.flush_user_all
240 #define __cpuc_flush_user_range cpu_cache.flush_user_range
241 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
242 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range
243 #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
246 * These are private to the dma-mapping API. Do not use directly.
247 * Their sole purpose is to ensure that data held in the cache
248 * is visible to DMA, or data written by DMA to system memory is
249 * visible to the CPU.
251 #define dmac_map_area cpu_cache.dma_map_area
252 #define dmac_unmap_area cpu_cache.dma_unmap_area
253 #define dmac_flush_range cpu_cache.dma_flush_range
257 #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
258 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
259 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
260 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
261 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
262 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
263 #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
265 extern void __cpuc_flush_icache_all(void);
266 extern void __cpuc_flush_kern_all(void);
267 extern void __cpuc_flush_user_all(void);
268 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
269 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
270 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
271 extern void __cpuc_flush_dcache_area(void *, size_t);
274 * These are private to the dma-mapping API. Do not use directly.
275 * Their sole purpose is to ensure that data held in the cache
276 * is visible to DMA, or data written by DMA to system memory is
277 * visible to the CPU.
279 #define dmac_map_area __glue(_CACHE,_dma_map_area)
280 #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
281 #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
283 extern void dmac_map_area(const void *, size_t, int);
284 extern void dmac_unmap_area(const void *, size_t, int);
285 extern void dmac_flush_range(const void *, const void *);
290 * Copy user data from/to a page which is mapped into a different
291 * processes address space. Really, we want to allow our "user
292 * space" model to handle this.
294 extern void copy_to_user_page(struct vm_area_struct *, struct page *,
295 unsigned long, void *, const void *, unsigned long);
296 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
298 memcpy(dst, src, len); \
302 * Convert calls to our calling convention.
305 /* Invalidate I-cache */
306 #define __flush_icache_all_generic() \
307 asm("mcr p15, 0, %0, c7, c5, 0" \
310 /* Invalidate I-cache inner shareable */
311 #define __flush_icache_all_v7_smp() \
312 asm("mcr p15, 0, %0, c7, c1, 0" \
316 * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
317 * will fall through to use __flush_icache_all_generic.
319 #if (defined(CONFIG_CPU_V7) && \
320 (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
321 defined(CONFIG_SMP_ON_UP)
322 #define __flush_icache_preferred __cpuc_flush_icache_all
323 #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
324 #define __flush_icache_preferred __flush_icache_all_v7_smp
325 #elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
326 #define __flush_icache_preferred __cpuc_flush_icache_all
328 #define __flush_icache_preferred __flush_icache_all_generic
331 static inline void __flush_icache_all(void)
333 __flush_icache_preferred();
336 #define flush_cache_all() __cpuc_flush_kern_all()
338 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
340 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
341 __cpuc_flush_user_all();
345 vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
347 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
348 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
353 vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
355 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
356 unsigned long addr = user_addr & PAGE_MASK;
357 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
361 #ifndef CONFIG_CPU_CACHE_VIPT
362 #define flush_cache_mm(mm) \
363 vivt_flush_cache_mm(mm)
364 #define flush_cache_range(vma,start,end) \
365 vivt_flush_cache_range(vma,start,end)
366 #define flush_cache_page(vma,addr,pfn) \
367 vivt_flush_cache_page(vma,addr,pfn)
369 extern void flush_cache_mm(struct mm_struct *mm);
370 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
371 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
374 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
377 * flush_cache_user_range is used when we want to ensure that the
378 * Harvard caches are synchronised for the user space address range.
379 * This is used for the ARM private sys_cacheflush system call.
381 #define flush_cache_user_range(vma,start,end) \
382 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
385 * Perform necessary cache operations to ensure that data previously
386 * stored within this range of addresses can be executed by the CPU.
388 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
391 * Perform necessary cache operations to ensure that the TLB will
392 * see data written in the specified area.
394 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
397 * flush_dcache_page is used when the kernel has written to the page
398 * cache page at virtual address page->virtual.
400 * If this page isn't mapped (ie, page_mapping == NULL), or it might
401 * have userspace mappings, then we _must_ always clean + invalidate
402 * the dcache entries associated with the kernel mapping.
404 * Otherwise we can defer the operation, and clean the cache when we are
405 * about to change to user space. This is the same method as used on SPARC64.
406 * See update_mmu_cache for the user space part.
408 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
409 extern void flush_dcache_page(struct page *);
411 static inline void flush_kernel_vmap_range(void *addr, int size)
413 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
414 __cpuc_flush_dcache_area(addr, (size_t)size);
416 static inline void invalidate_kernel_vmap_range(void *addr, int size)
418 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
419 __cpuc_flush_dcache_area(addr, (size_t)size);
422 #define ARCH_HAS_FLUSH_ANON_PAGE
423 static inline void flush_anon_page(struct vm_area_struct *vma,
424 struct page *page, unsigned long vmaddr)
426 extern void __flush_anon_page(struct vm_area_struct *vma,
427 struct page *, unsigned long);
429 __flush_anon_page(vma, page, vmaddr);
432 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
433 static inline void flush_kernel_dcache_page(struct page *page)
437 #define flush_dcache_mmap_lock(mapping) \
438 spin_lock_irq(&(mapping)->tree_lock)
439 #define flush_dcache_mmap_unlock(mapping) \
440 spin_unlock_irq(&(mapping)->tree_lock)
442 #define flush_icache_user_range(vma,page,addr,len) \
443 flush_dcache_page(page)
446 * We don't appear to need to do anything here. In fact, if we did, we'd
447 * duplicate cache flushing elsewhere performed by flush_dcache_page().
449 #define flush_icache_page(vma,page) do { } while (0)
452 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
453 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
454 * caches, since the direct-mappings of these pages may contain cached
455 * data, we need to do a full cache flush to ensure that writebacks
456 * don't corrupt data placed into these pages via the new mappings.
458 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
460 if (!cache_is_vipt_nonaliasing())
464 * set_pte_at() called from vmap_pte_range() does not
465 * have a DSB after cleaning the cache line.
470 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
472 if (!cache_is_vipt_nonaliasing())