2 * arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/compiler.h>
15 #include <linux/types.h>
16 #include <asm/system.h>
18 #define ATOMIC_INIT(i) { (i) }
23 * On ARM, ordinary assignment (str instruction) doesn't clear the local
24 * strex/ldrex monitor on some implementations. The reason we can use it for
25 * atomic_set() is the clrex or dummy strex done on every exception return.
27 #define atomic_read(v) (*(volatile int *)&(v)->counter)
28 #define atomic_set(v,i) (((v)->counter) = (i))
30 #if __LINUX_ARM_ARCH__ >= 6
33 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
34 * store exclusive to ensure that these are atomic. We may loop
35 * to ensure that the update happens.
37 static inline void atomic_add(int i, atomic_t *v)
42 __asm__ __volatile__("@ atomic_add\n"
45 " strex %1, %0, [%3]\n"
48 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
49 : "r" (&v->counter), "Ir" (i)
53 static inline int atomic_add_return(int i, atomic_t *v)
60 __asm__ __volatile__("@ atomic_add_return\n"
63 " strex %1, %0, [%3]\n"
66 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
67 : "r" (&v->counter), "Ir" (i)
75 static inline void atomic_sub(int i, atomic_t *v)
80 __asm__ __volatile__("@ atomic_sub\n"
83 " strex %1, %0, [%3]\n"
86 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
87 : "r" (&v->counter), "Ir" (i)
91 static inline int atomic_sub_return(int i, atomic_t *v)
98 __asm__ __volatile__("@ atomic_sub_return\n"
101 " strex %1, %0, [%3]\n"
104 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
105 : "r" (&v->counter), "Ir" (i)
113 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
115 unsigned long oldval, res;
120 __asm__ __volatile__("@ atomic_cmpxchg\n"
124 "strexeq %0, %5, [%3]\n"
125 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
126 : "r" (&ptr->counter), "Ir" (old), "r" (new)
135 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
137 unsigned long tmp, tmp2;
139 __asm__ __volatile__("@ atomic_clear_mask\n"
140 "1: ldrex %0, [%3]\n"
142 " strex %1, %0, [%3]\n"
145 : "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)
146 : "r" (addr), "Ir" (mask)
150 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
157 __asm__ __volatile__ ("@ atomic_add_unless\n"
158 "1: ldrex %0, [%4]\n"
162 " strex %2, %1, [%4]\n"
166 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
167 : "r" (&v->counter), "r" (u), "r" (a)
176 #else /* ARM_ARCH_6 */
179 #error SMP not supported on pre-ARMv6 CPUs
182 static inline int atomic_add_return(int i, atomic_t *v)
187 raw_local_irq_save(flags);
189 v->counter = val += i;
190 raw_local_irq_restore(flags);
194 #define atomic_add(i, v) (void) atomic_add_return(i, v)
196 static inline int atomic_sub_return(int i, atomic_t *v)
201 raw_local_irq_save(flags);
203 v->counter = val -= i;
204 raw_local_irq_restore(flags);
208 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
210 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
215 raw_local_irq_save(flags);
217 if (likely(ret == old))
219 raw_local_irq_restore(flags);
224 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
228 raw_local_irq_save(flags);
230 raw_local_irq_restore(flags);
233 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
238 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
243 #endif /* __LINUX_ARM_ARCH__ */
245 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
247 #define atomic_inc(v) atomic_add(1, v)
248 #define atomic_dec(v) atomic_sub(1, v)
250 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
251 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
252 #define atomic_inc_return(v) (atomic_add_return(1, v))
253 #define atomic_dec_return(v) (atomic_sub_return(1, v))
254 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
256 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
258 #define smp_mb__before_atomic_dec() smp_mb()
259 #define smp_mb__after_atomic_dec() smp_mb()
260 #define smp_mb__before_atomic_inc() smp_mb()
261 #define smp_mb__after_atomic_inc() smp_mb()
263 #ifndef CONFIG_GENERIC_ATOMIC64
265 u64 __aligned(8) counter;
268 #define ATOMIC64_INIT(i) { (i) }
270 static inline u64 atomic64_read(const atomic64_t *v)
274 __asm__ __volatile__("@ atomic64_read\n"
275 " ldrexd %0, %H0, [%1]"
277 : "r" (&v->counter), "Qo" (v->counter)
283 static inline void atomic64_set(atomic64_t *v, u64 i)
287 __asm__ __volatile__("@ atomic64_set\n"
288 "1: ldrexd %0, %H0, [%2]\n"
289 " strexd %0, %3, %H3, [%2]\n"
292 : "=&r" (tmp), "=Qo" (v->counter)
293 : "r" (&v->counter), "r" (i)
297 static inline void atomic64_add(u64 i, atomic64_t *v)
302 __asm__ __volatile__("@ atomic64_add\n"
303 "1: ldrexd %0, %H0, [%3]\n"
305 " adc %H0, %H0, %H4\n"
306 " strexd %1, %0, %H0, [%3]\n"
309 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
310 : "r" (&v->counter), "r" (i)
314 static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
321 __asm__ __volatile__("@ atomic64_add_return\n"
322 "1: ldrexd %0, %H0, [%3]\n"
324 " adc %H0, %H0, %H4\n"
325 " strexd %1, %0, %H0, [%3]\n"
328 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
329 : "r" (&v->counter), "r" (i)
337 static inline void atomic64_sub(u64 i, atomic64_t *v)
342 __asm__ __volatile__("@ atomic64_sub\n"
343 "1: ldrexd %0, %H0, [%3]\n"
345 " sbc %H0, %H0, %H4\n"
346 " strexd %1, %0, %H0, [%3]\n"
349 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
350 : "r" (&v->counter), "r" (i)
354 static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
361 __asm__ __volatile__("@ atomic64_sub_return\n"
362 "1: ldrexd %0, %H0, [%3]\n"
364 " sbc %H0, %H0, %H4\n"
365 " strexd %1, %0, %H0, [%3]\n"
368 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
369 : "r" (&v->counter), "r" (i)
377 static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
385 __asm__ __volatile__("@ atomic64_cmpxchg\n"
386 "ldrexd %1, %H1, [%3]\n"
390 "strexdeq %0, %5, %H5, [%3]"
391 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
392 : "r" (&ptr->counter), "r" (old), "r" (new)
401 static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
408 __asm__ __volatile__("@ atomic64_xchg\n"
409 "1: ldrexd %0, %H0, [%3]\n"
410 " strexd %1, %4, %H4, [%3]\n"
413 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
414 : "r" (&ptr->counter), "r" (new)
422 static inline u64 atomic64_dec_if_positive(atomic64_t *v)
429 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
430 "1: ldrexd %0, %H0, [%3]\n"
432 " sbc %H0, %H0, #0\n"
435 " strexd %1, %0, %H0, [%3]\n"
439 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
448 static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
456 __asm__ __volatile__("@ atomic64_add_unless\n"
457 "1: ldrexd %0, %H0, [%4]\n"
463 " adc %H0, %H0, %H6\n"
464 " strexd %2, %0, %H0, [%4]\n"
468 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
469 : "r" (&v->counter), "r" (u), "r" (a)
478 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
479 #define atomic64_inc(v) atomic64_add(1LL, (v))
480 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
481 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
482 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
483 #define atomic64_dec(v) atomic64_sub(1LL, (v))
484 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
485 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
486 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
488 #endif /* !CONFIG_GENERIC_ATOMIC64 */