arch/arm/boot/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53
  54 #include <dt-bindings/pinctrl/sun4i-a10.h>
  55
  56 / {
  57         interrupt-parent = <&gic>;
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0";
  68                         clocks = <&pll6 0>;
  69                         status = "disabled";
  70                 };
  71         };
  72
  73         cpus {
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76
  77                 cpu@0 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <0>;
  81                 };
  82
  83                 cpu@1 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                 };
  88         };
  89
  90         memory {
  91                 reg = <0x40000000 0x40000000>;
  92         };
  93
  94         clocks {
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 osc24M: osc24M_clk {
 100                         #clock-cells = <0>;
 101                         compatible = "fixed-clock";
 102                         clock-frequency = <24000000>;
 103                         clock-output-names = "osc24M";
 104                 };
 105
 106                 osc32k: osc32k_clk {
 107                         #clock-cells = <0>;
 108                         compatible = "fixed-clock";
 109                         clock-frequency = <32768>;
 110                         clock-output-names = "osc32k";
 111                 };
 112
 113                 pll1: clk@01c20000 {
 114                         #clock-cells = <0>;
 115                         compatible = "allwinner,sun8i-a23-pll1-clk";
 116                         reg = <0x01c20000 0x4>;
 117                         clocks = <&osc24M>;
 118                         clock-output-names = "pll1";
 119                 };
 120
 121                 /* dummy clock until actually implemented */
 122                 pll6: pll6_clk {
 123                         #clock-cells = <0>;
 124                         compatible = "fixed-clock";
 125                         clock-frequency = <600000000>;
 126                         clock-output-names = "pll6";
 127                 };
 128
 129                 cpu: cpu_clk@01c20050 {
 130                         #clock-cells = <0>;
 131                         compatible = "allwinner,sun4i-a10-cpu-clk";
 132                         reg = <0x01c20050 0x4>;
 133
 134                         /*
 135                          * PLL1 is listed twice here.
 136                          * While it looks suspicious, it's actually documented
 137                          * that way both in the datasheet and in the code from
 138                          * Allwinner.
 139                          */
 140                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 141                         clock-output-names = "cpu";
 142                 };
 143
 144                 axi: axi_clk@01c20050 {
 145                         #clock-cells = <0>;
 146                         compatible = "allwinner,sun8i-a23-axi-clk";
 147                         reg = <0x01c20050 0x4>;
 148                         clocks = <&cpu>;
 149                         clock-output-names = "axi";
 150                 };
 151
 152                 ahb1_mux: ahb1_mux_clk@01c20054 {
 153                         #clock-cells = <0>;
 154                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 155                         reg = <0x01c20054 0x4>;
 156                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 157                         clock-output-names = "ahb1_mux";
 158                 };
 159
 160                 ahb1: ahb1_clk@01c20054 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun4i-a10-ahb-clk";
 163                         reg = <0x01c20054 0x4>;
 164                         clocks = <&ahb1_mux>;
 165                         clock-output-names = "ahb1";
 166                 };
 167
 168                 apb1: apb1_clk@01c20054 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun4i-a10-apb0-clk";
 171                         reg = <0x01c20054 0x4>;
 172                         clocks = <&ahb1>;
 173                         clock-output-names = "apb1";
 174                 };
 175
 176                 ahb1_gates: clk@01c20060 {
 177                         #clock-cells = <1>;
 178                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 179                         reg = <0x01c20060 0x8>;
 180                         clocks = <&ahb1>;
 181                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 182                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 183                                         "ahb1_nand", "ahb1_sdram",
 184                                         "ahb1_hstimer", "ahb1_spi0",
 185                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
 186                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
 187                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
 188                                         "ahb1_gpu", "ahb1_spinlock",
 189                                         "ahb1_drc";
 190                 };
 191
 192                 apb1_gates: clk@01c20068 {
 193                         #clock-cells = <1>;
 194                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 195                         reg = <0x01c20068 0x4>;
 196                         clocks = <&apb1>;
 197                         clock-output-names = "apb1_codec", "apb1_pio",
 198                                         "apb1_daudio0", "apb1_daudio1";
 199                 };
 200
 201                 apb2: clk@01c20058 {
 202                         #clock-cells = <0>;
 203                         compatible = "allwinner,sun4i-a10-apb1-clk";
 204                         reg = <0x01c20058 0x4>;
 205                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 206                         clock-output-names = "apb2";
 207                 };
 208
 209                 apb2_gates: clk@01c2006c {
 210                         #clock-cells = <1>;
 211                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 212                         reg = <0x01c2006c 0x4>;
 213                         clocks = <&apb2>;
 214                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 215                                         "apb2_i2c2", "apb2_uart0",
 216                                         "apb2_uart1", "apb2_uart2",
 217                                         "apb2_uart3", "apb2_uart4";
 218                 };
 219
 220                 mmc0_clk: clk@01c20088 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-a10-mod0-clk";
 223                         reg = <0x01c20088 0x4>;
 224                         clocks = <&osc24M>, <&pll6>;
 225                         clock-output-names = "mmc0";
 226                 };
 227
 228                 mmc1_clk: clk@01c2008c {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-a10-mod0-clk";
 231                         reg = <0x01c2008c 0x4>;
 232                         clocks = <&osc24M>, <&pll6>;
 233                         clock-output-names = "mmc1";
 234                 };
 235
 236                 mmc2_clk: clk@01c20090 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-a10-mod0-clk";
 239                         reg = <0x01c20090 0x4>;
 240                         clocks = <&osc24M>, <&pll6>;
 241                         clock-output-names = "mmc2";
 242                 };
 243         };
 244
 245         soc@01c00000 {
 246                 compatible = "simple-bus";
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249                 ranges;
 250
 251                 dma: dma-controller@01c02000 {
 252                         compatible = "allwinner,sun8i-a23-dma";
 253                         reg = <0x01c02000 0x1000>;
 254                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 255                         clocks = <&ahb1_gates 6>;
 256                         resets = <&ahb1_rst 6>;
 257                         #dma-cells = <1>;
 258                 };
 259
 260                 mmc0: mmc@01c0f000 {
 261                         compatible = "allwinner,sun5i-a13-mmc";
 262                         reg = <0x01c0f000 0x1000>;
 263                         clocks = <&ahb1_gates 8>, <&mmc0_clk>;
 264                         clock-names = "ahb", "mmc";
 265                         resets = <&ahb1_rst 8>;
 266                         reset-names = "ahb";
 267                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 268                         status = "disabled";
 269                 };
 270
 271                 mmc1: mmc@01c10000 {
 272                         compatible = "allwinner,sun5i-a13-mmc";
 273                         reg = <0x01c10000 0x1000>;
 274                         clocks = <&ahb1_gates 9>, <&mmc1_clk>;
 275                         clock-names = "ahb", "mmc";
 276                         resets = <&ahb1_rst 9>;
 277                         reset-names = "ahb";
 278                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 279                         status = "disabled";
 280                 };
 281
 282                 mmc2: mmc@01c11000 {
 283                         compatible = "allwinner,sun5i-a13-mmc";
 284                         reg = <0x01c11000 0x1000>;
 285                         clocks = <&ahb1_gates 10>, <&mmc2_clk>;
 286                         clock-names = "ahb", "mmc";
 287                         resets = <&ahb1_rst 10>;
 288                         reset-names = "ahb";
 289                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 290                         status = "disabled";
 291                 };
 292
 293                 pio: pinctrl@01c20800 {
 294                         compatible = "allwinner,sun8i-a23-pinctrl";
 295                         reg = <0x01c20800 0x400>;
 296                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 297                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&apb1_gates 5>;
 300                         gpio-controller;
 301                         interrupt-controller;
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                         #gpio-cells = <3>;
 305
 306                         uart0_pins_a: uart0@0 {
 307                                 allwinner,pins = "PF2", "PF4";
 308                                 allwinner,function = "uart0";
 309                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 310                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 311                         };
 312
 313                         mmc0_pins_a: mmc0@0 {
 314                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 315                                 allwinner,function = "mmc0";
 316                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 317                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 318                         };
 319
 320                         mmc1_pins_a: mmc1@0 {
 321                                 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 322                                 allwinner,function = "mmc1";
 323                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 324                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 325                         };
 326
 327                         i2c0_pins_a: i2c0@0 {
 328                                 allwinner,pins = "PH2", "PH3";
 329                                 allwinner,function = "i2c0";
 330                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 331                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 332                         };
 333
 334                         i2c1_pins_a: i2c1@0 {
 335                                 allwinner,pins = "PH4", "PH5";
 336                                 allwinner,function = "i2c1";
 337                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 338                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 339                         };
 340
 341                         i2c2_pins_a: i2c2@0 {
 342                                 allwinner,pins = "PE12", "PE13";
 343                                 allwinner,function = "i2c2";
 344                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 345                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 346                         };
 347                 };
 348
 349                 ahb1_rst: reset@01c202c0 {
 350                         #reset-cells = <1>;
 351                         compatible = "allwinner,sun6i-a31-clock-reset";
 352                         reg = <0x01c202c0 0xc>;
 353                 };
 354
 355                 apb1_rst: reset@01c202d0 {
 356                         #reset-cells = <1>;
 357                         compatible = "allwinner,sun6i-a31-clock-reset";
 358                         reg = <0x01c202d0 0x4>;
 359                 };
 360
 361                 apb2_rst: reset@01c202d8 {
 362                         #reset-cells = <1>;
 363                         compatible = "allwinner,sun6i-a31-clock-reset";
 364                         reg = <0x01c202d8 0x4>;
 365                 };
 366
 367                 timer@01c20c00 {
 368                         compatible = "allwinner,sun4i-a10-timer";
 369                         reg = <0x01c20c00 0xa0>;
 370                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&osc24M>;
 373                 };
 374
 375                 wdt0: watchdog@01c20ca0 {
 376                         compatible = "allwinner,sun6i-a31-wdt";
 377                         reg = <0x01c20ca0 0x20>;
 378                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 379                 };
 380
 381                 lradc: lradc@01c22800 {
 382                         compatible = "allwinner,sun4i-a10-lradc-keys";
 383                         reg = <0x01c22800 0x100>;
 384                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 385                         status = "disabled";
 386                 };
 387
 388                 uart0: serial@01c28000 {
 389                         compatible = "snps,dw-apb-uart";
 390                         reg = <0x01c28000 0x400>;
 391                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 392                         reg-shift = <2>;
 393                         reg-io-width = <4>;
 394                         clocks = <&apb2_gates 16>;
 395                         resets = <&apb2_rst 16>;
 396                         dmas = <&dma 6>, <&dma 6>;
 397                         dma-names = "rx", "tx";
 398                         status = "disabled";
 399                 };
 400
 401                 uart1: serial@01c28400 {
 402                         compatible = "snps,dw-apb-uart";
 403                         reg = <0x01c28400 0x400>;
 404                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 405                         reg-shift = <2>;
 406                         reg-io-width = <4>;
 407                         clocks = <&apb2_gates 17>;
 408                         resets = <&apb2_rst 17>;
 409                         dmas = <&dma 7>, <&dma 7>;
 410                         dma-names = "rx", "tx";
 411                         status = "disabled";
 412                 };
 413
 414                 uart2: serial@01c28800 {
 415                         compatible = "snps,dw-apb-uart";
 416                         reg = <0x01c28800 0x400>;
 417                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 418                         reg-shift = <2>;
 419                         reg-io-width = <4>;
 420                         clocks = <&apb2_gates 18>;
 421                         resets = <&apb2_rst 18>;
 422                         dmas = <&dma 8>, <&dma 8>;
 423                         dma-names = "rx", "tx";
 424                         status = "disabled";
 425                 };
 426
 427                 uart3: serial@01c28c00 {
 428                         compatible = "snps,dw-apb-uart";
 429                         reg = <0x01c28c00 0x400>;
 430                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 431                         reg-shift = <2>;
 432                         reg-io-width = <4>;
 433                         clocks = <&apb2_gates 19>;
 434                         resets = <&apb2_rst 19>;
 435                         dmas = <&dma 9>, <&dma 9>;
 436                         dma-names = "rx", "tx";
 437                         status = "disabled";
 438                 };
 439
 440                 uart4: serial@01c29000 {
 441                         compatible = "snps,dw-apb-uart";
 442                         reg = <0x01c29000 0x400>;
 443                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 444                         reg-shift = <2>;
 445                         reg-io-width = <4>;
 446                         clocks = <&apb2_gates 20>;
 447                         resets = <&apb2_rst 20>;
 448                         dmas = <&dma 10>, <&dma 10>;
 449                         dma-names = "rx", "tx";
 450                         status = "disabled";
 451                 };
 452
 453                 i2c0: i2c@01c2ac00 {
 454                         compatible = "allwinner,sun6i-a31-i2c";
 455                         reg = <0x01c2ac00 0x400>;
 456                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&apb2_gates 0>;
 458                         resets = <&apb2_rst 0>;
 459                         status = "disabled";
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                 };
 463
 464                 i2c1: i2c@01c2b000 {
 465                         compatible = "allwinner,sun6i-a31-i2c";
 466                         reg = <0x01c2b000 0x400>;
 467                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 468                         clocks = <&apb2_gates 1>;
 469                         resets = <&apb2_rst 1>;
 470                         status = "disabled";
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                 };
 474
 475                 i2c2: i2c@01c2b400 {
 476                         compatible = "allwinner,sun6i-a31-i2c";
 477                         reg = <0x01c2b400 0x400>;
 478                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&apb2_gates 2>;
 480                         resets = <&apb2_rst 2>;
 481                         status = "disabled";
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                 };
 485
 486                 gic: interrupt-controller@01c81000 {
 487                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 488                         reg = <0x01c81000 0x1000>,
 489                               <0x01c82000 0x1000>,
 490                               <0x01c84000 0x2000>,
 491                               <0x01c86000 0x2000>;
 492                         interrupt-controller;
 493                         #interrupt-cells = <3>;
 494                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 495                 };
 496
 497                 rtc: rtc@01f00000 {
 498                         compatible = "allwinner,sun6i-a31-rtc";
 499                         reg = <0x01f00000 0x54>;
 500                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 501                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 502                 };
 503
 504                 prcm@01f01400 {
 505                         compatible = "allwinner,sun8i-a23-prcm";
 506                         reg = <0x01f01400 0x200>;
 507
 508                         ar100: ar100_clk {
 509                                 compatible = "fixed-factor-clock";
 510                                 #clock-cells = <0>;
 511                                 clock-div = <1>;
 512                                 clock-mult = <1>;
 513                                 clocks = <&osc24M>;
 514                                 clock-output-names = "ar100";
 515                         };
 516
 517                         ahb0: ahb0_clk {
 518                                 compatible = "fixed-factor-clock";
 519                                 #clock-cells = <0>;
 520                                 clock-div = <1>;
 521                                 clock-mult = <1>;
 522                                 clocks = <&ar100>;
 523                                 clock-output-names = "ahb0";
 524                         };
 525
 526                         apb0: apb0_clk {
 527                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 528                                 #clock-cells = <0>;
 529                                 clocks = <&ahb0>;
 530                                 clock-output-names = "apb0";
 531                         };
 532
 533                         apb0_gates: apb0_gates_clk {
 534                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 535                                 #clock-cells = <1>;
 536                                 clocks = <&apb0>;
 537                                 clock-output-names = "apb0_pio", "apb0_timer",
 538                                                 "apb0_rsb", "apb0_uart",
 539                                                 "apb0_i2c";
 540                         };
 541
 542                         apb0_rst: apb0_rst {
 543                                 compatible = "allwinner,sun6i-a31-clock-reset";
 544                                 #reset-cells = <1>;
 545                         };
 546                 };
 547
 548                 r_uart: serial@01f02800 {
 549                         compatible = "snps,dw-apb-uart";
 550                         reg = <0x01f02800 0x400>;
 551                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 552                         reg-shift = <2>;
 553                         reg-io-width = <4>;
 554                         clocks = <&apb0_gates 4>;
 555                         resets = <&apb0_rst 4>;
 556                         status = "disabled";
 557                 };
 558
 559                 r_pio: pinctrl@01f02c00 {
 560                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 561                         reg = <0x01f02c00 0x400>;
 562                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&apb0_gates 0>;
 564                         resets = <&apb0_rst 0>;
 565                         gpio-controller;
 566                         interrupt-controller;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         #gpio-cells = <3>;
 570
 571                         r_uart_pins_a: r_uart@0 {
 572                                 allwinner,pins = "PL2", "PL3";
 573                                 allwinner,function = "s_uart";
 574                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 575                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 576                         };
 577                 };
 578         };
 579 };