2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
15 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/dma/sun4i-a10.h>
18 #include <dt-bindings/pinctrl/sun4i-a10.h>
21 interrupt-parent = <&intc>;
33 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34 allwinner,pipeline = "de_be0-lcd0-hdmi";
35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
41 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
42 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
44 <&ahb_gates 44>, <&ahb_gates 46>;
49 compatible = "allwinner,simple-framebuffer",
51 allwinner,pipeline = "de_fe0-de_be0-lcd0";
52 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
58 compatible = "allwinner,simple-framebuffer",
60 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
61 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
62 <&ahb_gates 44>, <&ahb_gates 46>;
72 compatible = "arm,cortex-a8";
75 clock-latency = <244144>; /* 8 32k periods */
85 cooling-min-level = <0>;
86 cooling-max-level = <4>;
93 polling-delay-passive = <250>;
94 polling-delay = <1000>;
95 thermal-sensors = <&rtp>;
100 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
105 cpu_alert0: cpu_alert0 {
107 temperature = <850000>;
114 temperature = <100000>;
123 reg = <0x40000000 0x80000000>;
127 #address-cells = <1>;
132 * This is a dummy clock, to be used as placeholder on
133 * other mux clocks when a specific parent clock is not
134 * yet implemented. It should be dropped when the driver
139 compatible = "fixed-clock";
140 clock-frequency = <0>;
143 osc24M: clk@01c20050 {
145 compatible = "allwinner,sun4i-a10-osc-clk";
146 reg = <0x01c20050 0x4>;
147 clock-frequency = <24000000>;
148 clock-output-names = "osc24M";
153 compatible = "fixed-clock";
154 clock-frequency = <32768>;
155 clock-output-names = "osc32k";
160 compatible = "allwinner,sun4i-a10-pll1-clk";
161 reg = <0x01c20000 0x4>;
163 clock-output-names = "pll1";
168 compatible = "allwinner,sun4i-a10-pll1-clk";
169 reg = <0x01c20018 0x4>;
171 clock-output-names = "pll4";
176 compatible = "allwinner,sun4i-a10-pll5-clk";
177 reg = <0x01c20020 0x4>;
179 clock-output-names = "pll5_ddr", "pll5_other";
184 compatible = "allwinner,sun4i-a10-pll6-clk";
185 reg = <0x01c20028 0x4>;
187 clock-output-names = "pll6_sata", "pll6_other", "pll6";
193 compatible = "allwinner,sun4i-a10-cpu-clk";
194 reg = <0x01c20054 0x4>;
195 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
196 clock-output-names = "cpu";
201 compatible = "allwinner,sun4i-a10-axi-clk";
202 reg = <0x01c20054 0x4>;
204 clock-output-names = "axi";
207 axi_gates: clk@01c2005c {
209 compatible = "allwinner,sun4i-a10-axi-gates-clk";
210 reg = <0x01c2005c 0x4>;
212 clock-output-names = "axi_dram";
217 compatible = "allwinner,sun4i-a10-ahb-clk";
218 reg = <0x01c20054 0x4>;
220 clock-output-names = "ahb";
223 ahb_gates: clk@01c20060 {
225 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
226 reg = <0x01c20060 0x8>;
228 clock-output-names = "ahb_usb0", "ahb_ehci0",
229 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
230 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
231 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
232 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
233 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
234 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
235 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
236 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
237 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
238 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
241 apb0: apb0@01c20054 {
243 compatible = "allwinner,sun4i-a10-apb0-clk";
244 reg = <0x01c20054 0x4>;
246 clock-output-names = "apb0";
249 apb0_gates: clk@01c20068 {
251 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
252 reg = <0x01c20068 0x4>;
254 clock-output-names = "apb0_codec", "apb0_spdif",
255 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
256 "apb0_ir1", "apb0_keypad";
261 compatible = "allwinner,sun4i-a10-apb1-clk";
262 reg = <0x01c20058 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
264 clock-output-names = "apb1";
267 apb1_gates: clk@01c2006c {
269 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
270 reg = <0x01c2006c 0x4>;
272 clock-output-names = "apb1_i2c0", "apb1_i2c1",
273 "apb1_i2c2", "apb1_can", "apb1_scr",
274 "apb1_ps20", "apb1_ps21", "apb1_uart0",
275 "apb1_uart1", "apb1_uart2", "apb1_uart3",
276 "apb1_uart4", "apb1_uart5", "apb1_uart6",
280 nand_clk: clk@01c20080 {
282 compatible = "allwinner,sun4i-a10-mod0-clk";
283 reg = <0x01c20080 0x4>;
284 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
285 clock-output-names = "nand";
288 ms_clk: clk@01c20084 {
290 compatible = "allwinner,sun4i-a10-mod0-clk";
291 reg = <0x01c20084 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "ms";
296 mmc0_clk: clk@01c20088 {
298 compatible = "allwinner,sun4i-a10-mod0-clk";
299 reg = <0x01c20088 0x4>;
300 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 clock-output-names = "mmc0";
304 mmc1_clk: clk@01c2008c {
306 compatible = "allwinner,sun4i-a10-mod0-clk";
307 reg = <0x01c2008c 0x4>;
308 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
309 clock-output-names = "mmc1";
312 mmc2_clk: clk@01c20090 {
314 compatible = "allwinner,sun4i-a10-mod0-clk";
315 reg = <0x01c20090 0x4>;
316 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
317 clock-output-names = "mmc2";
320 mmc3_clk: clk@01c20094 {
322 compatible = "allwinner,sun4i-a10-mod0-clk";
323 reg = <0x01c20094 0x4>;
324 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
325 clock-output-names = "mmc3";
328 ts_clk: clk@01c20098 {
330 compatible = "allwinner,sun4i-a10-mod0-clk";
331 reg = <0x01c20098 0x4>;
332 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
333 clock-output-names = "ts";
336 ss_clk: clk@01c2009c {
338 compatible = "allwinner,sun4i-a10-mod0-clk";
339 reg = <0x01c2009c 0x4>;
340 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
341 clock-output-names = "ss";
344 spi0_clk: clk@01c200a0 {
346 compatible = "allwinner,sun4i-a10-mod0-clk";
347 reg = <0x01c200a0 0x4>;
348 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
349 clock-output-names = "spi0";
352 spi1_clk: clk@01c200a4 {
354 compatible = "allwinner,sun4i-a10-mod0-clk";
355 reg = <0x01c200a4 0x4>;
356 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
357 clock-output-names = "spi1";
360 spi2_clk: clk@01c200a8 {
362 compatible = "allwinner,sun4i-a10-mod0-clk";
363 reg = <0x01c200a8 0x4>;
364 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
365 clock-output-names = "spi2";
368 pata_clk: clk@01c200ac {
370 compatible = "allwinner,sun4i-a10-mod0-clk";
371 reg = <0x01c200ac 0x4>;
372 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
373 clock-output-names = "pata";
376 ir0_clk: clk@01c200b0 {
378 compatible = "allwinner,sun4i-a10-mod0-clk";
379 reg = <0x01c200b0 0x4>;
380 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
381 clock-output-names = "ir0";
384 ir1_clk: clk@01c200b4 {
386 compatible = "allwinner,sun4i-a10-mod0-clk";
387 reg = <0x01c200b4 0x4>;
388 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
389 clock-output-names = "ir1";
392 usb_clk: clk@01c200cc {
395 compatible = "allwinner,sun4i-a10-usb-clk";
396 reg = <0x01c200cc 0x4>;
398 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
401 spi3_clk: clk@01c200d4 {
403 compatible = "allwinner,sun4i-a10-mod0-clk";
404 reg = <0x01c200d4 0x4>;
405 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
406 clock-output-names = "spi3";
411 compatible = "simple-bus";
412 #address-cells = <1>;
416 dma: dma-controller@01c02000 {
417 compatible = "allwinner,sun4i-a10-dma";
418 reg = <0x01c02000 0x1000>;
420 clocks = <&ahb_gates 6>;
425 compatible = "allwinner,sun4i-a10-spi";
426 reg = <0x01c05000 0x1000>;
428 clocks = <&ahb_gates 20>, <&spi0_clk>;
429 clock-names = "ahb", "mod";
430 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
431 <&dma SUN4I_DMA_DEDICATED 26>;
432 dma-names = "rx", "tx";
434 #address-cells = <1>;
439 compatible = "allwinner,sun4i-a10-spi";
440 reg = <0x01c06000 0x1000>;
442 clocks = <&ahb_gates 21>, <&spi1_clk>;
443 clock-names = "ahb", "mod";
444 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
445 <&dma SUN4I_DMA_DEDICATED 8>;
446 dma-names = "rx", "tx";
448 #address-cells = <1>;
452 emac: ethernet@01c0b000 {
453 compatible = "allwinner,sun4i-a10-emac";
454 reg = <0x01c0b000 0x1000>;
456 clocks = <&ahb_gates 17>;
460 mdio: mdio@01c0b080 {
461 compatible = "allwinner,sun4i-a10-mdio";
462 reg = <0x01c0b080 0x14>;
464 #address-cells = <1>;
469 compatible = "allwinner,sun4i-a10-mmc";
470 reg = <0x01c0f000 0x1000>;
471 clocks = <&ahb_gates 8>, <&mmc0_clk>;
472 clock-names = "ahb", "mmc";
478 compatible = "allwinner,sun4i-a10-mmc";
479 reg = <0x01c10000 0x1000>;
480 clocks = <&ahb_gates 9>, <&mmc1_clk>;
481 clock-names = "ahb", "mmc";
487 compatible = "allwinner,sun4i-a10-mmc";
488 reg = <0x01c11000 0x1000>;
489 clocks = <&ahb_gates 10>, <&mmc2_clk>;
490 clock-names = "ahb", "mmc";
496 compatible = "allwinner,sun4i-a10-mmc";
497 reg = <0x01c12000 0x1000>;
498 clocks = <&ahb_gates 11>, <&mmc3_clk>;
499 clock-names = "ahb", "mmc";
504 usbphy: phy@01c13400 {
506 compatible = "allwinner,sun4i-a10-usb-phy";
507 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
508 reg-names = "phy_ctrl", "pmu1", "pmu2";
509 clocks = <&usb_clk 8>;
510 clock-names = "usb_phy";
511 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
512 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
516 ehci0: usb@01c14000 {
517 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
518 reg = <0x01c14000 0x100>;
520 clocks = <&ahb_gates 1>;
526 ohci0: usb@01c14400 {
527 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
528 reg = <0x01c14400 0x100>;
530 clocks = <&usb_clk 6>, <&ahb_gates 2>;
537 compatible = "allwinner,sun4i-a10-spi";
538 reg = <0x01c17000 0x1000>;
540 clocks = <&ahb_gates 22>, <&spi2_clk>;
541 clock-names = "ahb", "mod";
542 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
543 <&dma SUN4I_DMA_DEDICATED 28>;
544 dma-names = "rx", "tx";
546 #address-cells = <1>;
550 ahci: sata@01c18000 {
551 compatible = "allwinner,sun4i-a10-ahci";
552 reg = <0x01c18000 0x1000>;
554 clocks = <&pll6 0>, <&ahb_gates 25>;
558 ehci1: usb@01c1c000 {
559 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
560 reg = <0x01c1c000 0x100>;
562 clocks = <&ahb_gates 3>;
568 ohci1: usb@01c1c400 {
569 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
570 reg = <0x01c1c400 0x100>;
572 clocks = <&usb_clk 7>, <&ahb_gates 4>;
579 compatible = "allwinner,sun4i-a10-spi";
580 reg = <0x01c1f000 0x1000>;
582 clocks = <&ahb_gates 23>, <&spi3_clk>;
583 clock-names = "ahb", "mod";
584 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
585 <&dma SUN4I_DMA_DEDICATED 30>;
586 dma-names = "rx", "tx";
588 #address-cells = <1>;
592 intc: interrupt-controller@01c20400 {
593 compatible = "allwinner,sun4i-a10-ic";
594 reg = <0x01c20400 0x400>;
595 interrupt-controller;
596 #interrupt-cells = <1>;
599 pio: pinctrl@01c20800 {
600 compatible = "allwinner,sun4i-a10-pinctrl";
601 reg = <0x01c20800 0x400>;
603 clocks = <&apb0_gates 5>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
610 pwm0_pins_a: pwm0@0 {
611 allwinner,pins = "PB2";
612 allwinner,function = "pwm";
613 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
614 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
617 pwm1_pins_a: pwm1@0 {
618 allwinner,pins = "PI3";
619 allwinner,function = "pwm";
620 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
621 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
624 uart0_pins_a: uart0@0 {
625 allwinner,pins = "PB22", "PB23";
626 allwinner,function = "uart0";
627 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
628 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
631 uart0_pins_b: uart0@1 {
632 allwinner,pins = "PF2", "PF4";
633 allwinner,function = "uart0";
634 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
635 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
638 uart1_pins_a: uart1@0 {
639 allwinner,pins = "PA10", "PA11";
640 allwinner,function = "uart1";
641 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
642 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
645 i2c0_pins_a: i2c0@0 {
646 allwinner,pins = "PB0", "PB1";
647 allwinner,function = "i2c0";
648 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
649 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
652 i2c1_pins_a: i2c1@0 {
653 allwinner,pins = "PB18", "PB19";
654 allwinner,function = "i2c1";
655 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
656 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
659 i2c2_pins_a: i2c2@0 {
660 allwinner,pins = "PB20", "PB21";
661 allwinner,function = "i2c2";
662 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
663 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
666 emac_pins_a: emac0@0 {
667 allwinner,pins = "PA0", "PA1", "PA2",
668 "PA3", "PA4", "PA5", "PA6",
669 "PA7", "PA8", "PA9", "PA10",
670 "PA11", "PA12", "PA13", "PA14",
672 allwinner,function = "emac";
673 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
674 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
677 mmc0_pins_a: mmc0@0 {
678 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
679 allwinner,function = "mmc0";
680 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
681 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
684 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
685 allwinner,pins = "PH1";
686 allwinner,function = "gpio_in";
687 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
688 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
692 allwinner,pins = "PB3","PB4";
693 allwinner,function = "ir0";
694 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
695 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
699 allwinner,pins = "PB22","PB23";
700 allwinner,function = "ir1";
701 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
702 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
705 spi0_pins_a: spi0@0 {
706 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
707 allwinner,function = "spi0";
708 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
709 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
712 spi1_pins_a: spi1@0 {
713 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
714 allwinner,function = "spi1";
715 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
716 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
719 spi2_pins_a: spi2@0 {
720 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
721 allwinner,function = "spi2";
722 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
723 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
726 spi2_pins_b: spi2@1 {
727 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
728 allwinner,function = "spi2";
729 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
730 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
733 ps20_pins_a: ps20@0 {
734 allwinner,pins = "PI20", "PI21";
735 allwinner,function = "ps2";
736 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
737 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
740 ps21_pins_a: ps21@0 {
741 allwinner,pins = "PH12", "PH13";
742 allwinner,function = "ps2";
743 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
744 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
749 compatible = "allwinner,sun4i-a10-timer";
750 reg = <0x01c20c00 0x90>;
755 wdt: watchdog@01c20c90 {
756 compatible = "allwinner,sun4i-a10-wdt";
757 reg = <0x01c20c90 0x10>;
761 compatible = "allwinner,sun4i-a10-rtc";
762 reg = <0x01c20d00 0x20>;
767 compatible = "allwinner,sun4i-a10-pwm";
768 reg = <0x01c20e00 0xc>;
775 compatible = "allwinner,sun4i-a10-ir";
776 clocks = <&apb0_gates 6>, <&ir0_clk>;
777 clock-names = "apb", "ir";
779 reg = <0x01c21800 0x40>;
784 compatible = "allwinner,sun4i-a10-ir";
785 clocks = <&apb0_gates 7>, <&ir1_clk>;
786 clock-names = "apb", "ir";
788 reg = <0x01c21c00 0x40>;
792 lradc: lradc@01c22800 {
793 compatible = "allwinner,sun4i-a10-lradc-keys";
794 reg = <0x01c22800 0x100>;
799 sid: eeprom@01c23800 {
800 compatible = "allwinner,sun4i-a10-sid";
801 reg = <0x01c23800 0x10>;
805 compatible = "allwinner,sun4i-a10-ts";
806 reg = <0x01c25000 0x100>;
808 #thermal-sensor-cells = <0>;
811 uart0: serial@01c28000 {
812 compatible = "snps,dw-apb-uart";
813 reg = <0x01c28000 0x400>;
817 clocks = <&apb1_gates 16>;
821 uart1: serial@01c28400 {
822 compatible = "snps,dw-apb-uart";
823 reg = <0x01c28400 0x400>;
827 clocks = <&apb1_gates 17>;
831 uart2: serial@01c28800 {
832 compatible = "snps,dw-apb-uart";
833 reg = <0x01c28800 0x400>;
837 clocks = <&apb1_gates 18>;
841 uart3: serial@01c28c00 {
842 compatible = "snps,dw-apb-uart";
843 reg = <0x01c28c00 0x400>;
847 clocks = <&apb1_gates 19>;
851 uart4: serial@01c29000 {
852 compatible = "snps,dw-apb-uart";
853 reg = <0x01c29000 0x400>;
857 clocks = <&apb1_gates 20>;
861 uart5: serial@01c29400 {
862 compatible = "snps,dw-apb-uart";
863 reg = <0x01c29400 0x400>;
867 clocks = <&apb1_gates 21>;
871 uart6: serial@01c29800 {
872 compatible = "snps,dw-apb-uart";
873 reg = <0x01c29800 0x400>;
877 clocks = <&apb1_gates 22>;
881 uart7: serial@01c29c00 {
882 compatible = "snps,dw-apb-uart";
883 reg = <0x01c29c00 0x400>;
887 clocks = <&apb1_gates 23>;
892 compatible = "allwinner,sun4i-a10-i2c";
893 reg = <0x01c2ac00 0x400>;
895 clocks = <&apb1_gates 0>;
897 #address-cells = <1>;
902 compatible = "allwinner,sun4i-a10-i2c";
903 reg = <0x01c2b000 0x400>;
905 clocks = <&apb1_gates 1>;
907 #address-cells = <1>;
912 compatible = "allwinner,sun4i-a10-i2c";
913 reg = <0x01c2b400 0x400>;
915 clocks = <&apb1_gates 2>;
917 #address-cells = <1>;
922 compatible = "allwinner,sun4i-a10-ps2";
923 reg = <0x01c2a000 0x400>;
925 clocks = <&apb1_gates 6>;
930 compatible = "allwinner,sun4i-a10-ps2";
931 reg = <0x01c2a400 0x400>;
933 clocks = <&apb1_gates 7>;