arch/arm/boot/dts/stih410.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Peter Griffin <peter.griffin@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih410-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 #include "stih410-pinctrl.dtsi"
  12 / {
  13         soc {
  14                 usb2_picophy1: phy2 {
  15                         compatible = "st,stih407-usb2-phy";
  16                         #phy-cells = <0>;
  17                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
  18                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  19                                  <&picophyreset STIH407_PICOPHY0_RESET>;
  20                         reset-names = "global", "port";
  21                 };
  22
  23                 usb2_picophy2: phy3 {
  24                         compatible = "st,stih407-usb2-phy";
  25                         #phy-cells = <0>;
  26                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
  27                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  28                                  <&picophyreset STIH407_PICOPHY1_RESET>;
  29                         reset-names = "global", "port";
  30                 };
  31
  32                 ohci0: usb@9a03c00 {
  33                         compatible = "st,st-ohci-300x";
  34                         reg = <0x9a03c00 0x100>;
  35                         interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
  36                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  37                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  38                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  39                         reset-names = "power", "softreset";
  40                         phys = <&usb2_picophy1>;
  41                         phy-names = "usb";
  42                 };
  43
  44                 ehci0: usb@9a03e00 {
  45                         compatible = "st,st-ehci-300x";
  46                         reg = <0x9a03e00 0x100>;
  47                         interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
  48                         pinctrl-names = "default";
  49                         pinctrl-0 = <&pinctrl_usb0>;
  50                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  51                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  52                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  53                         reset-names = "power", "softreset";
  54                         phys = <&usb2_picophy1>;
  55                         phy-names = "usb";
  56                 };
  57
  58                 ohci1: usb@9a83c00 {
  59                         compatible = "st,st-ohci-300x";
  60                         reg = <0x9a83c00 0x100>;
  61                         interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
  62                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  63                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  64                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  65                         reset-names = "power", "softreset";
  66                         phys = <&usb2_picophy2>;
  67                         phy-names = "usb";
  68                 };
  69
  70                 ehci1: usb@9a83e00 {
  71                         compatible = "st,st-ehci-300x";
  72                         reg = <0x9a83e00 0x100>;
  73                         interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
  74                         pinctrl-names = "default";
  75                         pinctrl-0 = <&pinctrl_usb1>;
  76                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  77                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  78                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  79                         reset-names = "power", "softreset";
  80                         phys = <&usb2_picophy2>;
  81                         phy-names = "usb";
  82                 };
  83
  84                 /* Display */
  85                 vtg_main: sti-vtg-main@8d02800 {
  86                         compatible = "st,vtg";
  87                         reg = <0x8d02800 0x200>;
  88                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
  89                 };
  90
  91                 vtg_aux: sti-vtg-aux@8d00200 {
  92                         compatible = "st,vtg";
  93                         reg = <0x8d00200 0x100>;
  94                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
  95                 };
  96
  97                 sti-display-subsystem {
  98                         compatible = "st,sti-display-subsystem";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101
 102                         assigned-clocks = <&clk_s_d2_quadfs 0>,
 103                                           <&clk_s_d2_quadfs 0>,
 104                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 105                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 106                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 107                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 108                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 109                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
 110
 111                         assigned-clock-parents = <0>,
 112                                                  <0>,
 113                                                  <&clk_s_d2_quadfs 0>,
 114                                                  <&clk_s_d2_quadfs 0>,
 115                                                  <&clk_s_d2_quadfs 0>,
 116                                                  <&clk_s_d2_quadfs 0>,
 117                                                  <&clk_s_d2_quadfs 0>,
 118                                                  <&clk_s_d2_quadfs 0>;
 119
 120                         assigned-clock-rates = <297000000>, <297000000>;
 121
 122                         ranges;
 123
 124                         sti-compositor@9d11000 {
 125                                 compatible = "st,stih407-compositor";
 126                                 reg = <0x9d11000 0x1000>;
 127
 128                                 clock-names = "compo_main",
 129                                               "compo_aux",
 130                                               "pix_main",
 131                                               "pix_aux",
 132                                               "pix_gdp1",
 133                                               "pix_gdp2",
 134                                               "pix_gdp3",
 135                                               "pix_gdp4",
 136                                               "main_parent",
 137                                               "aux_parent";
 138
 139                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 140                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 141                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 142                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 143                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 144                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 145                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 146                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
 147                                          <&clk_s_d2_quadfs 0>,
 148                                          <&clk_s_d2_quadfs 1>;
 149
 150                                 reset-names = "compo-main", "compo-aux";
 151                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
 152                                          <&softreset STIH407_COMPO_SOFTRESET>;
 153                                 st,vtg = <&vtg_main>, <&vtg_aux>;
 154                         };
 155
 156                         sti-tvout@8d08000 {
 157                                 compatible = "st,stih407-tvout";
 158                                 reg = <0x8d08000 0x1000>;
 159                                 reg-names = "tvout-reg";
 160                                 reset-names = "tvout";
 161                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
 162                                 #address-cells = <1>;
 163                                 #size-cells = <1>;
 164                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 165                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 166                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 167                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
 168                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 169                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
 170
 171                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 172                                                          <&clk_tmdsout_hdmi>,
 173                                                          <&clk_s_d2_quadfs 0>,
 174                                                          <&clk_s_d0_quadfs 0>,
 175                                                          <&clk_s_d2_quadfs 0>,
 176                                                          <&clk_s_d2_quadfs 0>;
 177                                 ranges;
 178
 179                                 sti-hdmi@8d04000 {
 180                                         compatible = "st,stih407-hdmi";
 181                                         reg = <0x8d04000 0x1000>;
 182                                         reg-names = "hdmi-reg";
 183                                         interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
 184                                         interrupt-names = "irq";
 185                                         clock-names = "pix",
 186                                                       "tmds",
 187                                                       "phy",
 188                                                       "audio",
 189                                                       "main_parent",
 190                                                       "aux_parent";
 191
 192                                         clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 193                                                  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 194                                                  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 195                                                  <&clk_s_d0_flexgen CLK_PCM_0>,
 196                                                  <&clk_s_d2_quadfs 0>,
 197                                                  <&clk_s_d2_quadfs 1>;
 198
 199                                         hdmi,hpd-gpio = <&pio5 3>;
 200                                         reset-names = "hdmi";
 201                                         resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 202                                         ddc = <&hdmiddc>;
 203
 204                                 };
 205
 206                                 sti-hda@8d02000 {
 207                                         compatible = "st,stih407-hda";
 208                                         reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 209                                         reg-names = "hda-reg", "video-dacs-ctrl";
 210                                         clock-names = "pix",
 211                                                       "hddac",
 212                                                       "main_parent",
 213                                                       "aux_parent";
 214                                         clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 215                                                  <&clk_s_d2_flexgen CLK_HDDAC>,
 216                                                  <&clk_s_d2_quadfs 0>,
 217                                                  <&clk_s_d2_quadfs 1>;
 218                                 };
 219                         };
 220                 };
 221         };
 222 };