arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include "skeleton.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3288";
  23
  24         interrupt-parent = <&gic>;
  25
  26         aliases {
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mshc0 = &emmc;
  34                 mshc1 = &sdmmc;
  35                 mshc2 = &sdio0;
  36                 mshc3 = &sdio1;
  37                 serial0 = &uart0;
  38                 serial1 = &uart1;
  39                 serial2 = &uart2;
  40                 serial3 = &uart3;
  41                 serial4 = &uart4;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 enable-method = "rockchip,rk3066-smp";
  51                 rockchip,pmu = <&pmu>;
  52
  53                 cpu0: cpu@500 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a12";
  56                         reg = <0x500>;
  57                         resets = <&cru SRST_CORE0>;
  58                         operating-points = <
  59                                 /* KHz    uV */
  60                                 1608000 1350000
  61                                 1512000 1300000
  62                                 1416000 1200000
  63                                 1200000 1100000
  64                                 1008000 1050000
  65                                  816000 1000000
  66                                  696000  950000
  67                                  600000  900000
  68                                  408000  900000
  69                                  312000  900000
  70                                  216000  900000
  71                                  126000  900000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77                 cpu@501 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a12";
  80                         reg = <0x501>;
  81                         resets = <&cru SRST_CORE1>;
  82                 };
  83                 cpu@502 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a12";
  86                         reg = <0x502>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89                 cpu@503 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a12";
  92                         reg = <0x503>;
  93                         resets = <&cru SRST_CORE3>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 dmac_peri: dma-controller@ff250000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0xff250000 0x4000>;
 106                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112
 113                 dmac_bus_ns: dma-controller@ff600000 {
 114                         compatible = "arm,pl330", "arm,primecell";
 115                         reg = <0xff600000 0x4000>;
 116                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 118                         #dma-cells = <1>;
 119                         clocks = <&cru ACLK_DMAC1>;
 120                         clock-names = "apb_pclk";
 121                         status = "disabled";
 122                 };
 123
 124                 dmac_bus_s: dma-controller@ffb20000 {
 125                         compatible = "arm,pl330", "arm,primecell";
 126                         reg = <0xffb20000 0x4000>;
 127                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 129                         #dma-cells = <1>;
 130                         clocks = <&cru ACLK_DMAC1>;
 131                         clock-names = "apb_pclk";
 132                 };
 133         };
 134
 135         xin24m: oscillator {
 136                 compatible = "fixed-clock";
 137                 clock-frequency = <24000000>;
 138                 clock-output-names = "xin24m";
 139                 #clock-cells = <0>;
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv7-timer";
 144                 arm,cpu-registers-not-fw-configured;
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 clock-frequency = <24000000>;
 150         };
 151
 152         timer: timer@ff810000 {
 153                 compatible = "rockchip,rk3288-timer";
 154                 reg = <0xff810000 0x20>;
 155                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 157                 clock-names = "timer", "pclk";
 158         };
 159
 160         display-subsystem {
 161                 compatible = "rockchip,display-subsystem";
 162                 ports = <&vopl_out>, <&vopb_out>;
 163         };
 164
 165         sdmmc: dwmmc@ff0c0000 {
 166                 compatible = "rockchip,rk3288-dw-mshc";
 167                 clock-freq-min-max = <400000 150000000>;
 168                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 169                 clock-names = "biu", "ciu";
 170                 fifo-depth = <0x100>;
 171                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 172                 reg = <0xff0c0000 0x4000>;
 173                 status = "disabled";
 174         };
 175
 176         sdio0: dwmmc@ff0d0000 {
 177                 compatible = "rockchip,rk3288-dw-mshc";
 178                 clock-freq-min-max = <400000 150000000>;
 179                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 180                 clock-names = "biu", "ciu";
 181                 fifo-depth = <0x100>;
 182                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 183                 reg = <0xff0d0000 0x4000>;
 184                 status = "disabled";
 185         };
 186
 187         sdio1: dwmmc@ff0e0000 {
 188                 compatible = "rockchip,rk3288-dw-mshc";
 189                 clock-freq-min-max = <400000 150000000>;
 190                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 191                 clock-names = "biu", "ciu";
 192                 fifo-depth = <0x100>;
 193                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 194                 reg = <0xff0e0000 0x4000>;
 195                 status = "disabled";
 196         };
 197
 198         emmc: dwmmc@ff0f0000 {
 199                 compatible = "rockchip,rk3288-dw-mshc";
 200                 clock-freq-min-max = <400000 150000000>;
 201                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 202                 clock-names = "biu", "ciu";
 203                 fifo-depth = <0x100>;
 204                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 205                 reg = <0xff0f0000 0x4000>;
 206                 status = "disabled";
 207         };
 208
 209         saradc: saradc@ff100000 {
 210                 compatible = "rockchip,saradc";
 211                 reg = <0xff100000 0x100>;
 212                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 213                 #io-channel-cells = <1>;
 214                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 215                 clock-names = "saradc", "apb_pclk";
 216                 status = "disabled";
 217         };
 218
 219         spi0: spi@ff110000 {
 220                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 221                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 222                 clock-names = "spiclk", "apb_pclk";
 223                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 224                 dma-names = "tx", "rx";
 225                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 228                 reg = <0xff110000 0x1000>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 status = "disabled";
 232         };
 233
 234         spi1: spi@ff120000 {
 235                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 236                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 237                 clock-names = "spiclk", "apb_pclk";
 238                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 239                 dma-names = "tx", "rx";
 240                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 241                 pinctrl-names = "default";
 242                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 243                 reg = <0xff120000 0x1000>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 status = "disabled";
 247         };
 248
 249         spi2: spi@ff130000 {
 250                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 251                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 252                 clock-names = "spiclk", "apb_pclk";
 253                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 254                 dma-names = "tx", "rx";
 255                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 258                 reg = <0xff130000 0x1000>;
 259                 #address-cells = <1>;
 260                 #size-cells = <0>;
 261                 status = "disabled";
 262         };
 263
 264         i2c1: i2c@ff140000 {
 265                 compatible = "rockchip,rk3288-i2c";
 266                 reg = <0xff140000 0x1000>;
 267                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 268                 #address-cells = <1>;
 269                 #size-cells = <0>;
 270                 clock-names = "i2c";
 271                 clocks = <&cru PCLK_I2C1>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&i2c1_xfer>;
 274                 status = "disabled";
 275         };
 276
 277         i2c3: i2c@ff150000 {
 278                 compatible = "rockchip,rk3288-i2c";
 279                 reg = <0xff150000 0x1000>;
 280                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 clock-names = "i2c";
 284                 clocks = <&cru PCLK_I2C3>;
 285                 pinctrl-names = "default";
 286                 pinctrl-0 = <&i2c3_xfer>;
 287                 status = "disabled";
 288         };
 289
 290         i2c4: i2c@ff160000 {
 291                 compatible = "rockchip,rk3288-i2c";
 292                 reg = <0xff160000 0x1000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 clock-names = "i2c";
 297                 clocks = <&cru PCLK_I2C4>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&i2c4_xfer>;
 300                 status = "disabled";
 301         };
 302
 303         i2c5: i2c@ff170000 {
 304                 compatible = "rockchip,rk3288-i2c";
 305                 reg = <0xff170000 0x1000>;
 306                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 clock-names = "i2c";
 310                 clocks = <&cru PCLK_I2C5>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&i2c5_xfer>;
 313                 status = "disabled";
 314         };
 315
 316         uart0: serial@ff180000 {
 317                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 318                 reg = <0xff180000 0x100>;
 319                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 320                 reg-shift = <2>;
 321                 reg-io-width = <4>;
 322                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 323                 clock-names = "baudclk", "apb_pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&uart0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         uart1: serial@ff190000 {
 330                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 331                 reg = <0xff190000 0x100>;
 332                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 333                 reg-shift = <2>;
 334                 reg-io-width = <4>;
 335                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 336                 clock-names = "baudclk", "apb_pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&uart1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         uart2: serial@ff690000 {
 343                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 344                 reg = <0xff690000 0x100>;
 345                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 346                 reg-shift = <2>;
 347                 reg-io-width = <4>;
 348                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 349                 clock-names = "baudclk", "apb_pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&uart2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         uart3: serial@ff1b0000 {
 356                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 357                 reg = <0xff1b0000 0x100>;
 358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 359                 reg-shift = <2>;
 360                 reg-io-width = <4>;
 361                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 362                 clock-names = "baudclk", "apb_pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&uart3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         uart4: serial@ff1c0000 {
 369                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 370                 reg = <0xff1c0000 0x100>;
 371                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 372                 reg-shift = <2>;
 373                 reg-io-width = <4>;
 374                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 375                 clock-names = "baudclk", "apb_pclk";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&uart4_xfer>;
 378                 status = "disabled";
 379         };
 380
 381         thermal-zones {
 382                 #include "rk3288-thermal.dtsi"
 383         };
 384
 385         tsadc: tsadc@ff280000 {
 386                 compatible = "rockchip,rk3288-tsadc";
 387                 reg = <0xff280000 0x100>;
 388                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 390                 clock-names = "tsadc", "apb_pclk";
 391                 resets = <&cru SRST_TSADC>;
 392                 reset-names = "tsadc-apb";
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&otp_out>;
 395                 #thermal-sensor-cells = <1>;
 396                 rockchip,hw-tshut-temp = <95000>;
 397                 status = "disabled";
 398         };
 399
 400         gmac: ethernet@ff290000 {
 401                 compatible = "rockchip,rk3288-gmac";
 402                 reg = <0xff290000 0x10000>;
 403                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 404                 interrupt-names = "macirq";
 405                 rockchip,grf = <&grf>;
 406                 clocks = <&cru SCLK_MAC>,
 407                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 408                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 409                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 410                 clock-names = "stmmaceth",
 411                         "mac_clk_rx", "mac_clk_tx",
 412                         "clk_mac_ref", "clk_mac_refout",
 413                         "aclk_mac", "pclk_mac";
 414         };
 415
 416         usb_host0_ehci: usb@ff500000 {
 417                 compatible = "generic-ehci";
 418                 reg = <0xff500000 0x100>;
 419                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&cru HCLK_USBHOST0>;
 421                 clock-names = "usbhost";
 422                 status = "disabled";
 423         };
 424
 425         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 426
 427         usb_host1: usb@ff540000 {
 428                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 429                                 "snps,dwc2";
 430                 reg = <0xff540000 0x40000>;
 431                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&cru HCLK_USBHOST1>;
 433                 clock-names = "otg";
 434                 status = "disabled";
 435         };
 436
 437         usb_otg: usb@ff580000 {
 438                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 439                                 "snps,dwc2";
 440                 reg = <0xff580000 0x40000>;
 441                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&cru HCLK_OTG0>;
 443                 clock-names = "otg";
 444                 status = "disabled";
 445         };
 446
 447         usb_hsic: usb@ff5c0000 {
 448                 compatible = "generic-ehci";
 449                 reg = <0xff5c0000 0x100>;
 450                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 451                 clocks = <&cru HCLK_HSIC>;
 452                 clock-names = "usbhost";
 453                 status = "disabled";
 454         };
 455
 456         i2c0: i2c@ff650000 {
 457                 compatible = "rockchip,rk3288-i2c";
 458                 reg = <0xff650000 0x1000>;
 459                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clock-names = "i2c";
 463                 clocks = <&cru PCLK_I2C0>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&i2c0_xfer>;
 466                 status = "disabled";
 467         };
 468
 469         i2c2: i2c@ff660000 {
 470                 compatible = "rockchip,rk3288-i2c";
 471                 reg = <0xff660000 0x1000>;
 472                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clock-names = "i2c";
 476                 clocks = <&cru PCLK_I2C2>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&i2c2_xfer>;
 479                 status = "disabled";
 480         };
 481
 482         pwm0: pwm@ff680000 {
 483                 compatible = "rockchip,rk3288-pwm";
 484                 reg = <0xff680000 0x10>;
 485                 #pwm-cells = <3>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&pwm0_pin>;
 488                 clocks = <&cru PCLK_PWM>;
 489                 clock-names = "pwm";
 490                 status = "disabled";
 491         };
 492
 493         pwm1: pwm@ff680010 {
 494                 compatible = "rockchip,rk3288-pwm";
 495                 reg = <0xff680010 0x10>;
 496                 #pwm-cells = <3>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&pwm1_pin>;
 499                 clocks = <&cru PCLK_PWM>;
 500                 clock-names = "pwm";
 501                 status = "disabled";
 502         };
 503
 504         pwm2: pwm@ff680020 {
 505                 compatible = "rockchip,rk3288-pwm";
 506                 reg = <0xff680020 0x10>;
 507                 #pwm-cells = <3>;
 508                 pinctrl-names = "default";
 509                 pinctrl-0 = <&pwm2_pin>;
 510                 clocks = <&cru PCLK_PWM>;
 511                 clock-names = "pwm";
 512                 status = "disabled";
 513         };
 514
 515         pwm3: pwm@ff680030 {
 516                 compatible = "rockchip,rk3288-pwm";
 517                 reg = <0xff680030 0x10>;
 518                 #pwm-cells = <2>;
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&pwm3_pin>;
 521                 clocks = <&cru PCLK_PWM>;
 522                 clock-names = "pwm";
 523                 status = "disabled";
 524         };
 525
 526         bus_intmem@ff700000 {
 527                 compatible = "mmio-sram";
 528                 reg = <0xff700000 0x18000>;
 529                 #address-cells = <1>;
 530                 #size-cells = <1>;
 531                 ranges = <0 0xff700000 0x18000>;
 532                 smp-sram@0 {
 533                         compatible = "rockchip,rk3066-smp-sram";
 534                         reg = <0x00 0x10>;
 535                 };
 536         };
 537
 538         sram@ff720000 {
 539                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 540                 reg = <0xff720000 0x1000>;
 541         };
 542
 543         pmu: power-management@ff730000 {
 544                 compatible = "rockchip,rk3288-pmu", "syscon";
 545                 reg = <0xff730000 0x100>;
 546         };
 547
 548         sgrf: syscon@ff740000 {
 549                 compatible = "rockchip,rk3288-sgrf", "syscon";
 550                 reg = <0xff740000 0x1000>;
 551         };
 552
 553         cru: clock-controller@ff760000 {
 554                 compatible = "rockchip,rk3288-cru";
 555                 reg = <0xff760000 0x1000>;
 556                 rockchip,grf = <&grf>;
 557                 #clock-cells = <1>;
 558                 #reset-cells = <1>;
 559                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 560                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 561                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 562                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 563                                   <&cru PCLK_PERI>;
 564                 assigned-clock-rates = <594000000>, <400000000>,
 565                                        <500000000>, <300000000>,
 566                                        <150000000>, <75000000>,
 567                                        <300000000>, <150000000>,
 568                                        <75000000>;
 569         };
 570
 571         grf: syscon@ff770000 {
 572                 compatible = "rockchip,rk3288-grf", "syscon";
 573                 reg = <0xff770000 0x1000>;
 574         };
 575
 576         wdt: watchdog@ff800000 {
 577                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 578                 reg = <0xff800000 0x100>;
 579                 clocks = <&cru PCLK_WDT>;
 580                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 581                 status = "disabled";
 582         };
 583
 584         i2s: i2s@ff890000 {
 585                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 586                 reg = <0xff890000 0x10000>;
 587                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 591                 dma-names = "tx", "rx";
 592                 clock-names = "i2s_hclk", "i2s_clk";
 593                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&i2s0_bus>;
 596                 status = "disabled";
 597         };
 598
 599         vopb: vop@ff930000 {
 600                 compatible = "rockchip,rk3288-vop";
 601                 reg = <0xff930000 0x19c>;
 602                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 604                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 605                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 606                 reset-names = "axi", "ahb", "dclk";
 607                 iommus = <&vopb_mmu>;
 608                 status = "disabled";
 609
 610                 vopb_out: port {
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613
 614                         vopb_out_hdmi: endpoint@0 {
 615                                 reg = <0>;
 616                                 remote-endpoint = <&hdmi_in_vopb>;
 617                         };
 618                 };
 619         };
 620
 621         vopb_mmu: iommu@ff930300 {
 622                 compatible = "rockchip,iommu";
 623                 reg = <0xff930300 0x100>;
 624                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 625                 interrupt-names = "vopb_mmu";
 626                 #iommu-cells = <0>;
 627                 status = "disabled";
 628         };
 629
 630         vopl: vop@ff940000 {
 631                 compatible = "rockchip,rk3288-vop";
 632                 reg = <0xff940000 0x19c>;
 633                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 635                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 636                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 637                 reset-names = "axi", "ahb", "dclk";
 638                 iommus = <&vopl_mmu>;
 639                 status = "disabled";
 640
 641                 vopl_out: port {
 642                         #address-cells = <1>;
 643                         #size-cells = <0>;
 644
 645                         vopl_out_hdmi: endpoint@0 {
 646                                 reg = <0>;
 647                                 remote-endpoint = <&hdmi_in_vopl>;
 648                         };
 649                 };
 650         };
 651
 652         vopl_mmu: iommu@ff940300 {
 653                 compatible = "rockchip,iommu";
 654                 reg = <0xff940300 0x100>;
 655                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 656                 interrupt-names = "vopl_mmu";
 657                 #iommu-cells = <0>;
 658                 status = "disabled";
 659         };
 660
 661         hdmi: hdmi@ff980000 {
 662                 compatible = "rockchip,rk3288-dw-hdmi";
 663                 reg = <0xff980000 0x20000>;
 664                 reg-io-width = <4>;
 665                 rockchip,grf = <&grf>;
 666                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 667                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 668                 clock-names = "iahb", "isfr";
 669                 status = "disabled";
 670
 671                 ports {
 672                         hdmi_in: port {
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 hdmi_in_vopb: endpoint@0 {
 676                                         reg = <0>;
 677                                         remote-endpoint = <&vopb_out_hdmi>;
 678                                 };
 679                                 hdmi_in_vopl: endpoint@1 {
 680                                         reg = <1>;
 681                                         remote-endpoint = <&vopl_out_hdmi>;
 682                                 };
 683                         };
 684                 };
 685         };
 686
 687         gic: interrupt-controller@ffc01000 {
 688                 compatible = "arm,gic-400";
 689                 interrupt-controller;
 690                 #interrupt-cells = <3>;
 691                 #address-cells = <0>;
 692
 693                 reg = <0xffc01000 0x1000>,
 694                       <0xffc02000 0x1000>,
 695                       <0xffc04000 0x2000>,
 696                       <0xffc06000 0x2000>;
 697                 interrupts = <GIC_PPI 9 0xf04>;
 698         };
 699
 700         pinctrl: pinctrl {
 701                 compatible = "rockchip,rk3288-pinctrl";
 702                 rockchip,grf = <&grf>;
 703                 rockchip,pmu = <&pmu>;
 704                 #address-cells = <1>;
 705                 #size-cells = <1>;
 706                 ranges;
 707
 708                 gpio0: gpio0@ff750000 {
 709                         compatible = "rockchip,gpio-bank";
 710                         reg =   <0xff750000 0x100>;
 711                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 712                         clocks = <&cru PCLK_GPIO0>;
 713
 714                         gpio-controller;
 715                         #gpio-cells = <2>;
 716
 717                         interrupt-controller;
 718                         #interrupt-cells = <2>;
 719                 };
 720
 721                 gpio1: gpio1@ff780000 {
 722                         compatible = "rockchip,gpio-bank";
 723                         reg = <0xff780000 0x100>;
 724                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&cru PCLK_GPIO1>;
 726
 727                         gpio-controller;
 728                         #gpio-cells = <2>;
 729
 730                         interrupt-controller;
 731                         #interrupt-cells = <2>;
 732                 };
 733
 734                 gpio2: gpio2@ff790000 {
 735                         compatible = "rockchip,gpio-bank";
 736                         reg = <0xff790000 0x100>;
 737                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 738                         clocks = <&cru PCLK_GPIO2>;
 739
 740                         gpio-controller;
 741                         #gpio-cells = <2>;
 742
 743                         interrupt-controller;
 744                         #interrupt-cells = <2>;
 745                 };
 746
 747                 gpio3: gpio3@ff7a0000 {
 748                         compatible = "rockchip,gpio-bank";
 749                         reg = <0xff7a0000 0x100>;
 750                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 751                         clocks = <&cru PCLK_GPIO3>;
 752
 753                         gpio-controller;
 754                         #gpio-cells = <2>;
 755
 756                         interrupt-controller;
 757                         #interrupt-cells = <2>;
 758                 };
 759
 760                 gpio4: gpio4@ff7b0000 {
 761                         compatible = "rockchip,gpio-bank";
 762                         reg = <0xff7b0000 0x100>;
 763                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 764                         clocks = <&cru PCLK_GPIO4>;
 765
 766                         gpio-controller;
 767                         #gpio-cells = <2>;
 768
 769                         interrupt-controller;
 770                         #interrupt-cells = <2>;
 771                 };
 772
 773                 gpio5: gpio5@ff7c0000 {
 774                         compatible = "rockchip,gpio-bank";
 775                         reg = <0xff7c0000 0x100>;
 776                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 777                         clocks = <&cru PCLK_GPIO5>;
 778
 779                         gpio-controller;
 780                         #gpio-cells = <2>;
 781
 782                         interrupt-controller;
 783                         #interrupt-cells = <2>;
 784                 };
 785
 786                 gpio6: gpio6@ff7d0000 {
 787                         compatible = "rockchip,gpio-bank";
 788                         reg = <0xff7d0000 0x100>;
 789                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 790                         clocks = <&cru PCLK_GPIO6>;
 791
 792                         gpio-controller;
 793                         #gpio-cells = <2>;
 794
 795                         interrupt-controller;
 796                         #interrupt-cells = <2>;
 797                 };
 798
 799                 gpio7: gpio7@ff7e0000 {
 800                         compatible = "rockchip,gpio-bank";
 801                         reg = <0xff7e0000 0x100>;
 802                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 803                         clocks = <&cru PCLK_GPIO7>;
 804
 805                         gpio-controller;
 806                         #gpio-cells = <2>;
 807
 808                         interrupt-controller;
 809                         #interrupt-cells = <2>;
 810                 };
 811
 812                 gpio8: gpio8@ff7f0000 {
 813                         compatible = "rockchip,gpio-bank";
 814                         reg = <0xff7f0000 0x100>;
 815                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&cru PCLK_GPIO8>;
 817
 818                         gpio-controller;
 819                         #gpio-cells = <2>;
 820
 821                         interrupt-controller;
 822                         #interrupt-cells = <2>;
 823                 };
 824
 825                 pcfg_pull_up: pcfg-pull-up {
 826                         bias-pull-up;
 827                 };
 828
 829                 pcfg_pull_down: pcfg-pull-down {
 830                         bias-pull-down;
 831                 };
 832
 833                 pcfg_pull_none: pcfg-pull-none {
 834                         bias-disable;
 835                 };
 836
 837                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 838                         bias-disable;
 839                         drive-strength = <12>;
 840                 };
 841
 842                 sleep {
 843                         global_pwroff: global-pwroff {
 844                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
 845                         };
 846
 847                         ddrio_pwroff: ddrio-pwroff {
 848                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
 849                         };
 850
 851                         ddr0_retention: ddr0-retention {
 852                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
 853                         };
 854
 855                         ddr1_retention: ddr1-retention {
 856                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
 857                         };
 858                 };
 859
 860                 i2c0 {
 861                         i2c0_xfer: i2c0-xfer {
 862                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 863                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865                 };
 866
 867                 i2c1 {
 868                         i2c1_xfer: i2c1-xfer {
 869                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 870                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872                 };
 873
 874                 i2c2 {
 875                         i2c2_xfer: i2c2-xfer {
 876                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 877                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 878                         };
 879                 };
 880
 881                 i2c3 {
 882                         i2c3_xfer: i2c3-xfer {
 883                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 884                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 885                         };
 886                 };
 887
 888                 i2c4 {
 889                         i2c4_xfer: i2c4-xfer {
 890                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 891                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 892                         };
 893                 };
 894
 895                 i2c5 {
 896                         i2c5_xfer: i2c5-xfer {
 897                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 898                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 899                         };
 900                 };
 901
 902                 i2s0 {
 903                         i2s0_bus: i2s0-bus {
 904                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 905                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 906                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 907                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 908                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 909                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 910                         };
 911                 };
 912
 913                 sdmmc {
 914                         sdmmc_clk: sdmmc-clk {
 915                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 916                         };
 917
 918                         sdmmc_cmd: sdmmc-cmd {
 919                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 920                         };
 921
 922                         sdmmc_cd: sdmcc-cd {
 923                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 924                         };
 925
 926                         sdmmc_bus1: sdmmc-bus1 {
 927                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 928                         };
 929
 930                         sdmmc_bus4: sdmmc-bus4 {
 931                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 932                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 933                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 934                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 935                         };
 936                 };
 937
 938                 sdio0 {
 939                         sdio0_bus1: sdio0-bus1 {
 940                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 941                         };
 942
 943                         sdio0_bus4: sdio0-bus4 {
 944                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 945                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 946                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 947                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 948                         };
 949
 950                         sdio0_cmd: sdio0-cmd {
 951                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 952                         };
 953
 954                         sdio0_clk: sdio0-clk {
 955                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 956                         };
 957
 958                         sdio0_cd: sdio0-cd {
 959                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 960                         };
 961
 962                         sdio0_wp: sdio0-wp {
 963                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 964                         };
 965
 966                         sdio0_pwr: sdio0-pwr {
 967                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 968                         };
 969
 970                         sdio0_bkpwr: sdio0-bkpwr {
 971                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 972                         };
 973
 974                         sdio0_int: sdio0-int {
 975                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 976                         };
 977                 };
 978
 979                 sdio1 {
 980                         sdio1_bus1: sdio1-bus1 {
 981                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 982                         };
 983
 984                         sdio1_bus4: sdio1-bus4 {
 985                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 986                                                 <3 25 4 &pcfg_pull_up>,
 987                                                 <3 26 4 &pcfg_pull_up>,
 988                                                 <3 27 4 &pcfg_pull_up>;
 989                         };
 990
 991                         sdio1_cd: sdio1-cd {
 992                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 993                         };
 994
 995                         sdio1_wp: sdio1-wp {
 996                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 997                         };
 998
 999                         sdio1_bkpwr: sdio1-bkpwr {
1000                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1001                         };
1002
1003                         sdio1_int: sdio1-int {
1004                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1005                         };
1006
1007                         sdio1_cmd: sdio1-cmd {
1008                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1009                         };
1010
1011                         sdio1_clk: sdio1-clk {
1012                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1013                         };
1014
1015                         sdio1_pwr: sdio1-pwr {
1016                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1017                         };
1018                 };
1019
1020                 emmc {
1021                         emmc_clk: emmc-clk {
1022                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1023                         };
1024
1025                         emmc_cmd: emmc-cmd {
1026                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1027                         };
1028
1029                         emmc_pwr: emmc-pwr {
1030                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1031                         };
1032
1033                         emmc_bus1: emmc-bus1 {
1034                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1035                         };
1036
1037                         emmc_bus4: emmc-bus4 {
1038                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1039                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1040                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1041                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1042                         };
1043
1044                         emmc_bus8: emmc-bus8 {
1045                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1046                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1047                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1048                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1049                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1050                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1051                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1052                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1053                         };
1054                 };
1055
1056                 spi0 {
1057                         spi0_clk: spi0-clk {
1058                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1059                         };
1060                         spi0_cs0: spi0-cs0 {
1061                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1062                         };
1063                         spi0_tx: spi0-tx {
1064                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1065                         };
1066                         spi0_rx: spi0-rx {
1067                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1068                         };
1069                         spi0_cs1: spi0-cs1 {
1070                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1071                         };
1072                 };
1073                 spi1 {
1074                         spi1_clk: spi1-clk {
1075                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1076                         };
1077                         spi1_cs0: spi1-cs0 {
1078                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1079                         };
1080                         spi1_rx: spi1-rx {
1081                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1082                         };
1083                         spi1_tx: spi1-tx {
1084                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1085                         };
1086                 };
1087
1088                 spi2 {
1089                         spi2_cs1: spi2-cs1 {
1090                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1091                         };
1092                         spi2_clk: spi2-clk {
1093                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1094                         };
1095                         spi2_cs0: spi2-cs0 {
1096                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1097                         };
1098                         spi2_rx: spi2-rx {
1099                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1100                         };
1101                         spi2_tx: spi2-tx {
1102                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1103                         };
1104                 };
1105
1106                 uart0 {
1107                         uart0_xfer: uart0-xfer {
1108                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1109                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1110                         };
1111
1112                         uart0_cts: uart0-cts {
1113                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1114                         };
1115
1116                         uart0_rts: uart0-rts {
1117                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1118                         };
1119                 };
1120
1121                 uart1 {
1122                         uart1_xfer: uart1-xfer {
1123                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1124                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1125                         };
1126
1127                         uart1_cts: uart1-cts {
1128                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1129                         };
1130
1131                         uart1_rts: uart1-rts {
1132                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1133                         };
1134                 };
1135
1136                 uart2 {
1137                         uart2_xfer: uart2-xfer {
1138                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1139                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141                         /* no rts / cts for uart2 */
1142                 };
1143
1144                 uart3 {
1145                         uart3_xfer: uart3-xfer {
1146                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1147                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1148                         };
1149
1150                         uart3_cts: uart3-cts {
1151                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1152                         };
1153
1154                         uart3_rts: uart3-rts {
1155                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 uart4 {
1160                         uart4_xfer: uart4-xfer {
1161                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1162                                                 <5 13 3 &pcfg_pull_none>;
1163                         };
1164
1165                         uart4_cts: uart4-cts {
1166                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1167                         };
1168
1169                         uart4_rts: uart4-rts {
1170                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1171                         };
1172                 };
1173
1174                 tsadc {
1175                         otp_out: otp-out {
1176                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1177                         };
1178                 };
1179
1180                 pwm0 {
1181                         pwm0_pin: pwm0-pin {
1182                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1183                         };
1184                 };
1185
1186                 pwm1 {
1187                         pwm1_pin: pwm1-pin {
1188                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 pwm2 {
1193                         pwm2_pin: pwm2-pin {
1194                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1195                         };
1196                 };
1197
1198                 pwm3 {
1199                         pwm3_pin: pwm3-pin {
1200                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1201                         };
1202                 };
1203
1204                 gmac {
1205                         rgmii_pins: rgmii-pins {
1206                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1207                                                 <3 31 3 &pcfg_pull_none>,
1208                                                 <3 26 3 &pcfg_pull_none>,
1209                                                 <3 27 3 &pcfg_pull_none>,
1210                                                 <3 28 3 &pcfg_pull_none_12ma>,
1211                                                 <3 29 3 &pcfg_pull_none_12ma>,
1212                                                 <3 24 3 &pcfg_pull_none_12ma>,
1213                                                 <3 25 3 &pcfg_pull_none_12ma>,
1214                                                 <4 0 3 &pcfg_pull_none>,
1215                                                 <4 5 3 &pcfg_pull_none>,
1216                                                 <4 6 3 &pcfg_pull_none>,
1217                                                 <4 9 3 &pcfg_pull_none_12ma>,
1218                                                 <4 4 3 &pcfg_pull_none_12ma>,
1219                                                 <4 1 3 &pcfg_pull_none>,
1220                                                 <4 3 3 &pcfg_pull_none>;
1221                         };
1222
1223                         rmii_pins: rmii-pins {
1224                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1225                                                 <3 31 3 &pcfg_pull_none>,
1226                                                 <3 28 3 &pcfg_pull_none>,
1227                                                 <3 29 3 &pcfg_pull_none>,
1228                                                 <4 0 3 &pcfg_pull_none>,
1229                                                 <4 5 3 &pcfg_pull_none>,
1230                                                 <4 4 3 &pcfg_pull_none>,
1231                                                 <4 1 3 &pcfg_pull_none>,
1232                                                 <4 2 3 &pcfg_pull_none>,
1233                                                 <4 3 3 &pcfg_pull_none>;
1234                         };
1235                 };
1236         };
1237 };