arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include "skeleton.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3288";
  23
  24         interrupt-parent = <&gic>;
  25
  26         aliases {
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mshc0 = &emmc;
  34                 mshc1 = &sdmmc;
  35                 mshc2 = &sdio0;
  36                 mshc3 = &sdio1;
  37                 serial0 = &uart0;
  38                 serial1 = &uart1;
  39                 serial2 = &uart2;
  40                 serial3 = &uart3;
  41                 serial4 = &uart4;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 enable-method = "rockchip,rk3066-smp";
  51                 rockchip,pmu = <&pmu>;
  52
  53                 cpu0: cpu@500 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a12";
  56                         reg = <0x500>;
  57                         resets = <&cru SRST_CORE0>;
  58                         operating-points = <
  59                                 /* KHz    uV */
  60                                 1608000 1350000
  61                                 1512000 1300000
  62                                 1416000 1200000
  63                                 1200000 1100000
  64                                 1008000 1050000
  65                                  816000 1000000
  66                                  696000  950000
  67                                  600000  900000
  68                                  408000  900000
  69                                  312000  900000
  70                                  216000  900000
  71                                  126000  900000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77                 cpu@501 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a12";
  80                         reg = <0x501>;
  81                         resets = <&cru SRST_CORE1>;
  82                 };
  83                 cpu@502 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a12";
  86                         reg = <0x502>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89                 cpu@503 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a12";
  92                         reg = <0x503>;
  93                         resets = <&cru SRST_CORE3>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 dmac_peri: dma-controller@ff250000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0xff250000 0x4000>;
 106                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112
 113                 dmac_bus_ns: dma-controller@ff600000 {
 114                         compatible = "arm,pl330", "arm,primecell";
 115                         reg = <0xff600000 0x4000>;
 116                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 118                         #dma-cells = <1>;
 119                         clocks = <&cru ACLK_DMAC1>;
 120                         clock-names = "apb_pclk";
 121                         status = "disabled";
 122                 };
 123
 124                 dmac_bus_s: dma-controller@ffb20000 {
 125                         compatible = "arm,pl330", "arm,primecell";
 126                         reg = <0xffb20000 0x4000>;
 127                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 129                         #dma-cells = <1>;
 130                         clocks = <&cru ACLK_DMAC1>;
 131                         clock-names = "apb_pclk";
 132                 };
 133         };
 134
 135         xin24m: oscillator {
 136                 compatible = "fixed-clock";
 137                 clock-frequency = <24000000>;
 138                 clock-output-names = "xin24m";
 139                 #clock-cells = <0>;
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv7-timer";
 144                 arm,cpu-registers-not-fw-configured;
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 clock-frequency = <24000000>;
 150         };
 151
 152         timer: timer@ff810000 {
 153                 compatible = "rockchip,rk3288-timer";
 154                 reg = <0xff810000 0x20>;
 155                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 157                 clock-names = "timer", "pclk";
 158         };
 159
 160         display-subsystem {
 161                 compatible = "rockchip,display-subsystem";
 162                 ports = <&vopl_out>, <&vopb_out>;
 163         };
 164
 165         sdmmc: dwmmc@ff0c0000 {
 166                 compatible = "rockchip,rk3288-dw-mshc";
 167                 clock-freq-min-max = <400000 150000000>;
 168                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 169                 clock-names = "biu", "ciu";
 170                 fifo-depth = <0x100>;
 171                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 172                 reg = <0xff0c0000 0x4000>;
 173                 status = "disabled";
 174         };
 175
 176         sdio0: dwmmc@ff0d0000 {
 177                 compatible = "rockchip,rk3288-dw-mshc";
 178                 clock-freq-min-max = <400000 150000000>;
 179                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 180                 clock-names = "biu", "ciu";
 181                 fifo-depth = <0x100>;
 182                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 183                 reg = <0xff0d0000 0x4000>;
 184                 status = "disabled";
 185         };
 186
 187         sdio1: dwmmc@ff0e0000 {
 188                 compatible = "rockchip,rk3288-dw-mshc";
 189                 clock-freq-min-max = <400000 150000000>;
 190                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 191                 clock-names = "biu", "ciu";
 192                 fifo-depth = <0x100>;
 193                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 194                 reg = <0xff0e0000 0x4000>;
 195                 status = "disabled";
 196         };
 197
 198         emmc: dwmmc@ff0f0000 {
 199                 compatible = "rockchip,rk3288-dw-mshc";
 200                 clock-freq-min-max = <400000 150000000>;
 201                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 202                 clock-names = "biu", "ciu";
 203                 fifo-depth = <0x100>;
 204                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 205                 reg = <0xff0f0000 0x4000>;
 206                 status = "disabled";
 207         };
 208
 209         saradc: saradc@ff100000 {
 210                 compatible = "rockchip,saradc";
 211                 reg = <0xff100000 0x100>;
 212                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 213                 #io-channel-cells = <1>;
 214                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 215                 clock-names = "saradc", "apb_pclk";
 216                 status = "disabled";
 217         };
 218
 219         spi0: spi@ff110000 {
 220                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 221                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 222                 clock-names = "spiclk", "apb_pclk";
 223                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 224                 dma-names = "tx", "rx";
 225                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 228                 reg = <0xff110000 0x1000>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 status = "disabled";
 232         };
 233
 234         spi1: spi@ff120000 {
 235                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 236                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 237                 clock-names = "spiclk", "apb_pclk";
 238                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 239                 dma-names = "tx", "rx";
 240                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 241                 pinctrl-names = "default";
 242                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 243                 reg = <0xff120000 0x1000>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 status = "disabled";
 247         };
 248
 249         spi2: spi@ff130000 {
 250                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 251                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 252                 clock-names = "spiclk", "apb_pclk";
 253                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 254                 dma-names = "tx", "rx";
 255                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 258                 reg = <0xff130000 0x1000>;
 259                 #address-cells = <1>;
 260                 #size-cells = <0>;
 261                 status = "disabled";
 262         };
 263
 264         i2c1: i2c@ff140000 {
 265                 compatible = "rockchip,rk3288-i2c";
 266                 reg = <0xff140000 0x1000>;
 267                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 268                 #address-cells = <1>;
 269                 #size-cells = <0>;
 270                 clock-names = "i2c";
 271                 clocks = <&cru PCLK_I2C1>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&i2c1_xfer>;
 274                 status = "disabled";
 275         };
 276
 277         i2c3: i2c@ff150000 {
 278                 compatible = "rockchip,rk3288-i2c";
 279                 reg = <0xff150000 0x1000>;
 280                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 clock-names = "i2c";
 284                 clocks = <&cru PCLK_I2C3>;
 285                 pinctrl-names = "default";
 286                 pinctrl-0 = <&i2c3_xfer>;
 287                 status = "disabled";
 288         };
 289
 290         i2c4: i2c@ff160000 {
 291                 compatible = "rockchip,rk3288-i2c";
 292                 reg = <0xff160000 0x1000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 clock-names = "i2c";
 297                 clocks = <&cru PCLK_I2C4>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&i2c4_xfer>;
 300                 status = "disabled";
 301         };
 302
 303         i2c5: i2c@ff170000 {
 304                 compatible = "rockchip,rk3288-i2c";
 305                 reg = <0xff170000 0x1000>;
 306                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 clock-names = "i2c";
 310                 clocks = <&cru PCLK_I2C5>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&i2c5_xfer>;
 313                 status = "disabled";
 314         };
 315
 316         uart0: serial@ff180000 {
 317                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 318                 reg = <0xff180000 0x100>;
 319                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 320                 reg-shift = <2>;
 321                 reg-io-width = <4>;
 322                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 323                 clock-names = "baudclk", "apb_pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&uart0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         uart1: serial@ff190000 {
 330                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 331                 reg = <0xff190000 0x100>;
 332                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 333                 reg-shift = <2>;
 334                 reg-io-width = <4>;
 335                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 336                 clock-names = "baudclk", "apb_pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&uart1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         uart2: serial@ff690000 {
 343                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 344                 reg = <0xff690000 0x100>;
 345                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 346                 reg-shift = <2>;
 347                 reg-io-width = <4>;
 348                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 349                 clock-names = "baudclk", "apb_pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&uart2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         uart3: serial@ff1b0000 {
 356                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 357                 reg = <0xff1b0000 0x100>;
 358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 359                 reg-shift = <2>;
 360                 reg-io-width = <4>;
 361                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 362                 clock-names = "baudclk", "apb_pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&uart3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         uart4: serial@ff1c0000 {
 369                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 370                 reg = <0xff1c0000 0x100>;
 371                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 372                 reg-shift = <2>;
 373                 reg-io-width = <4>;
 374                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 375                 clock-names = "baudclk", "apb_pclk";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&uart4_xfer>;
 378                 status = "disabled";
 379         };
 380
 381         thermal-zones {
 382                 #include "rk3288-thermal.dtsi"
 383         };
 384
 385         tsadc: tsadc@ff280000 {
 386                 compatible = "rockchip,rk3288-tsadc";
 387                 reg = <0xff280000 0x100>;
 388                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 390                 clock-names = "tsadc", "apb_pclk";
 391                 resets = <&cru SRST_TSADC>;
 392                 reset-names = "tsadc-apb";
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&otp_out>;
 395                 #thermal-sensor-cells = <1>;
 396                 rockchip,hw-tshut-temp = <95000>;
 397                 status = "disabled";
 398         };
 399
 400         usb_host0_ehci: usb@ff500000 {
 401                 compatible = "generic-ehci";
 402                 reg = <0xff500000 0x100>;
 403                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&cru HCLK_USBHOST0>;
 405                 clock-names = "usbhost";
 406                 status = "disabled";
 407         };
 408
 409         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 410
 411         usb_host1: usb@ff540000 {
 412                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 413                                 "snps,dwc2";
 414                 reg = <0xff540000 0x40000>;
 415                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&cru HCLK_USBHOST1>;
 417                 clock-names = "otg";
 418                 status = "disabled";
 419         };
 420
 421         usb_otg: usb@ff580000 {
 422                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 423                                 "snps,dwc2";
 424                 reg = <0xff580000 0x40000>;
 425                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru HCLK_OTG0>;
 427                 clock-names = "otg";
 428                 status = "disabled";
 429         };
 430
 431         usb_hsic: usb@ff5c0000 {
 432                 compatible = "generic-ehci";
 433                 reg = <0xff5c0000 0x100>;
 434                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&cru HCLK_HSIC>;
 436                 clock-names = "usbhost";
 437                 status = "disabled";
 438         };
 439
 440         i2c0: i2c@ff650000 {
 441                 compatible = "rockchip,rk3288-i2c";
 442                 reg = <0xff650000 0x1000>;
 443                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clock-names = "i2c";
 447                 clocks = <&cru PCLK_I2C0>;
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&i2c0_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         i2c2: i2c@ff660000 {
 454                 compatible = "rockchip,rk3288-i2c";
 455                 reg = <0xff660000 0x1000>;
 456                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 clock-names = "i2c";
 460                 clocks = <&cru PCLK_I2C2>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&i2c2_xfer>;
 463                 status = "disabled";
 464         };
 465
 466         pwm0: pwm@ff680000 {
 467                 compatible = "rockchip,rk3288-pwm";
 468                 reg = <0xff680000 0x10>;
 469                 #pwm-cells = <3>;
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&pwm0_pin>;
 472                 clocks = <&cru PCLK_PWM>;
 473                 clock-names = "pwm";
 474                 status = "disabled";
 475         };
 476
 477         pwm1: pwm@ff680010 {
 478                 compatible = "rockchip,rk3288-pwm";
 479                 reg = <0xff680010 0x10>;
 480                 #pwm-cells = <3>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&pwm1_pin>;
 483                 clocks = <&cru PCLK_PWM>;
 484                 clock-names = "pwm";
 485                 status = "disabled";
 486         };
 487
 488         pwm2: pwm@ff680020 {
 489                 compatible = "rockchip,rk3288-pwm";
 490                 reg = <0xff680020 0x10>;
 491                 #pwm-cells = <3>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&pwm2_pin>;
 494                 clocks = <&cru PCLK_PWM>;
 495                 clock-names = "pwm";
 496                 status = "disabled";
 497         };
 498
 499         pwm3: pwm@ff680030 {
 500                 compatible = "rockchip,rk3288-pwm";
 501                 reg = <0xff680030 0x10>;
 502                 #pwm-cells = <2>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&pwm3_pin>;
 505                 clocks = <&cru PCLK_PWM>;
 506                 clock-names = "pwm";
 507                 status = "disabled";
 508         };
 509
 510         bus_intmem@ff700000 {
 511                 compatible = "mmio-sram";
 512                 reg = <0xff700000 0x18000>;
 513                 #address-cells = <1>;
 514                 #size-cells = <1>;
 515                 ranges = <0 0xff700000 0x18000>;
 516                 smp-sram@0 {
 517                         compatible = "rockchip,rk3066-smp-sram";
 518                         reg = <0x00 0x10>;
 519                 };
 520         };
 521
 522         sram@ff720000 {
 523                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 524                 reg = <0xff720000 0x1000>;
 525         };
 526
 527         pmu: power-management@ff730000 {
 528                 compatible = "rockchip,rk3288-pmu", "syscon";
 529                 reg = <0xff730000 0x100>;
 530         };
 531
 532         sgrf: syscon@ff740000 {
 533                 compatible = "rockchip,rk3288-sgrf", "syscon";
 534                 reg = <0xff740000 0x1000>;
 535         };
 536
 537         cru: clock-controller@ff760000 {
 538                 compatible = "rockchip,rk3288-cru";
 539                 reg = <0xff760000 0x1000>;
 540                 rockchip,grf = <&grf>;
 541                 #clock-cells = <1>;
 542                 #reset-cells = <1>;
 543                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 544                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 545                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 546                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 547                                   <&cru PCLK_PERI>;
 548                 assigned-clock-rates = <594000000>, <400000000>,
 549                                        <500000000>, <300000000>,
 550                                        <150000000>, <75000000>,
 551                                        <300000000>, <150000000>,
 552                                        <75000000>;
 553         };
 554
 555         grf: syscon@ff770000 {
 556                 compatible = "rockchip,rk3288-grf", "syscon";
 557                 reg = <0xff770000 0x1000>;
 558         };
 559
 560         wdt: watchdog@ff800000 {
 561                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 562                 reg = <0xff800000 0x100>;
 563                 clocks = <&cru PCLK_WDT>;
 564                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 565                 status = "disabled";
 566         };
 567
 568         i2s: i2s@ff890000 {
 569                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 570                 reg = <0xff890000 0x10000>;
 571                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 575                 dma-names = "tx", "rx";
 576                 clock-names = "i2s_hclk", "i2s_clk";
 577                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 578                 pinctrl-names = "default";
 579                 pinctrl-0 = <&i2s0_bus>;
 580                 status = "disabled";
 581         };
 582
 583         vopb: vop@ff930000 {
 584                 compatible = "rockchip,rk3288-vop";
 585                 reg = <0xff930000 0x19c>;
 586                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 587                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 588                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 589                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 590                 reset-names = "axi", "ahb", "dclk";
 591                 iommus = <&vopb_mmu>;
 592                 status = "disabled";
 593
 594                 vopb_out: port {
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597
 598                         vopb_out_hdmi: endpoint@0 {
 599                                 reg = <0>;
 600                                 remote-endpoint = <&hdmi_in_vopb>;
 601                         };
 602                 };
 603         };
 604
 605         vopb_mmu: iommu@ff930300 {
 606                 compatible = "rockchip,iommu";
 607                 reg = <0xff930300 0x100>;
 608                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 609                 interrupt-names = "vopb_mmu";
 610                 #iommu-cells = <0>;
 611                 status = "disabled";
 612         };
 613
 614         vopl: vop@ff940000 {
 615                 compatible = "rockchip,rk3288-vop";
 616                 reg = <0xff940000 0x19c>;
 617                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 618                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 619                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 620                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 621                 reset-names = "axi", "ahb", "dclk";
 622                 iommus = <&vopl_mmu>;
 623                 status = "disabled";
 624
 625                 vopl_out: port {
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628
 629                         vopl_out_hdmi: endpoint@0 {
 630                                 reg = <0>;
 631                                 remote-endpoint = <&hdmi_in_vopl>;
 632                         };
 633                 };
 634         };
 635
 636         vopl_mmu: iommu@ff940300 {
 637                 compatible = "rockchip,iommu";
 638                 reg = <0xff940300 0x100>;
 639                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 640                 interrupt-names = "vopl_mmu";
 641                 #iommu-cells = <0>;
 642                 status = "disabled";
 643         };
 644
 645         hdmi: hdmi@ff980000 {
 646                 compatible = "rockchip,rk3288-dw-hdmi";
 647                 reg = <0xff980000 0x20000>;
 648                 reg-io-width = <4>;
 649                 rockchip,grf = <&grf>;
 650                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 652                 clock-names = "iahb", "isfr";
 653                 status = "disabled";
 654
 655                 ports {
 656                         hdmi_in: port {
 657                                 #address-cells = <1>;
 658                                 #size-cells = <0>;
 659                                 hdmi_in_vopb: endpoint@0 {
 660                                         reg = <0>;
 661                                         remote-endpoint = <&vopb_out_hdmi>;
 662                                 };
 663                                 hdmi_in_vopl: endpoint@1 {
 664                                         reg = <1>;
 665                                         remote-endpoint = <&vopl_out_hdmi>;
 666                                 };
 667                         };
 668                 };
 669         };
 670
 671         gic: interrupt-controller@ffc01000 {
 672                 compatible = "arm,gic-400";
 673                 interrupt-controller;
 674                 #interrupt-cells = <3>;
 675                 #address-cells = <0>;
 676
 677                 reg = <0xffc01000 0x1000>,
 678                       <0xffc02000 0x1000>,
 679                       <0xffc04000 0x2000>,
 680                       <0xffc06000 0x2000>;
 681                 interrupts = <GIC_PPI 9 0xf04>;
 682         };
 683
 684         pinctrl: pinctrl {
 685                 compatible = "rockchip,rk3288-pinctrl";
 686                 rockchip,grf = <&grf>;
 687                 rockchip,pmu = <&pmu>;
 688                 #address-cells = <1>;
 689                 #size-cells = <1>;
 690                 ranges;
 691
 692                 gpio0: gpio0@ff750000 {
 693                         compatible = "rockchip,gpio-bank";
 694                         reg =   <0xff750000 0x100>;
 695                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&cru PCLK_GPIO0>;
 697
 698                         gpio-controller;
 699                         #gpio-cells = <2>;
 700
 701                         interrupt-controller;
 702                         #interrupt-cells = <2>;
 703                 };
 704
 705                 gpio1: gpio1@ff780000 {
 706                         compatible = "rockchip,gpio-bank";
 707                         reg = <0xff780000 0x100>;
 708                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&cru PCLK_GPIO1>;
 710
 711                         gpio-controller;
 712                         #gpio-cells = <2>;
 713
 714                         interrupt-controller;
 715                         #interrupt-cells = <2>;
 716                 };
 717
 718                 gpio2: gpio2@ff790000 {
 719                         compatible = "rockchip,gpio-bank";
 720                         reg = <0xff790000 0x100>;
 721                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&cru PCLK_GPIO2>;
 723
 724                         gpio-controller;
 725                         #gpio-cells = <2>;
 726
 727                         interrupt-controller;
 728                         #interrupt-cells = <2>;
 729                 };
 730
 731                 gpio3: gpio3@ff7a0000 {
 732                         compatible = "rockchip,gpio-bank";
 733                         reg = <0xff7a0000 0x100>;
 734                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&cru PCLK_GPIO3>;
 736
 737                         gpio-controller;
 738                         #gpio-cells = <2>;
 739
 740                         interrupt-controller;
 741                         #interrupt-cells = <2>;
 742                 };
 743
 744                 gpio4: gpio4@ff7b0000 {
 745                         compatible = "rockchip,gpio-bank";
 746                         reg = <0xff7b0000 0x100>;
 747                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&cru PCLK_GPIO4>;
 749
 750                         gpio-controller;
 751                         #gpio-cells = <2>;
 752
 753                         interrupt-controller;
 754                         #interrupt-cells = <2>;
 755                 };
 756
 757                 gpio5: gpio5@ff7c0000 {
 758                         compatible = "rockchip,gpio-bank";
 759                         reg = <0xff7c0000 0x100>;
 760                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&cru PCLK_GPIO5>;
 762
 763                         gpio-controller;
 764                         #gpio-cells = <2>;
 765
 766                         interrupt-controller;
 767                         #interrupt-cells = <2>;
 768                 };
 769
 770                 gpio6: gpio6@ff7d0000 {
 771                         compatible = "rockchip,gpio-bank";
 772                         reg = <0xff7d0000 0x100>;
 773                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 774                         clocks = <&cru PCLK_GPIO6>;
 775
 776                         gpio-controller;
 777                         #gpio-cells = <2>;
 778
 779                         interrupt-controller;
 780                         #interrupt-cells = <2>;
 781                 };
 782
 783                 gpio7: gpio7@ff7e0000 {
 784                         compatible = "rockchip,gpio-bank";
 785                         reg = <0xff7e0000 0x100>;
 786                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 787                         clocks = <&cru PCLK_GPIO7>;
 788
 789                         gpio-controller;
 790                         #gpio-cells = <2>;
 791
 792                         interrupt-controller;
 793                         #interrupt-cells = <2>;
 794                 };
 795
 796                 gpio8: gpio8@ff7f0000 {
 797                         compatible = "rockchip,gpio-bank";
 798                         reg = <0xff7f0000 0x100>;
 799                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 800                         clocks = <&cru PCLK_GPIO8>;
 801
 802                         gpio-controller;
 803                         #gpio-cells = <2>;
 804
 805                         interrupt-controller;
 806                         #interrupt-cells = <2>;
 807                 };
 808
 809                 pcfg_pull_up: pcfg-pull-up {
 810                         bias-pull-up;
 811                 };
 812
 813                 pcfg_pull_down: pcfg-pull-down {
 814                         bias-pull-down;
 815                 };
 816
 817                 pcfg_pull_none: pcfg-pull-none {
 818                         bias-disable;
 819                 };
 820
 821                 sleep {
 822                         global_pwroff: global-pwroff {
 823                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
 824                         };
 825
 826                         ddrio_pwroff: ddrio-pwroff {
 827                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
 828                         };
 829
 830                         ddr0_retention: ddr0-retention {
 831                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
 832                         };
 833
 834                         ddr1_retention: ddr1-retention {
 835                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
 836                         };
 837                 };
 838
 839                 i2c0 {
 840                         i2c0_xfer: i2c0-xfer {
 841                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 842                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 843                         };
 844                 };
 845
 846                 i2c1 {
 847                         i2c1_xfer: i2c1-xfer {
 848                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 849                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 850                         };
 851                 };
 852
 853                 i2c2 {
 854                         i2c2_xfer: i2c2-xfer {
 855                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 856                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858                 };
 859
 860                 i2c3 {
 861                         i2c3_xfer: i2c3-xfer {
 862                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 863                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865                 };
 866
 867                 i2c4 {
 868                         i2c4_xfer: i2c4-xfer {
 869                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 870                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872                 };
 873
 874                 i2c5 {
 875                         i2c5_xfer: i2c5-xfer {
 876                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 877                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 878                         };
 879                 };
 880
 881                 i2s0 {
 882                         i2s0_bus: i2s0-bus {
 883                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 884                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 885                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 886                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 887                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 888                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 889                         };
 890                 };
 891
 892                 sdmmc {
 893                         sdmmc_clk: sdmmc-clk {
 894                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 895                         };
 896
 897                         sdmmc_cmd: sdmmc-cmd {
 898                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 899                         };
 900
 901                         sdmmc_cd: sdmcc-cd {
 902                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 903                         };
 904
 905                         sdmmc_bus1: sdmmc-bus1 {
 906                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 907                         };
 908
 909                         sdmmc_bus4: sdmmc-bus4 {
 910                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 911                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 912                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 913                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 914                         };
 915                 };
 916
 917                 sdio0 {
 918                         sdio0_bus1: sdio0-bus1 {
 919                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 920                         };
 921
 922                         sdio0_bus4: sdio0-bus4 {
 923                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 924                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 925                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 926                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 927                         };
 928
 929                         sdio0_cmd: sdio0-cmd {
 930                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 931                         };
 932
 933                         sdio0_clk: sdio0-clk {
 934                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 935                         };
 936
 937                         sdio0_cd: sdio0-cd {
 938                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 939                         };
 940
 941                         sdio0_wp: sdio0-wp {
 942                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 943                         };
 944
 945                         sdio0_pwr: sdio0-pwr {
 946                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 947                         };
 948
 949                         sdio0_bkpwr: sdio0-bkpwr {
 950                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 951                         };
 952
 953                         sdio0_int: sdio0-int {
 954                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 955                         };
 956                 };
 957
 958                 sdio1 {
 959                         sdio1_bus1: sdio1-bus1 {
 960                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 961                         };
 962
 963                         sdio1_bus4: sdio1-bus4 {
 964                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 965                                                 <3 25 4 &pcfg_pull_up>,
 966                                                 <3 26 4 &pcfg_pull_up>,
 967                                                 <3 27 4 &pcfg_pull_up>;
 968                         };
 969
 970                         sdio1_cd: sdio1-cd {
 971                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 972                         };
 973
 974                         sdio1_wp: sdio1-wp {
 975                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 976                         };
 977
 978                         sdio1_bkpwr: sdio1-bkpwr {
 979                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 980                         };
 981
 982                         sdio1_int: sdio1-int {
 983                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 984                         };
 985
 986                         sdio1_cmd: sdio1-cmd {
 987                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 988                         };
 989
 990                         sdio1_clk: sdio1-clk {
 991                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 992                         };
 993
 994                         sdio1_pwr: sdio1-pwr {
 995                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 996                         };
 997                 };
 998
 999                 emmc {
1000                         emmc_clk: emmc-clk {
1001                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1002                         };
1003
1004                         emmc_cmd: emmc-cmd {
1005                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1006                         };
1007
1008                         emmc_pwr: emmc-pwr {
1009                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1010                         };
1011
1012                         emmc_bus1: emmc-bus1 {
1013                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1014                         };
1015
1016                         emmc_bus4: emmc-bus4 {
1017                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1018                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1019                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1020                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1021                         };
1022
1023                         emmc_bus8: emmc-bus8 {
1024                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1025                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1026                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1027                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1028                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1029                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1030                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1031                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1032                         };
1033                 };
1034
1035                 spi0 {
1036                         spi0_clk: spi0-clk {
1037                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1038                         };
1039                         spi0_cs0: spi0-cs0 {
1040                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1041                         };
1042                         spi0_tx: spi0-tx {
1043                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1044                         };
1045                         spi0_rx: spi0-rx {
1046                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1047                         };
1048                         spi0_cs1: spi0-cs1 {
1049                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1050                         };
1051                 };
1052                 spi1 {
1053                         spi1_clk: spi1-clk {
1054                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1055                         };
1056                         spi1_cs0: spi1-cs0 {
1057                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1058                         };
1059                         spi1_rx: spi1-rx {
1060                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1061                         };
1062                         spi1_tx: spi1-tx {
1063                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1064                         };
1065                 };
1066
1067                 spi2 {
1068                         spi2_cs1: spi2-cs1 {
1069                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1070                         };
1071                         spi2_clk: spi2-clk {
1072                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1073                         };
1074                         spi2_cs0: spi2-cs0 {
1075                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1076                         };
1077                         spi2_rx: spi2-rx {
1078                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1079                         };
1080                         spi2_tx: spi2-tx {
1081                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1082                         };
1083                 };
1084
1085                 uart0 {
1086                         uart0_xfer: uart0-xfer {
1087                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1088                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1089                         };
1090
1091                         uart0_cts: uart0-cts {
1092                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1093                         };
1094
1095                         uart0_rts: uart0-rts {
1096                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 uart1 {
1101                         uart1_xfer: uart1-xfer {
1102                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1103                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1104                         };
1105
1106                         uart1_cts: uart1-cts {
1107                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1108                         };
1109
1110                         uart1_rts: uart1-rts {
1111                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113                 };
1114
1115                 uart2 {
1116                         uart2_xfer: uart2-xfer {
1117                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1118                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1119                         };
1120                         /* no rts / cts for uart2 */
1121                 };
1122
1123                 uart3 {
1124                         uart3_xfer: uart3-xfer {
1125                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1126                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1127                         };
1128
1129                         uart3_cts: uart3-cts {
1130                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1131                         };
1132
1133                         uart3_rts: uart3-rts {
1134                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136                 };
1137
1138                 uart4 {
1139                         uart4_xfer: uart4-xfer {
1140                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1141                                                 <5 13 3 &pcfg_pull_none>;
1142                         };
1143
1144                         uart4_cts: uart4-cts {
1145                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1146                         };
1147
1148                         uart4_rts: uart4-rts {
1149                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1150                         };
1151                 };
1152
1153                 tsadc {
1154                         otp_out: otp-out {
1155                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 pwm0 {
1160                         pwm0_pin: pwm0-pin {
1161                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 pwm1 {
1166                         pwm1_pin: pwm1-pin {
1167                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1168                         };
1169                 };
1170
1171                 pwm2 {
1172                         pwm2_pin: pwm2-pin {
1173                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1174                         };
1175                 };
1176
1177                 pwm3 {
1178                         pwm3_pin: pwm3-pin {
1179                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1180                         };
1181                 };
1182         };
1183 };