arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52                         /* cooling options */
  53                         cooling-min-level = <0>;
  54                         cooling-max-level = <2>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57                 cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x1>;
  61                 };
  62         };
  63
  64         thermal-zones {
  65                 #include "omap4-cpu-thermal.dtsi"
  66                 #include "omap5-gpu-thermal.dtsi"
  67                 #include "omap5-core-thermal.dtsi"
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 /* PPI secure/nonsecure IRQ */
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  77         };
  78
  79         gic: interrupt-controller@48211000 {
  80                 compatible = "arm,cortex-a15-gic";
  81                 interrupt-controller;
  82                 #interrupt-cells = <3>;
  83                 reg = <0x48211000 0x1000>,
  84                       <0x48212000 0x1000>,
  85                       <0x48214000 0x2000>,
  86                       <0x48216000 0x2000>;
  87         };
  88
  89         /*
  90          * The soc node represents the soc top level view. It is uses for IPs
  91          * that are not memory mapped in the MPU view or for the MPU itself.
  92          */
  93         soc {
  94                 compatible = "ti,omap-infra";
  95                 mpu {
  96                         compatible = "ti,omap5-mpu";
  97                         ti,hwmods = "mpu";
  98                 };
  99         };
 100
 101         /*
 102          * XXX: Use a flat representation of the OMAP3 interconnect.
 103          * The real OMAP interconnect network is quite complex.
 104          * Since that will not bring real advantage to represent that in DT for
 105          * the moment, just use a fake OCP bus entry to represent the whole bus
 106          * hierarchy.
 107          */
 108         ocp {
 109                 compatible = "ti,omap4-l3-noc", "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges;
 113                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 114                 reg = <0x44000000 0x2000>,
 115                       <0x44800000 0x3000>,
 116                       <0x45000000 0x4000>;
 117                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 119
 120                 prm: prm@4ae06000 {
 121                         compatible = "ti,omap5-prm";
 122                         reg = <0x4ae06000 0x3000>;
 123
 124                         prm_clocks: clocks {
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                         };
 128
 129                         prm_clockdomains: clockdomains {
 130                         };
 131                 };
 132
 133                 cm_core_aon: cm_core_aon@4a004000 {
 134                         compatible = "ti,omap5-cm-core-aon";
 135                         reg = <0x4a004000 0x2000>;
 136
 137                         cm_core_aon_clocks: clocks {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                         };
 141
 142                         cm_core_aon_clockdomains: clockdomains {
 143                         };
 144                 };
 145
 146                 scrm: scrm@4ae0a000 {
 147                         compatible = "ti,omap5-scrm";
 148                         reg = <0x4ae0a000 0x2000>;
 149
 150                         scrm_clocks: clocks {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                         };
 154
 155                         scrm_clockdomains: clockdomains {
 156                         };
 157                 };
 158
 159                 cm_core: cm_core@4a008000 {
 160                         compatible = "ti,omap5-cm-core";
 161                         reg = <0x4a008000 0x3000>;
 162
 163                         cm_core_clocks: clocks {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                         };
 167
 168                         cm_core_clockdomains: clockdomains {
 169                         };
 170                 };
 171
 172                 counter32k: counter@4ae04000 {
 173                         compatible = "ti,omap-counter32k";
 174                         reg = <0x4ae04000 0x40>;
 175                         ti,hwmods = "counter_32k";
 176                 };
 177
 178                 omap5_pmx_core: pinmux@4a002840 {
 179                         compatible = "ti,omap4-padconf", "pinctrl-single";
 180                         reg = <0x4a002840 0x01b6>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         pinctrl-single,register-width = <16>;
 184                         pinctrl-single,function-mask = <0x7fff>;
 185                 };
 186                 omap5_pmx_wkup: pinmux@4ae0c840 {
 187                         compatible = "ti,omap4-padconf", "pinctrl-single";
 188                         reg = <0x4ae0c840 0x0038>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         pinctrl-single,register-width = <16>;
 192                         pinctrl-single,function-mask = <0x7fff>;
 193                 };
 194
 195                 sdma: dma-controller@4a056000 {
 196                         compatible = "ti,omap4430-sdma";
 197                         reg = <0x4a056000 0x1000>;
 198                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 202                         #dma-cells = <1>;
 203                         #dma-channels = <32>;
 204                         #dma-requests = <127>;
 205                 };
 206
 207                 gpio1: gpio@4ae10000 {
 208                         compatible = "ti,omap4-gpio";
 209                         reg = <0x4ae10000 0x200>;
 210                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 211                         ti,hwmods = "gpio1";
 212                         ti,gpio-always-on;
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                 };
 218
 219                 gpio2: gpio@48055000 {
 220                         compatible = "ti,omap4-gpio";
 221                         reg = <0x48055000 0x200>;
 222                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 223                         ti,hwmods = "gpio2";
 224                         gpio-controller;
 225                         #gpio-cells = <2>;
 226                         interrupt-controller;
 227                         #interrupt-cells = <2>;
 228                 };
 229
 230                 gpio3: gpio@48057000 {
 231                         compatible = "ti,omap4-gpio";
 232                         reg = <0x48057000 0x200>;
 233                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 234                         ti,hwmods = "gpio3";
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                         interrupt-controller;
 238                         #interrupt-cells = <2>;
 239                 };
 240
 241                 gpio4: gpio@48059000 {
 242                         compatible = "ti,omap4-gpio";
 243                         reg = <0x48059000 0x200>;
 244                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 245                         ti,hwmods = "gpio4";
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248                         interrupt-controller;
 249                         #interrupt-cells = <2>;
 250                 };
 251
 252                 gpio5: gpio@4805b000 {
 253                         compatible = "ti,omap4-gpio";
 254                         reg = <0x4805b000 0x200>;
 255                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 256                         ti,hwmods = "gpio5";
 257                         gpio-controller;
 258                         #gpio-cells = <2>;
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio6: gpio@4805d000 {
 264                         compatible = "ti,omap4-gpio";
 265                         reg = <0x4805d000 0x200>;
 266                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 267                         ti,hwmods = "gpio6";
 268                         gpio-controller;
 269                         #gpio-cells = <2>;
 270                         interrupt-controller;
 271                         #interrupt-cells = <2>;
 272                 };
 273
 274                 gpio7: gpio@48051000 {
 275                         compatible = "ti,omap4-gpio";
 276                         reg = <0x48051000 0x200>;
 277                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 278                         ti,hwmods = "gpio7";
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 gpio8: gpio@48053000 {
 286                         compatible = "ti,omap4-gpio";
 287                         reg = <0x48053000 0x200>;
 288                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 289                         ti,hwmods = "gpio8";
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpmc: gpmc@50000000 {
 297                         compatible = "ti,omap4430-gpmc";
 298                         reg = <0x50000000 0x1000>;
 299                         #address-cells = <2>;
 300                         #size-cells = <1>;
 301                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 302                         gpmc,num-cs = <8>;
 303                         gpmc,num-waitpins = <4>;
 304                         ti,hwmods = "gpmc";
 305                 };
 306
 307                 i2c1: i2c@48070000 {
 308                         compatible = "ti,omap4-i2c";
 309                         reg = <0x48070000 0x100>;
 310                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         ti,hwmods = "i2c1";
 314                 };
 315
 316                 i2c2: i2c@48072000 {
 317                         compatible = "ti,omap4-i2c";
 318                         reg = <0x48072000 0x100>;
 319                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         ti,hwmods = "i2c2";
 323                 };
 324
 325                 i2c3: i2c@48060000 {
 326                         compatible = "ti,omap4-i2c";
 327                         reg = <0x48060000 0x100>;
 328                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         ti,hwmods = "i2c3";
 332                 };
 333
 334                 i2c4: i2c@4807a000 {
 335                         compatible = "ti,omap4-i2c";
 336                         reg = <0x4807a000 0x100>;
 337                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         ti,hwmods = "i2c4";
 341                 };
 342
 343                 i2c5: i2c@4807c000 {
 344                         compatible = "ti,omap4-i2c";
 345                         reg = <0x4807c000 0x100>;
 346                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         ti,hwmods = "i2c5";
 350                 };
 351
 352                 hwspinlock: spinlock@4a0f6000 {
 353                         compatible = "ti,omap4-hwspinlock";
 354                         reg = <0x4a0f6000 0x1000>;
 355                         ti,hwmods = "spinlock";
 356                 };
 357
 358                 mcspi1: spi@48098000 {
 359                         compatible = "ti,omap4-mcspi";
 360                         reg = <0x48098000 0x200>;
 361                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         ti,hwmods = "mcspi1";
 365                         ti,spi-num-cs = <4>;
 366                         dmas = <&sdma 35>,
 367                                <&sdma 36>,
 368                                <&sdma 37>,
 369                                <&sdma 38>,
 370                                <&sdma 39>,
 371                                <&sdma 40>,
 372                                <&sdma 41>,
 373                                <&sdma 42>;
 374                         dma-names = "tx0", "rx0", "tx1", "rx1",
 375                                     "tx2", "rx2", "tx3", "rx3";
 376                 };
 377
 378                 mcspi2: spi@4809a000 {
 379                         compatible = "ti,omap4-mcspi";
 380                         reg = <0x4809a000 0x200>;
 381                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         ti,hwmods = "mcspi2";
 385                         ti,spi-num-cs = <2>;
 386                         dmas = <&sdma 43>,
 387                                <&sdma 44>,
 388                                <&sdma 45>,
 389                                <&sdma 46>;
 390                         dma-names = "tx0", "rx0", "tx1", "rx1";
 391                 };
 392
 393                 mcspi3: spi@480b8000 {
 394                         compatible = "ti,omap4-mcspi";
 395                         reg = <0x480b8000 0x200>;
 396                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         ti,hwmods = "mcspi3";
 400                         ti,spi-num-cs = <2>;
 401                         dmas = <&sdma 15>, <&sdma 16>;
 402                         dma-names = "tx0", "rx0";
 403                 };
 404
 405                 mcspi4: spi@480ba000 {
 406                         compatible = "ti,omap4-mcspi";
 407                         reg = <0x480ba000 0x200>;
 408                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         ti,hwmods = "mcspi4";
 412                         ti,spi-num-cs = <1>;
 413                         dmas = <&sdma 70>, <&sdma 71>;
 414                         dma-names = "tx0", "rx0";
 415                 };
 416
 417                 uart1: serial@4806a000 {
 418                         compatible = "ti,omap4-uart";
 419                         reg = <0x4806a000 0x100>;
 420                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 421                         ti,hwmods = "uart1";
 422                         clock-frequency = <48000000>;
 423                 };
 424
 425                 uart2: serial@4806c000 {
 426                         compatible = "ti,omap4-uart";
 427                         reg = <0x4806c000 0x100>;
 428                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 429                         ti,hwmods = "uart2";
 430                         clock-frequency = <48000000>;
 431                 };
 432
 433                 uart3: serial@48020000 {
 434                         compatible = "ti,omap4-uart";
 435                         reg = <0x48020000 0x100>;
 436                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 437                         ti,hwmods = "uart3";
 438                         clock-frequency = <48000000>;
 439                 };
 440
 441                 uart4: serial@4806e000 {
 442                         compatible = "ti,omap4-uart";
 443                         reg = <0x4806e000 0x100>;
 444                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 445                         ti,hwmods = "uart4";
 446                         clock-frequency = <48000000>;
 447                 };
 448
 449                 uart5: serial@48066000 {
 450                         compatible = "ti,omap4-uart";
 451                         reg = <0x48066000 0x100>;
 452                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 453                         ti,hwmods = "uart5";
 454                         clock-frequency = <48000000>;
 455                 };
 456
 457                 uart6: serial@48068000 {
 458                         compatible = "ti,omap4-uart";
 459                         reg = <0x48068000 0x100>;
 460                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 461                         ti,hwmods = "uart6";
 462                         clock-frequency = <48000000>;
 463                 };
 464
 465                 mmc1: mmc@4809c000 {
 466                         compatible = "ti,omap4-hsmmc";
 467                         reg = <0x4809c000 0x400>;
 468                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 469                         ti,hwmods = "mmc1";
 470                         ti,dual-volt;
 471                         ti,needs-special-reset;
 472                         dmas = <&sdma 61>, <&sdma 62>;
 473                         dma-names = "tx", "rx";
 474                 };
 475
 476                 mmc2: mmc@480b4000 {
 477                         compatible = "ti,omap4-hsmmc";
 478                         reg = <0x480b4000 0x400>;
 479                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 480                         ti,hwmods = "mmc2";
 481                         ti,needs-special-reset;
 482                         dmas = <&sdma 47>, <&sdma 48>;
 483                         dma-names = "tx", "rx";
 484                 };
 485
 486                 mmc3: mmc@480ad000 {
 487                         compatible = "ti,omap4-hsmmc";
 488                         reg = <0x480ad000 0x400>;
 489                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 490                         ti,hwmods = "mmc3";
 491                         ti,needs-special-reset;
 492                         dmas = <&sdma 77>, <&sdma 78>;
 493                         dma-names = "tx", "rx";
 494                 };
 495
 496                 mmc4: mmc@480d1000 {
 497                         compatible = "ti,omap4-hsmmc";
 498                         reg = <0x480d1000 0x400>;
 499                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 500                         ti,hwmods = "mmc4";
 501                         ti,needs-special-reset;
 502                         dmas = <&sdma 57>, <&sdma 58>;
 503                         dma-names = "tx", "rx";
 504                 };
 505
 506                 mmc5: mmc@480d5000 {
 507                         compatible = "ti,omap4-hsmmc";
 508                         reg = <0x480d5000 0x400>;
 509                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 510                         ti,hwmods = "mmc5";
 511                         ti,needs-special-reset;
 512                         dmas = <&sdma 59>, <&sdma 60>;
 513                         dma-names = "tx", "rx";
 514                 };
 515
 516                 keypad: keypad@4ae1c000 {
 517                         compatible = "ti,omap4-keypad";
 518                         reg = <0x4ae1c000 0x400>;
 519                         ti,hwmods = "kbd";
 520                 };
 521
 522                 mcpdm: mcpdm@40132000 {
 523                         compatible = "ti,omap4-mcpdm";
 524                         reg = <0x40132000 0x7f>, /* MPU private access */
 525                               <0x49032000 0x7f>; /* L3 Interconnect */
 526                         reg-names = "mpu", "dma";
 527                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 528                         ti,hwmods = "mcpdm";
 529                         dmas = <&sdma 65>,
 530                                <&sdma 66>;
 531                         dma-names = "up_link", "dn_link";
 532                 };
 533
 534                 dmic: dmic@4012e000 {
 535                         compatible = "ti,omap4-dmic";
 536                         reg = <0x4012e000 0x7f>, /* MPU private access */
 537                               <0x4902e000 0x7f>; /* L3 Interconnect */
 538                         reg-names = "mpu", "dma";
 539                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 540                         ti,hwmods = "dmic";
 541                         dmas = <&sdma 67>;
 542                         dma-names = "up_link";
 543                 };
 544
 545                 mcbsp1: mcbsp@40122000 {
 546                         compatible = "ti,omap4-mcbsp";
 547                         reg = <0x40122000 0xff>, /* MPU private access */
 548                               <0x49022000 0xff>; /* L3 Interconnect */
 549                         reg-names = "mpu", "dma";
 550                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 551                         interrupt-names = "common";
 552                         ti,buffer-size = <128>;
 553                         ti,hwmods = "mcbsp1";
 554                         dmas = <&sdma 33>,
 555                                <&sdma 34>;
 556                         dma-names = "tx", "rx";
 557                 };
 558
 559                 mcbsp2: mcbsp@40124000 {
 560                         compatible = "ti,omap4-mcbsp";
 561                         reg = <0x40124000 0xff>, /* MPU private access */
 562                               <0x49024000 0xff>; /* L3 Interconnect */
 563                         reg-names = "mpu", "dma";
 564                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 565                         interrupt-names = "common";
 566                         ti,buffer-size = <128>;
 567                         ti,hwmods = "mcbsp2";
 568                         dmas = <&sdma 17>,
 569                                <&sdma 18>;
 570                         dma-names = "tx", "rx";
 571                 };
 572
 573                 mcbsp3: mcbsp@40126000 {
 574                         compatible = "ti,omap4-mcbsp";
 575                         reg = <0x40126000 0xff>, /* MPU private access */
 576                               <0x49026000 0xff>; /* L3 Interconnect */
 577                         reg-names = "mpu", "dma";
 578                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 579                         interrupt-names = "common";
 580                         ti,buffer-size = <128>;
 581                         ti,hwmods = "mcbsp3";
 582                         dmas = <&sdma 19>,
 583                                <&sdma 20>;
 584                         dma-names = "tx", "rx";
 585                 };
 586
 587                 timer1: timer@4ae18000 {
 588                         compatible = "ti,omap5430-timer";
 589                         reg = <0x4ae18000 0x80>;
 590                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 591                         ti,hwmods = "timer1";
 592                         ti,timer-alwon;
 593                 };
 594
 595                 timer2: timer@48032000 {
 596                         compatible = "ti,omap5430-timer";
 597                         reg = <0x48032000 0x80>;
 598                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 599                         ti,hwmods = "timer2";
 600                 };
 601
 602                 timer3: timer@48034000 {
 603                         compatible = "ti,omap5430-timer";
 604                         reg = <0x48034000 0x80>;
 605                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 606                         ti,hwmods = "timer3";
 607                 };
 608
 609                 timer4: timer@48036000 {
 610                         compatible = "ti,omap5430-timer";
 611                         reg = <0x48036000 0x80>;
 612                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 613                         ti,hwmods = "timer4";
 614                 };
 615
 616                 timer5: timer@40138000 {
 617                         compatible = "ti,omap5430-timer";
 618                         reg = <0x40138000 0x80>,
 619                               <0x49038000 0x80>;
 620                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 621                         ti,hwmods = "timer5";
 622                         ti,timer-dsp;
 623                         ti,timer-pwm;
 624                 };
 625
 626                 timer6: timer@4013a000 {
 627                         compatible = "ti,omap5430-timer";
 628                         reg = <0x4013a000 0x80>,
 629                               <0x4903a000 0x80>;
 630                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 631                         ti,hwmods = "timer6";
 632                         ti,timer-dsp;
 633                         ti,timer-pwm;
 634                 };
 635
 636                 timer7: timer@4013c000 {
 637                         compatible = "ti,omap5430-timer";
 638                         reg = <0x4013c000 0x80>,
 639                               <0x4903c000 0x80>;
 640                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 641                         ti,hwmods = "timer7";
 642                         ti,timer-dsp;
 643                 };
 644
 645                 timer8: timer@4013e000 {
 646                         compatible = "ti,omap5430-timer";
 647                         reg = <0x4013e000 0x80>,
 648                               <0x4903e000 0x80>;
 649                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 650                         ti,hwmods = "timer8";
 651                         ti,timer-dsp;
 652                         ti,timer-pwm;
 653                 };
 654
 655                 timer9: timer@4803e000 {
 656                         compatible = "ti,omap5430-timer";
 657                         reg = <0x4803e000 0x80>;
 658                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 659                         ti,hwmods = "timer9";
 660                         ti,timer-pwm;
 661                 };
 662
 663                 timer10: timer@48086000 {
 664                         compatible = "ti,omap5430-timer";
 665                         reg = <0x48086000 0x80>;
 666                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 667                         ti,hwmods = "timer10";
 668                         ti,timer-pwm;
 669                 };
 670
 671                 timer11: timer@48088000 {
 672                         compatible = "ti,omap5430-timer";
 673                         reg = <0x48088000 0x80>;
 674                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 675                         ti,hwmods = "timer11";
 676                         ti,timer-pwm;
 677                 };
 678
 679                 wdt2: wdt@4ae14000 {
 680                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 681                         reg = <0x4ae14000 0x80>;
 682                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 683                         ti,hwmods = "wd_timer2";
 684                 };
 685
 686                 emif1: emif@4c000000 {
 687                         compatible      = "ti,emif-4d5";
 688                         ti,hwmods       = "emif1";
 689                         ti,no-idle-on-init;
 690                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 691                         reg = <0x4c000000 0x400>;
 692                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 693                         hw-caps-read-idle-ctrl;
 694                         hw-caps-ll-interface;
 695                         hw-caps-temp-alert;
 696                 };
 697
 698                 emif2: emif@4d000000 {
 699                         compatible      = "ti,emif-4d5";
 700                         ti,hwmods       = "emif2";
 701                         ti,no-idle-on-init;
 702                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 703                         reg = <0x4d000000 0x400>;
 704                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 705                         hw-caps-read-idle-ctrl;
 706                         hw-caps-ll-interface;
 707                         hw-caps-temp-alert;
 708                 };
 709
 710                 omap_control_usb2phy: control-phy@4a002300 {
 711                         compatible = "ti,control-phy-usb2";
 712                         reg = <0x4a002300 0x4>;
 713                         reg-names = "power";
 714                 };
 715
 716                 omap_control_usb3phy: control-phy@4a002370 {
 717                         compatible = "ti,control-phy-pipe3";
 718                         reg = <0x4a002370 0x4>;
 719                         reg-names = "power";
 720                 };
 721
 722                 usb3: omap_dwc3@4a020000 {
 723                         compatible = "ti,dwc3";
 724                         ti,hwmods = "usb_otg_ss";
 725                         reg = <0x4a020000 0x10000>;
 726                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 727                         #address-cells = <1>;
 728                         #size-cells = <1>;
 729                         utmi-mode = <2>;
 730                         ranges;
 731                         dwc3@4a030000 {
 732                                 compatible = "snps,dwc3";
 733                                 reg = <0x4a030000 0x10000>;
 734                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 735                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
 736                                 dr_mode = "peripheral";
 737                                 tx-fifo-resize;
 738                         };
 739                 };
 740
 741                 ocp2scp@4a080000 {
 742                         compatible = "ti,omap-ocp2scp";
 743                         #address-cells = <1>;
 744                         #size-cells = <1>;
 745                         reg = <0x4a080000 0x20>;
 746                         ranges;
 747                         ti,hwmods = "ocp2scp1";
 748                         usb2_phy: usb2phy@4a084000 {
 749                                 compatible = "ti,omap-usb2";
 750                                 reg = <0x4a084000 0x7c>;
 751                                 ctrl-module = <&omap_control_usb2phy>;
 752                         };
 753
 754                         usb3_phy: usb3phy@4a084400 {
 755                                 compatible = "ti,omap-usb3";
 756                                 reg = <0x4a084400 0x80>,
 757                                       <0x4a084800 0x64>,
 758                                       <0x4a084c00 0x40>;
 759                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 760                                 ctrl-module = <&omap_control_usb3phy>;
 761                         };
 762                 };
 763
 764                 usbhstll: usbhstll@4a062000 {
 765                         compatible = "ti,usbhs-tll";
 766                         reg = <0x4a062000 0x1000>;
 767                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 768                         ti,hwmods = "usb_tll_hs";
 769                 };
 770
 771                 usbhshost: usbhshost@4a064000 {
 772                         compatible = "ti,usbhs-host";
 773                         reg = <0x4a064000 0x800>;
 774                         ti,hwmods = "usb_host_hs";
 775                         #address-cells = <1>;
 776                         #size-cells = <1>;
 777                         ranges;
 778                         clocks = <&l3init_60m_fclk>,
 779                                  <&xclk60mhsp1_ck>,
 780                                  <&xclk60mhsp2_ck>;
 781                         clock-names = "refclk_60m_int",
 782                                       "refclk_60m_ext_p1",
 783                                       "refclk_60m_ext_p2";
 784
 785                         usbhsohci: ohci@4a064800 {
 786                                 compatible = "ti,ohci-omap3", "usb-ohci";
 787                                 reg = <0x4a064800 0x400>;
 788                                 interrupt-parent = <&gic>;
 789                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 790                         };
 791
 792                         usbhsehci: ehci@4a064c00 {
 793                                 compatible = "ti,ehci-omap", "usb-ehci";
 794                                 reg = <0x4a064c00 0x400>;
 795                                 interrupt-parent = <&gic>;
 796                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 797                         };
 798                 };
 799
 800                 bandgap: bandgap@4a0021e0 {
 801                         reg = <0x4a0021e0 0xc
 802                                0x4a00232c 0xc
 803                                0x4a002380 0x2c
 804                                0x4a0023C0 0x3c>;
 805                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 806                         compatible = "ti,omap5430-bandgap";
 807
 808                         #thermal-sensor-cells = <1>;
 809                 };
 810         };
 811 };
 812
 813 /include/ "omap54xx-clocks.dtsi"