arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 ethernet0 = &fec;
  21                 can0 = &can1;
  22                 can1 = &can2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 mmc3 = &usdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         intc: interrupt-controller@00a01000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 ckil {
  63                         compatible = "fsl,imx-ckil", "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <32768>;
  66                 };
  67
  68                 ckih1 {
  69                         compatible = "fsl,imx-ckih1", "fixed-clock";
  70                         #clock-cells = <0>;
  71                         clock-frequency = <0>;
  72                 };
  73
  74                 osc {
  75                         compatible = "fsl,imx-osc", "fixed-clock";
  76                         #clock-cells = <0>;
  77                         clock-frequency = <24000000>;
  78                 };
  79         };
  80
  81         soc {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 compatible = "simple-bus";
  85                 interrupt-parent = <&intc>;
  86                 ranges;
  87
  88                 dma_apbh: dma-apbh@00110000 {
  89                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  90                         reg = <0x00110000 0x2000>;
  91                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  95                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  96                         #dma-cells = <1>;
  97                         dma-channels = <4>;
  98                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
  99                 };
 100
 101                 gpmi: gpmi-nand@00112000 {
 102                         compatible = "fsl,imx6q-gpmi-nand";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 106                         reg-names = "gpmi-nand", "bch";
 107                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 108                         interrupt-names = "bch";
 109                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 110                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 111                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 112                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 113                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 114                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 115                                       "gpmi_bch_apb", "per1_bch";
 116                         dmas = <&dma_apbh 0>;
 117                         dma-names = "rx-tx";
 118                         status = "disabled";
 119                 };
 120
 121                 timer@00a00600 {
 122                         compatible = "arm,cortex-a9-twd-timer";
 123                         reg = <0x00a00600 0x20>;
 124                         interrupts = <1 13 0xf01>;
 125                         clocks = <&clks IMX6QDL_CLK_TWD>;
 126                 };
 127
 128                 L2: l2-cache@00a02000 {
 129                         compatible = "arm,pl310-cache";
 130                         reg = <0x00a02000 0x1000>;
 131                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 132                         cache-unified;
 133                         cache-level = <2>;
 134                         arm,tag-latency = <4 2 3>;
 135                         arm,data-latency = <4 2 3>;
 136                 };
 137
 138                 pcie: pcie@0x01000000 {
 139                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 140                         reg = <0x01ffc000 0x04000>,
 141                               <0x01f00000 0x80000>;
 142                         reg-names = "dbi", "config";
 143                         #address-cells = <3>;
 144                         #size-cells = <2>;
 145                         device_type = "pci";
 146                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 147                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 148                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 149                         num-lanes = <1>;
 150                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "msi";
 152                         #interrupt-cells = <1>;
 153                         interrupt-map-mask = <0 0 0 0x7>;
 154                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 155                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 156                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 157                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 159                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 160                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 161                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 162                         status = "disabled";
 163                 };
 164
 165                 pmu {
 166                         compatible = "arm,cortex-a9-pmu";
 167                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 168                 };
 169
 170                 aips-bus@02000000 { /* AIPS1 */
 171                         compatible = "fsl,aips-bus", "simple-bus";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         reg = <0x02000000 0x100000>;
 175                         ranges;
 176
 177                         spba-bus@02000000 {
 178                                 compatible = "fsl,spba-bus", "simple-bus";
 179                                 #address-cells = <1>;
 180                                 #size-cells = <1>;
 181                                 reg = <0x02000000 0x40000>;
 182                                 ranges;
 183
 184                                 spdif: spdif@02004000 {
 185                                         compatible = "fsl,imx35-spdif";
 186                                         reg = <0x02004000 0x4000>;
 187                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 188                                         dmas = <&sdma 14 18 0>,
 189                                                <&sdma 15 18 0>;
 190                                         dma-names = "rx", "tx";
 191                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 192                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
 193                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 194                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 195                                                  <&clks IMX6QDL_CLK_DUMMY>;
 196                                         clock-names = "core",  "rxtx0",
 197                                                       "rxtx1", "rxtx2",
 198                                                       "rxtx3", "rxtx4",
 199                                                       "rxtx5", "rxtx6",
 200                                                       "rxtx7";
 201                                         status = "disabled";
 202                                 };
 203
 204                                 ecspi1: ecspi@02008000 {
 205                                         #address-cells = <1>;
 206                                         #size-cells = <0>;
 207                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 208                                         reg = <0x02008000 0x4000>;
 209                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 210                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 211                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 212                                         clock-names = "ipg", "per";
 213                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 214                                         dma-names = "rx", "tx";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ecspi2: ecspi@0200c000 {
 219                                         #address-cells = <1>;
 220                                         #size-cells = <0>;
 221                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 222                                         reg = <0x0200c000 0x4000>;
 223                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 224                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 225                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 226                                         clock-names = "ipg", "per";
 227                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 228                                         dma-names = "rx", "tx";
 229                                         status = "disabled";
 230                                 };
 231
 232                                 ecspi3: ecspi@02010000 {
 233                                         #address-cells = <1>;
 234                                         #size-cells = <0>;
 235                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 236                                         reg = <0x02010000 0x4000>;
 237                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 238                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 239                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 240                                         clock-names = "ipg", "per";
 241                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 242                                         dma-names = "rx", "tx";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 ecspi4: ecspi@02014000 {
 247                                         #address-cells = <1>;
 248                                         #size-cells = <0>;
 249                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 250                                         reg = <0x02014000 0x4000>;
 251                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 252                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 253                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 254                                         clock-names = "ipg", "per";
 255                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 256                                         dma-names = "rx", "tx";
 257                                         status = "disabled";
 258                                 };
 259
 260                                 uart1: serial@02020000 {
 261                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 262                                         reg = <0x02020000 0x4000>;
 263                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 264                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 265                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 266                                         clock-names = "ipg", "per";
 267                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 268                                         dma-names = "rx", "tx";
 269                                         status = "disabled";
 270                                 };
 271
 272                                 esai: esai@02024000 {
 273                                         reg = <0x02024000 0x4000>;
 274                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 275                                 };
 276
 277                                 ssi1: ssi@02028000 {
 278                                         #sound-dai-cells = <0>;
 279                                         compatible = "fsl,imx6q-ssi",
 280                                                         "fsl,imx51-ssi";
 281                                         reg = <0x02028000 0x4000>;
 282                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 283                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 284                                                  <&clks IMX6QDL_CLK_SSI1>;
 285                                         clock-names = "ipg", "baud";
 286                                         dmas = <&sdma 37 1 0>,
 287                                                <&sdma 38 1 0>;
 288                                         dma-names = "rx", "tx";
 289                                         fsl,fifo-depth = <15>;
 290                                         status = "disabled";
 291                                 };
 292
 293                                 ssi2: ssi@0202c000 {
 294                                         #sound-dai-cells = <0>;
 295                                         compatible = "fsl,imx6q-ssi",
 296                                                         "fsl,imx51-ssi";
 297                                         reg = <0x0202c000 0x4000>;
 298                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 299                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 300                                                  <&clks IMX6QDL_CLK_SSI2>;
 301                                         clock-names = "ipg", "baud";
 302                                         dmas = <&sdma 41 1 0>,
 303                                                <&sdma 42 1 0>;
 304                                         dma-names = "rx", "tx";
 305                                         fsl,fifo-depth = <15>;
 306                                         status = "disabled";
 307                                 };
 308
 309                                 ssi3: ssi@02030000 {
 310                                         #sound-dai-cells = <0>;
 311                                         compatible = "fsl,imx6q-ssi",
 312                                                         "fsl,imx51-ssi";
 313                                         reg = <0x02030000 0x4000>;
 314                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 315                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 316                                                  <&clks IMX6QDL_CLK_SSI3>;
 317                                         clock-names = "ipg", "baud";
 318                                         dmas = <&sdma 45 1 0>,
 319                                                <&sdma 46 1 0>;
 320                                         dma-names = "rx", "tx";
 321                                         fsl,fifo-depth = <15>;
 322                                         status = "disabled";
 323                                 };
 324
 325                                 asrc: asrc@02034000 {
 326                                         reg = <0x02034000 0x4000>;
 327                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 328                                 };
 329
 330                                 spba@0203c000 {
 331                                         reg = <0x0203c000 0x4000>;
 332                                 };
 333                         };
 334
 335                         vpu: vpu@02040000 {
 336                                 compatible = "cnm,coda960";
 337                                 reg = <0x02040000 0x3c000>;
 338                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 339                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 340                                 interrupt-names = "bit", "jpeg";
 341                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 342                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
 343                                          <&clks IMX6QDL_CLK_OCRAM>;
 344                                 clock-names = "per", "ahb", "ocram";
 345                                 resets = <&src 1>;
 346                                 iram = <&ocram>;
 347                         };
 348
 349                         aipstz@0207c000 { /* AIPSTZ1 */
 350                                 reg = <0x0207c000 0x4000>;
 351                         };
 352
 353                         pwm1: pwm@02080000 {
 354                                 #pwm-cells = <2>;
 355                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 356                                 reg = <0x02080000 0x4000>;
 357                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 358                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 359                                          <&clks IMX6QDL_CLK_PWM1>;
 360                                 clock-names = "ipg", "per";
 361                         };
 362
 363                         pwm2: pwm@02084000 {
 364                                 #pwm-cells = <2>;
 365                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 366                                 reg = <0x02084000 0x4000>;
 367                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 369                                          <&clks IMX6QDL_CLK_PWM2>;
 370                                 clock-names = "ipg", "per";
 371                         };
 372
 373                         pwm3: pwm@02088000 {
 374                                 #pwm-cells = <2>;
 375                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 376                                 reg = <0x02088000 0x4000>;
 377                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 379                                          <&clks IMX6QDL_CLK_PWM3>;
 380                                 clock-names = "ipg", "per";
 381                         };
 382
 383                         pwm4: pwm@0208c000 {
 384                                 #pwm-cells = <2>;
 385                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 386                                 reg = <0x0208c000 0x4000>;
 387                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 388                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 389                                          <&clks IMX6QDL_CLK_PWM4>;
 390                                 clock-names = "ipg", "per";
 391                         };
 392
 393                         can1: flexcan@02090000 {
 394                                 compatible = "fsl,imx6q-flexcan";
 395                                 reg = <0x02090000 0x4000>;
 396                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 397                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 398                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 399                                 clock-names = "ipg", "per";
 400                                 status = "disabled";
 401                         };
 402
 403                         can2: flexcan@02094000 {
 404                                 compatible = "fsl,imx6q-flexcan";
 405                                 reg = <0x02094000 0x4000>;
 406                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 407                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 408                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 409                                 clock-names = "ipg", "per";
 410                                 status = "disabled";
 411                         };
 412
 413                         gpt: gpt@02098000 {
 414                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 415                                 reg = <0x02098000 0x4000>;
 416                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 418                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 419                                          <&clks IMX6QDL_CLK_GPT_3M>;
 420                                 clock-names = "ipg", "per", "osc_per";
 421                         };
 422
 423                         gpio1: gpio@0209c000 {
 424                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 425                                 reg = <0x0209c000 0x4000>;
 426                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 427                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 428                                 gpio-controller;
 429                                 #gpio-cells = <2>;
 430                                 interrupt-controller;
 431                                 #interrupt-cells = <2>;
 432                         };
 433
 434                         gpio2: gpio@020a0000 {
 435                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 436                                 reg = <0x020a0000 0x4000>;
 437                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 438                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 439                                 gpio-controller;
 440                                 #gpio-cells = <2>;
 441                                 interrupt-controller;
 442                                 #interrupt-cells = <2>;
 443                         };
 444
 445                         gpio3: gpio@020a4000 {
 446                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 447                                 reg = <0x020a4000 0x4000>;
 448                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 449                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 450                                 gpio-controller;
 451                                 #gpio-cells = <2>;
 452                                 interrupt-controller;
 453                                 #interrupt-cells = <2>;
 454                         };
 455
 456                         gpio4: gpio@020a8000 {
 457                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 458                                 reg = <0x020a8000 0x4000>;
 459                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 460                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 461                                 gpio-controller;
 462                                 #gpio-cells = <2>;
 463                                 interrupt-controller;
 464                                 #interrupt-cells = <2>;
 465                         };
 466
 467                         gpio5: gpio@020ac000 {
 468                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 469                                 reg = <0x020ac000 0x4000>;
 470                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 471                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 472                                 gpio-controller;
 473                                 #gpio-cells = <2>;
 474                                 interrupt-controller;
 475                                 #interrupt-cells = <2>;
 476                         };
 477
 478                         gpio6: gpio@020b0000 {
 479                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 480                                 reg = <0x020b0000 0x4000>;
 481                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 482                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 483                                 gpio-controller;
 484                                 #gpio-cells = <2>;
 485                                 interrupt-controller;
 486                                 #interrupt-cells = <2>;
 487                         };
 488
 489                         gpio7: gpio@020b4000 {
 490                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 491                                 reg = <0x020b4000 0x4000>;
 492                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 493                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 494                                 gpio-controller;
 495                                 #gpio-cells = <2>;
 496                                 interrupt-controller;
 497                                 #interrupt-cells = <2>;
 498                         };
 499
 500                         kpp: kpp@020b8000 {
 501                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 502                                 reg = <0x020b8000 0x4000>;
 503                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 505                                 status = "disabled";
 506                         };
 507
 508                         wdog1: wdog@020bc000 {
 509                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 510                                 reg = <0x020bc000 0x4000>;
 511                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 512                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 513                         };
 514
 515                         wdog2: wdog@020c0000 {
 516                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 517                                 reg = <0x020c0000 0x4000>;
 518                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 519                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 520                                 status = "disabled";
 521                         };
 522
 523                         clks: ccm@020c4000 {
 524                                 compatible = "fsl,imx6q-ccm";
 525                                 reg = <0x020c4000 0x4000>;
 526                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 527                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 528                                 #clock-cells = <1>;
 529                         };
 530
 531                         anatop: anatop@020c8000 {
 532                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 533                                 reg = <0x020c8000 0x1000>;
 534                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 535                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 536                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 537
 538                                 regulator-1p1@110 {
 539                                         compatible = "fsl,anatop-regulator";
 540                                         regulator-name = "vdd1p1";
 541                                         regulator-min-microvolt = <800000>;
 542                                         regulator-max-microvolt = <1375000>;
 543                                         regulator-always-on;
 544                                         anatop-reg-offset = <0x110>;
 545                                         anatop-vol-bit-shift = <8>;
 546                                         anatop-vol-bit-width = <5>;
 547                                         anatop-min-bit-val = <4>;
 548                                         anatop-min-voltage = <800000>;
 549                                         anatop-max-voltage = <1375000>;
 550                                 };
 551
 552                                 regulator-3p0@120 {
 553                                         compatible = "fsl,anatop-regulator";
 554                                         regulator-name = "vdd3p0";
 555                                         regulator-min-microvolt = <2800000>;
 556                                         regulator-max-microvolt = <3150000>;
 557                                         regulator-always-on;
 558                                         anatop-reg-offset = <0x120>;
 559                                         anatop-vol-bit-shift = <8>;
 560                                         anatop-vol-bit-width = <5>;
 561                                         anatop-min-bit-val = <0>;
 562                                         anatop-min-voltage = <2625000>;
 563                                         anatop-max-voltage = <3400000>;
 564                                 };
 565
 566                                 regulator-2p5@130 {
 567                                         compatible = "fsl,anatop-regulator";
 568                                         regulator-name = "vdd2p5";
 569                                         regulator-min-microvolt = <2000000>;
 570                                         regulator-max-microvolt = <2750000>;
 571                                         regulator-always-on;
 572                                         anatop-reg-offset = <0x130>;
 573                                         anatop-vol-bit-shift = <8>;
 574                                         anatop-vol-bit-width = <5>;
 575                                         anatop-min-bit-val = <0>;
 576                                         anatop-min-voltage = <2000000>;
 577                                         anatop-max-voltage = <2750000>;
 578                                 };
 579
 580                                 reg_arm: regulator-vddcore@140 {
 581                                         compatible = "fsl,anatop-regulator";
 582                                         regulator-name = "vddarm";
 583                                         regulator-min-microvolt = <725000>;
 584                                         regulator-max-microvolt = <1450000>;
 585                                         regulator-always-on;
 586                                         anatop-reg-offset = <0x140>;
 587                                         anatop-vol-bit-shift = <0>;
 588                                         anatop-vol-bit-width = <5>;
 589                                         anatop-delay-reg-offset = <0x170>;
 590                                         anatop-delay-bit-shift = <24>;
 591                                         anatop-delay-bit-width = <2>;
 592                                         anatop-min-bit-val = <1>;
 593                                         anatop-min-voltage = <725000>;
 594                                         anatop-max-voltage = <1450000>;
 595                                 };
 596
 597                                 reg_pu: regulator-vddpu@140 {
 598                                         compatible = "fsl,anatop-regulator";
 599                                         regulator-name = "vddpu";
 600                                         regulator-min-microvolt = <725000>;
 601                                         regulator-max-microvolt = <1450000>;
 602                                         regulator-always-on;
 603                                         anatop-reg-offset = <0x140>;
 604                                         anatop-vol-bit-shift = <9>;
 605                                         anatop-vol-bit-width = <5>;
 606                                         anatop-delay-reg-offset = <0x170>;
 607                                         anatop-delay-bit-shift = <26>;
 608                                         anatop-delay-bit-width = <2>;
 609                                         anatop-min-bit-val = <1>;
 610                                         anatop-min-voltage = <725000>;
 611                                         anatop-max-voltage = <1450000>;
 612                                 };
 613
 614                                 reg_soc: regulator-vddsoc@140 {
 615                                         compatible = "fsl,anatop-regulator";
 616                                         regulator-name = "vddsoc";
 617                                         regulator-min-microvolt = <725000>;
 618                                         regulator-max-microvolt = <1450000>;
 619                                         regulator-always-on;
 620                                         anatop-reg-offset = <0x140>;
 621                                         anatop-vol-bit-shift = <18>;
 622                                         anatop-vol-bit-width = <5>;
 623                                         anatop-delay-reg-offset = <0x170>;
 624                                         anatop-delay-bit-shift = <28>;
 625                                         anatop-delay-bit-width = <2>;
 626                                         anatop-min-bit-val = <1>;
 627                                         anatop-min-voltage = <725000>;
 628                                         anatop-max-voltage = <1450000>;
 629                                 };
 630                         };
 631
 632                         tempmon: tempmon {
 633                                 compatible = "fsl,imx6q-tempmon";
 634                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 635                                 fsl,tempmon = <&anatop>;
 636                                 fsl,tempmon-data = <&ocotp>;
 637                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 638                         };
 639
 640                         usbphy1: usbphy@020c9000 {
 641                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 642                                 reg = <0x020c9000 0x1000>;
 643                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 644                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 645                                 fsl,anatop = <&anatop>;
 646                         };
 647
 648                         usbphy2: usbphy@020ca000 {
 649                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 650                                 reg = <0x020ca000 0x1000>;
 651                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 652                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 653                                 fsl,anatop = <&anatop>;
 654                         };
 655
 656                         snvs@020cc000 {
 657                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 658                                 #address-cells = <1>;
 659                                 #size-cells = <1>;
 660                                 ranges = <0 0x020cc000 0x4000>;
 661
 662                                 snvs-rtc-lp@34 {
 663                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 664                                         reg = <0x34 0x58>;
 665                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 666                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 667                                 };
 668
 669                                 snvs_poweroff: snvs-poweroff@38 {
 670                                         compatible = "fsl,sec-v4.0-poweroff";
 671                                         reg = <0x38 0x4>;
 672                                         status = "disabled";
 673                                 };
 674                         };
 675
 676                         epit1: epit@020d0000 { /* EPIT1 */
 677                                 reg = <0x020d0000 0x4000>;
 678                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 679                         };
 680
 681                         epit2: epit@020d4000 { /* EPIT2 */
 682                                 reg = <0x020d4000 0x4000>;
 683                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 684                         };
 685
 686                         src: src@020d8000 {
 687                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 688                                 reg = <0x020d8000 0x4000>;
 689                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 690                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 691                                 #reset-cells = <1>;
 692                         };
 693
 694                         gpc: gpc@020dc000 {
 695                                 compatible = "fsl,imx6q-gpc";
 696                                 reg = <0x020dc000 0x4000>;
 697                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 698                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 699                         };
 700
 701                         gpr: iomuxc-gpr@020e0000 {
 702                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 703                                 reg = <0x020e0000 0x38>;
 704                         };
 705
 706                         iomuxc: iomuxc@020e0000 {
 707                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 708                                 reg = <0x020e0000 0x4000>;
 709                         };
 710
 711                         ldb: ldb@020e0008 {
 712                                 #address-cells = <1>;
 713                                 #size-cells = <0>;
 714                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 715                                 gpr = <&gpr>;
 716                                 status = "disabled";
 717
 718                                 lvds-channel@0 {
 719                                         #address-cells = <1>;
 720                                         #size-cells = <0>;
 721                                         reg = <0>;
 722                                         status = "disabled";
 723
 724                                         port@0 {
 725                                                 reg = <0>;
 726
 727                                                 lvds0_mux_0: endpoint {
 728                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 729                                                 };
 730                                         };
 731
 732                                         port@1 {
 733                                                 reg = <1>;
 734
 735                                                 lvds0_mux_1: endpoint {
 736                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 737                                                 };
 738                                         };
 739                                 };
 740
 741                                 lvds-channel@1 {
 742                                         #address-cells = <1>;
 743                                         #size-cells = <0>;
 744                                         reg = <1>;
 745                                         status = "disabled";
 746
 747                                         port@0 {
 748                                                 reg = <0>;
 749
 750                                                 lvds1_mux_0: endpoint {
 751                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 752                                                 };
 753                                         };
 754
 755                                         port@1 {
 756                                                 reg = <1>;
 757
 758                                                 lvds1_mux_1: endpoint {
 759                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 760                                                 };
 761                                         };
 762                                 };
 763                         };
 764
 765                         hdmi: hdmi@0120000 {
 766                                 #address-cells = <1>;
 767                                 #size-cells = <0>;
 768                                 reg = <0x00120000 0x9000>;
 769                                 interrupts = <0 115 0x04>;
 770                                 gpr = <&gpr>;
 771                                 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 772                                          <&clks IMX6QDL_CLK_HDMI_ISFR>;
 773                                 clock-names = "iahb", "isfr";
 774                                 status = "disabled";
 775
 776                                 port@0 {
 777                                         reg = <0>;
 778
 779                                         hdmi_mux_0: endpoint {
 780                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 781                                         };
 782                                 };
 783
 784                                 port@1 {
 785                                         reg = <1>;
 786
 787                                         hdmi_mux_1: endpoint {
 788                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 789                                         };
 790                                 };
 791                         };
 792
 793                         dcic1: dcic@020e4000 {
 794                                 reg = <0x020e4000 0x4000>;
 795                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 796                         };
 797
 798                         dcic2: dcic@020e8000 {
 799                                 reg = <0x020e8000 0x4000>;
 800                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 801                         };
 802
 803                         sdma: sdma@020ec000 {
 804                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 805                                 reg = <0x020ec000 0x4000>;
 806                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 808                                          <&clks IMX6QDL_CLK_SDMA>;
 809                                 clock-names = "ipg", "ahb";
 810                                 #dma-cells = <3>;
 811                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 812                         };
 813                 };
 814
 815                 aips-bus@02100000 { /* AIPS2 */
 816                         compatible = "fsl,aips-bus", "simple-bus";
 817                         #address-cells = <1>;
 818                         #size-cells = <1>;
 819                         reg = <0x02100000 0x100000>;
 820                         ranges;
 821
 822                         caam@02100000 {
 823                                 reg = <0x02100000 0x40000>;
 824                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 825                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 826                         };
 827
 828                         aipstz@0217c000 { /* AIPSTZ2 */
 829                                 reg = <0x0217c000 0x4000>;
 830                         };
 831
 832                         usbotg: usb@02184000 {
 833                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 834                                 reg = <0x02184000 0x200>;
 835                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 836                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 837                                 fsl,usbphy = <&usbphy1>;
 838                                 fsl,usbmisc = <&usbmisc 0>;
 839                                 status = "disabled";
 840                         };
 841
 842                         usbh1: usb@02184200 {
 843                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 844                                 reg = <0x02184200 0x200>;
 845                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 846                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 847                                 fsl,usbphy = <&usbphy2>;
 848                                 fsl,usbmisc = <&usbmisc 1>;
 849                                 status = "disabled";
 850                         };
 851
 852                         usbh2: usb@02184400 {
 853                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 854                                 reg = <0x02184400 0x200>;
 855                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 856                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 857                                 fsl,usbmisc = <&usbmisc 2>;
 858                                 status = "disabled";
 859                         };
 860
 861                         usbh3: usb@02184600 {
 862                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 863                                 reg = <0x02184600 0x200>;
 864                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 866                                 fsl,usbmisc = <&usbmisc 3>;
 867                                 status = "disabled";
 868                         };
 869
 870                         usbmisc: usbmisc@02184800 {
 871                                 #index-cells = <1>;
 872                                 compatible = "fsl,imx6q-usbmisc";
 873                                 reg = <0x02184800 0x200>;
 874                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 875                         };
 876
 877                         fec: ethernet@02188000 {
 878                                 compatible = "fsl,imx6q-fec";
 879                                 reg = <0x02188000 0x4000>;
 880                                 interrupts-extended =
 881                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 882                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 884                                          <&clks IMX6QDL_CLK_ENET>,
 885                                          <&clks IMX6QDL_CLK_ENET_REF>;
 886                                 clock-names = "ipg", "ahb", "ptp";
 887                                 status = "disabled";
 888                         };
 889
 890                         mlb@0218c000 {
 891                                 reg = <0x0218c000 0x4000>;
 892                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 893                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 894                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 895                         };
 896
 897                         usdhc1: usdhc@02190000 {
 898                                 compatible = "fsl,imx6q-usdhc";
 899                                 reg = <0x02190000 0x4000>;
 900                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 902                                          <&clks IMX6QDL_CLK_USDHC1>,
 903                                          <&clks IMX6QDL_CLK_USDHC1>;
 904                                 clock-names = "ipg", "ahb", "per";
 905                                 bus-width = <4>;
 906                                 status = "disabled";
 907                         };
 908
 909                         usdhc2: usdhc@02194000 {
 910                                 compatible = "fsl,imx6q-usdhc";
 911                                 reg = <0x02194000 0x4000>;
 912                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 913                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 914                                          <&clks IMX6QDL_CLK_USDHC2>,
 915                                          <&clks IMX6QDL_CLK_USDHC2>;
 916                                 clock-names = "ipg", "ahb", "per";
 917                                 bus-width = <4>;
 918                                 status = "disabled";
 919                         };
 920
 921                         usdhc3: usdhc@02198000 {
 922                                 compatible = "fsl,imx6q-usdhc";
 923                                 reg = <0x02198000 0x4000>;
 924                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 925                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 926                                          <&clks IMX6QDL_CLK_USDHC3>,
 927                                          <&clks IMX6QDL_CLK_USDHC3>;
 928                                 clock-names = "ipg", "ahb", "per";
 929                                 bus-width = <4>;
 930                                 status = "disabled";
 931                         };
 932
 933                         usdhc4: usdhc@0219c000 {
 934                                 compatible = "fsl,imx6q-usdhc";
 935                                 reg = <0x0219c000 0x4000>;
 936                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 937                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 938                                          <&clks IMX6QDL_CLK_USDHC4>,
 939                                          <&clks IMX6QDL_CLK_USDHC4>;
 940                                 clock-names = "ipg", "ahb", "per";
 941                                 bus-width = <4>;
 942                                 status = "disabled";
 943                         };
 944
 945                         i2c1: i2c@021a0000 {
 946                                 #address-cells = <1>;
 947                                 #size-cells = <0>;
 948                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 949                                 reg = <0x021a0000 0x4000>;
 950                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 951                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 952                                 status = "disabled";
 953                         };
 954
 955                         i2c2: i2c@021a4000 {
 956                                 #address-cells = <1>;
 957                                 #size-cells = <0>;
 958                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 959                                 reg = <0x021a4000 0x4000>;
 960                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 961                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 962                                 status = "disabled";
 963                         };
 964
 965                         i2c3: i2c@021a8000 {
 966                                 #address-cells = <1>;
 967                                 #size-cells = <0>;
 968                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 969                                 reg = <0x021a8000 0x4000>;
 970                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 971                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 972                                 status = "disabled";
 973                         };
 974
 975                         romcp@021ac000 {
 976                                 reg = <0x021ac000 0x4000>;
 977                         };
 978
 979                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 980                                 compatible = "fsl,imx6q-mmdc";
 981                                 reg = <0x021b0000 0x4000>;
 982                         };
 983
 984                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 985                                 reg = <0x021b4000 0x4000>;
 986                         };
 987
 988                         weim: weim@021b8000 {
 989                                 compatible = "fsl,imx6q-weim";
 990                                 reg = <0x021b8000 0x4000>;
 991                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 992                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
 993                         };
 994
 995                         ocotp: ocotp@021bc000 {
 996                                 compatible = "fsl,imx6q-ocotp", "syscon";
 997                                 reg = <0x021bc000 0x4000>;
 998                         };
 999
1000                         tzasc@021d0000 { /* TZASC1 */
1001                                 reg = <0x021d0000 0x4000>;
1002                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1003                         };
1004
1005                         tzasc@021d4000 { /* TZASC2 */
1006                                 reg = <0x021d4000 0x4000>;
1007                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1008                         };
1009
1010                         audmux: audmux@021d8000 {
1011                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1012                                 reg = <0x021d8000 0x4000>;
1013                                 status = "disabled";
1014                         };
1015
1016                         mipi_csi: mipi@021dc000 {
1017                                 reg = <0x021dc000 0x4000>;
1018                         };
1019
1020                         mipi_dsi: mipi@021e0000 {
1021                                 #address-cells = <1>;
1022                                 #size-cells = <0>;
1023                                 reg = <0x021e0000 0x4000>;
1024                                 status = "disabled";
1025
1026                                 port@0 {
1027                                         reg = <0>;
1028
1029                                         mipi_mux_0: endpoint {
1030                                                 remote-endpoint = <&ipu1_di0_mipi>;
1031                                         };
1032                                 };
1033
1034                                 port@1 {
1035                                         reg = <1>;
1036
1037                                         mipi_mux_1: endpoint {
1038                                                 remote-endpoint = <&ipu1_di1_mipi>;
1039                                         };
1040                                 };
1041                         };
1042
1043                         vdoa@021e4000 {
1044                                 reg = <0x021e4000 0x4000>;
1045                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1046                         };
1047
1048                         uart2: serial@021e8000 {
1049                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1050                                 reg = <0x021e8000 0x4000>;
1051                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1052                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1053                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1054                                 clock-names = "ipg", "per";
1055                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1056                                 dma-names = "rx", "tx";
1057                                 status = "disabled";
1058                         };
1059
1060                         uart3: serial@021ec000 {
1061                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1062                                 reg = <0x021ec000 0x4000>;
1063                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1064                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1065                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1066                                 clock-names = "ipg", "per";
1067                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1068                                 dma-names = "rx", "tx";
1069                                 status = "disabled";
1070                         };
1071
1072                         uart4: serial@021f0000 {
1073                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1074                                 reg = <0x021f0000 0x4000>;
1075                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1076                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1077                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1078                                 clock-names = "ipg", "per";
1079                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1080                                 dma-names = "rx", "tx";
1081                                 status = "disabled";
1082                         };
1083
1084                         uart5: serial@021f4000 {
1085                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1086                                 reg = <0x021f4000 0x4000>;
1087                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1088                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1089                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1090                                 clock-names = "ipg", "per";
1091                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1092                                 dma-names = "rx", "tx";
1093                                 status = "disabled";
1094                         };
1095                 };
1096
1097                 ipu1: ipu@02400000 {
1098                         #address-cells = <1>;
1099                         #size-cells = <0>;
1100                         compatible = "fsl,imx6q-ipu";
1101                         reg = <0x02400000 0x400000>;
1102                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1103                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1104                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1105                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1106                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1107                         clock-names = "bus", "di0", "di1";
1108                         resets = <&src 2>;
1109
1110                         ipu1_csi0: port@0 {
1111                                 reg = <0>;
1112                         };
1113
1114                         ipu1_csi1: port@1 {
1115                                 reg = <1>;
1116                         };
1117
1118                         ipu1_di0: port@2 {
1119                                 #address-cells = <1>;
1120                                 #size-cells = <0>;
1121                                 reg = <2>;
1122
1123                                 ipu1_di0_disp0: endpoint@0 {
1124                                 };
1125
1126                                 ipu1_di0_hdmi: endpoint@1 {
1127                                         remote-endpoint = <&hdmi_mux_0>;
1128                                 };
1129
1130                                 ipu1_di0_mipi: endpoint@2 {
1131                                         remote-endpoint = <&mipi_mux_0>;
1132                                 };
1133
1134                                 ipu1_di0_lvds0: endpoint@3 {
1135                                         remote-endpoint = <&lvds0_mux_0>;
1136                                 };
1137
1138                                 ipu1_di0_lvds1: endpoint@4 {
1139                                         remote-endpoint = <&lvds1_mux_0>;
1140                                 };
1141                         };
1142
1143                         ipu1_di1: port@3 {
1144                                 #address-cells = <1>;
1145                                 #size-cells = <0>;
1146                                 reg = <3>;
1147
1148                                 ipu1_di0_disp1: endpoint@0 {
1149                                 };
1150
1151                                 ipu1_di1_hdmi: endpoint@1 {
1152                                         remote-endpoint = <&hdmi_mux_1>;
1153                                 };
1154
1155                                 ipu1_di1_mipi: endpoint@2 {
1156                                         remote-endpoint = <&mipi_mux_1>;
1157                                 };
1158
1159                                 ipu1_di1_lvds0: endpoint@3 {
1160                                         remote-endpoint = <&lvds0_mux_1>;
1161                                 };
1162
1163                                 ipu1_di1_lvds1: endpoint@4 {
1164                                         remote-endpoint = <&lvds1_mux_1>;
1165                                 };
1166                         };
1167                 };
1168         };
1169 };