arch/arm/boot/dts/hip01.dtsi

   1 /*
   2  * Hisilicon Ltd. HiP01 SoC
   3  *
   4  * Copyright (c) 2014 Hisilicon Ltd.
   5  * Copyright (c) 2014 Huawei Ltd.
   6  *
   7  * Author: Wang Long <long.wanglong@huawei.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         gic: interrupt-controller@1e001000 {
  22                 compatible = "arm,cortex-a9-gic";
  23                 #interrupt-cells = <3>;
  24                 #address-cells = <0>;
  25                 interrupt-controller;
  26                 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
  27         };
  28
  29         hisi_refclk144mhz: refclk144mkhz {
  30                 compatible = "fixed-clock";
  31                 #clock-cells = <0>;
  32                 clock-frequency = <144000000>;
  33                 clock-output-names = "hisi:refclk144khz";
  34         };
  35
  36         soc {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "simple-bus";
  40                 interrupt-parent = <&gic>;
  41                 ranges = <0 0x10000000 0x20000000>;
  42
  43                 amba {
  44                         #address-cells = <1>;
  45                         #size-cells = <1>;
  46                         compatible = "arm,amba-bus";
  47                         ranges;
  48
  49                         uart0: uart@10001000 {
  50                                 compatible = "snps,dw-apb-uart";
  51                                 reg = <0x10001000 0x1000>;
  52                                 clocks = <&hisi_refclk144mhz>;
  53                                 clock-names = "apb_pclk";
  54                                 reg-shift = <2>;
  55                                 interrupts = <0 32 4>;
  56                                 status = "disabled";
  57                         };
  58
  59                         uart1: uart@10002000 {
  60                                 compatible = "snps,dw-apb-uart";
  61                                 reg = <0x10002000 0x1000>;
  62                                 clocks = <&hisi_refclk144mhz>;
  63                                 clock-names = "apb_pclk";
  64                                 reg-shift = <2>;
  65                                 interrupts = <0 33 4>;
  66                                 status = "disabled";
  67                         };
  68
  69                         uart2: uart@10003000 {
  70                                 compatible = "snps,dw-apb-uart";
  71                                 reg = <0x10003000 0x1000>;
  72                                 clocks = <&hisi_refclk144mhz>;
  73                                 clock-names = "apb_pclk";
  74                                 reg-shift = <2>;
  75                                 interrupts = <0 34 4>;
  76                                 status = "disabled";
  77                         };
  78
  79                         uart3: uart@10006000 {
  80                                 compatible = "snps,dw-apb-uart";
  81                                 reg = <0x10006000 0x1000>;
  82                                 clocks = <&hisi_refclk144mhz>;
  83                                 clock-names = "apb_pclk";
  84                                 reg-shift = <2>;
  85                                 interrupts = <0 4 4>;
  86                                 status = "disabled";
  87                         };
  88                 };
  89
  90                 system-controller@10000000 {
  91                         compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
  92                         reg = <0x10000000 0x1000>;
  93                         reboot-offset = <0x4>;
  94                 };
  95
  96                 global_timer@0a000200 {
  97                         compatible = "arm,cortex-a9-global-timer";
  98                         reg = <0x0a000200 0x100>;
  99                         interrupts = <1 11 0xf04>;
 100                         clocks = <&hisi_refclk144mhz>;
 101                 };
 102
 103                 local_timer@0a000600 {
 104                         compatible = "arm,cortex-a9-twd-timer";
 105                         reg = <0x0a000600 0x100>;
 106                         interrupts = <1 13 0xf04>;
 107                         clocks = <&hisi_refclk144mhz>;
 108                 };
 109         };
 110 };