arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include "skeleton.dtsi"
  25
  26 / {
  27         interrupt-parent = <&gic>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 csis0 = &csis_0;
  42                 csis1 = &csis_1;
  43                 fimc0 = &fimc_0;
  44                 fimc1 = &fimc_1;
  45                 fimc2 = &fimc_2;
  46                 fimc3 = &fimc_3;
  47                 serial0 = &serial_0;
  48                 serial1 = &serial_1;
  49                 serial2 = &serial_2;
  50                 serial3 = &serial_3;
  51         };
  52
  53         clock_audss: clock-controller@03810000 {
  54                 compatible = "samsung,exynos4210-audss-clock";
  55                 reg = <0x03810000 0x0C>;
  56                 #clock-cells = <1>;
  57         };
  58
  59         i2s0: i2s@03830000 {
  60                 compatible = "samsung,s5pv210-i2s";
  61                 reg = <0x03830000 0x100>;
  62                 clocks = <&clock_audss EXYNOS_I2S_BUS>;
  63                 clock-names = "iis";
  64                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  65                 dma-names = "tx", "rx", "tx-sec";
  66                 samsung,idma-addr = <0x03000000>;
  67                 status = "disabled";
  68         };
  69
  70         chipid@10000000 {
  71                 compatible = "samsung,exynos4210-chipid";
  72                 reg = <0x10000000 0x100>;
  73         };
  74
  75         mipi_phy: video-phy@10020710 {
  76                 compatible = "samsung,s5pv210-mipi-video-phy";
  77                 reg = <0x10020710 8>;
  78                 #phy-cells = <1>;
  79         };
  80
  81         pd_mfc: mfc-power-domain@10023C40 {
  82                 compatible = "samsung,exynos4210-pd";
  83                 reg = <0x10023C40 0x20>;
  84                 #power-domain-cells = <0>;
  85         };
  86
  87         pd_g3d: g3d-power-domain@10023C60 {
  88                 compatible = "samsung,exynos4210-pd";
  89                 reg = <0x10023C60 0x20>;
  90                 #power-domain-cells = <0>;
  91         };
  92
  93         pd_lcd0: lcd0-power-domain@10023C80 {
  94                 compatible = "samsung,exynos4210-pd";
  95                 reg = <0x10023C80 0x20>;
  96                 #power-domain-cells = <0>;
  97         };
  98
  99         pd_tv: tv-power-domain@10023C20 {
 100                 compatible = "samsung,exynos4210-pd";
 101                 reg = <0x10023C20 0x20>;
 102                 #power-domain-cells = <0>;
 103         };
 104
 105         pd_cam: cam-power-domain@10023C00 {
 106                 compatible = "samsung,exynos4210-pd";
 107                 reg = <0x10023C00 0x20>;
 108                 #power-domain-cells = <0>;
 109         };
 110
 111         pd_gps: gps-power-domain@10023CE0 {
 112                 compatible = "samsung,exynos4210-pd";
 113                 reg = <0x10023CE0 0x20>;
 114                 #power-domain-cells = <0>;
 115         };
 116
 117         pd_gps_alive: gps-alive-power-domain@10023D00 {
 118                 compatible = "samsung,exynos4210-pd";
 119                 reg = <0x10023D00 0x20>;
 120                 #power-domain-cells = <0>;
 121         };
 122
 123         gic: interrupt-controller@10490000 {
 124                 compatible = "arm,cortex-a9-gic";
 125                 #interrupt-cells = <3>;
 126                 interrupt-controller;
 127                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 128         };
 129
 130         combiner: interrupt-controller@10440000 {
 131                 compatible = "samsung,exynos4210-combiner";
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134                 reg = <0x10440000 0x1000>;
 135         };
 136
 137         pmu {
 138                 compatible = "arm,cortex-a9-pmu";
 139                 interrupt-parent = <&combiner>;
 140                 interrupts = <2 2>, <3 2>;
 141         };
 142
 143         sys_reg: syscon@10010000 {
 144                 compatible = "samsung,exynos4-sysreg", "syscon";
 145                 reg = <0x10010000 0x400>;
 146         };
 147
 148         pmu_system_controller: system-controller@10020000 {
 149                 compatible = "samsung,exynos4210-pmu", "syscon";
 150                 reg = <0x10020000 0x4000>;
 151         };
 152
 153         dsi_0: dsi@11C80000 {
 154                 compatible = "samsung,exynos4210-mipi-dsi";
 155                 reg = <0x11C80000 0x10000>;
 156                 interrupts = <0 79 0>;
 157                 power-domains = <&pd_lcd0>;
 158                 phys = <&mipi_phy 1>;
 159                 phy-names = "dsim";
 160                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 161                 clock-names = "bus_clk", "pll_clk";
 162                 status = "disabled";
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165         };
 166
 167         camera {
 168                 compatible = "samsung,fimc", "simple-bus";
 169                 status = "disabled";
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 #clock-cells = <1>;
 173                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 174                 ranges;
 175
 176                 fimc_0: fimc@11800000 {
 177                         compatible = "samsung,exynos4210-fimc";
 178                         reg = <0x11800000 0x1000>;
 179                         interrupts = <0 84 0>;
 180                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 181                         clock-names = "fimc", "sclk_fimc";
 182                         power-domains = <&pd_cam>;
 183                         samsung,sysreg = <&sys_reg>;
 184                         status = "disabled";
 185                 };
 186
 187                 fimc_1: fimc@11810000 {
 188                         compatible = "samsung,exynos4210-fimc";
 189                         reg = <0x11810000 0x1000>;
 190                         interrupts = <0 85 0>;
 191                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 192                         clock-names = "fimc", "sclk_fimc";
 193                         power-domains = <&pd_cam>;
 194                         samsung,sysreg = <&sys_reg>;
 195                         status = "disabled";
 196                 };
 197
 198                 fimc_2: fimc@11820000 {
 199                         compatible = "samsung,exynos4210-fimc";
 200                         reg = <0x11820000 0x1000>;
 201                         interrupts = <0 86 0>;
 202                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 203                         clock-names = "fimc", "sclk_fimc";
 204                         power-domains = <&pd_cam>;
 205                         samsung,sysreg = <&sys_reg>;
 206                         status = "disabled";
 207                 };
 208
 209                 fimc_3: fimc@11830000 {
 210                         compatible = "samsung,exynos4210-fimc";
 211                         reg = <0x11830000 0x1000>;
 212                         interrupts = <0 87 0>;
 213                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 214                         clock-names = "fimc", "sclk_fimc";
 215                         power-domains = <&pd_cam>;
 216                         samsung,sysreg = <&sys_reg>;
 217                         status = "disabled";
 218                 };
 219
 220                 csis_0: csis@11880000 {
 221                         compatible = "samsung,exynos4210-csis";
 222                         reg = <0x11880000 0x4000>;
 223                         interrupts = <0 78 0>;
 224                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 225                         clock-names = "csis", "sclk_csis";
 226                         bus-width = <4>;
 227                         power-domains = <&pd_cam>;
 228                         phys = <&mipi_phy 0>;
 229                         phy-names = "csis";
 230                         status = "disabled";
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                 };
 234
 235                 csis_1: csis@11890000 {
 236                         compatible = "samsung,exynos4210-csis";
 237                         reg = <0x11890000 0x4000>;
 238                         interrupts = <0 80 0>;
 239                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 240                         clock-names = "csis", "sclk_csis";
 241                         bus-width = <2>;
 242                         power-domains = <&pd_cam>;
 243                         phys = <&mipi_phy 2>;
 244                         phy-names = "csis";
 245                         status = "disabled";
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                 };
 249         };
 250
 251         watchdog@10060000 {
 252                 compatible = "samsung,s3c2410-wdt";
 253                 reg = <0x10060000 0x100>;
 254                 interrupts = <0 43 0>;
 255                 clocks = <&clock CLK_WDT>;
 256                 clock-names = "watchdog";
 257                 status = "disabled";
 258         };
 259
 260         rtc@10070000 {
 261                 compatible = "samsung,s3c6410-rtc";
 262                 reg = <0x10070000 0x100>;
 263                 interrupts = <0 44 0>, <0 45 0>;
 264                 clocks = <&clock CLK_RTC>;
 265                 clock-names = "rtc";
 266                 status = "disabled";
 267         };
 268
 269         keypad@100A0000 {
 270                 compatible = "samsung,s5pv210-keypad";
 271                 reg = <0x100A0000 0x100>;
 272                 interrupts = <0 109 0>;
 273                 clocks = <&clock CLK_KEYIF>;
 274                 clock-names = "keypad";
 275                 status = "disabled";
 276         };
 277
 278         sdhci@12510000 {
 279                 compatible = "samsung,exynos4210-sdhci";
 280                 reg = <0x12510000 0x100>;
 281                 interrupts = <0 73 0>;
 282                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 283                 clock-names = "hsmmc", "mmc_busclk.2";
 284                 status = "disabled";
 285         };
 286
 287         sdhci@12520000 {
 288                 compatible = "samsung,exynos4210-sdhci";
 289                 reg = <0x12520000 0x100>;
 290                 interrupts = <0 74 0>;
 291                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 292                 clock-names = "hsmmc", "mmc_busclk.2";
 293                 status = "disabled";
 294         };
 295
 296         sdhci@12530000 {
 297                 compatible = "samsung,exynos4210-sdhci";
 298                 reg = <0x12530000 0x100>;
 299                 interrupts = <0 75 0>;
 300                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 301                 clock-names = "hsmmc", "mmc_busclk.2";
 302                 status = "disabled";
 303         };
 304
 305         sdhci@12540000 {
 306                 compatible = "samsung,exynos4210-sdhci";
 307                 reg = <0x12540000 0x100>;
 308                 interrupts = <0 76 0>;
 309                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 310                 clock-names = "hsmmc", "mmc_busclk.2";
 311                 status = "disabled";
 312         };
 313
 314         exynos_usbphy: exynos-usbphy@125B0000 {
 315                 compatible = "samsung,exynos4210-usb2-phy";
 316                 reg = <0x125B0000 0x100>;
 317                 samsung,pmureg-phandle = <&pmu_system_controller>;
 318                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 319                 clock-names = "phy", "ref";
 320                 #phy-cells = <1>;
 321                 status = "disabled";
 322         };
 323
 324         hsotg@12480000 {
 325                 compatible = "samsung,s3c6400-hsotg";
 326                 reg = <0x12480000 0x20000>;
 327                 interrupts = <0 71 0>;
 328                 clocks = <&clock CLK_USB_DEVICE>;
 329                 clock-names = "otg";
 330                 phys = <&exynos_usbphy 0>;
 331                 phy-names = "usb2-phy";
 332                 status = "disabled";
 333         };
 334
 335         ehci@12580000 {
 336                 compatible = "samsung,exynos4210-ehci";
 337                 reg = <0x12580000 0x100>;
 338                 interrupts = <0 70 0>;
 339                 clocks = <&clock CLK_USB_HOST>;
 340                 clock-names = "usbhost";
 341                 status = "disabled";
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 port@0 {
 345                     reg = <0>;
 346                     phys = <&exynos_usbphy 1>;
 347                     status = "disabled";
 348                 };
 349                 port@1 {
 350                     reg = <1>;
 351                     phys = <&exynos_usbphy 2>;
 352                     status = "disabled";
 353                 };
 354                 port@2 {
 355                     reg = <2>;
 356                     phys = <&exynos_usbphy 3>;
 357                     status = "disabled";
 358                 };
 359         };
 360
 361         ohci@12590000 {
 362                 compatible = "samsung,exynos4210-ohci";
 363                 reg = <0x12590000 0x100>;
 364                 interrupts = <0 70 0>;
 365                 clocks = <&clock CLK_USB_HOST>;
 366                 clock-names = "usbhost";
 367                 status = "disabled";
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 port@0 {
 371                     reg = <0>;
 372                     phys = <&exynos_usbphy 1>;
 373                     status = "disabled";
 374                 };
 375         };
 376
 377         i2s1: i2s@13960000 {
 378                 compatible = "samsung,s5pv210-i2s";
 379                 reg = <0x13960000 0x100>;
 380                 clocks = <&clock CLK_I2S1>;
 381                 clock-names = "iis";
 382                 dmas = <&pdma1 12>, <&pdma1 11>;
 383                 dma-names = "tx", "rx";
 384                 status = "disabled";
 385         };
 386
 387         i2s2: i2s@13970000 {
 388                 compatible = "samsung,s5pv210-i2s";
 389                 reg = <0x13970000 0x100>;
 390                 clocks = <&clock CLK_I2S2>;
 391                 clock-names = "iis";
 392                 dmas = <&pdma0 14>, <&pdma0 13>;
 393                 dma-names = "tx", "rx";
 394                 status = "disabled";
 395         };
 396
 397         mfc: codec@13400000 {
 398                 compatible = "samsung,mfc-v5";
 399                 reg = <0x13400000 0x10000>;
 400                 interrupts = <0 94 0>;
 401                 power-domains = <&pd_mfc>;
 402                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 403                 clock-names = "mfc", "sclk_mfc";
 404                 status = "disabled";
 405         };
 406
 407         serial_0: serial@13800000 {
 408                 compatible = "samsung,exynos4210-uart";
 409                 reg = <0x13800000 0x100>;
 410                 interrupts = <0 52 0>;
 411                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 412                 clock-names = "uart", "clk_uart_baud0";
 413                 status = "disabled";
 414         };
 415
 416         serial_1: serial@13810000 {
 417                 compatible = "samsung,exynos4210-uart";
 418                 reg = <0x13810000 0x100>;
 419                 interrupts = <0 53 0>;
 420                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 421                 clock-names = "uart", "clk_uart_baud0";
 422                 status = "disabled";
 423         };
 424
 425         serial_2: serial@13820000 {
 426                 compatible = "samsung,exynos4210-uart";
 427                 reg = <0x13820000 0x100>;
 428                 interrupts = <0 54 0>;
 429                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 430                 clock-names = "uart", "clk_uart_baud0";
 431                 status = "disabled";
 432         };
 433
 434         serial_3: serial@13830000 {
 435                 compatible = "samsung,exynos4210-uart";
 436                 reg = <0x13830000 0x100>;
 437                 interrupts = <0 55 0>;
 438                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 439                 clock-names = "uart", "clk_uart_baud0";
 440                 status = "disabled";
 441         };
 442
 443         i2c_0: i2c@13860000 {
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 compatible = "samsung,s3c2440-i2c";
 447                 reg = <0x13860000 0x100>;
 448                 interrupts = <0 58 0>;
 449                 clocks = <&clock CLK_I2C0>;
 450                 clock-names = "i2c";
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&i2c0_bus>;
 453                 status = "disabled";
 454         };
 455
 456         i2c_1: i2c@13870000 {
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 compatible = "samsung,s3c2440-i2c";
 460                 reg = <0x13870000 0x100>;
 461                 interrupts = <0 59 0>;
 462                 clocks = <&clock CLK_I2C1>;
 463                 clock-names = "i2c";
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&i2c1_bus>;
 466                 status = "disabled";
 467         };
 468
 469         i2c_2: i2c@13880000 {
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 compatible = "samsung,s3c2440-i2c";
 473                 reg = <0x13880000 0x100>;
 474                 interrupts = <0 60 0>;
 475                 clocks = <&clock CLK_I2C2>;
 476                 clock-names = "i2c";
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&i2c2_bus>;
 479                 status = "disabled";
 480         };
 481
 482         i2c_3: i2c@13890000 {
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 compatible = "samsung,s3c2440-i2c";
 486                 reg = <0x13890000 0x100>;
 487                 interrupts = <0 61 0>;
 488                 clocks = <&clock CLK_I2C3>;
 489                 clock-names = "i2c";
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c3_bus>;
 492                 status = "disabled";
 493         };
 494
 495         i2c_4: i2c@138A0000 {
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 compatible = "samsung,s3c2440-i2c";
 499                 reg = <0x138A0000 0x100>;
 500                 interrupts = <0 62 0>;
 501                 clocks = <&clock CLK_I2C4>;
 502                 clock-names = "i2c";
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c4_bus>;
 505                 status = "disabled";
 506         };
 507
 508         i2c_5: i2c@138B0000 {
 509                 #address-cells = <1>;
 510                 #size-cells = <0>;
 511                 compatible = "samsung,s3c2440-i2c";
 512                 reg = <0x138B0000 0x100>;
 513                 interrupts = <0 63 0>;
 514                 clocks = <&clock CLK_I2C5>;
 515                 clock-names = "i2c";
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&i2c5_bus>;
 518                 status = "disabled";
 519         };
 520
 521         i2c_6: i2c@138C0000 {
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 compatible = "samsung,s3c2440-i2c";
 525                 reg = <0x138C0000 0x100>;
 526                 interrupts = <0 64 0>;
 527                 clocks = <&clock CLK_I2C6>;
 528                 clock-names = "i2c";
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2c6_bus>;
 531                 status = "disabled";
 532         };
 533
 534         i2c_7: i2c@138D0000 {
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 compatible = "samsung,s3c2440-i2c";
 538                 reg = <0x138D0000 0x100>;
 539                 interrupts = <0 65 0>;
 540                 clocks = <&clock CLK_I2C7>;
 541                 clock-names = "i2c";
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&i2c7_bus>;
 544                 status = "disabled";
 545         };
 546
 547         spi_0: spi@13920000 {
 548                 compatible = "samsung,exynos4210-spi";
 549                 reg = <0x13920000 0x100>;
 550                 interrupts = <0 66 0>;
 551                 dmas = <&pdma0 7>, <&pdma0 6>;
 552                 dma-names = "tx", "rx";
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 556                 clock-names = "spi", "spi_busclk0";
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&spi0_bus>;
 559                 status = "disabled";
 560         };
 561
 562         spi_1: spi@13930000 {
 563                 compatible = "samsung,exynos4210-spi";
 564                 reg = <0x13930000 0x100>;
 565                 interrupts = <0 67 0>;
 566                 dmas = <&pdma1 7>, <&pdma1 6>;
 567                 dma-names = "tx", "rx";
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 571                 clock-names = "spi", "spi_busclk0";
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&spi1_bus>;
 574                 status = "disabled";
 575         };
 576
 577         spi_2: spi@13940000 {
 578                 compatible = "samsung,exynos4210-spi";
 579                 reg = <0x13940000 0x100>;
 580                 interrupts = <0 68 0>;
 581                 dmas = <&pdma0 9>, <&pdma0 8>;
 582                 dma-names = "tx", "rx";
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 586                 clock-names = "spi", "spi_busclk0";
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&spi2_bus>;
 589                 status = "disabled";
 590         };
 591
 592         pwm@139D0000 {
 593                 compatible = "samsung,exynos4210-pwm";
 594                 reg = <0x139D0000 0x1000>;
 595                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
 596                 clocks = <&clock CLK_PWM>;
 597                 clock-names = "timers";
 598                 #pwm-cells = <3>;
 599                 status = "disabled";
 600         };
 601
 602         amba {
 603                 #address-cells = <1>;
 604                 #size-cells = <1>;
 605                 compatible = "arm,amba-bus";
 606                 interrupt-parent = <&gic>;
 607                 ranges;
 608
 609                 pdma0: pdma@12680000 {
 610                         compatible = "arm,pl330", "arm,primecell";
 611                         reg = <0x12680000 0x1000>;
 612                         interrupts = <0 35 0>;
 613                         clocks = <&clock CLK_PDMA0>;
 614                         clock-names = "apb_pclk";
 615                         #dma-cells = <1>;
 616                         #dma-channels = <8>;
 617                         #dma-requests = <32>;
 618                 };
 619
 620                 pdma1: pdma@12690000 {
 621                         compatible = "arm,pl330", "arm,primecell";
 622                         reg = <0x12690000 0x1000>;
 623                         interrupts = <0 36 0>;
 624                         clocks = <&clock CLK_PDMA1>;
 625                         clock-names = "apb_pclk";
 626                         #dma-cells = <1>;
 627                         #dma-channels = <8>;
 628                         #dma-requests = <32>;
 629                 };
 630
 631                 mdma1: mdma@12850000 {
 632                         compatible = "arm,pl330", "arm,primecell";
 633                         reg = <0x12850000 0x1000>;
 634                         interrupts = <0 34 0>;
 635                         clocks = <&clock CLK_MDMA>;
 636                         clock-names = "apb_pclk";
 637                         #dma-cells = <1>;
 638                         #dma-channels = <8>;
 639                         #dma-requests = <1>;
 640                 };
 641         };
 642
 643         fimd: fimd@11c00000 {
 644                 compatible = "samsung,exynos4210-fimd";
 645                 interrupt-parent = <&combiner>;
 646                 reg = <0x11c00000 0x20000>;
 647                 interrupt-names = "fifo", "vsync", "lcd_sys";
 648                 interrupts = <11 0>, <11 1>, <11 2>;
 649                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 650                 clock-names = "sclk_fimd", "fimd";
 651                 power-domains = <&pd_lcd0>;
 652                 samsung,sysreg = <&sys_reg>;
 653                 status = "disabled";
 654         };
 655 };