arch/arm/boot/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA722";
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  20         };
  21
  22         aliases {
  23                 display0 = &hdmi0;
  24         };
  25
  26         evm_3v3: fixedregulator-evm_3v3 {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "evm_3v3";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31         };
  32
  33         aic_dvdd: fixedregulator-aic_dvdd {
  34                 /* TPS77018DBVT */
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "aic_dvdd";
  37                 vin-supply = <&evm_3v3>;
  38                 regulator-min-microvolt = <1800000>;
  39                 regulator-max-microvolt = <1800000>;
  40         };
  41
  42         evm_3v3_sd: fixedregulator-sd {
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "evm_3v3_sd";
  45                 regulator-min-microvolt = <3300000>;
  46                 regulator-max-microvolt = <3300000>;
  47                 enable-active-high;
  48                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  49         };
  50
  51         extcon_usb1: extcon_usb1 {
  52                 compatible = "linux,extcon-usb-gpio";
  53                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  54         };
  55
  56         extcon_usb2: extcon_usb2 {
  57                 compatible = "linux,extcon-usb-gpio";
  58                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  59         };
  60
  61         hdmi0: connector {
  62                 compatible = "hdmi-connector";
  63                 label = "hdmi";
  64
  65                 type = "a";
  66
  67                 port {
  68                         hdmi_connector_in: endpoint {
  69                                 remote-endpoint = <&tpd12s015_out>;
  70                         };
  71                 };
  72         };
  73
  74         tpd12s015: encoder {
  75                 compatible = "ti,tpd12s015";
  76
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&tpd12s015_pins>;
  79
  80                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
  81                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
  82                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
  83
  84                 ports {
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87
  88                         port@0 {
  89                                 reg = <0>;
  90
  91                                 tpd12s015_in: endpoint {
  92                                         remote-endpoint = <&hdmi_out>;
  93                                 };
  94                         };
  95
  96                         port@1 {
  97                                 reg = <1>;
  98
  99                                 tpd12s015_out: endpoint {
 100                                         remote-endpoint = <&hdmi_connector_in>;
 101                                 };
 102                         };
 103                 };
 104         };
 105 };
 106
 107 &dra7_pmx_core {
 108         i2c1_pins: pinmux_i2c1_pins {
 109                 pinctrl-single,pins = <
 110                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
 111                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 112                 >;
 113         };
 114
 115         i2c5_pins: pinmux_i2c5_pins {
 116                 pinctrl-single,pins = <
 117                         0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
 118                         0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
 119                 >;
 120         };
 121
 122         nand_default: nand_default {
 123                 pinctrl-single,pins = <
 124                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
 125                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
 126                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
 127                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
 128                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
 129                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
 130                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
 131                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
 132                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
 133                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
 134                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
 135                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
 136                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
 137                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
 138                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
 139                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
 140                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
 141                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
 142                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
 143                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
 144                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
 145                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
 146                 >;
 147         };
 148
 149         usb1_pins: pinmux_usb1_pins {
 150                 pinctrl-single,pins = <
 151                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 152                 >;
 153         };
 154
 155         usb2_pins: pinmux_usb2_pins {
 156                 pinctrl-single,pins = <
 157                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 158                 >;
 159         };
 160
 161         tps65917_pins_default: tps65917_pins_default {
 162                 pinctrl-single,pins = <
 163                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
 164                 >;
 165         };
 166
 167         mmc1_pins_default: mmc1_pins_default {
 168                 pinctrl-single,pins = <
 169                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
 170                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 171                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 172                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 173                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 174                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 175                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 176                 >;
 177         };
 178
 179         mmc2_pins_default: mmc2_pins_default {
 180                 pinctrl-single,pins = <
 181                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 182                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 183                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 184                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 185                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 186                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 187                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 188                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 189                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 190                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 191                 >;
 192         };
 193
 194         dcan1_pins_default: dcan1_pins_default {
 195                 pinctrl-single,pins = <
 196                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 197                         0x418   (PULL_UP | MUX_MODE1)   /* wakeup0.dcan1_rx */
 198                 >;
 199         };
 200
 201         dcan1_pins_sleep: dcan1_pins_sleep {
 202                 pinctrl-single,pins = <
 203                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 204                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 205                 >;
 206         };
 207
 208         qspi1_pins: pinmux_qspi1_pins {
 209                 pinctrl-single,pins = <
 210                         0x74 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_a13.qspi1_rtclk */
 211                         0x78 (PIN_INPUT | MUX_MODE1)    /* gpmc_a14.qspi1_d3 */
 212                         0x7c (PIN_INPUT | MUX_MODE1)    /* gpmc_a15.qspi1_d2 */
 213                         0x80 (PIN_INPUT | MUX_MODE1)    /* gpmc_a16.qspi1_d1 */
 214                         0x84 (PIN_INPUT | MUX_MODE1)    /* gpmc_a17.qspi1_d0 */
 215                         0x88 (PIN_OUTPUT | MUX_MODE1)   /* qpmc_a18.qspi1_sclk */
 216                         0xb8 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_cs2.qspi1_cs0 */
 217                 >;
 218         };
 219
 220         hdmi_pins: pinmux_hdmi_pins {
 221                 pinctrl-single,pins = <
 222                         0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
 223                         0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
 224                 >;
 225         };
 226
 227         tpd12s015_pins: pinmux_tpd12s015_pins {
 228                 pinctrl-single,pins = <
 229                         0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
 230                 >;
 231         };
 232 };
 233
 234 &i2c1 {
 235         status = "okay";
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&i2c1_pins>;
 238         clock-frequency = <400000>;
 239
 240         tps65917: tps65917@58 {
 241                 compatible = "ti,tps65917";
 242                 reg = <0x58>;
 243
 244                 pinctrl-names = "default";
 245                 pinctrl-0 = <&tps65917_pins_default>;
 246
 247                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 248                 interrupt-controller;
 249                 #interrupt-cells = <2>;
 250
 251                 ti,system-power-controller;
 252
 253                 tps65917_pmic {
 254                         compatible = "ti,tps65917-pmic";
 255
 256                         regulators {
 257                                 smps1_reg: smps1 {
 258                                         /* VDD_MPU */
 259                                         regulator-name = "smps1";
 260                                         regulator-min-microvolt = <850000>;
 261                                         regulator-max-microvolt = <1250000>;
 262                                         regulator-always-on;
 263                                         regulator-boot-on;
 264                                 };
 265
 266                                 smps2_reg: smps2 {
 267                                         /* VDD_CORE */
 268                                         regulator-name = "smps2";
 269                                         regulator-min-microvolt = <850000>;
 270                                         regulator-max-microvolt = <1060000>;
 271                                         regulator-boot-on;
 272                                         regulator-always-on;
 273                                 };
 274
 275                                 smps3_reg: smps3 {
 276                                         /* VDD_GPU IVA DSPEVE */
 277                                         regulator-name = "smps3";
 278                                         regulator-min-microvolt = <850000>;
 279                                         regulator-max-microvolt = <1250000>;
 280                                         regulator-boot-on;
 281                                         regulator-always-on;
 282                                 };
 283
 284                                 smps4_reg: smps4 {
 285                                         /* VDDS1V8 */
 286                                         regulator-name = "smps4";
 287                                         regulator-min-microvolt = <1800000>;
 288                                         regulator-max-microvolt = <1800000>;
 289                                         regulator-always-on;
 290                                         regulator-boot-on;
 291                                 };
 292
 293                                 smps5_reg: smps5 {
 294                                         /* VDD_DDR */
 295                                         regulator-name = "smps5";
 296                                         regulator-min-microvolt = <1350000>;
 297                                         regulator-max-microvolt = <1350000>;
 298                                         regulator-boot-on;
 299                                         regulator-always-on;
 300                                 };
 301
 302                                 ldo1_reg: ldo1 {
 303                                         /* LDO1_OUT --> SDIO  */
 304                                         regulator-name = "ldo1";
 305                                         regulator-min-microvolt = <1800000>;
 306                                         regulator-max-microvolt = <3300000>;
 307                                         regulator-always-on;
 308                                         regulator-boot-on;
 309                                 };
 310
 311                                 ldo2_reg: ldo2 {
 312                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 313                                         regulator-name = "ldo2";
 314                                         regulator-min-microvolt = <1800000>;
 315                                         regulator-max-microvolt = <3300000>;
 316                                 };
 317
 318                                 ldo3_reg: ldo3 {
 319                                         /* VDDA_1V8_PHY */
 320                                         regulator-name = "ldo3";
 321                                         regulator-min-microvolt = <1800000>;
 322                                         regulator-max-microvolt = <1800000>;
 323                                         regulator-boot-on;
 324                                         regulator-always-on;
 325                                 };
 326
 327                                 ldo5_reg: ldo5 {
 328                                         /* VDDA_1V8_PLL */
 329                                         regulator-name = "ldo5";
 330                                         regulator-min-microvolt = <1800000>;
 331                                         regulator-max-microvolt = <1800000>;
 332                                         regulator-always-on;
 333                                         regulator-boot-on;
 334                                 };
 335
 336                                 ldo4_reg: ldo4 {
 337                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 338                                         regulator-name = "ldo4";
 339                                         regulator-min-microvolt = <3300000>;
 340                                         regulator-max-microvolt = <3300000>;
 341                                         regulator-boot-on;
 342                                 };
 343                         };
 344                 };
 345
 346                 tps65917_power_button {
 347                         compatible = "ti,palmas-pwrbutton";
 348                         interrupt-parent = <&tps65917>;
 349                         interrupts = <1 IRQ_TYPE_NONE>;
 350                         wakeup-source;
 351                         ti,palmas-long-press-seconds = <6>;
 352                 };
 353         };
 354
 355         pcf_gpio_21: gpio@21 {
 356                 compatible = "ti,pcf8575";
 357                 reg = <0x21>;
 358                 lines-initial-states = <0x1408>;
 359                 gpio-controller;
 360                 #gpio-cells = <2>;
 361                 interrupt-parent = <&gpio6>;
 362                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 363                 interrupt-controller;
 364                 #interrupt-cells = <2>;
 365
 366                 cpsw_sel_s0 {
 367                         gpio-hog;
 368                         gpios = <4 GPIO_ACTIVE_HIGH>;
 369                         output-low;
 370                 };
 371         };
 372 };
 373
 374 &i2c5 {
 375         status = "okay";
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&i2c5_pins>;
 378         clock-frequency = <400000>;
 379
 380         pcf_hdmi: pcf8575@26 {
 381                 compatible = "nxp,pcf8575";
 382                 reg = <0x26>;
 383                 gpio-controller;
 384                 #gpio-cells = <2>;
 385                 /*
 386                  * initial state is used here to keep the mdio interface
 387                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 388                  * VIN2_S0 driven high otherwise Ethernet stops working
 389                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 390                  */
 391                 lines-initial-states = <0x0f2b>;
 392         };
 393 };
 394
 395 &uart1 {
 396         status = "okay";
 397 };
 398
 399 &elm {
 400         status = "okay";
 401 };
 402
 403 &gpmc {
 404         status = "okay";
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&nand_default>;
 407         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 408         nand@0,0 {
 409                 /* To use NAND, DIP switch SW5 must be set like so:
 410                  * SW5.1 (NAND_SELn) = ON (LOW)
 411                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 412                  */
 413                 reg = <0 0 4>;          /* device IO registers */
 414                 ti,nand-ecc-opt = "bch8";
 415                 ti,elm-id = <&elm>;
 416                 nand-bus-width = <16>;
 417                 gpmc,device-width = <2>;
 418                 gpmc,sync-clk-ps = <0>;
 419                 gpmc,cs-on-ns = <0>;
 420                 gpmc,cs-rd-off-ns = <80>;
 421                 gpmc,cs-wr-off-ns = <80>;
 422                 gpmc,adv-on-ns = <0>;
 423                 gpmc,adv-rd-off-ns = <60>;
 424                 gpmc,adv-wr-off-ns = <60>;
 425                 gpmc,we-on-ns = <10>;
 426                 gpmc,we-off-ns = <50>;
 427                 gpmc,oe-on-ns = <4>;
 428                 gpmc,oe-off-ns = <40>;
 429                 gpmc,access-ns = <40>;
 430                 gpmc,wr-access-ns = <80>;
 431                 gpmc,rd-cycle-ns = <80>;
 432                 gpmc,wr-cycle-ns = <80>;
 433                 gpmc,bus-turnaround-ns = <0>;
 434                 gpmc,cycle2cycle-delay-ns = <0>;
 435                 gpmc,clk-activation-ns = <0>;
 436                 gpmc,wait-monitoring-ns = <0>;
 437                 gpmc,wr-data-mux-bus-ns = <0>;
 438                 /* MTD partition table */
 439                 /* All SPL-* partitions are sized to minimal length
 440                  * which can be independently programmable. For
 441                  * NAND flash this is equal to size of erase-block */
 442                 #address-cells = <1>;
 443                 #size-cells = <1>;
 444                 partition@0 {
 445                         label = "NAND.SPL";
 446                         reg = <0x00000000 0x000020000>;
 447                 };
 448                 partition@1 {
 449                         label = "NAND.SPL.backup1";
 450                         reg = <0x00020000 0x00020000>;
 451                 };
 452                 partition@2 {
 453                         label = "NAND.SPL.backup2";
 454                         reg = <0x00040000 0x00020000>;
 455                 };
 456                 partition@3 {
 457                         label = "NAND.SPL.backup3";
 458                         reg = <0x00060000 0x00020000>;
 459                 };
 460                 partition@4 {
 461                         label = "NAND.u-boot-spl-os";
 462                         reg = <0x00080000 0x00040000>;
 463                 };
 464                 partition@5 {
 465                         label = "NAND.u-boot";
 466                         reg = <0x000c0000 0x00100000>;
 467                 };
 468                 partition@6 {
 469                         label = "NAND.u-boot-env";
 470                         reg = <0x001c0000 0x00020000>;
 471                 };
 472                 partition@7 {
 473                         label = "NAND.u-boot-env.backup1";
 474                         reg = <0x001e0000 0x00020000>;
 475                 };
 476                 partition@8 {
 477                         label = "NAND.kernel";
 478                         reg = <0x00200000 0x00800000>;
 479                 };
 480                 partition@9 {
 481                         label = "NAND.file-system";
 482                         reg = <0x00a00000 0x0f600000>;
 483                 };
 484         };
 485 };
 486
 487 &usb2_phy1 {
 488         phy-supply = <&ldo4_reg>;
 489 };
 490
 491 &usb2_phy2 {
 492         phy-supply = <&ldo4_reg>;
 493 };
 494
 495 &omap_dwc3_1 {
 496         extcon = <&extcon_usb1>;
 497 };
 498
 499 &omap_dwc3_2 {
 500         extcon = <&extcon_usb2>;
 501 };
 502
 503 &usb1 {
 504         dr_mode = "peripheral";
 505         pinctrl-names = "default";
 506         pinctrl-0 = <&usb1_pins>;
 507 };
 508
 509 &usb2 {
 510         dr_mode = "host";
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&usb2_pins>;
 513 };
 514
 515 &mmc1 {
 516         status = "okay";
 517         pinctrl-names = "default";
 518         pinctrl-0 = <&mmc1_pins_default>;
 519         vmmc-supply = <&evm_3v3_sd>;
 520         vmmc_aux-supply = <&ldo1_reg>;
 521         bus-width = <4>;
 522         /*
 523          * SDCD signal is not being used here - using the fact that GPIO mode
 524          * is a viable alternative
 525          */
 526         cd-gpios = <&gpio6 27 0>;
 527         max-frequency = <192000000>;
 528 };
 529
 530 &mmc2 {
 531         /* SW5-3 in ON position */
 532         status = "okay";
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&mmc2_pins_default>;
 535
 536         vmmc-supply = <&evm_3v3>;
 537         bus-width = <8>;
 538         ti,non-removable;
 539         max-frequency = <192000000>;
 540 };
 541
 542 &dra7_pmx_core {
 543         cpsw_default: cpsw_default {
 544                 pinctrl-single,pins = <
 545                         /* Slave 2 */
 546                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 547                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 548                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 549                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 550                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 551                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 552                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 553                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 554                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 555                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 556                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 557                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 558                 >;
 559
 560         };
 561
 562         cpsw_sleep: cpsw_sleep {
 563                 pinctrl-single,pins = <
 564                         /* Slave 2 */
 565                         0x198 (MUX_MODE15)
 566                         0x19c (MUX_MODE15)
 567                         0x1a0 (MUX_MODE15)
 568                         0x1a4 (MUX_MODE15)
 569                         0x1a8 (MUX_MODE15)
 570                         0x1ac (MUX_MODE15)
 571                         0x1b0 (MUX_MODE15)
 572                         0x1b4 (MUX_MODE15)
 573                         0x1b8 (MUX_MODE15)
 574                         0x1bc (MUX_MODE15)
 575                         0x1c0 (MUX_MODE15)
 576                         0x1c4 (MUX_MODE15)
 577                 >;
 578         };
 579
 580         davinci_mdio_default: davinci_mdio_default {
 581                 pinctrl-single,pins = <
 582                         /* MDIO */
 583                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 584                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 585                 >;
 586         };
 587
 588         davinci_mdio_sleep: davinci_mdio_sleep {
 589                 pinctrl-single,pins = <
 590                         0x23c (MUX_MODE15)
 591                         0x240 (MUX_MODE15)
 592                 >;
 593         };
 594 };
 595
 596 &mac {
 597         status = "okay";
 598         pinctrl-names = "default", "sleep";
 599         pinctrl-0 = <&cpsw_default>;
 600         pinctrl-1 = <&cpsw_sleep>;
 601         slaves = <1>;
 602 };
 603
 604 &cpsw_emac0 {
 605         phy_id = <&davinci_mdio>, <3>;
 606         phy-mode = "rgmii";
 607 };
 608
 609 &davinci_mdio {
 610         pinctrl-names = "default", "sleep";
 611         pinctrl-0 = <&davinci_mdio_default>;
 612         pinctrl-1 = <&davinci_mdio_sleep>;
 613 };
 614
 615 &dcan1 {
 616         status = "ok";
 617         pinctrl-names = "default", "sleep", "active";
 618         pinctrl-0 = <&dcan1_pins_sleep>;
 619         pinctrl-1 = <&dcan1_pins_sleep>;
 620         pinctrl-2 = <&dcan1_pins_default>;
 621 };
 622
 623 &qspi {
 624         status = "okay";
 625         pinctrl-names = "default";
 626         pinctrl-0 = <&qspi1_pins>;
 627
 628         spi-max-frequency = <48000000>;
 629         m25p80@0 {
 630                 compatible = "s25fl256s1";
 631                 spi-max-frequency = <48000000>;
 632                 reg = <0>;
 633                 spi-tx-bus-width = <1>;
 634                 spi-rx-bus-width = <4>;
 635                 spi-cpol;
 636                 spi-cpha;
 637                 #address-cells = <1>;
 638                 #size-cells = <1>;
 639
 640                 /* MTD partition table.
 641                  * The ROM checks the first four physical blocks
 642                  * for a valid file to boot and the flash here is
 643                  * 64KiB block size.
 644                  */
 645                 partition@0 {
 646                         label = "QSPI.SPL";
 647                         reg = <0x00000000 0x000010000>;
 648                 };
 649                 partition@1 {
 650                         label = "QSPI.SPL.backup1";
 651                         reg = <0x00010000 0x00010000>;
 652                 };
 653                 partition@2 {
 654                         label = "QSPI.SPL.backup2";
 655                         reg = <0x00020000 0x00010000>;
 656                 };
 657                 partition@3 {
 658                         label = "QSPI.SPL.backup3";
 659                         reg = <0x00030000 0x00010000>;
 660                 };
 661                 partition@4 {
 662                         label = "QSPI.u-boot";
 663                         reg = <0x00040000 0x00100000>;
 664                 };
 665                 partition@5 {
 666                         label = "QSPI.u-boot-spl-os";
 667                         reg = <0x00140000 0x00080000>;
 668                 };
 669                 partition@6 {
 670                         label = "QSPI.u-boot-env";
 671                         reg = <0x001c0000 0x00010000>;
 672                 };
 673                 partition@7 {
 674                         label = "QSPI.u-boot-env.backup1";
 675                         reg = <0x001d0000 0x0010000>;
 676                 };
 677                 partition@8 {
 678                         label = "QSPI.kernel";
 679                         reg = <0x001e0000 0x0800000>;
 680                 };
 681                 partition@9 {
 682                         label = "QSPI.file-system";
 683                         reg = <0x009e0000 0x01620000>;
 684                 };
 685         };
 686 };
 687
 688 &dss {
 689         status = "ok";
 690
 691         vdda_video-supply = <&ldo5_reg>;
 692 };
 693
 694 &hdmi {
 695         status = "ok";
 696         vdda-supply = <&ldo3_reg>;
 697
 698         pinctrl-names = "default";
 699         pinctrl-0 = <&hdmi_pins>;
 700
 701         port {
 702                 hdmi_out: endpoint {
 703                         remote-endpoint = <&tpd12s015_in>;
 704                 };
 705         };
 706 };