5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary, or theoretically 64K
206 for the MSM machine class.
208 config ARM_PATCH_PHYS_VIRT_16BIT
210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
212 This option extends the physical to virtual translation patching
213 to allow physical memory down to a theoretical minimum of 64K
216 source "init/Kconfig"
218 source "kernel/Kconfig.freezer"
223 bool "MMU-based Paged Memory Management Support"
226 Select if you want MMU-based virtualised addressing space
227 support by paged memory management. If unsure, say 'Y'.
230 # The "ARM system type" choice list is ordered alphabetically by option
231 # text. Please add new entries in the option alphabetic order.
234 prompt "ARM system type"
235 default ARCH_VERSATILE
237 config ARCH_INTEGRATOR
238 bool "ARM Ltd. Integrator family"
240 select ARCH_HAS_CPUFREQ
243 select GENERIC_CLOCKEVENTS
244 select PLAT_VERSATILE
245 select PLAT_VERSATILE_FPGA_IRQ
247 Support for ARM's Integrator platform.
250 bool "ARM Ltd. RealView family"
254 select GENERIC_CLOCKEVENTS
255 select ARCH_WANT_OPTIONAL_GPIOLIB
256 select PLAT_VERSATILE
257 select PLAT_VERSATILE_CLCD
258 select ARM_TIMER_SP804
259 select GPIO_PL061 if GPIOLIB
261 This enables support for ARM Ltd RealView boards.
263 config ARCH_VERSATILE
264 bool "ARM Ltd. Versatile family"
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select PLAT_VERSATILE_FPGA_IRQ
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_PATA_PLATFORM
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
291 This enables support for the ARM Ltd Versatile Express boards.
295 select ARCH_REQUIRE_GPIOLIB
298 select ARM_PATCH_PHYS_VIRT if MMU
300 This enables support for systems based on the Atmel AT91RM9200,
301 AT91SAM9 and AT91CAP9 processors.
304 bool "Broadcom BCMRING"
308 select ARM_TIMER_SP804
310 select GENERIC_CLOCKEVENTS
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 Support for Broadcom's BCMRing platform.
316 bool "Cirrus Logic CLPS711x/EP721x-based"
318 select ARCH_USES_GETTIMEOFFSET
320 Support for Cirrus Logic 711x/721x based boards.
323 bool "Cavium Networks CNS3XXX family"
325 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select PCI_DOMAINS if PCI
330 Support for Cavium Networks CNS3XXX platform.
333 bool "Cortina Systems Gemini"
335 select ARCH_REQUIRE_GPIOLIB
336 select ARCH_USES_GETTIMEOFFSET
338 Support for the Cortina Systems Gemini family SoCs
345 select ARCH_USES_GETTIMEOFFSET
347 This is an evaluation board for the StrongARM processor available
348 from Digital. It has limited hardware on-board, including an
349 Ethernet interface, two PCMCIA sockets, two serial ports and a
358 select ARCH_REQUIRE_GPIOLIB
359 select ARCH_HAS_HOLES_MEMORYMODEL
360 select ARCH_USES_GETTIMEOFFSET
362 This enables support for the Cirrus EP93xx series of CPUs.
364 config ARCH_FOOTBRIDGE
368 select GENERIC_CLOCKEVENTS
370 Support for systems based on the DC21285 companion chip
371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
374 bool "Freescale MXC/iMX-based"
375 select GENERIC_CLOCKEVENTS
376 select ARCH_REQUIRE_GPIOLIB
379 select HAVE_SCHED_CLOCK
381 Support for Freescale MXC/iMX-based family of processors
384 bool "Freescale MXS-based"
385 select GENERIC_CLOCKEVENTS
386 select ARCH_REQUIRE_GPIOLIB
390 Support for Freescale MXS-based family of processors
393 bool "Hilscher NetX based"
397 select GENERIC_CLOCKEVENTS
399 This enables support for systems based on the Hilscher NetX Soc
402 bool "Hynix HMS720x-based"
405 select ARCH_USES_GETTIMEOFFSET
407 This enables support for systems based on the Hynix HMS720x
415 select ARCH_SUPPORTS_MSI
418 Support for Intel's IOP13XX (XScale) family of processors.
426 select ARCH_REQUIRE_GPIOLIB
428 Support for Intel's 80219 and IOP32X (XScale) family of
437 select ARCH_REQUIRE_GPIOLIB
439 Support for Intel's IOP33X (XScale) family of processors.
446 select ARCH_USES_GETTIMEOFFSET
448 Support for Intel's IXP23xx (XScale) family of processors.
451 bool "IXP2400/2800-based"
455 select ARCH_USES_GETTIMEOFFSET
457 Support for Intel's IXP2400/2800 (XScale) family of processors.
465 select GENERIC_CLOCKEVENTS
466 select HAVE_SCHED_CLOCK
467 select MIGHT_HAVE_PCI
468 select DMABOUNCE if PCI
470 Support for Intel's IXP4XX (XScale) family of processors.
476 select ARCH_REQUIRE_GPIOLIB
477 select GENERIC_CLOCKEVENTS
480 Support for the Marvell Dove SoC 88AP510
483 bool "Marvell Kirkwood"
486 select ARCH_REQUIRE_GPIOLIB
487 select GENERIC_CLOCKEVENTS
490 Support for the following Marvell Kirkwood series SoCs:
491 88F6180, 88F6192 and 88F6281.
497 select ARCH_REQUIRE_GPIOLIB
500 select USB_ARCH_HAS_OHCI
503 select GENERIC_CLOCKEVENTS
505 Support for the NXP LPC32XX family of processors
508 bool "Marvell MV78xx0"
511 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
515 Support for the following Marvell MV78xx0 series SoCs:
523 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
527 Support for the following Marvell Orion 5x series SoCs:
528 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
529 Orion-2 (5281), Orion-1-90 (6183).
532 bool "Marvell PXA168/910/MMP2"
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
537 select HAVE_SCHED_CLOCK
542 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
545 bool "Micrel/Kendin KS8695"
547 select ARCH_REQUIRE_GPIOLIB
548 select ARCH_USES_GETTIMEOFFSET
550 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
551 System-on-Chip devices.
554 bool "Nuvoton W90X900 CPU"
556 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
561 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
562 At present, the w90x900 has been renamed nuc900, regarding
563 the ARM series product line, you can login the following
564 link address to know more.
566 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
567 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
570 bool "Nuvoton NUC93X CPU"
574 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
575 low-power and high performance MPEG-4/JPEG multimedia controller chip.
582 select GENERIC_CLOCKEVENTS
585 select HAVE_SCHED_CLOCK
586 select ARCH_HAS_BARRIERS if CACHE_L2X0
587 select ARCH_HAS_CPUFREQ
589 This enables support for NVIDIA Tegra based systems (Tegra APX,
590 Tegra 6xx and Tegra 2 series).
593 bool "Philips Nexperia PNX4008 Mobile"
596 select ARCH_USES_GETTIMEOFFSET
598 This enables support for Philips PNX4008 mobile platform.
601 bool "PXA2xx/PXA3xx-based"
604 select ARCH_HAS_CPUFREQ
607 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
609 select HAVE_SCHED_CLOCK
614 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
619 select GENERIC_CLOCKEVENTS
620 select ARCH_REQUIRE_GPIOLIB
623 Support for Qualcomm MSM/QSD based systems. This runs on the
624 apps processor of the MSM/QSD and depends on a shared memory
625 interface to the modem processor which runs the baseband
626 stack and controls some vital subsystems
627 (clock and power control, etc).
630 bool "Renesas SH-Mobile / R-Mobile"
633 select GENERIC_CLOCKEVENTS
636 select MULTI_IRQ_HANDLER
638 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
645 select ARCH_MAY_HAVE_PC_FDC
646 select HAVE_PATA_PLATFORM
649 select ARCH_SPARSEMEM_ENABLE
650 select ARCH_USES_GETTIMEOFFSET
652 On the Acorn Risc-PC, Linux can support the internal IDE disk and
653 CD-ROM interface, serial and parallel port, and the floppy drive.
660 select ARCH_SPARSEMEM_ENABLE
662 select ARCH_HAS_CPUFREQ
664 select GENERIC_CLOCKEVENTS
666 select HAVE_SCHED_CLOCK
668 select ARCH_REQUIRE_GPIOLIB
670 Support for StrongARM 11x0 based boards.
673 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
675 select ARCH_HAS_CPUFREQ
677 select ARCH_USES_GETTIMEOFFSET
678 select HAVE_S3C2410_I2C if I2C
680 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
681 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
682 the Samsung SMDK2410 development board (and derivatives).
684 Note, the S3C2416 and the S3C2450 are so close that they even share
685 the same SoC ID code. This means that there is no separate machine
686 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
689 bool "Samsung S3C64XX"
695 select ARCH_USES_GETTIMEOFFSET
696 select ARCH_HAS_CPUFREQ
697 select ARCH_REQUIRE_GPIOLIB
698 select SAMSUNG_CLKSRC
699 select SAMSUNG_IRQ_VIC_TIMER
700 select SAMSUNG_IRQ_UART
701 select S3C_GPIO_TRACK
702 select S3C_GPIO_PULL_UPDOWN
703 select S3C_GPIO_CFG_S3C24XX
704 select S3C_GPIO_CFG_S3C64XX
706 select USB_ARCH_HAS_OHCI
707 select SAMSUNG_GPIOLIB_4BIT
708 select HAVE_S3C2410_I2C if I2C
709 select HAVE_S3C2410_WATCHDOG if WATCHDOG
711 Samsung S3C64XX series based systems
714 bool "Samsung S5P6440 S5P6450"
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
719 select GENERIC_CLOCKEVENTS
720 select HAVE_SCHED_CLOCK
721 select HAVE_S3C2410_I2C if I2C
722 select HAVE_S3C_RTC if RTC_CLASS
724 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
728 bool "Samsung S5PC100"
732 select ARM_L1_CACHE_SHIFT_6
733 select ARCH_USES_GETTIMEOFFSET
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C_RTC if RTC_CLASS
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 Samsung S5PC100 series based systems
741 bool "Samsung S5PV210/S5PC110"
743 select ARCH_SPARSEMEM_ENABLE
746 select ARM_L1_CACHE_SHIFT_6
747 select ARCH_HAS_CPUFREQ
748 select GENERIC_CLOCKEVENTS
749 select HAVE_SCHED_CLOCK
750 select HAVE_S3C2410_I2C if I2C
751 select HAVE_S3C_RTC if RTC_CLASS
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 Samsung S5PV210/S5PC110 series based systems
757 bool "Samsung EXYNOS4"
759 select ARCH_SPARSEMEM_ENABLE
762 select ARCH_HAS_CPUFREQ
763 select GENERIC_CLOCKEVENTS
764 select HAVE_S3C_RTC if RTC_CLASS
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 Samsung EXYNOS4 series based systems
777 select ARCH_USES_GETTIMEOFFSET
779 Support for the StrongARM based Digital DNARD machine, also known
780 as "Shark" (<http://www.shark-linux.de/shark.html>).
783 bool "Telechips TCC ARM926-based systems"
788 select GENERIC_CLOCKEVENTS
790 Support for Telechips TCC ARM926-based systems.
793 bool "ST-Ericsson U300 Series"
797 select HAVE_SCHED_CLOCK
801 select GENERIC_CLOCKEVENTS
805 Support for ST-Ericsson U300 series mobile platforms.
808 bool "ST-Ericsson U8500 Series"
811 select GENERIC_CLOCKEVENTS
813 select ARCH_REQUIRE_GPIOLIB
814 select ARCH_HAS_CPUFREQ
816 Support for ST-Ericsson's Ux500 architecture
819 bool "STMicroelectronics Nomadik"
824 select GENERIC_CLOCKEVENTS
825 select ARCH_REQUIRE_GPIOLIB
827 Support for the Nomadik platform by ST-Ericsson
831 select GENERIC_CLOCKEVENTS
832 select ARCH_REQUIRE_GPIOLIB
836 select GENERIC_ALLOCATOR
837 select GENERIC_IRQ_CHIP
838 select ARCH_HAS_HOLES_MEMORYMODEL
840 Support for TI's DaVinci platform.
845 select ARCH_REQUIRE_GPIOLIB
846 select ARCH_HAS_CPUFREQ
847 select GENERIC_CLOCKEVENTS
848 select HAVE_SCHED_CLOCK
849 select ARCH_HAS_HOLES_MEMORYMODEL
851 Support for TI's OMAP platform (OMAP1/2/3/4).
856 select ARCH_REQUIRE_GPIOLIB
859 select GENERIC_CLOCKEVENTS
862 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
865 bool "VIA/WonderMedia 85xx"
868 select ARCH_HAS_CPUFREQ
869 select GENERIC_CLOCKEVENTS
870 select ARCH_REQUIRE_GPIOLIB
873 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
877 # This is sorted alphabetically by mach-* pathname. However, plat-*
878 # Kconfigs may be included either alphabetically (according to the
879 # plat- suffix) or along side the corresponding mach-* source.
881 source "arch/arm/mach-at91/Kconfig"
883 source "arch/arm/mach-bcmring/Kconfig"
885 source "arch/arm/mach-clps711x/Kconfig"
887 source "arch/arm/mach-cns3xxx/Kconfig"
889 source "arch/arm/mach-davinci/Kconfig"
891 source "arch/arm/mach-dove/Kconfig"
893 source "arch/arm/mach-ep93xx/Kconfig"
895 source "arch/arm/mach-footbridge/Kconfig"
897 source "arch/arm/mach-gemini/Kconfig"
899 source "arch/arm/mach-h720x/Kconfig"
901 source "arch/arm/mach-integrator/Kconfig"
903 source "arch/arm/mach-iop32x/Kconfig"
905 source "arch/arm/mach-iop33x/Kconfig"
907 source "arch/arm/mach-iop13xx/Kconfig"
909 source "arch/arm/mach-ixp4xx/Kconfig"
911 source "arch/arm/mach-ixp2000/Kconfig"
913 source "arch/arm/mach-ixp23xx/Kconfig"
915 source "arch/arm/mach-kirkwood/Kconfig"
917 source "arch/arm/mach-ks8695/Kconfig"
919 source "arch/arm/mach-lpc32xx/Kconfig"
921 source "arch/arm/mach-msm/Kconfig"
923 source "arch/arm/mach-mv78xx0/Kconfig"
925 source "arch/arm/plat-mxc/Kconfig"
927 source "arch/arm/mach-mxs/Kconfig"
929 source "arch/arm/mach-netx/Kconfig"
931 source "arch/arm/mach-nomadik/Kconfig"
932 source "arch/arm/plat-nomadik/Kconfig"
934 source "arch/arm/mach-nuc93x/Kconfig"
936 source "arch/arm/plat-omap/Kconfig"
938 source "arch/arm/mach-omap1/Kconfig"
940 source "arch/arm/mach-omap2/Kconfig"
942 source "arch/arm/mach-orion5x/Kconfig"
944 source "arch/arm/mach-pxa/Kconfig"
945 source "arch/arm/plat-pxa/Kconfig"
947 source "arch/arm/mach-mmp/Kconfig"
949 source "arch/arm/mach-realview/Kconfig"
951 source "arch/arm/mach-sa1100/Kconfig"
953 source "arch/arm/plat-samsung/Kconfig"
954 source "arch/arm/plat-s3c24xx/Kconfig"
955 source "arch/arm/plat-s5p/Kconfig"
957 source "arch/arm/plat-spear/Kconfig"
959 source "arch/arm/plat-tcc/Kconfig"
962 source "arch/arm/mach-s3c2410/Kconfig"
963 source "arch/arm/mach-s3c2412/Kconfig"
964 source "arch/arm/mach-s3c2416/Kconfig"
965 source "arch/arm/mach-s3c2440/Kconfig"
966 source "arch/arm/mach-s3c2443/Kconfig"
970 source "arch/arm/mach-s3c64xx/Kconfig"
973 source "arch/arm/mach-s5p64x0/Kconfig"
975 source "arch/arm/mach-s5pc100/Kconfig"
977 source "arch/arm/mach-s5pv210/Kconfig"
979 source "arch/arm/mach-exynos4/Kconfig"
981 source "arch/arm/mach-shmobile/Kconfig"
983 source "arch/arm/mach-tegra/Kconfig"
985 source "arch/arm/mach-u300/Kconfig"
987 source "arch/arm/mach-ux500/Kconfig"
989 source "arch/arm/mach-versatile/Kconfig"
991 source "arch/arm/mach-vexpress/Kconfig"
992 source "arch/arm/plat-versatile/Kconfig"
994 source "arch/arm/mach-vt8500/Kconfig"
996 source "arch/arm/mach-w90x900/Kconfig"
998 # Definitions to make life easier
1004 select GENERIC_CLOCKEVENTS
1005 select HAVE_SCHED_CLOCK
1010 select GENERIC_IRQ_CHIP
1011 select HAVE_SCHED_CLOCK
1016 config PLAT_VERSATILE
1019 config ARM_TIMER_SP804
1023 source arch/arm/mm/Kconfig
1026 bool "Enable iWMMXt support"
1027 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1028 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1030 Enable support for iWMMXt context switching at run time if
1031 running on a CPU that supports it.
1033 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1036 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1040 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1041 (!ARCH_OMAP3 || OMAP3_EMU)
1045 config MULTI_IRQ_HANDLER
1048 Allow each machine to specify it's own IRQ handler at run time.
1051 source "arch/arm/Kconfig-nommu"
1054 config ARM_ERRATA_411920
1055 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1056 depends on CPU_V6 || CPU_V6K
1058 Invalidation of the Instruction Cache operation can
1059 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1060 It does not affect the MPCore. This option enables the ARM Ltd.
1061 recommended workaround.
1063 config ARM_ERRATA_430973
1064 bool "ARM errata: Stale prediction on replaced interworking branch"
1067 This option enables the workaround for the 430973 Cortex-A8
1068 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1069 interworking branch is replaced with another code sequence at the
1070 same virtual address, whether due to self-modifying code or virtual
1071 to physical address re-mapping, Cortex-A8 does not recover from the
1072 stale interworking branch prediction. This results in Cortex-A8
1073 executing the new code sequence in the incorrect ARM or Thumb state.
1074 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1075 and also flushes the branch target cache at every context switch.
1076 Note that setting specific bits in the ACTLR register may not be
1077 available in non-secure mode.
1079 config ARM_ERRATA_458693
1080 bool "ARM errata: Processor deadlock when a false hazard is created"
1083 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1084 erratum. For very specific sequences of memory operations, it is
1085 possible for a hazard condition intended for a cache line to instead
1086 be incorrectly associated with a different cache line. This false
1087 hazard might then cause a processor deadlock. The workaround enables
1088 the L1 caching of the NEON accesses and disables the PLD instruction
1089 in the ACTLR register. Note that setting specific bits in the ACTLR
1090 register may not be available in non-secure mode.
1092 config ARM_ERRATA_460075
1093 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1096 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1097 erratum. Any asynchronous access to the L2 cache may encounter a
1098 situation in which recent store transactions to the L2 cache are lost
1099 and overwritten with stale memory contents from external memory. The
1100 workaround disables the write-allocate mode for the L2 cache via the
1101 ACTLR register. Note that setting specific bits in the ACTLR register
1102 may not be available in non-secure mode.
1104 config ARM_ERRATA_742230
1105 bool "ARM errata: DMB operation may be faulty"
1106 depends on CPU_V7 && SMP
1108 This option enables the workaround for the 742230 Cortex-A9
1109 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1110 between two write operations may not ensure the correct visibility
1111 ordering of the two writes. This workaround sets a specific bit in
1112 the diagnostic register of the Cortex-A9 which causes the DMB
1113 instruction to behave as a DSB, ensuring the correct behaviour of
1116 config ARM_ERRATA_742231
1117 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1118 depends on CPU_V7 && SMP
1120 This option enables the workaround for the 742231 Cortex-A9
1121 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1122 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1123 accessing some data located in the same cache line, may get corrupted
1124 data due to bad handling of the address hazard when the line gets
1125 replaced from one of the CPUs at the same time as another CPU is
1126 accessing it. This workaround sets specific bits in the diagnostic
1127 register of the Cortex-A9 which reduces the linefill issuing
1128 capabilities of the processor.
1130 config PL310_ERRATA_588369
1131 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1132 depends on CACHE_L2X0
1134 The PL310 L2 cache controller implements three types of Clean &
1135 Invalidate maintenance operations: by Physical Address
1136 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1137 They are architecturally defined to behave as the execution of a
1138 clean operation followed immediately by an invalidate operation,
1139 both performing to the same memory location. This functionality
1140 is not correctly implemented in PL310 as clean lines are not
1141 invalidated as a result of these operations.
1143 config ARM_ERRATA_720789
1144 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1145 depends on CPU_V7 && SMP
1147 This option enables the workaround for the 720789 Cortex-A9 (prior to
1148 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1149 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1150 As a consequence of this erratum, some TLB entries which should be
1151 invalidated are not, resulting in an incoherency in the system page
1152 tables. The workaround changes the TLB flushing routines to invalidate
1153 entries regardless of the ASID.
1155 config PL310_ERRATA_727915
1156 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1157 depends on CACHE_L2X0
1159 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1160 operation (offset 0x7FC). This operation runs in background so that
1161 PL310 can handle normal accesses while it is in progress. Under very
1162 rare circumstances, due to this erratum, write data can be lost when
1163 PL310 treats a cacheable write transaction during a Clean &
1164 Invalidate by Way operation.
1166 config ARM_ERRATA_743622
1167 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1170 This option enables the workaround for the 743622 Cortex-A9
1171 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1172 optimisation in the Cortex-A9 Store Buffer may lead to data
1173 corruption. This workaround sets a specific bit in the diagnostic
1174 register of the Cortex-A9 which disables the Store Buffer
1175 optimisation, preventing the defect from occurring. This has no
1176 visible impact on the overall performance or power consumption of the
1179 config ARM_ERRATA_751472
1180 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1181 depends on CPU_V7 && SMP
1183 This option enables the workaround for the 751472 Cortex-A9 (prior
1184 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1185 completion of a following broadcasted operation if the second
1186 operation is received by a CPU before the ICIALLUIS has completed,
1187 potentially leading to corrupted entries in the cache or TLB.
1189 config ARM_ERRATA_753970
1190 bool "ARM errata: cache sync operation may be faulty"
1191 depends on CACHE_PL310
1193 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1195 Under some condition the effect of cache sync operation on
1196 the store buffer still remains when the operation completes.
1197 This means that the store buffer is always asked to drain and
1198 this prevents it from merging any further writes. The workaround
1199 is to replace the normal offset of cache sync operation (0x730)
1200 by another offset targeting an unmapped PL310 register 0x740.
1201 This has the same effect as the cache sync operation: store buffer
1202 drain and waiting for all buffers empty.
1204 config ARM_ERRATA_754322
1205 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1208 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1209 r3p*) erratum. A speculative memory access may cause a page table walk
1210 which starts prior to an ASID switch but completes afterwards. This
1211 can populate the micro-TLB with a stale entry which may be hit with
1212 the new ASID. This workaround places two dsb instructions in the mm
1213 switching code so that no page table walks can cross the ASID switch.
1215 config ARM_ERRATA_754327
1216 bool "ARM errata: no automatic Store Buffer drain"
1217 depends on CPU_V7 && SMP
1219 This option enables the workaround for the 754327 Cortex-A9 (prior to
1220 r2p0) erratum. The Store Buffer does not have any automatic draining
1221 mechanism and therefore a livelock may occur if an external agent
1222 continuously polls a memory location waiting to observe an update.
1223 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1224 written polling loops from denying visibility of updates to memory.
1228 source "arch/arm/common/Kconfig"
1238 Find out whether you have ISA slots on your motherboard. ISA is the
1239 name of a bus system, i.e. the way the CPU talks to the other stuff
1240 inside your box. Other bus systems are PCI, EISA, MicroChannel
1241 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1242 newer boards don't support it. If you have ISA, say Y, otherwise N.
1244 # Select ISA DMA controller support
1249 # Select ISA DMA interface
1254 bool "PCI support" if MIGHT_HAVE_PCI
1256 Find out whether you have a PCI motherboard. PCI is the name of a
1257 bus system, i.e. the way the CPU talks to the other stuff inside
1258 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1259 VESA. If you have PCI, say Y, otherwise N.
1265 config PCI_NANOENGINE
1266 bool "BSE nanoEngine PCI support"
1267 depends on SA1100_NANOENGINE
1269 Enable PCI on the BSE nanoEngine board.
1274 # Select the host bridge type
1275 config PCI_HOST_VIA82C505
1277 depends on PCI && ARCH_SHARK
1280 config PCI_HOST_ITE8152
1282 depends on PCI && MACH_ARMCORE
1286 source "drivers/pci/Kconfig"
1288 source "drivers/pcmcia/Kconfig"
1292 menu "Kernel Features"
1294 source "kernel/time/Kconfig"
1297 bool "Symmetric Multi-Processing"
1298 depends on CPU_V6K || CPU_V7
1299 depends on GENERIC_CLOCKEVENTS
1300 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1301 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1302 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1303 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1304 select USE_GENERIC_SMP_HELPERS
1305 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1307 This enables support for systems with more than one CPU. If you have
1308 a system with only one CPU, like most personal computers, say N. If
1309 you have a system with more than one CPU, say Y.
1311 If you say N here, the kernel will run on single and multiprocessor
1312 machines, but will use only one CPU of a multiprocessor machine. If
1313 you say Y here, the kernel will run on many, but not all, single
1314 processor machines. On a single processor machine, the kernel will
1315 run faster if you say N here.
1317 See also <file:Documentation/i386/IO-APIC.txt>,
1318 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1319 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1321 If you don't know what to do here, say N.
1324 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1325 depends on EXPERIMENTAL
1326 depends on SMP && !XIP_KERNEL
1329 SMP kernels contain instructions which fail on non-SMP processors.
1330 Enabling this option allows the kernel to modify itself to make
1331 these instructions safe. Disabling it allows about 1K of space
1334 If you don't know what to do here, say Y.
1340 This option enables support for the ARM system coherency unit
1347 This options enables support for the ARM timer and watchdog unit
1350 prompt "Memory split"
1353 Select the desired split between kernel and user memory.
1355 If you are not absolutely sure what you are doing, leave this
1359 bool "3G/1G user/kernel split"
1361 bool "2G/2G user/kernel split"
1363 bool "1G/3G user/kernel split"
1368 default 0x40000000 if VMSPLIT_1G
1369 default 0x80000000 if VMSPLIT_2G
1373 int "Maximum number of CPUs (2-32)"
1379 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1380 depends on SMP && HOTPLUG && EXPERIMENTAL
1382 Say Y here to experiment with turning CPUs off and on. CPUs
1383 can be controlled through /sys/devices/system/cpu.
1386 bool "Use local timer interrupts"
1389 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1391 Enable support for local timers on SMP platforms, rather then the
1392 legacy IPI broadcast method. Local timers allows the system
1393 accounting to be spread across the timer interval, preventing a
1394 "thundering herd" at every timer tick.
1396 source kernel/Kconfig.preempt
1400 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1401 ARCH_S5PV210 || ARCH_EXYNOS4
1402 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1403 default AT91_TIMER_HZ if ARCH_AT91
1404 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1407 config THUMB2_KERNEL
1408 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1409 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1411 select ARM_ASM_UNIFIED
1413 By enabling this option, the kernel will be compiled in
1414 Thumb-2 mode. A compiler/assembler that understand the unified
1415 ARM-Thumb syntax is needed.
1419 config THUMB2_AVOID_R_ARM_THM_JUMP11
1420 bool "Work around buggy Thumb-2 short branch relocations in gas"
1421 depends on THUMB2_KERNEL && MODULES
1424 Various binutils versions can resolve Thumb-2 branches to
1425 locally-defined, preemptible global symbols as short-range "b.n"
1426 branch instructions.
1428 This is a problem, because there's no guarantee the final
1429 destination of the symbol, or any candidate locations for a
1430 trampoline, are within range of the branch. For this reason, the
1431 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1432 relocation in modules at all, and it makes little sense to add
1435 The symptom is that the kernel fails with an "unsupported
1436 relocation" error when loading some modules.
1438 Until fixed tools are available, passing
1439 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1440 code which hits this problem, at the cost of a bit of extra runtime
1441 stack usage in some cases.
1443 The problem is described in more detail at:
1444 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1446 Only Thumb-2 kernels are affected.
1448 Unless you are sure your tools don't have this problem, say Y.
1450 config ARM_ASM_UNIFIED
1454 bool "Use the ARM EABI to compile the kernel"
1456 This option allows for the kernel to be compiled using the latest
1457 ARM ABI (aka EABI). This is only useful if you are using a user
1458 space environment that is also compiled with EABI.
1460 Since there are major incompatibilities between the legacy ABI and
1461 EABI, especially with regard to structure member alignment, this
1462 option also changes the kernel syscall calling convention to
1463 disambiguate both ABIs and allow for backward compatibility support
1464 (selected with CONFIG_OABI_COMPAT).
1466 To use this you need GCC version 4.0.0 or later.
1469 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1470 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1473 This option preserves the old syscall interface along with the
1474 new (ARM EABI) one. It also provides a compatibility layer to
1475 intercept syscalls that have structure arguments which layout
1476 in memory differs between the legacy ABI and the new ARM EABI
1477 (only for non "thumb" binaries). This option adds a tiny
1478 overhead to all syscalls and produces a slightly larger kernel.
1479 If you know you'll be using only pure EABI user space then you
1480 can say N here. If this option is not selected and you attempt
1481 to execute a legacy ABI binary then the result will be
1482 UNPREDICTABLE (in fact it can be predicted that it won't work
1483 at all). If in doubt say Y.
1485 config ARCH_HAS_HOLES_MEMORYMODEL
1488 config ARCH_SPARSEMEM_ENABLE
1491 config ARCH_SPARSEMEM_DEFAULT
1492 def_bool ARCH_SPARSEMEM_ENABLE
1494 config ARCH_SELECT_MEMORY_MODEL
1495 def_bool ARCH_SPARSEMEM_ENABLE
1497 config HAVE_ARCH_PFN_VALID
1498 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1501 bool "High Memory Support"
1504 The address space of ARM processors is only 4 Gigabytes large
1505 and it has to accommodate user address space, kernel address
1506 space as well as some memory mapped IO. That means that, if you
1507 have a large amount of physical memory and/or IO, not all of the
1508 memory can be "permanently mapped" by the kernel. The physical
1509 memory that is not permanently mapped is called "high memory".
1511 Depending on the selected kernel/user memory split, minimum
1512 vmalloc space and actual amount of RAM, you may not need this
1513 option which should result in a slightly faster kernel.
1518 bool "Allocate 2nd-level pagetables from highmem"
1521 config HW_PERF_EVENTS
1522 bool "Enable hardware performance counter support for perf events"
1523 depends on PERF_EVENTS && CPU_HAS_PMU
1526 Enable hardware performance counter support for perf events. If
1527 disabled, perf events will use software events only.
1531 config FORCE_MAX_ZONEORDER
1532 int "Maximum zone order" if ARCH_SHMOBILE
1533 range 11 64 if ARCH_SHMOBILE
1534 default "9" if SA1111
1537 The kernel memory allocator divides physically contiguous memory
1538 blocks into "zones", where each zone is a power of two number of
1539 pages. This option selects the largest power of two that the kernel
1540 keeps in the memory allocator. If you need to allocate very large
1541 blocks of physically contiguous memory, then you may need to
1542 increase this value.
1544 This config option is actually maximum order plus one. For example,
1545 a value of 11 means that the largest free memory block is 2^10 pages.
1548 bool "Timer and CPU usage LEDs"
1549 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1550 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1551 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1552 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1553 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1554 ARCH_AT91 || ARCH_DAVINCI || \
1555 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1557 If you say Y here, the LEDs on your machine will be used
1558 to provide useful information about your current system status.
1560 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1561 be able to select which LEDs are active using the options below. If
1562 you are compiling a kernel for the EBSA-110 or the LART however, the
1563 red LED will simply flash regularly to indicate that the system is
1564 still functional. It is safe to say Y here if you have a CATS
1565 system, but the driver will do nothing.
1568 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1569 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1570 || MACH_OMAP_PERSEUS2
1572 depends on !GENERIC_CLOCKEVENTS
1573 default y if ARCH_EBSA110
1575 If you say Y here, one of the system LEDs (the green one on the
1576 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1577 will flash regularly to indicate that the system is still
1578 operational. This is mainly useful to kernel hackers who are
1579 debugging unstable kernels.
1581 The LART uses the same LED for both Timer LED and CPU usage LED
1582 functions. You may choose to use both, but the Timer LED function
1583 will overrule the CPU usage LED.
1586 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1588 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1589 || MACH_OMAP_PERSEUS2
1592 If you say Y here, the red LED will be used to give a good real
1593 time indication of CPU usage, by lighting whenever the idle task
1594 is not currently executing.
1596 The LART uses the same LED for both Timer LED and CPU usage LED
1597 functions. You may choose to use both, but the Timer LED function
1598 will overrule the CPU usage LED.
1600 config ALIGNMENT_TRAP
1602 depends on CPU_CP15_MMU
1603 default y if !ARCH_EBSA110
1604 select HAVE_PROC_CPU if PROC_FS
1606 ARM processors cannot fetch/store information which is not
1607 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1608 address divisible by 4. On 32-bit ARM processors, these non-aligned
1609 fetch/store instructions will be emulated in software if you say
1610 here, which has a severe performance impact. This is necessary for
1611 correct operation of some network protocols. With an IP-only
1612 configuration it is safe to say N, otherwise say Y.
1614 config UACCESS_WITH_MEMCPY
1615 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1616 depends on MMU && EXPERIMENTAL
1617 default y if CPU_FEROCEON
1619 Implement faster copy_to_user and clear_user methods for CPU
1620 cores where a 8-word STM instruction give significantly higher
1621 memory write throughput than a sequence of individual 32bit stores.
1623 A possible side effect is a slight increase in scheduling latency
1624 between threads sharing the same address space if they invoke
1625 such copy operations with large buffers.
1627 However, if the CPU data cache is using a write-allocate mode,
1628 this option is unlikely to provide any performance gain.
1632 prompt "Enable seccomp to safely compute untrusted bytecode"
1634 This kernel feature is useful for number crunching applications
1635 that may need to compute untrusted bytecode during their
1636 execution. By using pipes or other transports made available to
1637 the process as file descriptors supporting the read/write
1638 syscalls, it's possible to isolate those applications in
1639 their own address space using seccomp. Once seccomp is
1640 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1641 and the task is only allowed to execute a few safe syscalls
1642 defined by each seccomp mode.
1644 config CC_STACKPROTECTOR
1645 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1646 depends on EXPERIMENTAL
1648 This option turns on the -fstack-protector GCC feature. This
1649 feature puts, at the beginning of functions, a canary value on
1650 the stack just before the return address, and validates
1651 the value just before actually returning. Stack based buffer
1652 overflows (that need to overwrite this return address) now also
1653 overwrite the canary, which gets detected and the attack is then
1654 neutralized via a kernel panic.
1655 This feature requires gcc version 4.2 or above.
1657 config DEPRECATED_PARAM_STRUCT
1658 bool "Provide old way to pass kernel parameters"
1660 This was deprecated in 2001 and announced to live on for 5 years.
1661 Some old boot loaders still use this way.
1668 bool "Flattened Device Tree support"
1670 select OF_EARLY_FLATTREE
1672 Include support for flattened device tree machine descriptions.
1674 # Compressed boot loader in ROM. Yes, we really want to ask about
1675 # TEXT and BSS so we preserve their values in the config files.
1676 config ZBOOT_ROM_TEXT
1677 hex "Compressed ROM boot loader base address"
1680 The physical address at which the ROM-able zImage is to be
1681 placed in the target. Platforms which normally make use of
1682 ROM-able zImage formats normally set this to a suitable
1683 value in their defconfig file.
1685 If ZBOOT_ROM is not enabled, this has no effect.
1687 config ZBOOT_ROM_BSS
1688 hex "Compressed ROM boot loader BSS address"
1691 The base address of an area of read/write memory in the target
1692 for the ROM-able zImage which must be available while the
1693 decompressor is running. It must be large enough to hold the
1694 entire decompressed kernel plus an additional 128 KiB.
1695 Platforms which normally make use of ROM-able zImage formats
1696 normally set this to a suitable value in their defconfig file.
1698 If ZBOOT_ROM is not enabled, this has no effect.
1701 bool "Compressed boot loader in ROM/flash"
1702 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1704 Say Y here if you intend to execute your compressed kernel image
1705 (zImage) directly from ROM or flash. If unsure, say N.
1707 config ZBOOT_ROM_MMCIF
1708 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1709 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1711 Say Y here to include experimental MMCIF loading code in the
1712 ROM-able zImage. With this enabled it is possible to write the
1713 the ROM-able zImage kernel image to an MMC card and boot the
1714 kernel straight from the reset vector. At reset the processor
1715 Mask ROM will load the first part of the the ROM-able zImage
1716 which in turn loads the rest the kernel image to RAM using the
1717 MMCIF hardware block.
1720 string "Default kernel command string"
1723 On some architectures (EBSA110 and CATS), there is currently no way
1724 for the boot loader to pass arguments to the kernel. For these
1725 architectures, you should supply some command-line options at build
1726 time by entering them here. As a minimum, you should specify the
1727 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1730 prompt "Kernel command line type" if CMDLINE != ""
1731 default CMDLINE_FROM_BOOTLOADER
1733 config CMDLINE_FROM_BOOTLOADER
1734 bool "Use bootloader kernel arguments if available"
1736 Uses the command-line options passed by the boot loader. If
1737 the boot loader doesn't provide any, the default kernel command
1738 string provided in CMDLINE will be used.
1740 config CMDLINE_EXTEND
1741 bool "Extend bootloader kernel arguments"
1743 The command-line arguments provided by the boot loader will be
1744 appended to the default kernel command string.
1746 config CMDLINE_FORCE
1747 bool "Always use the default kernel command string"
1749 Always use the default kernel command string, even if the boot
1750 loader passes other arguments to the kernel.
1751 This is useful if you cannot or don't want to change the
1752 command-line options your boot loader passes to the kernel.
1756 bool "Kernel Execute-In-Place from ROM"
1757 depends on !ZBOOT_ROM
1759 Execute-In-Place allows the kernel to run from non-volatile storage
1760 directly addressable by the CPU, such as NOR flash. This saves RAM
1761 space since the text section of the kernel is not loaded from flash
1762 to RAM. Read-write sections, such as the data section and stack,
1763 are still copied to RAM. The XIP kernel is not compressed since
1764 it has to run directly from flash, so it will take more space to
1765 store it. The flash address used to link the kernel object files,
1766 and for storing it, is configuration dependent. Therefore, if you
1767 say Y here, you must know the proper physical address where to
1768 store the kernel image depending on your own flash memory usage.
1770 Also note that the make target becomes "make xipImage" rather than
1771 "make zImage" or "make Image". The final kernel binary to put in
1772 ROM memory will be arch/arm/boot/xipImage.
1776 config XIP_PHYS_ADDR
1777 hex "XIP Kernel Physical Location"
1778 depends on XIP_KERNEL
1779 default "0x00080000"
1781 This is the physical address in your flash memory the kernel will
1782 be linked for and stored to. This address is dependent on your
1786 bool "Kexec system call (EXPERIMENTAL)"
1787 depends on EXPERIMENTAL
1789 kexec is a system call that implements the ability to shutdown your
1790 current kernel, and to start another kernel. It is like a reboot
1791 but it is independent of the system firmware. And like a reboot
1792 you can start any kernel with it, not just Linux.
1794 It is an ongoing process to be certain the hardware in a machine
1795 is properly shutdown, so do not be surprised if this code does not
1796 initially work for you. It may help to enable device hotplugging
1800 bool "Export atags in procfs"
1804 Should the atags used to boot the kernel be exported in an "atags"
1805 file in procfs. Useful with kexec.
1808 bool "Build kdump crash kernel (EXPERIMENTAL)"
1809 depends on EXPERIMENTAL
1811 Generate crash dump after being started by kexec. This should
1812 be normally only set in special crash dump kernels which are
1813 loaded in the main kernel with kexec-tools into a specially
1814 reserved region and then later executed after a crash by
1815 kdump/kexec. The crash dump kernel must be compiled to a
1816 memory address not used by the main kernel
1818 For more details see Documentation/kdump/kdump.txt
1820 config AUTO_ZRELADDR
1821 bool "Auto calculation of the decompressed kernel image address"
1822 depends on !ZBOOT_ROM && !ARCH_U300
1824 ZRELADDR is the physical address where the decompressed kernel
1825 image will be placed. If AUTO_ZRELADDR is selected, the address
1826 will be determined at run-time by masking the current IP with
1827 0xf8000000. This assumes the zImage being placed in the first 128MB
1828 from start of memory.
1832 menu "CPU Power Management"
1836 source "drivers/cpufreq/Kconfig"
1839 tristate "CPUfreq driver for i.MX CPUs"
1840 depends on ARCH_MXC && CPU_FREQ
1842 This enables the CPUfreq driver for i.MX CPUs.
1844 config CPU_FREQ_SA1100
1847 config CPU_FREQ_SA1110
1850 config CPU_FREQ_INTEGRATOR
1851 tristate "CPUfreq driver for ARM Integrator CPUs"
1852 depends on ARCH_INTEGRATOR && CPU_FREQ
1855 This enables the CPUfreq driver for ARM Integrator CPUs.
1857 For details, take a look at <file:Documentation/cpu-freq>.
1863 depends on CPU_FREQ && ARCH_PXA && PXA25x
1865 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1867 config CPU_FREQ_S3C64XX
1868 bool "CPUfreq support for Samsung S3C64XX CPUs"
1869 depends on CPU_FREQ && CPU_S3C6410
1874 Internal configuration node for common cpufreq on Samsung SoC
1876 config CPU_FREQ_S3C24XX
1877 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1878 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1881 This enables the CPUfreq driver for the Samsung S3C24XX family
1884 For details, take a look at <file:Documentation/cpu-freq>.
1888 config CPU_FREQ_S3C24XX_PLL
1889 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1890 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1892 Compile in support for changing the PLL frequency from the
1893 S3C24XX series CPUfreq driver. The PLL takes time to settle
1894 after a frequency change, so by default it is not enabled.
1896 This also means that the PLL tables for the selected CPU(s) will
1897 be built which may increase the size of the kernel image.
1899 config CPU_FREQ_S3C24XX_DEBUG
1900 bool "Debug CPUfreq Samsung driver core"
1901 depends on CPU_FREQ_S3C24XX
1903 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1905 config CPU_FREQ_S3C24XX_IODEBUG
1906 bool "Debug CPUfreq Samsung driver IO timing"
1907 depends on CPU_FREQ_S3C24XX
1909 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1911 config CPU_FREQ_S3C24XX_DEBUGFS
1912 bool "Export debugfs for CPUFreq"
1913 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1915 Export status information via debugfs.
1919 source "drivers/cpuidle/Kconfig"
1923 menu "Floating point emulation"
1925 comment "At least one emulation must be selected"
1928 bool "NWFPE math emulation"
1929 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1931 Say Y to include the NWFPE floating point emulator in the kernel.
1932 This is necessary to run most binaries. Linux does not currently
1933 support floating point hardware so you need to say Y here even if
1934 your machine has an FPA or floating point co-processor podule.
1936 You may say N here if you are going to load the Acorn FPEmulator
1937 early in the bootup.
1940 bool "Support extended precision"
1941 depends on FPE_NWFPE
1943 Say Y to include 80-bit support in the kernel floating-point
1944 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1945 Note that gcc does not generate 80-bit operations by default,
1946 so in most cases this option only enlarges the size of the
1947 floating point emulator without any good reason.
1949 You almost surely want to say N here.
1952 bool "FastFPE math emulation (EXPERIMENTAL)"
1953 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1955 Say Y here to include the FAST floating point emulator in the kernel.
1956 This is an experimental much faster emulator which now also has full
1957 precision for the mantissa. It does not support any exceptions.
1958 It is very simple, and approximately 3-6 times faster than NWFPE.
1960 It should be sufficient for most programs. It may be not suitable
1961 for scientific calculations, but you have to check this for yourself.
1962 If you do not feel you need a faster FP emulation you should better
1966 bool "VFP-format floating point maths"
1967 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1969 Say Y to include VFP support code in the kernel. This is needed
1970 if your hardware includes a VFP unit.
1972 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1973 release notes and additional status information.
1975 Say N if your target does not have VFP hardware.
1983 bool "Advanced SIMD (NEON) Extension support"
1984 depends on VFPv3 && CPU_V7
1986 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1991 menu "Userspace binary formats"
1993 source "fs/Kconfig.binfmt"
1996 tristate "RISC OS personality"
1999 Say Y here to include the kernel code necessary if you want to run
2000 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2001 experimental; if this sounds frightening, say N and sleep in peace.
2002 You can also say M here to compile this support as a module (which
2003 will be called arthur).
2007 menu "Power management options"
2009 source "kernel/power/Kconfig"
2011 config ARCH_SUSPEND_POSSIBLE
2012 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2013 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2014 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2019 source "net/Kconfig"
2021 source "drivers/Kconfig"
2025 source "arch/arm/Kconfig.debug"
2027 source "security/Kconfig"
2029 source "crypto/Kconfig"
2031 source "lib/Kconfig"