5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select NO_MACH_MEMORY_H
329 Support for Broadcom's BCMRing platform.
332 bool "Cirrus Logic CLPS711x/EP721x-based"
334 select ARCH_USES_GETTIMEOFFSET
336 Support for Cirrus Logic 711x/721x based boards.
339 bool "Cavium Networks CNS3XXX family"
341 select GENERIC_CLOCKEVENTS
343 select MIGHT_HAVE_PCI
344 select PCI_DOMAINS if PCI
345 select NO_MACH_MEMORY_H
347 Support for Cavium Networks CNS3XXX platform.
350 bool "Cortina Systems Gemini"
352 select ARCH_REQUIRE_GPIOLIB
353 select ARCH_USES_GETTIMEOFFSET
354 select NO_MACH_MEMORY_H
356 Support for the Cortina Systems Gemini family SoCs
359 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
363 select GENERIC_CLOCKEVENTS
365 select GENERIC_IRQ_CHIP
368 select NO_MACH_MEMORY_H
370 Support for CSR SiRFSoC ARM Cortex A9 Platform
377 select ARCH_USES_GETTIMEOFFSET
379 This is an evaluation board for the StrongARM processor available
380 from Digital. It has limited hardware on-board, including an
381 Ethernet interface, two PCMCIA sockets, two serial ports and a
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_HAS_HOLES_MEMORYMODEL
392 select ARCH_USES_GETTIMEOFFSET
394 This enables support for the Cirrus EP93xx series of CPUs.
396 config ARCH_FOOTBRIDGE
400 select GENERIC_CLOCKEVENTS
402 Support for systems based on the DC21285 companion chip
403 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
406 bool "Freescale MXC/iMX-based"
407 select GENERIC_CLOCKEVENTS
408 select ARCH_REQUIRE_GPIOLIB
411 select GENERIC_IRQ_CHIP
412 select HAVE_SCHED_CLOCK
413 select NO_MACH_MEMORY_H
415 Support for Freescale MXC/iMX-based family of processors
418 bool "Freescale MXS-based"
419 select GENERIC_CLOCKEVENTS
420 select ARCH_REQUIRE_GPIOLIB
423 select NO_MACH_MEMORY_H
425 Support for Freescale MXS-based family of processors
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
433 select NO_MACH_MEMORY_H
435 This enables support for systems based on the Hilscher NetX Soc
438 bool "Hynix HMS720x-based"
441 select ARCH_USES_GETTIMEOFFSET
442 select NO_MACH_MEMORY_H
444 This enables support for systems based on the Hynix HMS720x
452 select ARCH_SUPPORTS_MSI
455 Support for Intel's IOP13XX (XScale) family of processors.
463 select ARCH_REQUIRE_GPIOLIB
464 select NO_MACH_MEMORY_H
466 Support for Intel's 80219 and IOP32X (XScale) family of
475 select ARCH_REQUIRE_GPIOLIB
476 select NO_MACH_MEMORY_H
478 Support for Intel's IOP33X (XScale) family of processors.
485 select ARCH_USES_GETTIMEOFFSET
487 Support for Intel's IXP23xx (XScale) family of processors.
490 bool "IXP2400/2800-based"
494 select ARCH_USES_GETTIMEOFFSET
496 Support for Intel's IXP2400/2800 (XScale) family of processors.
504 select GENERIC_CLOCKEVENTS
505 select HAVE_SCHED_CLOCK
506 select MIGHT_HAVE_PCI
507 select DMABOUNCE if PCI
508 select NO_MACH_MEMORY_H
510 Support for Intel's IXP4XX (XScale) family of processors.
516 select ARCH_REQUIRE_GPIOLIB
517 select GENERIC_CLOCKEVENTS
519 select NO_MACH_MEMORY_H
521 Support for the Marvell Dove SoC 88AP510
524 bool "Marvell Kirkwood"
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
530 select NO_MACH_MEMORY_H
532 Support for the following Marvell Kirkwood series SoCs:
533 88F6180, 88F6192 and 88F6281.
539 select ARCH_REQUIRE_GPIOLIB
542 select USB_ARCH_HAS_OHCI
545 select GENERIC_CLOCKEVENTS
546 select NO_MACH_MEMORY_H
548 Support for the NXP LPC32XX family of processors
551 bool "Marvell MV78xx0"
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
557 select NO_MACH_MEMORY_H
559 Support for the following Marvell MV78xx0 series SoCs:
567 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
570 select NO_MACH_MEMORY_H
572 Support for the following Marvell Orion 5x series SoCs:
573 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
574 Orion-2 (5281), Orion-1-90 (6183).
577 bool "Marvell PXA168/910/MMP2"
579 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
582 select HAVE_SCHED_CLOCK
586 select NO_MACH_MEMORY_H
588 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
591 bool "Micrel/Kendin KS8695"
593 select ARCH_REQUIRE_GPIOLIB
594 select ARCH_USES_GETTIMEOFFSET
596 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
597 System-on-Chip devices.
600 bool "Nuvoton W90X900 CPU"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NO_MACH_MEMORY_H
608 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
609 At present, the w90x900 has been renamed nuc900, regarding
610 the ARM series product line, you can login the following
611 link address to know more.
613 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
614 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
617 bool "Nuvoton NUC93X CPU"
620 select NO_MACH_MEMORY_H
622 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
623 low-power and high performance MPEG-4/JPEG multimedia controller chip.
630 select GENERIC_CLOCKEVENTS
633 select HAVE_SCHED_CLOCK
634 select ARCH_HAS_CPUFREQ
635 select NO_MACH_MEMORY_H
637 This enables support for NVIDIA Tegra based systems (Tegra APX,
638 Tegra 6xx and Tegra 2 series).
641 bool "Philips Nexperia PNX4008 Mobile"
644 select ARCH_USES_GETTIMEOFFSET
645 select NO_MACH_MEMORY_H
647 This enables support for Philips PNX4008 mobile platform.
650 bool "PXA2xx/PXA3xx-based"
653 select ARCH_HAS_CPUFREQ
656 select ARCH_REQUIRE_GPIOLIB
657 select GENERIC_CLOCKEVENTS
658 select HAVE_SCHED_CLOCK
663 select MULTI_IRQ_HANDLER
664 select NO_MACH_MEMORY_H
666 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
671 select GENERIC_CLOCKEVENTS
672 select ARCH_REQUIRE_GPIOLIB
674 select NO_MACH_MEMORY_H
676 Support for Qualcomm MSM/QSD based systems. This runs on the
677 apps processor of the MSM/QSD and depends on a shared memory
678 interface to the modem processor which runs the baseband
679 stack and controls some vital subsystems
680 (clock and power control, etc).
683 bool "Renesas SH-Mobile / R-Mobile"
686 select HAVE_MACH_CLKDEV
687 select GENERIC_CLOCKEVENTS
690 select MULTI_IRQ_HANDLER
691 select PM_GENERIC_DOMAINS if PM
693 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
700 select ARCH_MAY_HAVE_PC_FDC
701 select HAVE_PATA_PLATFORM
704 select ARCH_SPARSEMEM_ENABLE
705 select ARCH_USES_GETTIMEOFFSET
707 On the Acorn Risc-PC, Linux can support the internal IDE disk and
708 CD-ROM interface, serial and parallel port, and the floppy drive.
715 select ARCH_SPARSEMEM_ENABLE
717 select ARCH_HAS_CPUFREQ
719 select GENERIC_CLOCKEVENTS
721 select HAVE_SCHED_CLOCK
723 select ARCH_REQUIRE_GPIOLIB
725 Support for StrongARM 11x0 based boards.
728 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
730 select ARCH_HAS_CPUFREQ
733 select ARCH_USES_GETTIMEOFFSET
734 select HAVE_S3C2410_I2C if I2C
735 select NO_MACH_MEMORY_H
737 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
738 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
739 the Samsung SMDK2410 development board (and derivatives).
741 Note, the S3C2416 and the S3C2450 are so close that they even share
742 the same SoC ID code. This means that there is no separate machine
743 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
746 bool "Samsung S3C64XX"
753 select ARCH_USES_GETTIMEOFFSET
754 select ARCH_HAS_CPUFREQ
755 select ARCH_REQUIRE_GPIOLIB
756 select SAMSUNG_CLKSRC
757 select SAMSUNG_IRQ_VIC_TIMER
758 select SAMSUNG_IRQ_UART
759 select S3C_GPIO_TRACK
760 select S3C_GPIO_PULL_UPDOWN
761 select S3C_GPIO_CFG_S3C24XX
762 select S3C_GPIO_CFG_S3C64XX
764 select USB_ARCH_HAS_OHCI
765 select SAMSUNG_GPIOLIB_4BIT
766 select HAVE_S3C2410_I2C if I2C
767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select NO_MACH_MEMORY_H
770 Samsung S3C64XX series based systems
773 bool "Samsung S5P6440 S5P6450"
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select GENERIC_CLOCKEVENTS
781 select HAVE_SCHED_CLOCK
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C_RTC if RTC_CLASS
785 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
789 bool "Samsung S5PC100"
794 select ARM_L1_CACHE_SHIFT_6
795 select ARCH_USES_GETTIMEOFFSET
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C_RTC if RTC_CLASS
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select NO_MACH_MEMORY_H
801 Samsung S5PC100 series based systems
804 bool "Samsung S5PV210/S5PC110"
806 select ARCH_SPARSEMEM_ENABLE
807 select ARCH_HAS_HOLES_MEMORYMODEL
812 select ARM_L1_CACHE_SHIFT_6
813 select ARCH_HAS_CPUFREQ
814 select GENERIC_CLOCKEVENTS
815 select HAVE_SCHED_CLOCK
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 Samsung S5PV210/S5PC110 series based systems
823 bool "Samsung EXYNOS4"
825 select ARCH_SPARSEMEM_ENABLE
826 select ARCH_HAS_HOLES_MEMORYMODEL
830 select ARCH_HAS_CPUFREQ
831 select GENERIC_CLOCKEVENTS
832 select HAVE_S3C_RTC if RTC_CLASS
833 select HAVE_S3C2410_I2C if I2C
834 select HAVE_S3C2410_WATCHDOG if WATCHDOG
836 Samsung EXYNOS4 series based systems
845 select ARCH_USES_GETTIMEOFFSET
847 Support for the StrongARM based Digital DNARD machine, also known
848 as "Shark" (<http://www.shark-linux.de/shark.html>).
851 bool "Telechips TCC ARM926-based systems"
856 select GENERIC_CLOCKEVENTS
857 select NO_MACH_MEMORY_H
859 Support for Telechips TCC ARM926-based systems.
862 bool "ST-Ericsson U300 Series"
866 select HAVE_SCHED_CLOCK
870 select GENERIC_CLOCKEVENTS
872 select HAVE_MACH_CLKDEV
875 Support for ST-Ericsson U300 series mobile platforms.
878 bool "ST-Ericsson U8500 Series"
881 select GENERIC_CLOCKEVENTS
883 select ARCH_REQUIRE_GPIOLIB
884 select ARCH_HAS_CPUFREQ
885 select NO_MACH_MEMORY_H
887 Support for ST-Ericsson's Ux500 architecture
890 bool "STMicroelectronics Nomadik"
895 select GENERIC_CLOCKEVENTS
896 select ARCH_REQUIRE_GPIOLIB
897 select NO_MACH_MEMORY_H
899 Support for the Nomadik platform by ST-Ericsson
903 select GENERIC_CLOCKEVENTS
904 select ARCH_REQUIRE_GPIOLIB
908 select GENERIC_ALLOCATOR
909 select GENERIC_IRQ_CHIP
910 select ARCH_HAS_HOLES_MEMORYMODEL
911 select NO_MACH_MEMORY_H
913 Support for TI's DaVinci platform.
918 select ARCH_REQUIRE_GPIOLIB
919 select ARCH_HAS_CPUFREQ
921 select GENERIC_CLOCKEVENTS
922 select HAVE_SCHED_CLOCK
923 select ARCH_HAS_HOLES_MEMORYMODEL
925 Support for TI's OMAP platform (OMAP1/2/3/4).
930 select ARCH_REQUIRE_GPIOLIB
933 select GENERIC_CLOCKEVENTS
935 select NO_MACH_MEMORY_H
937 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
940 bool "VIA/WonderMedia 85xx"
943 select ARCH_HAS_CPUFREQ
944 select GENERIC_CLOCKEVENTS
945 select ARCH_REQUIRE_GPIOLIB
947 select NO_MACH_MEMORY_H
949 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
952 bool "Xilinx Zynq ARM Cortex A9 Platform"
955 select GENERIC_CLOCKEVENTS
961 select NO_MACH_MEMORY_H
963 Support for Xilinx Zynq ARM Cortex A9 Platform
967 # This is sorted alphabetically by mach-* pathname. However, plat-*
968 # Kconfigs may be included either alphabetically (according to the
969 # plat- suffix) or along side the corresponding mach-* source.
971 source "arch/arm/mach-at91/Kconfig"
973 source "arch/arm/mach-bcmring/Kconfig"
975 source "arch/arm/mach-clps711x/Kconfig"
977 source "arch/arm/mach-cns3xxx/Kconfig"
979 source "arch/arm/mach-davinci/Kconfig"
981 source "arch/arm/mach-dove/Kconfig"
983 source "arch/arm/mach-ep93xx/Kconfig"
985 source "arch/arm/mach-footbridge/Kconfig"
987 source "arch/arm/mach-gemini/Kconfig"
989 source "arch/arm/mach-h720x/Kconfig"
991 source "arch/arm/mach-integrator/Kconfig"
993 source "arch/arm/mach-iop32x/Kconfig"
995 source "arch/arm/mach-iop33x/Kconfig"
997 source "arch/arm/mach-iop13xx/Kconfig"
999 source "arch/arm/mach-ixp4xx/Kconfig"
1001 source "arch/arm/mach-ixp2000/Kconfig"
1003 source "arch/arm/mach-ixp23xx/Kconfig"
1005 source "arch/arm/mach-kirkwood/Kconfig"
1007 source "arch/arm/mach-ks8695/Kconfig"
1009 source "arch/arm/mach-lpc32xx/Kconfig"
1011 source "arch/arm/mach-msm/Kconfig"
1013 source "arch/arm/mach-mv78xx0/Kconfig"
1015 source "arch/arm/plat-mxc/Kconfig"
1017 source "arch/arm/mach-mxs/Kconfig"
1019 source "arch/arm/mach-netx/Kconfig"
1021 source "arch/arm/mach-nomadik/Kconfig"
1022 source "arch/arm/plat-nomadik/Kconfig"
1024 source "arch/arm/mach-nuc93x/Kconfig"
1026 source "arch/arm/plat-omap/Kconfig"
1028 source "arch/arm/mach-omap1/Kconfig"
1030 source "arch/arm/mach-omap2/Kconfig"
1032 source "arch/arm/mach-orion5x/Kconfig"
1034 source "arch/arm/mach-pxa/Kconfig"
1035 source "arch/arm/plat-pxa/Kconfig"
1037 source "arch/arm/mach-mmp/Kconfig"
1039 source "arch/arm/mach-realview/Kconfig"
1041 source "arch/arm/mach-sa1100/Kconfig"
1043 source "arch/arm/plat-samsung/Kconfig"
1044 source "arch/arm/plat-s3c24xx/Kconfig"
1045 source "arch/arm/plat-s5p/Kconfig"
1047 source "arch/arm/plat-spear/Kconfig"
1049 source "arch/arm/plat-tcc/Kconfig"
1052 source "arch/arm/mach-s3c2410/Kconfig"
1053 source "arch/arm/mach-s3c2412/Kconfig"
1054 source "arch/arm/mach-s3c2416/Kconfig"
1055 source "arch/arm/mach-s3c2440/Kconfig"
1056 source "arch/arm/mach-s3c2443/Kconfig"
1060 source "arch/arm/mach-s3c64xx/Kconfig"
1063 source "arch/arm/mach-s5p64x0/Kconfig"
1065 source "arch/arm/mach-s5pc100/Kconfig"
1067 source "arch/arm/mach-s5pv210/Kconfig"
1069 source "arch/arm/mach-exynos4/Kconfig"
1071 source "arch/arm/mach-shmobile/Kconfig"
1073 source "arch/arm/mach-tegra/Kconfig"
1075 source "arch/arm/mach-u300/Kconfig"
1077 source "arch/arm/mach-ux500/Kconfig"
1079 source "arch/arm/mach-versatile/Kconfig"
1081 source "arch/arm/mach-vexpress/Kconfig"
1082 source "arch/arm/plat-versatile/Kconfig"
1084 source "arch/arm/mach-vt8500/Kconfig"
1086 source "arch/arm/mach-w90x900/Kconfig"
1088 # Definitions to make life easier
1094 select GENERIC_CLOCKEVENTS
1095 select HAVE_SCHED_CLOCK
1100 select GENERIC_IRQ_CHIP
1101 select HAVE_SCHED_CLOCK
1106 config PLAT_VERSATILE
1109 config ARM_TIMER_SP804
1113 source arch/arm/mm/Kconfig
1116 bool "Enable iWMMXt support"
1117 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1118 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1120 Enable support for iWMMXt context switching at run time if
1121 running on a CPU that supports it.
1123 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1126 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1130 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1131 (!ARCH_OMAP3 || OMAP3_EMU)
1135 config MULTI_IRQ_HANDLER
1138 Allow each machine to specify it's own IRQ handler at run time.
1141 source "arch/arm/Kconfig-nommu"
1144 config ARM_ERRATA_411920
1145 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1146 depends on CPU_V6 || CPU_V6K
1148 Invalidation of the Instruction Cache operation can
1149 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1150 It does not affect the MPCore. This option enables the ARM Ltd.
1151 recommended workaround.
1153 config ARM_ERRATA_430973
1154 bool "ARM errata: Stale prediction on replaced interworking branch"
1157 This option enables the workaround for the 430973 Cortex-A8
1158 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1159 interworking branch is replaced with another code sequence at the
1160 same virtual address, whether due to self-modifying code or virtual
1161 to physical address re-mapping, Cortex-A8 does not recover from the
1162 stale interworking branch prediction. This results in Cortex-A8
1163 executing the new code sequence in the incorrect ARM or Thumb state.
1164 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1165 and also flushes the branch target cache at every context switch.
1166 Note that setting specific bits in the ACTLR register may not be
1167 available in non-secure mode.
1169 config ARM_ERRATA_458693
1170 bool "ARM errata: Processor deadlock when a false hazard is created"
1173 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1174 erratum. For very specific sequences of memory operations, it is
1175 possible for a hazard condition intended for a cache line to instead
1176 be incorrectly associated with a different cache line. This false
1177 hazard might then cause a processor deadlock. The workaround enables
1178 the L1 caching of the NEON accesses and disables the PLD instruction
1179 in the ACTLR register. Note that setting specific bits in the ACTLR
1180 register may not be available in non-secure mode.
1182 config ARM_ERRATA_460075
1183 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1186 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1187 erratum. Any asynchronous access to the L2 cache may encounter a
1188 situation in which recent store transactions to the L2 cache are lost
1189 and overwritten with stale memory contents from external memory. The
1190 workaround disables the write-allocate mode for the L2 cache via the
1191 ACTLR register. Note that setting specific bits in the ACTLR register
1192 may not be available in non-secure mode.
1194 config ARM_ERRATA_742230
1195 bool "ARM errata: DMB operation may be faulty"
1196 depends on CPU_V7 && SMP
1198 This option enables the workaround for the 742230 Cortex-A9
1199 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1200 between two write operations may not ensure the correct visibility
1201 ordering of the two writes. This workaround sets a specific bit in
1202 the diagnostic register of the Cortex-A9 which causes the DMB
1203 instruction to behave as a DSB, ensuring the correct behaviour of
1206 config ARM_ERRATA_742231
1207 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for the 742231 Cortex-A9
1211 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1212 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1213 accessing some data located in the same cache line, may get corrupted
1214 data due to bad handling of the address hazard when the line gets
1215 replaced from one of the CPUs at the same time as another CPU is
1216 accessing it. This workaround sets specific bits in the diagnostic
1217 register of the Cortex-A9 which reduces the linefill issuing
1218 capabilities of the processor.
1220 config PL310_ERRATA_588369
1221 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1222 depends on CACHE_L2X0
1224 The PL310 L2 cache controller implements three types of Clean &
1225 Invalidate maintenance operations: by Physical Address
1226 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1227 They are architecturally defined to behave as the execution of a
1228 clean operation followed immediately by an invalidate operation,
1229 both performing to the same memory location. This functionality
1230 is not correctly implemented in PL310 as clean lines are not
1231 invalidated as a result of these operations.
1233 config ARM_ERRATA_720789
1234 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for the 720789 Cortex-A9 (prior to
1238 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1239 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1240 As a consequence of this erratum, some TLB entries which should be
1241 invalidated are not, resulting in an incoherency in the system page
1242 tables. The workaround changes the TLB flushing routines to invalidate
1243 entries regardless of the ASID.
1245 config PL310_ERRATA_727915
1246 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1247 depends on CACHE_L2X0
1249 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1250 operation (offset 0x7FC). This operation runs in background so that
1251 PL310 can handle normal accesses while it is in progress. Under very
1252 rare circumstances, due to this erratum, write data can be lost when
1253 PL310 treats a cacheable write transaction during a Clean &
1254 Invalidate by Way operation.
1256 config ARM_ERRATA_743622
1257 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1260 This option enables the workaround for the 743622 Cortex-A9
1261 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1262 optimisation in the Cortex-A9 Store Buffer may lead to data
1263 corruption. This workaround sets a specific bit in the diagnostic
1264 register of the Cortex-A9 which disables the Store Buffer
1265 optimisation, preventing the defect from occurring. This has no
1266 visible impact on the overall performance or power consumption of the
1269 config ARM_ERRATA_751472
1270 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1271 depends on CPU_V7 && SMP
1273 This option enables the workaround for the 751472 Cortex-A9 (prior
1274 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1275 completion of a following broadcasted operation if the second
1276 operation is received by a CPU before the ICIALLUIS has completed,
1277 potentially leading to corrupted entries in the cache or TLB.
1279 config ARM_ERRATA_753970
1280 bool "ARM errata: cache sync operation may be faulty"
1281 depends on CACHE_PL310
1283 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1285 Under some condition the effect of cache sync operation on
1286 the store buffer still remains when the operation completes.
1287 This means that the store buffer is always asked to drain and
1288 this prevents it from merging any further writes. The workaround
1289 is to replace the normal offset of cache sync operation (0x730)
1290 by another offset targeting an unmapped PL310 register 0x740.
1291 This has the same effect as the cache sync operation: store buffer
1292 drain and waiting for all buffers empty.
1294 config ARM_ERRATA_754322
1295 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1298 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1299 r3p*) erratum. A speculative memory access may cause a page table walk
1300 which starts prior to an ASID switch but completes afterwards. This
1301 can populate the micro-TLB with a stale entry which may be hit with
1302 the new ASID. This workaround places two dsb instructions in the mm
1303 switching code so that no page table walks can cross the ASID switch.
1305 config ARM_ERRATA_754327
1306 bool "ARM errata: no automatic Store Buffer drain"
1307 depends on CPU_V7 && SMP
1309 This option enables the workaround for the 754327 Cortex-A9 (prior to
1310 r2p0) erratum. The Store Buffer does not have any automatic draining
1311 mechanism and therefore a livelock may occur if an external agent
1312 continuously polls a memory location waiting to observe an update.
1313 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1314 written polling loops from denying visibility of updates to memory.
1318 source "arch/arm/common/Kconfig"
1328 Find out whether you have ISA slots on your motherboard. ISA is the
1329 name of a bus system, i.e. the way the CPU talks to the other stuff
1330 inside your box. Other bus systems are PCI, EISA, MicroChannel
1331 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1332 newer boards don't support it. If you have ISA, say Y, otherwise N.
1334 # Select ISA DMA controller support
1339 # Select ISA DMA interface
1344 bool "PCI support" if MIGHT_HAVE_PCI
1346 Find out whether you have a PCI motherboard. PCI is the name of a
1347 bus system, i.e. the way the CPU talks to the other stuff inside
1348 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1349 VESA. If you have PCI, say Y, otherwise N.
1355 config PCI_NANOENGINE
1356 bool "BSE nanoEngine PCI support"
1357 depends on SA1100_NANOENGINE
1359 Enable PCI on the BSE nanoEngine board.
1364 # Select the host bridge type
1365 config PCI_HOST_VIA82C505
1367 depends on PCI && ARCH_SHARK
1370 config PCI_HOST_ITE8152
1372 depends on PCI && MACH_ARMCORE
1376 source "drivers/pci/Kconfig"
1378 source "drivers/pcmcia/Kconfig"
1382 menu "Kernel Features"
1384 source "kernel/time/Kconfig"
1387 bool "Symmetric Multi-Processing"
1388 depends on CPU_V6K || CPU_V7
1389 depends on GENERIC_CLOCKEVENTS
1390 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1391 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1392 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1393 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1394 select USE_GENERIC_SMP_HELPERS
1395 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1397 This enables support for systems with more than one CPU. If you have
1398 a system with only one CPU, like most personal computers, say N. If
1399 you have a system with more than one CPU, say Y.
1401 If you say N here, the kernel will run on single and multiprocessor
1402 machines, but will use only one CPU of a multiprocessor machine. If
1403 you say Y here, the kernel will run on many, but not all, single
1404 processor machines. On a single processor machine, the kernel will
1405 run faster if you say N here.
1407 See also <file:Documentation/i386/IO-APIC.txt>,
1408 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1409 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1411 If you don't know what to do here, say N.
1414 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1415 depends on EXPERIMENTAL
1416 depends on SMP && !XIP_KERNEL
1419 SMP kernels contain instructions which fail on non-SMP processors.
1420 Enabling this option allows the kernel to modify itself to make
1421 these instructions safe. Disabling it allows about 1K of space
1424 If you don't know what to do here, say Y.
1429 This option enables support for the ARM system coherency unit
1436 This options enables support for the ARM timer and watchdog unit
1439 prompt "Memory split"
1442 Select the desired split between kernel and user memory.
1444 If you are not absolutely sure what you are doing, leave this
1448 bool "3G/1G user/kernel split"
1450 bool "2G/2G user/kernel split"
1452 bool "1G/3G user/kernel split"
1457 default 0x40000000 if VMSPLIT_1G
1458 default 0x80000000 if VMSPLIT_2G
1462 int "Maximum number of CPUs (2-32)"
1468 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1469 depends on SMP && HOTPLUG && EXPERIMENTAL
1471 Say Y here to experiment with turning CPUs off and on. CPUs
1472 can be controlled through /sys/devices/system/cpu.
1475 bool "Use local timer interrupts"
1478 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1480 Enable support for local timers on SMP platforms, rather then the
1481 legacy IPI broadcast method. Local timers allows the system
1482 accounting to be spread across the timer interval, preventing a
1483 "thundering herd" at every timer tick.
1485 source kernel/Kconfig.preempt
1489 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1490 ARCH_S5PV210 || ARCH_EXYNOS4
1491 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1492 default AT91_TIMER_HZ if ARCH_AT91
1493 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1496 config THUMB2_KERNEL
1497 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1498 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1500 select ARM_ASM_UNIFIED
1502 By enabling this option, the kernel will be compiled in
1503 Thumb-2 mode. A compiler/assembler that understand the unified
1504 ARM-Thumb syntax is needed.
1508 config THUMB2_AVOID_R_ARM_THM_JUMP11
1509 bool "Work around buggy Thumb-2 short branch relocations in gas"
1510 depends on THUMB2_KERNEL && MODULES
1513 Various binutils versions can resolve Thumb-2 branches to
1514 locally-defined, preemptible global symbols as short-range "b.n"
1515 branch instructions.
1517 This is a problem, because there's no guarantee the final
1518 destination of the symbol, or any candidate locations for a
1519 trampoline, are within range of the branch. For this reason, the
1520 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1521 relocation in modules at all, and it makes little sense to add
1524 The symptom is that the kernel fails with an "unsupported
1525 relocation" error when loading some modules.
1527 Until fixed tools are available, passing
1528 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1529 code which hits this problem, at the cost of a bit of extra runtime
1530 stack usage in some cases.
1532 The problem is described in more detail at:
1533 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1535 Only Thumb-2 kernels are affected.
1537 Unless you are sure your tools don't have this problem, say Y.
1539 config ARM_ASM_UNIFIED
1543 bool "Use the ARM EABI to compile the kernel"
1545 This option allows for the kernel to be compiled using the latest
1546 ARM ABI (aka EABI). This is only useful if you are using a user
1547 space environment that is also compiled with EABI.
1549 Since there are major incompatibilities between the legacy ABI and
1550 EABI, especially with regard to structure member alignment, this
1551 option also changes the kernel syscall calling convention to
1552 disambiguate both ABIs and allow for backward compatibility support
1553 (selected with CONFIG_OABI_COMPAT).
1555 To use this you need GCC version 4.0.0 or later.
1558 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1559 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1562 This option preserves the old syscall interface along with the
1563 new (ARM EABI) one. It also provides a compatibility layer to
1564 intercept syscalls that have structure arguments which layout
1565 in memory differs between the legacy ABI and the new ARM EABI
1566 (only for non "thumb" binaries). This option adds a tiny
1567 overhead to all syscalls and produces a slightly larger kernel.
1568 If you know you'll be using only pure EABI user space then you
1569 can say N here. If this option is not selected and you attempt
1570 to execute a legacy ABI binary then the result will be
1571 UNPREDICTABLE (in fact it can be predicted that it won't work
1572 at all). If in doubt say Y.
1574 config ARCH_HAS_HOLES_MEMORYMODEL
1577 config ARCH_SPARSEMEM_ENABLE
1580 config ARCH_SPARSEMEM_DEFAULT
1581 def_bool ARCH_SPARSEMEM_ENABLE
1583 config ARCH_SELECT_MEMORY_MODEL
1584 def_bool ARCH_SPARSEMEM_ENABLE
1586 config HAVE_ARCH_PFN_VALID
1587 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1590 bool "High Memory Support"
1593 The address space of ARM processors is only 4 Gigabytes large
1594 and it has to accommodate user address space, kernel address
1595 space as well as some memory mapped IO. That means that, if you
1596 have a large amount of physical memory and/or IO, not all of the
1597 memory can be "permanently mapped" by the kernel. The physical
1598 memory that is not permanently mapped is called "high memory".
1600 Depending on the selected kernel/user memory split, minimum
1601 vmalloc space and actual amount of RAM, you may not need this
1602 option which should result in a slightly faster kernel.
1607 bool "Allocate 2nd-level pagetables from highmem"
1610 config HW_PERF_EVENTS
1611 bool "Enable hardware performance counter support for perf events"
1612 depends on PERF_EVENTS && CPU_HAS_PMU
1615 Enable hardware performance counter support for perf events. If
1616 disabled, perf events will use software events only.
1620 config FORCE_MAX_ZONEORDER
1621 int "Maximum zone order" if ARCH_SHMOBILE
1622 range 11 64 if ARCH_SHMOBILE
1623 default "9" if SA1111
1626 The kernel memory allocator divides physically contiguous memory
1627 blocks into "zones", where each zone is a power of two number of
1628 pages. This option selects the largest power of two that the kernel
1629 keeps in the memory allocator. If you need to allocate very large
1630 blocks of physically contiguous memory, then you may need to
1631 increase this value.
1633 This config option is actually maximum order plus one. For example,
1634 a value of 11 means that the largest free memory block is 2^10 pages.
1637 bool "Timer and CPU usage LEDs"
1638 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1639 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1640 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1641 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1642 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1643 ARCH_AT91 || ARCH_DAVINCI || \
1644 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1646 If you say Y here, the LEDs on your machine will be used
1647 to provide useful information about your current system status.
1649 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1650 be able to select which LEDs are active using the options below. If
1651 you are compiling a kernel for the EBSA-110 or the LART however, the
1652 red LED will simply flash regularly to indicate that the system is
1653 still functional. It is safe to say Y here if you have a CATS
1654 system, but the driver will do nothing.
1657 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1658 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1659 || MACH_OMAP_PERSEUS2
1661 depends on !GENERIC_CLOCKEVENTS
1662 default y if ARCH_EBSA110
1664 If you say Y here, one of the system LEDs (the green one on the
1665 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1666 will flash regularly to indicate that the system is still
1667 operational. This is mainly useful to kernel hackers who are
1668 debugging unstable kernels.
1670 The LART uses the same LED for both Timer LED and CPU usage LED
1671 functions. You may choose to use both, but the Timer LED function
1672 will overrule the CPU usage LED.
1675 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1677 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1678 || MACH_OMAP_PERSEUS2
1681 If you say Y here, the red LED will be used to give a good real
1682 time indication of CPU usage, by lighting whenever the idle task
1683 is not currently executing.
1685 The LART uses the same LED for both Timer LED and CPU usage LED
1686 functions. You may choose to use both, but the Timer LED function
1687 will overrule the CPU usage LED.
1689 config ALIGNMENT_TRAP
1691 depends on CPU_CP15_MMU
1692 default y if !ARCH_EBSA110
1693 select HAVE_PROC_CPU if PROC_FS
1695 ARM processors cannot fetch/store information which is not
1696 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1697 address divisible by 4. On 32-bit ARM processors, these non-aligned
1698 fetch/store instructions will be emulated in software if you say
1699 here, which has a severe performance impact. This is necessary for
1700 correct operation of some network protocols. With an IP-only
1701 configuration it is safe to say N, otherwise say Y.
1703 config UACCESS_WITH_MEMCPY
1704 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1705 depends on MMU && EXPERIMENTAL
1706 default y if CPU_FEROCEON
1708 Implement faster copy_to_user and clear_user methods for CPU
1709 cores where a 8-word STM instruction give significantly higher
1710 memory write throughput than a sequence of individual 32bit stores.
1712 A possible side effect is a slight increase in scheduling latency
1713 between threads sharing the same address space if they invoke
1714 such copy operations with large buffers.
1716 However, if the CPU data cache is using a write-allocate mode,
1717 this option is unlikely to provide any performance gain.
1721 prompt "Enable seccomp to safely compute untrusted bytecode"
1723 This kernel feature is useful for number crunching applications
1724 that may need to compute untrusted bytecode during their
1725 execution. By using pipes or other transports made available to
1726 the process as file descriptors supporting the read/write
1727 syscalls, it's possible to isolate those applications in
1728 their own address space using seccomp. Once seccomp is
1729 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1730 and the task is only allowed to execute a few safe syscalls
1731 defined by each seccomp mode.
1733 config CC_STACKPROTECTOR
1734 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1735 depends on EXPERIMENTAL
1737 This option turns on the -fstack-protector GCC feature. This
1738 feature puts, at the beginning of functions, a canary value on
1739 the stack just before the return address, and validates
1740 the value just before actually returning. Stack based buffer
1741 overflows (that need to overwrite this return address) now also
1742 overwrite the canary, which gets detected and the attack is then
1743 neutralized via a kernel panic.
1744 This feature requires gcc version 4.2 or above.
1746 config DEPRECATED_PARAM_STRUCT
1747 bool "Provide old way to pass kernel parameters"
1749 This was deprecated in 2001 and announced to live on for 5 years.
1750 Some old boot loaders still use this way.
1757 bool "Flattened Device Tree support"
1759 select OF_EARLY_FLATTREE
1762 Include support for flattened device tree machine descriptions.
1764 # Compressed boot loader in ROM. Yes, we really want to ask about
1765 # TEXT and BSS so we preserve their values in the config files.
1766 config ZBOOT_ROM_TEXT
1767 hex "Compressed ROM boot loader base address"
1770 The physical address at which the ROM-able zImage is to be
1771 placed in the target. Platforms which normally make use of
1772 ROM-able zImage formats normally set this to a suitable
1773 value in their defconfig file.
1775 If ZBOOT_ROM is not enabled, this has no effect.
1777 config ZBOOT_ROM_BSS
1778 hex "Compressed ROM boot loader BSS address"
1781 The base address of an area of read/write memory in the target
1782 for the ROM-able zImage which must be available while the
1783 decompressor is running. It must be large enough to hold the
1784 entire decompressed kernel plus an additional 128 KiB.
1785 Platforms which normally make use of ROM-able zImage formats
1786 normally set this to a suitable value in their defconfig file.
1788 If ZBOOT_ROM is not enabled, this has no effect.
1791 bool "Compressed boot loader in ROM/flash"
1792 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1794 Say Y here if you intend to execute your compressed kernel image
1795 (zImage) directly from ROM or flash. If unsure, say N.
1798 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1799 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1800 default ZBOOT_ROM_NONE
1802 Include experimental SD/MMC loading code in the ROM-able zImage.
1803 With this enabled it is possible to write the the ROM-able zImage
1804 kernel image to an MMC or SD card and boot the kernel straight
1805 from the reset vector. At reset the processor Mask ROM will load
1806 the first part of the the ROM-able zImage which in turn loads the
1807 rest the kernel image to RAM.
1809 config ZBOOT_ROM_NONE
1810 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1812 Do not load image from SD or MMC
1814 config ZBOOT_ROM_MMCIF
1815 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1817 Load image from MMCIF hardware block.
1819 config ZBOOT_ROM_SH_MOBILE_SDHI
1820 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1822 Load image from SDHI hardware block
1827 string "Default kernel command string"
1830 On some architectures (EBSA110 and CATS), there is currently no way
1831 for the boot loader to pass arguments to the kernel. For these
1832 architectures, you should supply some command-line options at build
1833 time by entering them here. As a minimum, you should specify the
1834 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1837 prompt "Kernel command line type" if CMDLINE != ""
1838 default CMDLINE_FROM_BOOTLOADER
1840 config CMDLINE_FROM_BOOTLOADER
1841 bool "Use bootloader kernel arguments if available"
1843 Uses the command-line options passed by the boot loader. If
1844 the boot loader doesn't provide any, the default kernel command
1845 string provided in CMDLINE will be used.
1847 config CMDLINE_EXTEND
1848 bool "Extend bootloader kernel arguments"
1850 The command-line arguments provided by the boot loader will be
1851 appended to the default kernel command string.
1853 config CMDLINE_FORCE
1854 bool "Always use the default kernel command string"
1856 Always use the default kernel command string, even if the boot
1857 loader passes other arguments to the kernel.
1858 This is useful if you cannot or don't want to change the
1859 command-line options your boot loader passes to the kernel.
1863 bool "Kernel Execute-In-Place from ROM"
1864 depends on !ZBOOT_ROM
1866 Execute-In-Place allows the kernel to run from non-volatile storage
1867 directly addressable by the CPU, such as NOR flash. This saves RAM
1868 space since the text section of the kernel is not loaded from flash
1869 to RAM. Read-write sections, such as the data section and stack,
1870 are still copied to RAM. The XIP kernel is not compressed since
1871 it has to run directly from flash, so it will take more space to
1872 store it. The flash address used to link the kernel object files,
1873 and for storing it, is configuration dependent. Therefore, if you
1874 say Y here, you must know the proper physical address where to
1875 store the kernel image depending on your own flash memory usage.
1877 Also note that the make target becomes "make xipImage" rather than
1878 "make zImage" or "make Image". The final kernel binary to put in
1879 ROM memory will be arch/arm/boot/xipImage.
1883 config XIP_PHYS_ADDR
1884 hex "XIP Kernel Physical Location"
1885 depends on XIP_KERNEL
1886 default "0x00080000"
1888 This is the physical address in your flash memory the kernel will
1889 be linked for and stored to. This address is dependent on your
1893 bool "Kexec system call (EXPERIMENTAL)"
1894 depends on EXPERIMENTAL
1896 kexec is a system call that implements the ability to shutdown your
1897 current kernel, and to start another kernel. It is like a reboot
1898 but it is independent of the system firmware. And like a reboot
1899 you can start any kernel with it, not just Linux.
1901 It is an ongoing process to be certain the hardware in a machine
1902 is properly shutdown, so do not be surprised if this code does not
1903 initially work for you. It may help to enable device hotplugging
1907 bool "Export atags in procfs"
1911 Should the atags used to boot the kernel be exported in an "atags"
1912 file in procfs. Useful with kexec.
1915 bool "Build kdump crash kernel (EXPERIMENTAL)"
1916 depends on EXPERIMENTAL
1918 Generate crash dump after being started by kexec. This should
1919 be normally only set in special crash dump kernels which are
1920 loaded in the main kernel with kexec-tools into a specially
1921 reserved region and then later executed after a crash by
1922 kdump/kexec. The crash dump kernel must be compiled to a
1923 memory address not used by the main kernel
1925 For more details see Documentation/kdump/kdump.txt
1927 config AUTO_ZRELADDR
1928 bool "Auto calculation of the decompressed kernel image address"
1929 depends on !ZBOOT_ROM && !ARCH_U300
1931 ZRELADDR is the physical address where the decompressed kernel
1932 image will be placed. If AUTO_ZRELADDR is selected, the address
1933 will be determined at run-time by masking the current IP with
1934 0xf8000000. This assumes the zImage being placed in the first 128MB
1935 from start of memory.
1939 menu "CPU Power Management"
1943 source "drivers/cpufreq/Kconfig"
1946 tristate "CPUfreq driver for i.MX CPUs"
1947 depends on ARCH_MXC && CPU_FREQ
1949 This enables the CPUfreq driver for i.MX CPUs.
1951 config CPU_FREQ_SA1100
1954 config CPU_FREQ_SA1110
1957 config CPU_FREQ_INTEGRATOR
1958 tristate "CPUfreq driver for ARM Integrator CPUs"
1959 depends on ARCH_INTEGRATOR && CPU_FREQ
1962 This enables the CPUfreq driver for ARM Integrator CPUs.
1964 For details, take a look at <file:Documentation/cpu-freq>.
1970 depends on CPU_FREQ && ARCH_PXA && PXA25x
1972 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1977 Internal configuration node for common cpufreq on Samsung SoC
1979 config CPU_FREQ_S3C24XX
1980 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1981 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1984 This enables the CPUfreq driver for the Samsung S3C24XX family
1987 For details, take a look at <file:Documentation/cpu-freq>.
1991 config CPU_FREQ_S3C24XX_PLL
1992 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1993 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1995 Compile in support for changing the PLL frequency from the
1996 S3C24XX series CPUfreq driver. The PLL takes time to settle
1997 after a frequency change, so by default it is not enabled.
1999 This also means that the PLL tables for the selected CPU(s) will
2000 be built which may increase the size of the kernel image.
2002 config CPU_FREQ_S3C24XX_DEBUG
2003 bool "Debug CPUfreq Samsung driver core"
2004 depends on CPU_FREQ_S3C24XX
2006 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2008 config CPU_FREQ_S3C24XX_IODEBUG
2009 bool "Debug CPUfreq Samsung driver IO timing"
2010 depends on CPU_FREQ_S3C24XX
2012 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2014 config CPU_FREQ_S3C24XX_DEBUGFS
2015 bool "Export debugfs for CPUFreq"
2016 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2018 Export status information via debugfs.
2022 source "drivers/cpuidle/Kconfig"
2026 menu "Floating point emulation"
2028 comment "At least one emulation must be selected"
2031 bool "NWFPE math emulation"
2032 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2034 Say Y to include the NWFPE floating point emulator in the kernel.
2035 This is necessary to run most binaries. Linux does not currently
2036 support floating point hardware so you need to say Y here even if
2037 your machine has an FPA or floating point co-processor podule.
2039 You may say N here if you are going to load the Acorn FPEmulator
2040 early in the bootup.
2043 bool "Support extended precision"
2044 depends on FPE_NWFPE
2046 Say Y to include 80-bit support in the kernel floating-point
2047 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2048 Note that gcc does not generate 80-bit operations by default,
2049 so in most cases this option only enlarges the size of the
2050 floating point emulator without any good reason.
2052 You almost surely want to say N here.
2055 bool "FastFPE math emulation (EXPERIMENTAL)"
2056 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2058 Say Y here to include the FAST floating point emulator in the kernel.
2059 This is an experimental much faster emulator which now also has full
2060 precision for the mantissa. It does not support any exceptions.
2061 It is very simple, and approximately 3-6 times faster than NWFPE.
2063 It should be sufficient for most programs. It may be not suitable
2064 for scientific calculations, but you have to check this for yourself.
2065 If you do not feel you need a faster FP emulation you should better
2069 bool "VFP-format floating point maths"
2070 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2072 Say Y to include VFP support code in the kernel. This is needed
2073 if your hardware includes a VFP unit.
2075 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2076 release notes and additional status information.
2078 Say N if your target does not have VFP hardware.
2086 bool "Advanced SIMD (NEON) Extension support"
2087 depends on VFPv3 && CPU_V7
2089 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2094 menu "Userspace binary formats"
2096 source "fs/Kconfig.binfmt"
2099 tristate "RISC OS personality"
2102 Say Y here to include the kernel code necessary if you want to run
2103 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2104 experimental; if this sounds frightening, say N and sleep in peace.
2105 You can also say M here to compile this support as a module (which
2106 will be called arthur).
2110 menu "Power management options"
2112 source "kernel/power/Kconfig"
2114 config ARCH_SUSPEND_POSSIBLE
2115 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2116 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2117 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2122 source "net/Kconfig"
2124 source "drivers/Kconfig"
2128 source "arch/arm/Kconfig.debug"
2130 source "security/Kconfig"
2132 source "crypto/Kconfig"
2134 source "lib/Kconfig"