5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime"
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary, or theoretically 64K
208 for the MSM machine class.
210 config ARM_PATCH_PHYS_VIRT_16BIT
212 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
214 This option extends the physical to virtual translation patching
215 to allow physical memory down to a theoretical minimum of 64K
222 source "init/Kconfig"
224 source "kernel/Kconfig.freezer"
229 bool "MMU-based Paged Memory Management Support"
232 Select if you want MMU-based virtualised addressing space
233 support by paged memory management. If unsure, say 'Y'.
236 # The "ARM system type" choice list is ordered alphabetically by option
237 # text. Please add new entries in the option alphabetic order.
240 prompt "ARM system type"
241 default ARCH_VERSATILE
243 config ARCH_INTEGRATOR
244 bool "ARM Ltd. Integrator family"
246 select ARCH_HAS_CPUFREQ
248 select HAVE_MACH_CLKDEV
250 select GENERIC_CLOCKEVENTS
251 select PLAT_VERSATILE
252 select PLAT_VERSATILE_FPGA_IRQ
254 Support for ARM's Integrator platform.
257 bool "ARM Ltd. RealView family"
260 select HAVE_MACH_CLKDEV
262 select GENERIC_CLOCKEVENTS
263 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select PLAT_VERSATILE
265 select PLAT_VERSATILE_CLCD
266 select ARM_TIMER_SP804
267 select GPIO_PL061 if GPIOLIB
269 This enables support for ARM Ltd RealView boards.
271 config ARCH_VERSATILE
272 bool "ARM Ltd. Versatile family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLCD
282 select PLAT_VERSATILE_FPGA_IRQ
283 select ARM_TIMER_SP804
285 This enables support for ARM Ltd Versatile board.
288 bool "ARM Ltd. Versatile Express family"
289 select ARCH_WANT_OPTIONAL_GPIOLIB
291 select ARM_TIMER_SP804
293 select HAVE_MACH_CLKDEV
294 select GENERIC_CLOCKEVENTS
296 select HAVE_PATA_PLATFORM
298 select PLAT_VERSATILE
299 select PLAT_VERSATILE_CLCD
301 This enables support for the ARM Ltd Versatile Express boards.
305 select ARCH_REQUIRE_GPIOLIB
308 select ARM_PATCH_PHYS_VIRT if MMU
310 This enables support for systems based on the Atmel AT91RM9200,
311 AT91SAM9 and AT91CAP9 processors.
314 bool "Broadcom BCMRING"
318 select ARM_TIMER_SP804
320 select GENERIC_CLOCKEVENTS
321 select ARCH_WANT_OPTIONAL_GPIOLIB
323 Support for Broadcom's BCMRing platform.
326 bool "Cirrus Logic CLPS711x/EP721x-based"
328 select ARCH_USES_GETTIMEOFFSET
330 Support for Cirrus Logic 711x/721x based boards.
333 bool "Cavium Networks CNS3XXX family"
335 select GENERIC_CLOCKEVENTS
337 select MIGHT_HAVE_PCI
338 select PCI_DOMAINS if PCI
340 Support for Cavium Networks CNS3XXX platform.
343 bool "Cortina Systems Gemini"
345 select ARCH_REQUIRE_GPIOLIB
346 select ARCH_USES_GETTIMEOFFSET
348 Support for the Cortina Systems Gemini family SoCs
351 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
355 select GENERIC_CLOCKEVENTS
357 select GENERIC_IRQ_CHIP
361 Support for CSR SiRFSoC ARM Cortex A9 Platform
368 select ARCH_USES_GETTIMEOFFSET
370 This is an evaluation board for the StrongARM processor available
371 from Digital. It has limited hardware on-board, including an
372 Ethernet interface, two PCMCIA sockets, two serial ports and a
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_HAS_HOLES_MEMORYMODEL
383 select ARCH_USES_GETTIMEOFFSET
385 This enables support for the Cirrus EP93xx series of CPUs.
387 config ARCH_FOOTBRIDGE
391 select GENERIC_CLOCKEVENTS
393 Support for systems based on the DC21285 companion chip
394 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
397 bool "Freescale MXC/iMX-based"
398 select GENERIC_CLOCKEVENTS
399 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_IRQ_CHIP
403 select HAVE_SCHED_CLOCK
405 Support for Freescale MXC/iMX-based family of processors
408 bool "Freescale MXS-based"
409 select GENERIC_CLOCKEVENTS
410 select ARCH_REQUIRE_GPIOLIB
414 Support for Freescale MXS-based family of processors
417 bool "Hilscher NetX based"
421 select GENERIC_CLOCKEVENTS
423 This enables support for systems based on the Hilscher NetX Soc
426 bool "Hynix HMS720x-based"
429 select ARCH_USES_GETTIMEOFFSET
431 This enables support for systems based on the Hynix HMS720x
439 select ARCH_SUPPORTS_MSI
442 Support for Intel's IOP13XX (XScale) family of processors.
450 select ARCH_REQUIRE_GPIOLIB
452 Support for Intel's 80219 and IOP32X (XScale) family of
461 select ARCH_REQUIRE_GPIOLIB
463 Support for Intel's IOP33X (XScale) family of processors.
470 select ARCH_USES_GETTIMEOFFSET
472 Support for Intel's IXP23xx (XScale) family of processors.
475 bool "IXP2400/2800-based"
479 select ARCH_USES_GETTIMEOFFSET
481 Support for Intel's IXP2400/2800 (XScale) family of processors.
489 select GENERIC_CLOCKEVENTS
490 select HAVE_SCHED_CLOCK
491 select MIGHT_HAVE_PCI
492 select DMABOUNCE if PCI
494 Support for Intel's IXP4XX (XScale) family of processors.
500 select ARCH_REQUIRE_GPIOLIB
501 select GENERIC_CLOCKEVENTS
504 Support for the Marvell Dove SoC 88AP510
507 bool "Marvell Kirkwood"
510 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
514 Support for the following Marvell Kirkwood series SoCs:
515 88F6180, 88F6192 and 88F6281.
521 select ARCH_REQUIRE_GPIOLIB
524 select USB_ARCH_HAS_OHCI
527 select GENERIC_CLOCKEVENTS
529 Support for the NXP LPC32XX family of processors
532 bool "Marvell MV78xx0"
535 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
539 Support for the following Marvell MV78xx0 series SoCs:
547 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 Support for the following Marvell Orion 5x series SoCs:
552 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
553 Orion-2 (5281), Orion-1-90 (6183).
556 bool "Marvell PXA168/910/MMP2"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
561 select HAVE_SCHED_CLOCK
566 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
569 bool "Micrel/Kendin KS8695"
571 select ARCH_REQUIRE_GPIOLIB
572 select ARCH_USES_GETTIMEOFFSET
574 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
575 System-on-Chip devices.
578 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
585 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
586 At present, the w90x900 has been renamed nuc900, regarding
587 the ARM series product line, you can login the following
588 link address to know more.
590 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
591 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
594 bool "Nuvoton NUC93X CPU"
598 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
599 low-power and high performance MPEG-4/JPEG multimedia controller chip.
606 select GENERIC_CLOCKEVENTS
609 select HAVE_SCHED_CLOCK
610 select ARCH_HAS_CPUFREQ
612 This enables support for NVIDIA Tegra based systems (Tegra APX,
613 Tegra 6xx and Tegra 2 series).
616 bool "Philips Nexperia PNX4008 Mobile"
619 select ARCH_USES_GETTIMEOFFSET
621 This enables support for Philips PNX4008 mobile platform.
624 bool "PXA2xx/PXA3xx-based"
627 select ARCH_HAS_CPUFREQ
630 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
632 select HAVE_SCHED_CLOCK
637 select MULTI_IRQ_HANDLER
639 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
644 select GENERIC_CLOCKEVENTS
645 select ARCH_REQUIRE_GPIOLIB
648 Support for Qualcomm MSM/QSD based systems. This runs on the
649 apps processor of the MSM/QSD and depends on a shared memory
650 interface to the modem processor which runs the baseband
651 stack and controls some vital subsystems
652 (clock and power control, etc).
655 bool "Renesas SH-Mobile / R-Mobile"
658 select HAVE_MACH_CLKDEV
659 select GENERIC_CLOCKEVENTS
662 select MULTI_IRQ_HANDLER
663 select PM_GENERIC_DOMAINS if PM
665 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
672 select ARCH_MAY_HAVE_PC_FDC
673 select HAVE_PATA_PLATFORM
676 select ARCH_SPARSEMEM_ENABLE
677 select ARCH_USES_GETTIMEOFFSET
679 On the Acorn Risc-PC, Linux can support the internal IDE disk and
680 CD-ROM interface, serial and parallel port, and the floppy drive.
687 select ARCH_SPARSEMEM_ENABLE
689 select ARCH_HAS_CPUFREQ
691 select GENERIC_CLOCKEVENTS
693 select HAVE_SCHED_CLOCK
695 select ARCH_REQUIRE_GPIOLIB
697 Support for StrongARM 11x0 based boards.
700 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
702 select ARCH_HAS_CPUFREQ
705 select ARCH_USES_GETTIMEOFFSET
706 select HAVE_S3C2410_I2C if I2C
708 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
709 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
710 the Samsung SMDK2410 development board (and derivatives).
712 Note, the S3C2416 and the S3C2450 are so close that they even share
713 the same SoC ID code. This means that there is no separate machine
714 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
717 bool "Samsung S3C64XX"
724 select ARCH_USES_GETTIMEOFFSET
725 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
727 select SAMSUNG_CLKSRC
728 select SAMSUNG_IRQ_VIC_TIMER
729 select SAMSUNG_IRQ_UART
730 select S3C_GPIO_TRACK
731 select S3C_GPIO_PULL_UPDOWN
732 select S3C_GPIO_CFG_S3C24XX
733 select S3C_GPIO_CFG_S3C64XX
735 select USB_ARCH_HAS_OHCI
736 select SAMSUNG_GPIOLIB_4BIT
737 select HAVE_S3C2410_I2C if I2C
738 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 Samsung S3C64XX series based systems
743 bool "Samsung S5P6440 S5P6450"
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
750 select GENERIC_CLOCKEVENTS
751 select HAVE_SCHED_CLOCK
752 select HAVE_S3C2410_I2C if I2C
753 select HAVE_S3C_RTC if RTC_CLASS
755 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
759 bool "Samsung S5PC100"
764 select ARM_L1_CACHE_SHIFT_6
765 select ARCH_USES_GETTIMEOFFSET
766 select HAVE_S3C2410_I2C if I2C
767 select HAVE_S3C_RTC if RTC_CLASS
768 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 Samsung S5PC100 series based systems
773 bool "Samsung S5PV210/S5PC110"
775 select ARCH_SPARSEMEM_ENABLE
776 select ARCH_HAS_HOLES_MEMORYMODEL
781 select ARM_L1_CACHE_SHIFT_6
782 select ARCH_HAS_CPUFREQ
783 select GENERIC_CLOCKEVENTS
784 select HAVE_SCHED_CLOCK
785 select HAVE_S3C2410_I2C if I2C
786 select HAVE_S3C_RTC if RTC_CLASS
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 Samsung S5PV210/S5PC110 series based systems
792 bool "Samsung EXYNOS4"
794 select ARCH_SPARSEMEM_ENABLE
795 select ARCH_HAS_HOLES_MEMORYMODEL
799 select ARCH_HAS_CPUFREQ
800 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C_RTC if RTC_CLASS
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 Samsung EXYNOS4 series based systems
814 select ARCH_USES_GETTIMEOFFSET
816 Support for the StrongARM based Digital DNARD machine, also known
817 as "Shark" (<http://www.shark-linux.de/shark.html>).
820 bool "Telechips TCC ARM926-based systems"
825 select GENERIC_CLOCKEVENTS
827 Support for Telechips TCC ARM926-based systems.
830 bool "ST-Ericsson U300 Series"
834 select HAVE_SCHED_CLOCK
838 select GENERIC_CLOCKEVENTS
840 select HAVE_MACH_CLKDEV
843 Support for ST-Ericsson U300 series mobile platforms.
846 bool "ST-Ericsson U8500 Series"
849 select GENERIC_CLOCKEVENTS
851 select ARCH_REQUIRE_GPIOLIB
852 select ARCH_HAS_CPUFREQ
854 Support for ST-Ericsson's Ux500 architecture
857 bool "STMicroelectronics Nomadik"
862 select GENERIC_CLOCKEVENTS
863 select ARCH_REQUIRE_GPIOLIB
865 Support for the Nomadik platform by ST-Ericsson
869 select GENERIC_CLOCKEVENTS
870 select ARCH_REQUIRE_GPIOLIB
874 select GENERIC_ALLOCATOR
875 select GENERIC_IRQ_CHIP
876 select ARCH_HAS_HOLES_MEMORYMODEL
878 Support for TI's DaVinci platform.
883 select ARCH_REQUIRE_GPIOLIB
884 select ARCH_HAS_CPUFREQ
886 select GENERIC_CLOCKEVENTS
887 select HAVE_SCHED_CLOCK
888 select ARCH_HAS_HOLES_MEMORYMODEL
890 Support for TI's OMAP platform (OMAP1/2/3/4).
895 select ARCH_REQUIRE_GPIOLIB
898 select GENERIC_CLOCKEVENTS
901 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
904 bool "VIA/WonderMedia 85xx"
907 select ARCH_HAS_CPUFREQ
908 select GENERIC_CLOCKEVENTS
909 select ARCH_REQUIRE_GPIOLIB
912 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
915 bool "Xilinx Zynq ARM Cortex A9 Platform"
918 select GENERIC_CLOCKEVENTS
925 Support for Xilinx Zynq ARM Cortex A9 Platform
929 # This is sorted alphabetically by mach-* pathname. However, plat-*
930 # Kconfigs may be included either alphabetically (according to the
931 # plat- suffix) or along side the corresponding mach-* source.
933 source "arch/arm/mach-at91/Kconfig"
935 source "arch/arm/mach-bcmring/Kconfig"
937 source "arch/arm/mach-clps711x/Kconfig"
939 source "arch/arm/mach-cns3xxx/Kconfig"
941 source "arch/arm/mach-davinci/Kconfig"
943 source "arch/arm/mach-dove/Kconfig"
945 source "arch/arm/mach-ep93xx/Kconfig"
947 source "arch/arm/mach-footbridge/Kconfig"
949 source "arch/arm/mach-gemini/Kconfig"
951 source "arch/arm/mach-h720x/Kconfig"
953 source "arch/arm/mach-integrator/Kconfig"
955 source "arch/arm/mach-iop32x/Kconfig"
957 source "arch/arm/mach-iop33x/Kconfig"
959 source "arch/arm/mach-iop13xx/Kconfig"
961 source "arch/arm/mach-ixp4xx/Kconfig"
963 source "arch/arm/mach-ixp2000/Kconfig"
965 source "arch/arm/mach-ixp23xx/Kconfig"
967 source "arch/arm/mach-kirkwood/Kconfig"
969 source "arch/arm/mach-ks8695/Kconfig"
971 source "arch/arm/mach-lpc32xx/Kconfig"
973 source "arch/arm/mach-msm/Kconfig"
975 source "arch/arm/mach-mv78xx0/Kconfig"
977 source "arch/arm/plat-mxc/Kconfig"
979 source "arch/arm/mach-mxs/Kconfig"
981 source "arch/arm/mach-netx/Kconfig"
983 source "arch/arm/mach-nomadik/Kconfig"
984 source "arch/arm/plat-nomadik/Kconfig"
986 source "arch/arm/mach-nuc93x/Kconfig"
988 source "arch/arm/plat-omap/Kconfig"
990 source "arch/arm/mach-omap1/Kconfig"
992 source "arch/arm/mach-omap2/Kconfig"
994 source "arch/arm/mach-orion5x/Kconfig"
996 source "arch/arm/mach-pxa/Kconfig"
997 source "arch/arm/plat-pxa/Kconfig"
999 source "arch/arm/mach-mmp/Kconfig"
1001 source "arch/arm/mach-realview/Kconfig"
1003 source "arch/arm/mach-sa1100/Kconfig"
1005 source "arch/arm/plat-samsung/Kconfig"
1006 source "arch/arm/plat-s3c24xx/Kconfig"
1007 source "arch/arm/plat-s5p/Kconfig"
1009 source "arch/arm/plat-spear/Kconfig"
1011 source "arch/arm/plat-tcc/Kconfig"
1014 source "arch/arm/mach-s3c2410/Kconfig"
1015 source "arch/arm/mach-s3c2412/Kconfig"
1016 source "arch/arm/mach-s3c2416/Kconfig"
1017 source "arch/arm/mach-s3c2440/Kconfig"
1018 source "arch/arm/mach-s3c2443/Kconfig"
1022 source "arch/arm/mach-s3c64xx/Kconfig"
1025 source "arch/arm/mach-s5p64x0/Kconfig"
1027 source "arch/arm/mach-s5pc100/Kconfig"
1029 source "arch/arm/mach-s5pv210/Kconfig"
1031 source "arch/arm/mach-exynos4/Kconfig"
1033 source "arch/arm/mach-shmobile/Kconfig"
1035 source "arch/arm/mach-tegra/Kconfig"
1037 source "arch/arm/mach-u300/Kconfig"
1039 source "arch/arm/mach-ux500/Kconfig"
1041 source "arch/arm/mach-versatile/Kconfig"
1043 source "arch/arm/mach-vexpress/Kconfig"
1044 source "arch/arm/plat-versatile/Kconfig"
1046 source "arch/arm/mach-vt8500/Kconfig"
1048 source "arch/arm/mach-w90x900/Kconfig"
1050 # Definitions to make life easier
1056 select GENERIC_CLOCKEVENTS
1057 select HAVE_SCHED_CLOCK
1062 select GENERIC_IRQ_CHIP
1063 select HAVE_SCHED_CLOCK
1068 config PLAT_VERSATILE
1071 config ARM_TIMER_SP804
1075 source arch/arm/mm/Kconfig
1078 bool "Enable iWMMXt support"
1079 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1080 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1082 Enable support for iWMMXt context switching at run time if
1083 running on a CPU that supports it.
1085 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1088 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1092 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1093 (!ARCH_OMAP3 || OMAP3_EMU)
1097 config MULTI_IRQ_HANDLER
1100 Allow each machine to specify it's own IRQ handler at run time.
1103 source "arch/arm/Kconfig-nommu"
1106 config ARM_ERRATA_411920
1107 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1108 depends on CPU_V6 || CPU_V6K
1110 Invalidation of the Instruction Cache operation can
1111 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1112 It does not affect the MPCore. This option enables the ARM Ltd.
1113 recommended workaround.
1115 config ARM_ERRATA_430973
1116 bool "ARM errata: Stale prediction on replaced interworking branch"
1119 This option enables the workaround for the 430973 Cortex-A8
1120 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1121 interworking branch is replaced with another code sequence at the
1122 same virtual address, whether due to self-modifying code or virtual
1123 to physical address re-mapping, Cortex-A8 does not recover from the
1124 stale interworking branch prediction. This results in Cortex-A8
1125 executing the new code sequence in the incorrect ARM or Thumb state.
1126 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1127 and also flushes the branch target cache at every context switch.
1128 Note that setting specific bits in the ACTLR register may not be
1129 available in non-secure mode.
1131 config ARM_ERRATA_458693
1132 bool "ARM errata: Processor deadlock when a false hazard is created"
1135 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1136 erratum. For very specific sequences of memory operations, it is
1137 possible for a hazard condition intended for a cache line to instead
1138 be incorrectly associated with a different cache line. This false
1139 hazard might then cause a processor deadlock. The workaround enables
1140 the L1 caching of the NEON accesses and disables the PLD instruction
1141 in the ACTLR register. Note that setting specific bits in the ACTLR
1142 register may not be available in non-secure mode.
1144 config ARM_ERRATA_460075
1145 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1148 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1149 erratum. Any asynchronous access to the L2 cache may encounter a
1150 situation in which recent store transactions to the L2 cache are lost
1151 and overwritten with stale memory contents from external memory. The
1152 workaround disables the write-allocate mode for the L2 cache via the
1153 ACTLR register. Note that setting specific bits in the ACTLR register
1154 may not be available in non-secure mode.
1156 config ARM_ERRATA_742230
1157 bool "ARM errata: DMB operation may be faulty"
1158 depends on CPU_V7 && SMP
1160 This option enables the workaround for the 742230 Cortex-A9
1161 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1162 between two write operations may not ensure the correct visibility
1163 ordering of the two writes. This workaround sets a specific bit in
1164 the diagnostic register of the Cortex-A9 which causes the DMB
1165 instruction to behave as a DSB, ensuring the correct behaviour of
1168 config ARM_ERRATA_742231
1169 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1170 depends on CPU_V7 && SMP
1172 This option enables the workaround for the 742231 Cortex-A9
1173 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1174 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1175 accessing some data located in the same cache line, may get corrupted
1176 data due to bad handling of the address hazard when the line gets
1177 replaced from one of the CPUs at the same time as another CPU is
1178 accessing it. This workaround sets specific bits in the diagnostic
1179 register of the Cortex-A9 which reduces the linefill issuing
1180 capabilities of the processor.
1182 config PL310_ERRATA_588369
1183 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1184 depends on CACHE_L2X0
1186 The PL310 L2 cache controller implements three types of Clean &
1187 Invalidate maintenance operations: by Physical Address
1188 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1189 They are architecturally defined to behave as the execution of a
1190 clean operation followed immediately by an invalidate operation,
1191 both performing to the same memory location. This functionality
1192 is not correctly implemented in PL310 as clean lines are not
1193 invalidated as a result of these operations.
1195 config ARM_ERRATA_720789
1196 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1197 depends on CPU_V7 && SMP
1199 This option enables the workaround for the 720789 Cortex-A9 (prior to
1200 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1201 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1202 As a consequence of this erratum, some TLB entries which should be
1203 invalidated are not, resulting in an incoherency in the system page
1204 tables. The workaround changes the TLB flushing routines to invalidate
1205 entries regardless of the ASID.
1207 config PL310_ERRATA_727915
1208 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1209 depends on CACHE_L2X0
1211 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1212 operation (offset 0x7FC). This operation runs in background so that
1213 PL310 can handle normal accesses while it is in progress. Under very
1214 rare circumstances, due to this erratum, write data can be lost when
1215 PL310 treats a cacheable write transaction during a Clean &
1216 Invalidate by Way operation.
1218 config ARM_ERRATA_743622
1219 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1222 This option enables the workaround for the 743622 Cortex-A9
1223 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1224 optimisation in the Cortex-A9 Store Buffer may lead to data
1225 corruption. This workaround sets a specific bit in the diagnostic
1226 register of the Cortex-A9 which disables the Store Buffer
1227 optimisation, preventing the defect from occurring. This has no
1228 visible impact on the overall performance or power consumption of the
1231 config ARM_ERRATA_751472
1232 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1233 depends on CPU_V7 && SMP
1235 This option enables the workaround for the 751472 Cortex-A9 (prior
1236 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1237 completion of a following broadcasted operation if the second
1238 operation is received by a CPU before the ICIALLUIS has completed,
1239 potentially leading to corrupted entries in the cache or TLB.
1241 config ARM_ERRATA_753970
1242 bool "ARM errata: cache sync operation may be faulty"
1243 depends on CACHE_PL310
1245 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1247 Under some condition the effect of cache sync operation on
1248 the store buffer still remains when the operation completes.
1249 This means that the store buffer is always asked to drain and
1250 this prevents it from merging any further writes. The workaround
1251 is to replace the normal offset of cache sync operation (0x730)
1252 by another offset targeting an unmapped PL310 register 0x740.
1253 This has the same effect as the cache sync operation: store buffer
1254 drain and waiting for all buffers empty.
1256 config ARM_ERRATA_754322
1257 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1260 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1261 r3p*) erratum. A speculative memory access may cause a page table walk
1262 which starts prior to an ASID switch but completes afterwards. This
1263 can populate the micro-TLB with a stale entry which may be hit with
1264 the new ASID. This workaround places two dsb instructions in the mm
1265 switching code so that no page table walks can cross the ASID switch.
1267 config ARM_ERRATA_754327
1268 bool "ARM errata: no automatic Store Buffer drain"
1269 depends on CPU_V7 && SMP
1271 This option enables the workaround for the 754327 Cortex-A9 (prior to
1272 r2p0) erratum. The Store Buffer does not have any automatic draining
1273 mechanism and therefore a livelock may occur if an external agent
1274 continuously polls a memory location waiting to observe an update.
1275 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1276 written polling loops from denying visibility of updates to memory.
1278 config ARM_ERRATA_364296
1279 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1280 depends on CPU_V6 && !SMP
1282 This options enables the workaround for the 364296 ARM1136
1283 r0p2 erratum (possible cache data corruption with
1284 hit-under-miss enabled). It sets the undocumented bit 31 in
1285 the auxiliary control register and the FI bit in the control
1286 register, thus disabling hit-under-miss without putting the
1287 processor into full low interrupt latency mode. ARM11MPCore
1292 source "arch/arm/common/Kconfig"
1302 Find out whether you have ISA slots on your motherboard. ISA is the
1303 name of a bus system, i.e. the way the CPU talks to the other stuff
1304 inside your box. Other bus systems are PCI, EISA, MicroChannel
1305 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1306 newer boards don't support it. If you have ISA, say Y, otherwise N.
1308 # Select ISA DMA controller support
1313 # Select ISA DMA interface
1318 bool "PCI support" if MIGHT_HAVE_PCI
1320 Find out whether you have a PCI motherboard. PCI is the name of a
1321 bus system, i.e. the way the CPU talks to the other stuff inside
1322 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1323 VESA. If you have PCI, say Y, otherwise N.
1329 config PCI_NANOENGINE
1330 bool "BSE nanoEngine PCI support"
1331 depends on SA1100_NANOENGINE
1333 Enable PCI on the BSE nanoEngine board.
1338 # Select the host bridge type
1339 config PCI_HOST_VIA82C505
1341 depends on PCI && ARCH_SHARK
1344 config PCI_HOST_ITE8152
1346 depends on PCI && MACH_ARMCORE
1350 source "drivers/pci/Kconfig"
1352 source "drivers/pcmcia/Kconfig"
1356 menu "Kernel Features"
1358 source "kernel/time/Kconfig"
1361 bool "Symmetric Multi-Processing"
1362 depends on CPU_V6K || CPU_V7
1363 depends on GENERIC_CLOCKEVENTS
1364 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1365 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1366 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1367 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1368 select USE_GENERIC_SMP_HELPERS
1369 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1371 This enables support for systems with more than one CPU. If you have
1372 a system with only one CPU, like most personal computers, say N. If
1373 you have a system with more than one CPU, say Y.
1375 If you say N here, the kernel will run on single and multiprocessor
1376 machines, but will use only one CPU of a multiprocessor machine. If
1377 you say Y here, the kernel will run on many, but not all, single
1378 processor machines. On a single processor machine, the kernel will
1379 run faster if you say N here.
1381 See also <file:Documentation/i386/IO-APIC.txt>,
1382 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1383 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1385 If you don't know what to do here, say N.
1388 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1389 depends on EXPERIMENTAL
1390 depends on SMP && !XIP_KERNEL
1393 SMP kernels contain instructions which fail on non-SMP processors.
1394 Enabling this option allows the kernel to modify itself to make
1395 these instructions safe. Disabling it allows about 1K of space
1398 If you don't know what to do here, say Y.
1403 This option enables support for the ARM system coherency unit
1410 This options enables support for the ARM timer and watchdog unit
1413 prompt "Memory split"
1416 Select the desired split between kernel and user memory.
1418 If you are not absolutely sure what you are doing, leave this
1422 bool "3G/1G user/kernel split"
1424 bool "2G/2G user/kernel split"
1426 bool "1G/3G user/kernel split"
1431 default 0x40000000 if VMSPLIT_1G
1432 default 0x80000000 if VMSPLIT_2G
1436 int "Maximum number of CPUs (2-32)"
1442 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1443 depends on SMP && HOTPLUG && EXPERIMENTAL
1445 Say Y here to experiment with turning CPUs off and on. CPUs
1446 can be controlled through /sys/devices/system/cpu.
1449 bool "Use local timer interrupts"
1452 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1454 Enable support for local timers on SMP platforms, rather then the
1455 legacy IPI broadcast method. Local timers allows the system
1456 accounting to be spread across the timer interval, preventing a
1457 "thundering herd" at every timer tick.
1459 source kernel/Kconfig.preempt
1463 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1464 ARCH_S5PV210 || ARCH_EXYNOS4
1465 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1466 default AT91_TIMER_HZ if ARCH_AT91
1467 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1470 config THUMB2_KERNEL
1471 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1472 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1474 select ARM_ASM_UNIFIED
1476 By enabling this option, the kernel will be compiled in
1477 Thumb-2 mode. A compiler/assembler that understand the unified
1478 ARM-Thumb syntax is needed.
1482 config THUMB2_AVOID_R_ARM_THM_JUMP11
1483 bool "Work around buggy Thumb-2 short branch relocations in gas"
1484 depends on THUMB2_KERNEL && MODULES
1487 Various binutils versions can resolve Thumb-2 branches to
1488 locally-defined, preemptible global symbols as short-range "b.n"
1489 branch instructions.
1491 This is a problem, because there's no guarantee the final
1492 destination of the symbol, or any candidate locations for a
1493 trampoline, are within range of the branch. For this reason, the
1494 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1495 relocation in modules at all, and it makes little sense to add
1498 The symptom is that the kernel fails with an "unsupported
1499 relocation" error when loading some modules.
1501 Until fixed tools are available, passing
1502 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1503 code which hits this problem, at the cost of a bit of extra runtime
1504 stack usage in some cases.
1506 The problem is described in more detail at:
1507 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1509 Only Thumb-2 kernels are affected.
1511 Unless you are sure your tools don't have this problem, say Y.
1513 config ARM_ASM_UNIFIED
1517 bool "Use the ARM EABI to compile the kernel"
1519 This option allows for the kernel to be compiled using the latest
1520 ARM ABI (aka EABI). This is only useful if you are using a user
1521 space environment that is also compiled with EABI.
1523 Since there are major incompatibilities between the legacy ABI and
1524 EABI, especially with regard to structure member alignment, this
1525 option also changes the kernel syscall calling convention to
1526 disambiguate both ABIs and allow for backward compatibility support
1527 (selected with CONFIG_OABI_COMPAT).
1529 To use this you need GCC version 4.0.0 or later.
1532 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1533 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1536 This option preserves the old syscall interface along with the
1537 new (ARM EABI) one. It also provides a compatibility layer to
1538 intercept syscalls that have structure arguments which layout
1539 in memory differs between the legacy ABI and the new ARM EABI
1540 (only for non "thumb" binaries). This option adds a tiny
1541 overhead to all syscalls and produces a slightly larger kernel.
1542 If you know you'll be using only pure EABI user space then you
1543 can say N here. If this option is not selected and you attempt
1544 to execute a legacy ABI binary then the result will be
1545 UNPREDICTABLE (in fact it can be predicted that it won't work
1546 at all). If in doubt say Y.
1548 config ARCH_HAS_HOLES_MEMORYMODEL
1551 config ARCH_SPARSEMEM_ENABLE
1554 config ARCH_SPARSEMEM_DEFAULT
1555 def_bool ARCH_SPARSEMEM_ENABLE
1557 config ARCH_SELECT_MEMORY_MODEL
1558 def_bool ARCH_SPARSEMEM_ENABLE
1560 config HAVE_ARCH_PFN_VALID
1561 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1564 bool "High Memory Support"
1567 The address space of ARM processors is only 4 Gigabytes large
1568 and it has to accommodate user address space, kernel address
1569 space as well as some memory mapped IO. That means that, if you
1570 have a large amount of physical memory and/or IO, not all of the
1571 memory can be "permanently mapped" by the kernel. The physical
1572 memory that is not permanently mapped is called "high memory".
1574 Depending on the selected kernel/user memory split, minimum
1575 vmalloc space and actual amount of RAM, you may not need this
1576 option which should result in a slightly faster kernel.
1581 bool "Allocate 2nd-level pagetables from highmem"
1584 config HW_PERF_EVENTS
1585 bool "Enable hardware performance counter support for perf events"
1586 depends on PERF_EVENTS && CPU_HAS_PMU
1589 Enable hardware performance counter support for perf events. If
1590 disabled, perf events will use software events only.
1594 config FORCE_MAX_ZONEORDER
1595 int "Maximum zone order" if ARCH_SHMOBILE
1596 range 11 64 if ARCH_SHMOBILE
1597 default "9" if SA1111
1600 The kernel memory allocator divides physically contiguous memory
1601 blocks into "zones", where each zone is a power of two number of
1602 pages. This option selects the largest power of two that the kernel
1603 keeps in the memory allocator. If you need to allocate very large
1604 blocks of physically contiguous memory, then you may need to
1605 increase this value.
1607 This config option is actually maximum order plus one. For example,
1608 a value of 11 means that the largest free memory block is 2^10 pages.
1611 bool "Timer and CPU usage LEDs"
1612 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1613 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1614 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1615 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1616 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1617 ARCH_AT91 || ARCH_DAVINCI || \
1618 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1620 If you say Y here, the LEDs on your machine will be used
1621 to provide useful information about your current system status.
1623 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1624 be able to select which LEDs are active using the options below. If
1625 you are compiling a kernel for the EBSA-110 or the LART however, the
1626 red LED will simply flash regularly to indicate that the system is
1627 still functional. It is safe to say Y here if you have a CATS
1628 system, but the driver will do nothing.
1631 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1632 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1633 || MACH_OMAP_PERSEUS2
1635 depends on !GENERIC_CLOCKEVENTS
1636 default y if ARCH_EBSA110
1638 If you say Y here, one of the system LEDs (the green one on the
1639 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1640 will flash regularly to indicate that the system is still
1641 operational. This is mainly useful to kernel hackers who are
1642 debugging unstable kernels.
1644 The LART uses the same LED for both Timer LED and CPU usage LED
1645 functions. You may choose to use both, but the Timer LED function
1646 will overrule the CPU usage LED.
1649 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1651 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1652 || MACH_OMAP_PERSEUS2
1655 If you say Y here, the red LED will be used to give a good real
1656 time indication of CPU usage, by lighting whenever the idle task
1657 is not currently executing.
1659 The LART uses the same LED for both Timer LED and CPU usage LED
1660 functions. You may choose to use both, but the Timer LED function
1661 will overrule the CPU usage LED.
1663 config ALIGNMENT_TRAP
1665 depends on CPU_CP15_MMU
1666 default y if !ARCH_EBSA110
1667 select HAVE_PROC_CPU if PROC_FS
1669 ARM processors cannot fetch/store information which is not
1670 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1671 address divisible by 4. On 32-bit ARM processors, these non-aligned
1672 fetch/store instructions will be emulated in software if you say
1673 here, which has a severe performance impact. This is necessary for
1674 correct operation of some network protocols. With an IP-only
1675 configuration it is safe to say N, otherwise say Y.
1677 config UACCESS_WITH_MEMCPY
1678 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1679 depends on MMU && EXPERIMENTAL
1680 default y if CPU_FEROCEON
1682 Implement faster copy_to_user and clear_user methods for CPU
1683 cores where a 8-word STM instruction give significantly higher
1684 memory write throughput than a sequence of individual 32bit stores.
1686 A possible side effect is a slight increase in scheduling latency
1687 between threads sharing the same address space if they invoke
1688 such copy operations with large buffers.
1690 However, if the CPU data cache is using a write-allocate mode,
1691 this option is unlikely to provide any performance gain.
1695 prompt "Enable seccomp to safely compute untrusted bytecode"
1697 This kernel feature is useful for number crunching applications
1698 that may need to compute untrusted bytecode during their
1699 execution. By using pipes or other transports made available to
1700 the process as file descriptors supporting the read/write
1701 syscalls, it's possible to isolate those applications in
1702 their own address space using seccomp. Once seccomp is
1703 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1704 and the task is only allowed to execute a few safe syscalls
1705 defined by each seccomp mode.
1707 config CC_STACKPROTECTOR
1708 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1709 depends on EXPERIMENTAL
1711 This option turns on the -fstack-protector GCC feature. This
1712 feature puts, at the beginning of functions, a canary value on
1713 the stack just before the return address, and validates
1714 the value just before actually returning. Stack based buffer
1715 overflows (that need to overwrite this return address) now also
1716 overwrite the canary, which gets detected and the attack is then
1717 neutralized via a kernel panic.
1718 This feature requires gcc version 4.2 or above.
1720 config DEPRECATED_PARAM_STRUCT
1721 bool "Provide old way to pass kernel parameters"
1723 This was deprecated in 2001 and announced to live on for 5 years.
1724 Some old boot loaders still use this way.
1731 bool "Flattened Device Tree support"
1733 select OF_EARLY_FLATTREE
1736 Include support for flattened device tree machine descriptions.
1738 # Compressed boot loader in ROM. Yes, we really want to ask about
1739 # TEXT and BSS so we preserve their values in the config files.
1740 config ZBOOT_ROM_TEXT
1741 hex "Compressed ROM boot loader base address"
1744 The physical address at which the ROM-able zImage is to be
1745 placed in the target. Platforms which normally make use of
1746 ROM-able zImage formats normally set this to a suitable
1747 value in their defconfig file.
1749 If ZBOOT_ROM is not enabled, this has no effect.
1751 config ZBOOT_ROM_BSS
1752 hex "Compressed ROM boot loader BSS address"
1755 The base address of an area of read/write memory in the target
1756 for the ROM-able zImage which must be available while the
1757 decompressor is running. It must be large enough to hold the
1758 entire decompressed kernel plus an additional 128 KiB.
1759 Platforms which normally make use of ROM-able zImage formats
1760 normally set this to a suitable value in their defconfig file.
1762 If ZBOOT_ROM is not enabled, this has no effect.
1765 bool "Compressed boot loader in ROM/flash"
1766 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1768 Say Y here if you intend to execute your compressed kernel image
1769 (zImage) directly from ROM or flash. If unsure, say N.
1772 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1773 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1774 default ZBOOT_ROM_NONE
1776 Include experimental SD/MMC loading code in the ROM-able zImage.
1777 With this enabled it is possible to write the the ROM-able zImage
1778 kernel image to an MMC or SD card and boot the kernel straight
1779 from the reset vector. At reset the processor Mask ROM will load
1780 the first part of the the ROM-able zImage which in turn loads the
1781 rest the kernel image to RAM.
1783 config ZBOOT_ROM_NONE
1784 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1786 Do not load image from SD or MMC
1788 config ZBOOT_ROM_MMCIF
1789 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1791 Load image from MMCIF hardware block.
1793 config ZBOOT_ROM_SH_MOBILE_SDHI
1794 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1796 Load image from SDHI hardware block
1801 string "Default kernel command string"
1804 On some architectures (EBSA110 and CATS), there is currently no way
1805 for the boot loader to pass arguments to the kernel. For these
1806 architectures, you should supply some command-line options at build
1807 time by entering them here. As a minimum, you should specify the
1808 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1811 prompt "Kernel command line type" if CMDLINE != ""
1812 default CMDLINE_FROM_BOOTLOADER
1814 config CMDLINE_FROM_BOOTLOADER
1815 bool "Use bootloader kernel arguments if available"
1817 Uses the command-line options passed by the boot loader. If
1818 the boot loader doesn't provide any, the default kernel command
1819 string provided in CMDLINE will be used.
1821 config CMDLINE_EXTEND
1822 bool "Extend bootloader kernel arguments"
1824 The command-line arguments provided by the boot loader will be
1825 appended to the default kernel command string.
1827 config CMDLINE_FORCE
1828 bool "Always use the default kernel command string"
1830 Always use the default kernel command string, even if the boot
1831 loader passes other arguments to the kernel.
1832 This is useful if you cannot or don't want to change the
1833 command-line options your boot loader passes to the kernel.
1837 bool "Kernel Execute-In-Place from ROM"
1838 depends on !ZBOOT_ROM
1840 Execute-In-Place allows the kernel to run from non-volatile storage
1841 directly addressable by the CPU, such as NOR flash. This saves RAM
1842 space since the text section of the kernel is not loaded from flash
1843 to RAM. Read-write sections, such as the data section and stack,
1844 are still copied to RAM. The XIP kernel is not compressed since
1845 it has to run directly from flash, so it will take more space to
1846 store it. The flash address used to link the kernel object files,
1847 and for storing it, is configuration dependent. Therefore, if you
1848 say Y here, you must know the proper physical address where to
1849 store the kernel image depending on your own flash memory usage.
1851 Also note that the make target becomes "make xipImage" rather than
1852 "make zImage" or "make Image". The final kernel binary to put in
1853 ROM memory will be arch/arm/boot/xipImage.
1857 config XIP_PHYS_ADDR
1858 hex "XIP Kernel Physical Location"
1859 depends on XIP_KERNEL
1860 default "0x00080000"
1862 This is the physical address in your flash memory the kernel will
1863 be linked for and stored to. This address is dependent on your
1867 bool "Kexec system call (EXPERIMENTAL)"
1868 depends on EXPERIMENTAL
1870 kexec is a system call that implements the ability to shutdown your
1871 current kernel, and to start another kernel. It is like a reboot
1872 but it is independent of the system firmware. And like a reboot
1873 you can start any kernel with it, not just Linux.
1875 It is an ongoing process to be certain the hardware in a machine
1876 is properly shutdown, so do not be surprised if this code does not
1877 initially work for you. It may help to enable device hotplugging
1881 bool "Export atags in procfs"
1885 Should the atags used to boot the kernel be exported in an "atags"
1886 file in procfs. Useful with kexec.
1889 bool "Build kdump crash kernel (EXPERIMENTAL)"
1890 depends on EXPERIMENTAL
1892 Generate crash dump after being started by kexec. This should
1893 be normally only set in special crash dump kernels which are
1894 loaded in the main kernel with kexec-tools into a specially
1895 reserved region and then later executed after a crash by
1896 kdump/kexec. The crash dump kernel must be compiled to a
1897 memory address not used by the main kernel
1899 For more details see Documentation/kdump/kdump.txt
1901 config AUTO_ZRELADDR
1902 bool "Auto calculation of the decompressed kernel image address"
1903 depends on !ZBOOT_ROM && !ARCH_U300
1905 ZRELADDR is the physical address where the decompressed kernel
1906 image will be placed. If AUTO_ZRELADDR is selected, the address
1907 will be determined at run-time by masking the current IP with
1908 0xf8000000. This assumes the zImage being placed in the first 128MB
1909 from start of memory.
1913 menu "CPU Power Management"
1917 source "drivers/cpufreq/Kconfig"
1920 tristate "CPUfreq driver for i.MX CPUs"
1921 depends on ARCH_MXC && CPU_FREQ
1923 This enables the CPUfreq driver for i.MX CPUs.
1925 config CPU_FREQ_SA1100
1928 config CPU_FREQ_SA1110
1931 config CPU_FREQ_INTEGRATOR
1932 tristate "CPUfreq driver for ARM Integrator CPUs"
1933 depends on ARCH_INTEGRATOR && CPU_FREQ
1936 This enables the CPUfreq driver for ARM Integrator CPUs.
1938 For details, take a look at <file:Documentation/cpu-freq>.
1944 depends on CPU_FREQ && ARCH_PXA && PXA25x
1946 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1951 Internal configuration node for common cpufreq on Samsung SoC
1953 config CPU_FREQ_S3C24XX
1954 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1955 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1958 This enables the CPUfreq driver for the Samsung S3C24XX family
1961 For details, take a look at <file:Documentation/cpu-freq>.
1965 config CPU_FREQ_S3C24XX_PLL
1966 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1967 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1969 Compile in support for changing the PLL frequency from the
1970 S3C24XX series CPUfreq driver. The PLL takes time to settle
1971 after a frequency change, so by default it is not enabled.
1973 This also means that the PLL tables for the selected CPU(s) will
1974 be built which may increase the size of the kernel image.
1976 config CPU_FREQ_S3C24XX_DEBUG
1977 bool "Debug CPUfreq Samsung driver core"
1978 depends on CPU_FREQ_S3C24XX
1980 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1982 config CPU_FREQ_S3C24XX_IODEBUG
1983 bool "Debug CPUfreq Samsung driver IO timing"
1984 depends on CPU_FREQ_S3C24XX
1986 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1988 config CPU_FREQ_S3C24XX_DEBUGFS
1989 bool "Export debugfs for CPUFreq"
1990 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1992 Export status information via debugfs.
1996 source "drivers/cpuidle/Kconfig"
2000 menu "Floating point emulation"
2002 comment "At least one emulation must be selected"
2005 bool "NWFPE math emulation"
2006 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2008 Say Y to include the NWFPE floating point emulator in the kernel.
2009 This is necessary to run most binaries. Linux does not currently
2010 support floating point hardware so you need to say Y here even if
2011 your machine has an FPA or floating point co-processor podule.
2013 You may say N here if you are going to load the Acorn FPEmulator
2014 early in the bootup.
2017 bool "Support extended precision"
2018 depends on FPE_NWFPE
2020 Say Y to include 80-bit support in the kernel floating-point
2021 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2022 Note that gcc does not generate 80-bit operations by default,
2023 so in most cases this option only enlarges the size of the
2024 floating point emulator without any good reason.
2026 You almost surely want to say N here.
2029 bool "FastFPE math emulation (EXPERIMENTAL)"
2030 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2032 Say Y here to include the FAST floating point emulator in the kernel.
2033 This is an experimental much faster emulator which now also has full
2034 precision for the mantissa. It does not support any exceptions.
2035 It is very simple, and approximately 3-6 times faster than NWFPE.
2037 It should be sufficient for most programs. It may be not suitable
2038 for scientific calculations, but you have to check this for yourself.
2039 If you do not feel you need a faster FP emulation you should better
2043 bool "VFP-format floating point maths"
2044 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2046 Say Y to include VFP support code in the kernel. This is needed
2047 if your hardware includes a VFP unit.
2049 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2050 release notes and additional status information.
2052 Say N if your target does not have VFP hardware.
2060 bool "Advanced SIMD (NEON) Extension support"
2061 depends on VFPv3 && CPU_V7
2063 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2068 menu "Userspace binary formats"
2070 source "fs/Kconfig.binfmt"
2073 tristate "RISC OS personality"
2076 Say Y here to include the kernel code necessary if you want to run
2077 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2078 experimental; if this sounds frightening, say N and sleep in peace.
2079 You can also say M here to compile this support as a module (which
2080 will be called arthur).
2084 menu "Power management options"
2086 source "kernel/power/Kconfig"
2088 config ARCH_SUSPEND_POSSIBLE
2089 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2090 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2091 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2096 source "net/Kconfig"
2098 source "drivers/Kconfig"
2102 source "arch/arm/Kconfig.debug"
2104 source "security/Kconfig"
2106 source "crypto/Kconfig"
2108 source "lib/Kconfig"