5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt translation functions at runtime according to
201 the position of the kernel in system memory.
203 This can only be used with non-XIP with MMU kernels where
204 the base of physical memory is at a 16MB boundary.
206 config ARM_PATCH_PHYS_VIRT_16BIT
208 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
210 source "init/Kconfig"
212 source "kernel/Kconfig.freezer"
217 bool "MMU-based Paged Memory Management Support"
220 Select if you want MMU-based virtualised addressing space
221 support by paged memory management. If unsure, say 'Y'.
224 # The "ARM system type" choice list is ordered alphabetically by option
225 # text. Please add new entries in the option alphabetic order.
228 prompt "ARM system type"
229 default ARCH_VERSATILE
231 config ARCH_INTEGRATOR
232 bool "ARM Ltd. Integrator family"
234 select ARCH_HAS_CPUFREQ
237 select GENERIC_CLOCKEVENTS
238 select PLAT_VERSATILE
239 select PLAT_VERSATILE_FPGA_IRQ
241 Support for ARM's Integrator platform.
244 bool "ARM Ltd. RealView family"
248 select GENERIC_CLOCKEVENTS
249 select ARCH_WANT_OPTIONAL_GPIOLIB
250 select PLAT_VERSATILE
251 select PLAT_VERSATILE_CLCD
252 select ARM_TIMER_SP804
253 select GPIO_PL061 if GPIOLIB
255 This enables support for ARM Ltd RealView boards.
257 config ARCH_VERSATILE
258 bool "ARM Ltd. Versatile family"
263 select GENERIC_CLOCKEVENTS
264 select ARCH_WANT_OPTIONAL_GPIOLIB
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_CLCD
267 select PLAT_VERSATILE_FPGA_IRQ
268 select ARM_TIMER_SP804
270 This enables support for ARM Ltd Versatile board.
273 bool "ARM Ltd. Versatile Express family"
274 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select ARM_TIMER_SP804
278 select GENERIC_CLOCKEVENTS
280 select HAVE_PATA_PLATFORM
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_CLCD
285 This enables support for the ARM Ltd Versatile Express boards.
289 select ARCH_REQUIRE_GPIOLIB
292 This enables support for systems based on the Atmel AT91RM9200,
293 AT91SAM9 and AT91CAP9 processors.
296 bool "Broadcom BCMRING"
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 Support for Broadcom's BCMRing platform.
307 bool "Cirrus Logic CLPS711x/EP721x-based"
309 select ARCH_USES_GETTIMEOFFSET
311 Support for Cirrus Logic 711x/721x based boards.
314 bool "Cavium Networks CNS3XXX family"
316 select GENERIC_CLOCKEVENTS
318 select MIGHT_HAVE_PCI
319 select PCI_DOMAINS if PCI
321 Support for Cavium Networks CNS3XXX platform.
324 bool "Cortina Systems Gemini"
326 select ARCH_REQUIRE_GPIOLIB
327 select ARCH_USES_GETTIMEOFFSET
329 Support for the Cortina Systems Gemini family SoCs
336 select ARCH_USES_GETTIMEOFFSET
338 This is an evaluation board for the StrongARM processor available
339 from Digital. It has limited hardware on-board, including an
340 Ethernet interface, two PCMCIA sockets, two serial ports and a
349 select ARCH_REQUIRE_GPIOLIB
350 select ARCH_HAS_HOLES_MEMORYMODEL
351 select ARCH_USES_GETTIMEOFFSET
353 This enables support for the Cirrus EP93xx series of CPUs.
355 config ARCH_FOOTBRIDGE
359 select GENERIC_CLOCKEVENTS
361 Support for systems based on the DC21285 companion chip
362 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
365 bool "Freescale MXC/iMX-based"
366 select GENERIC_CLOCKEVENTS
367 select ARCH_REQUIRE_GPIOLIB
370 select HAVE_SCHED_CLOCK
372 Support for Freescale MXC/iMX-based family of processors
375 bool "Freescale MXS-based"
376 select GENERIC_CLOCKEVENTS
377 select ARCH_REQUIRE_GPIOLIB
381 Support for Freescale MXS-based family of processors
384 bool "Freescale STMP3xxx"
387 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
389 select USB_ARCH_HAS_EHCI
391 Support for systems based on the Freescale 3xxx CPUs.
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
403 bool "Hynix HMS720x-based"
406 select ARCH_USES_GETTIMEOFFSET
408 This enables support for systems based on the Hynix HMS720x
416 select ARCH_SUPPORTS_MSI
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select ARCH_REQUIRE_GPIOLIB
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select ARCH_REQUIRE_GPIOLIB
440 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP23xx (XScale) family of processors.
452 bool "IXP2400/2800-based"
456 select ARCH_USES_GETTIMEOFFSET
458 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
506 select ARCH_REQUIRE_GPIOLIB
509 select USB_ARCH_HAS_OHCI
512 select GENERIC_CLOCKEVENTS
514 Support for the NXP LPC32XX family of processors
517 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the following Marvell MV78xx0 series SoCs:
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select HAVE_SCHED_CLOCK
551 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
554 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
557 select ARCH_USES_GETTIMEOFFSET
559 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
560 System-on-Chip devices.
563 bool "NetSilicon NS9xxx"
566 select GENERIC_CLOCKEVENTS
569 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
572 <http://www.digi.com/products/microprocessors/index.jsp>
575 bool "Nuvoton W90X900 CPU"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 bool "Nuvoton NUC93X CPU"
595 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
596 low-power and high performance MPEG-4/JPEG multimedia controller chip.
603 select GENERIC_CLOCKEVENTS
606 select HAVE_SCHED_CLOCK
607 select ARCH_HAS_BARRIERS if CACHE_L2X0
608 select ARCH_HAS_CPUFREQ
610 This enables support for NVIDIA Tegra based systems (Tegra APX,
611 Tegra 6xx and Tegra 2 series).
614 bool "Philips Nexperia PNX4008 Mobile"
617 select ARCH_USES_GETTIMEOFFSET
619 This enables support for Philips PNX4008 mobile platform.
622 bool "PXA2xx/PXA3xx-based"
625 select ARCH_HAS_CPUFREQ
628 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
630 select HAVE_SCHED_CLOCK
635 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
640 select GENERIC_CLOCKEVENTS
641 select ARCH_REQUIRE_GPIOLIB
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
651 bool "Renesas SH-Mobile / R-Mobile"
654 select GENERIC_CLOCKEVENTS
657 select MULTI_IRQ_HANDLER
659 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
666 select ARCH_MAY_HAVE_PC_FDC
667 select HAVE_PATA_PLATFORM
670 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_USES_GETTIMEOFFSET
673 On the Acorn Risc-PC, Linux can support the internal IDE disk and
674 CD-ROM interface, serial and parallel port, and the floppy drive.
681 select ARCH_SPARSEMEM_ENABLE
683 select ARCH_HAS_CPUFREQ
685 select GENERIC_CLOCKEVENTS
687 select HAVE_SCHED_CLOCK
689 select ARCH_REQUIRE_GPIOLIB
691 Support for StrongARM 11x0 based boards.
694 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
696 select ARCH_HAS_CPUFREQ
698 select ARCH_USES_GETTIMEOFFSET
699 select HAVE_S3C2410_I2C if I2C
701 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
702 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
703 the Samsung SMDK2410 development board (and derivatives).
705 Note, the S3C2416 and the S3C2450 are so close that they even share
706 the same SoC ID code. This means that there is no separate machine
707 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
710 bool "Samsung S3C64XX"
716 select ARCH_USES_GETTIMEOFFSET
717 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
719 select SAMSUNG_CLKSRC
720 select SAMSUNG_IRQ_VIC_TIMER
721 select SAMSUNG_IRQ_UART
722 select S3C_GPIO_TRACK
723 select S3C_GPIO_PULL_UPDOWN
724 select S3C_GPIO_CFG_S3C24XX
725 select S3C_GPIO_CFG_S3C64XX
727 select USB_ARCH_HAS_OHCI
728 select SAMSUNG_GPIOLIB_4BIT
729 select HAVE_S3C2410_I2C if I2C
730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
732 Samsung S3C64XX series based systems
735 bool "Samsung S5P6440 S5P6450"
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select GENERIC_CLOCKEVENTS
741 select HAVE_SCHED_CLOCK
742 select HAVE_S3C2410_I2C if I2C
743 select HAVE_S3C_RTC if RTC_CLASS
745 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
749 bool "Samsung S5P6442"
753 select ARCH_USES_GETTIMEOFFSET
754 select HAVE_S3C2410_WATCHDOG if WATCHDOG
756 Samsung S5P6442 CPU based systems
759 bool "Samsung S5PC100"
763 select ARM_L1_CACHE_SHIFT_6
764 select ARCH_USES_GETTIMEOFFSET
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C_RTC if RTC_CLASS
767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
769 Samsung S5PC100 series based systems
772 bool "Samsung S5PV210/S5PC110"
774 select ARCH_SPARSEMEM_ENABLE
777 select ARM_L1_CACHE_SHIFT_6
778 select ARCH_HAS_CPUFREQ
779 select GENERIC_CLOCKEVENTS
780 select HAVE_SCHED_CLOCK
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C_RTC if RTC_CLASS
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 Samsung S5PV210/S5PC110 series based systems
788 bool "Samsung EXYNOS4"
790 select ARCH_SPARSEMEM_ENABLE
793 select ARCH_HAS_CPUFREQ
794 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C_RTC if RTC_CLASS
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 Samsung EXYNOS4 series based systems
808 select ARCH_USES_GETTIMEOFFSET
810 Support for the StrongARM based Digital DNARD machine, also known
811 as "Shark" (<http://www.shark-linux.de/shark.html>).
814 bool "Telechips TCC ARM926-based systems"
819 select GENERIC_CLOCKEVENTS
821 Support for Telechips TCC ARM926-based systems.
824 bool "ST-Ericsson U300 Series"
828 select HAVE_SCHED_CLOCK
832 select GENERIC_CLOCKEVENTS
836 Support for ST-Ericsson U300 series mobile platforms.
839 bool "ST-Ericsson U8500 Series"
842 select GENERIC_CLOCKEVENTS
844 select ARCH_REQUIRE_GPIOLIB
845 select ARCH_HAS_CPUFREQ
847 Support for ST-Ericsson's Ux500 architecture
850 bool "STMicroelectronics Nomadik"
855 select GENERIC_CLOCKEVENTS
856 select ARCH_REQUIRE_GPIOLIB
858 Support for the Nomadik platform by ST-Ericsson
862 select GENERIC_CLOCKEVENTS
863 select ARCH_REQUIRE_GPIOLIB
867 select GENERIC_ALLOCATOR
868 select ARCH_HAS_HOLES_MEMORYMODEL
870 Support for TI's DaVinci platform.
875 select ARCH_REQUIRE_GPIOLIB
876 select ARCH_HAS_CPUFREQ
877 select GENERIC_CLOCKEVENTS
878 select HAVE_SCHED_CLOCK
879 select ARCH_HAS_HOLES_MEMORYMODEL
881 Support for TI's OMAP platform (OMAP1/2/3/4).
886 select ARCH_REQUIRE_GPIOLIB
889 select GENERIC_CLOCKEVENTS
892 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
895 bool "VIA/WonderMedia 85xx"
898 select ARCH_HAS_CPUFREQ
899 select GENERIC_CLOCKEVENTS
900 select ARCH_REQUIRE_GPIOLIB
903 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
907 # This is sorted alphabetically by mach-* pathname. However, plat-*
908 # Kconfigs may be included either alphabetically (according to the
909 # plat- suffix) or along side the corresponding mach-* source.
911 source "arch/arm/mach-at91/Kconfig"
913 source "arch/arm/mach-bcmring/Kconfig"
915 source "arch/arm/mach-clps711x/Kconfig"
917 source "arch/arm/mach-cns3xxx/Kconfig"
919 source "arch/arm/mach-davinci/Kconfig"
921 source "arch/arm/mach-dove/Kconfig"
923 source "arch/arm/mach-ep93xx/Kconfig"
925 source "arch/arm/mach-footbridge/Kconfig"
927 source "arch/arm/mach-gemini/Kconfig"
929 source "arch/arm/mach-h720x/Kconfig"
931 source "arch/arm/mach-integrator/Kconfig"
933 source "arch/arm/mach-iop32x/Kconfig"
935 source "arch/arm/mach-iop33x/Kconfig"
937 source "arch/arm/mach-iop13xx/Kconfig"
939 source "arch/arm/mach-ixp4xx/Kconfig"
941 source "arch/arm/mach-ixp2000/Kconfig"
943 source "arch/arm/mach-ixp23xx/Kconfig"
945 source "arch/arm/mach-kirkwood/Kconfig"
947 source "arch/arm/mach-ks8695/Kconfig"
949 source "arch/arm/mach-loki/Kconfig"
951 source "arch/arm/mach-lpc32xx/Kconfig"
953 source "arch/arm/mach-msm/Kconfig"
955 source "arch/arm/mach-mv78xx0/Kconfig"
957 source "arch/arm/plat-mxc/Kconfig"
959 source "arch/arm/mach-mxs/Kconfig"
961 source "arch/arm/mach-netx/Kconfig"
963 source "arch/arm/mach-nomadik/Kconfig"
964 source "arch/arm/plat-nomadik/Kconfig"
966 source "arch/arm/mach-ns9xxx/Kconfig"
968 source "arch/arm/mach-nuc93x/Kconfig"
970 source "arch/arm/plat-omap/Kconfig"
972 source "arch/arm/mach-omap1/Kconfig"
974 source "arch/arm/mach-omap2/Kconfig"
976 source "arch/arm/mach-orion5x/Kconfig"
978 source "arch/arm/mach-pxa/Kconfig"
979 source "arch/arm/plat-pxa/Kconfig"
981 source "arch/arm/mach-mmp/Kconfig"
983 source "arch/arm/mach-realview/Kconfig"
985 source "arch/arm/mach-sa1100/Kconfig"
987 source "arch/arm/plat-samsung/Kconfig"
988 source "arch/arm/plat-s3c24xx/Kconfig"
989 source "arch/arm/plat-s5p/Kconfig"
991 source "arch/arm/plat-spear/Kconfig"
993 source "arch/arm/plat-tcc/Kconfig"
996 source "arch/arm/mach-s3c2400/Kconfig"
997 source "arch/arm/mach-s3c2410/Kconfig"
998 source "arch/arm/mach-s3c2412/Kconfig"
999 source "arch/arm/mach-s3c2416/Kconfig"
1000 source "arch/arm/mach-s3c2440/Kconfig"
1001 source "arch/arm/mach-s3c2443/Kconfig"
1005 source "arch/arm/mach-s3c64xx/Kconfig"
1008 source "arch/arm/mach-s5p64x0/Kconfig"
1010 source "arch/arm/mach-s5p6442/Kconfig"
1012 source "arch/arm/mach-s5pc100/Kconfig"
1014 source "arch/arm/mach-s5pv210/Kconfig"
1016 source "arch/arm/mach-exynos4/Kconfig"
1018 source "arch/arm/mach-shmobile/Kconfig"
1020 source "arch/arm/plat-stmp3xxx/Kconfig"
1022 source "arch/arm/mach-tegra/Kconfig"
1024 source "arch/arm/mach-u300/Kconfig"
1026 source "arch/arm/mach-ux500/Kconfig"
1028 source "arch/arm/mach-versatile/Kconfig"
1030 source "arch/arm/mach-vexpress/Kconfig"
1031 source "arch/arm/plat-versatile/Kconfig"
1033 source "arch/arm/mach-vt8500/Kconfig"
1035 source "arch/arm/mach-w90x900/Kconfig"
1037 # Definitions to make life easier
1043 select GENERIC_CLOCKEVENTS
1044 select HAVE_SCHED_CLOCK
1049 select HAVE_SCHED_CLOCK
1054 config PLAT_VERSATILE
1057 config ARM_TIMER_SP804
1061 source arch/arm/mm/Kconfig
1064 bool "Enable iWMMXt support"
1065 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1066 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1068 Enable support for iWMMXt context switching at run time if
1069 running on a CPU that supports it.
1071 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1074 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1078 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1079 (!ARCH_OMAP3 || OMAP3_EMU)
1083 config MULTI_IRQ_HANDLER
1086 Allow each machine to specify it's own IRQ handler at run time.
1089 source "arch/arm/Kconfig-nommu"
1092 config ARM_ERRATA_411920
1093 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1094 depends on CPU_V6 || CPU_V6K
1096 Invalidation of the Instruction Cache operation can
1097 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1098 It does not affect the MPCore. This option enables the ARM Ltd.
1099 recommended workaround.
1101 config ARM_ERRATA_430973
1102 bool "ARM errata: Stale prediction on replaced interworking branch"
1105 This option enables the workaround for the 430973 Cortex-A8
1106 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1107 interworking branch is replaced with another code sequence at the
1108 same virtual address, whether due to self-modifying code or virtual
1109 to physical address re-mapping, Cortex-A8 does not recover from the
1110 stale interworking branch prediction. This results in Cortex-A8
1111 executing the new code sequence in the incorrect ARM or Thumb state.
1112 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1113 and also flushes the branch target cache at every context switch.
1114 Note that setting specific bits in the ACTLR register may not be
1115 available in non-secure mode.
1117 config ARM_ERRATA_458693
1118 bool "ARM errata: Processor deadlock when a false hazard is created"
1121 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1122 erratum. For very specific sequences of memory operations, it is
1123 possible for a hazard condition intended for a cache line to instead
1124 be incorrectly associated with a different cache line. This false
1125 hazard might then cause a processor deadlock. The workaround enables
1126 the L1 caching of the NEON accesses and disables the PLD instruction
1127 in the ACTLR register. Note that setting specific bits in the ACTLR
1128 register may not be available in non-secure mode.
1130 config ARM_ERRATA_460075
1131 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1134 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1135 erratum. Any asynchronous access to the L2 cache may encounter a
1136 situation in which recent store transactions to the L2 cache are lost
1137 and overwritten with stale memory contents from external memory. The
1138 workaround disables the write-allocate mode for the L2 cache via the
1139 ACTLR register. Note that setting specific bits in the ACTLR register
1140 may not be available in non-secure mode.
1142 config ARM_ERRATA_742230
1143 bool "ARM errata: DMB operation may be faulty"
1144 depends on CPU_V7 && SMP
1146 This option enables the workaround for the 742230 Cortex-A9
1147 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1148 between two write operations may not ensure the correct visibility
1149 ordering of the two writes. This workaround sets a specific bit in
1150 the diagnostic register of the Cortex-A9 which causes the DMB
1151 instruction to behave as a DSB, ensuring the correct behaviour of
1154 config ARM_ERRATA_742231
1155 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1156 depends on CPU_V7 && SMP
1158 This option enables the workaround for the 742231 Cortex-A9
1159 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1160 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1161 accessing some data located in the same cache line, may get corrupted
1162 data due to bad handling of the address hazard when the line gets
1163 replaced from one of the CPUs at the same time as another CPU is
1164 accessing it. This workaround sets specific bits in the diagnostic
1165 register of the Cortex-A9 which reduces the linefill issuing
1166 capabilities of the processor.
1168 config PL310_ERRATA_588369
1169 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1170 depends on CACHE_L2X0
1172 The PL310 L2 cache controller implements three types of Clean &
1173 Invalidate maintenance operations: by Physical Address
1174 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1175 They are architecturally defined to behave as the execution of a
1176 clean operation followed immediately by an invalidate operation,
1177 both performing to the same memory location. This functionality
1178 is not correctly implemented in PL310 as clean lines are not
1179 invalidated as a result of these operations.
1181 config ARM_ERRATA_720789
1182 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1183 depends on CPU_V7 && SMP
1185 This option enables the workaround for the 720789 Cortex-A9 (prior to
1186 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1187 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1188 As a consequence of this erratum, some TLB entries which should be
1189 invalidated are not, resulting in an incoherency in the system page
1190 tables. The workaround changes the TLB flushing routines to invalidate
1191 entries regardless of the ASID.
1193 config PL310_ERRATA_727915
1194 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1195 depends on CACHE_L2X0
1197 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1198 operation (offset 0x7FC). This operation runs in background so that
1199 PL310 can handle normal accesses while it is in progress. Under very
1200 rare circumstances, due to this erratum, write data can be lost when
1201 PL310 treats a cacheable write transaction during a Clean &
1202 Invalidate by Way operation.
1204 config ARM_ERRATA_743622
1205 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1208 This option enables the workaround for the 743622 Cortex-A9
1209 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1210 optimisation in the Cortex-A9 Store Buffer may lead to data
1211 corruption. This workaround sets a specific bit in the diagnostic
1212 register of the Cortex-A9 which disables the Store Buffer
1213 optimisation, preventing the defect from occurring. This has no
1214 visible impact on the overall performance or power consumption of the
1217 config ARM_ERRATA_751472
1218 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1219 depends on CPU_V7 && SMP
1221 This option enables the workaround for the 751472 Cortex-A9 (prior
1222 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1223 completion of a following broadcasted operation if the second
1224 operation is received by a CPU before the ICIALLUIS has completed,
1225 potentially leading to corrupted entries in the cache or TLB.
1227 config ARM_ERRATA_753970
1228 bool "ARM errata: cache sync operation may be faulty"
1229 depends on CACHE_PL310
1231 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1233 Under some condition the effect of cache sync operation on
1234 the store buffer still remains when the operation completes.
1235 This means that the store buffer is always asked to drain and
1236 this prevents it from merging any further writes. The workaround
1237 is to replace the normal offset of cache sync operation (0x730)
1238 by another offset targeting an unmapped PL310 register 0x740.
1239 This has the same effect as the cache sync operation: store buffer
1240 drain and waiting for all buffers empty.
1242 config ARM_ERRATA_754322
1243 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1246 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1247 r3p*) erratum. A speculative memory access may cause a page table walk
1248 which starts prior to an ASID switch but completes afterwards. This
1249 can populate the micro-TLB with a stale entry which may be hit with
1250 the new ASID. This workaround places two dsb instructions in the mm
1251 switching code so that no page table walks can cross the ASID switch.
1253 config ARM_ERRATA_754327
1254 bool "ARM errata: no automatic Store Buffer drain"
1255 depends on CPU_V7 && SMP
1257 This option enables the workaround for the 754327 Cortex-A9 (prior to
1258 r2p0) erratum. The Store Buffer does not have any automatic draining
1259 mechanism and therefore a livelock may occur if an external agent
1260 continuously polls a memory location waiting to observe an update.
1261 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1262 written polling loops from denying visibility of updates to memory.
1266 source "arch/arm/common/Kconfig"
1276 Find out whether you have ISA slots on your motherboard. ISA is the
1277 name of a bus system, i.e. the way the CPU talks to the other stuff
1278 inside your box. Other bus systems are PCI, EISA, MicroChannel
1279 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1280 newer boards don't support it. If you have ISA, say Y, otherwise N.
1282 # Select ISA DMA controller support
1287 # Select ISA DMA interface
1292 bool "PCI support" if MIGHT_HAVE_PCI
1294 Find out whether you have a PCI motherboard. PCI is the name of a
1295 bus system, i.e. the way the CPU talks to the other stuff inside
1296 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1297 VESA. If you have PCI, say Y, otherwise N.
1303 config PCI_NANOENGINE
1304 bool "BSE nanoEngine PCI support"
1305 depends on SA1100_NANOENGINE
1307 Enable PCI on the BSE nanoEngine board.
1312 # Select the host bridge type
1313 config PCI_HOST_VIA82C505
1315 depends on PCI && ARCH_SHARK
1318 config PCI_HOST_ITE8152
1320 depends on PCI && MACH_ARMCORE
1324 source "drivers/pci/Kconfig"
1326 source "drivers/pcmcia/Kconfig"
1330 menu "Kernel Features"
1332 source "kernel/time/Kconfig"
1335 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1336 depends on EXPERIMENTAL
1337 depends on CPU_V6K || CPU_V7
1338 depends on GENERIC_CLOCKEVENTS
1339 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1340 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1341 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1342 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1343 select USE_GENERIC_SMP_HELPERS
1344 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1346 This enables support for systems with more than one CPU. If you have
1347 a system with only one CPU, like most personal computers, say N. If
1348 you have a system with more than one CPU, say Y.
1350 If you say N here, the kernel will run on single and multiprocessor
1351 machines, but will use only one CPU of a multiprocessor machine. If
1352 you say Y here, the kernel will run on many, but not all, single
1353 processor machines. On a single processor machine, the kernel will
1354 run faster if you say N here.
1356 See also <file:Documentation/i386/IO-APIC.txt>,
1357 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1358 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1360 If you don't know what to do here, say N.
1363 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1364 depends on EXPERIMENTAL
1365 depends on SMP && !XIP_KERNEL
1368 SMP kernels contain instructions which fail on non-SMP processors.
1369 Enabling this option allows the kernel to modify itself to make
1370 these instructions safe. Disabling it allows about 1K of space
1373 If you don't know what to do here, say Y.
1379 This option enables support for the ARM system coherency unit
1386 This options enables support for the ARM timer and watchdog unit
1389 prompt "Memory split"
1392 Select the desired split between kernel and user memory.
1394 If you are not absolutely sure what you are doing, leave this
1398 bool "3G/1G user/kernel split"
1400 bool "2G/2G user/kernel split"
1402 bool "1G/3G user/kernel split"
1407 default 0x40000000 if VMSPLIT_1G
1408 default 0x80000000 if VMSPLIT_2G
1412 int "Maximum number of CPUs (2-32)"
1418 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1419 depends on SMP && HOTPLUG && EXPERIMENTAL
1420 depends on !ARCH_MSM
1422 Say Y here to experiment with turning CPUs off and on. CPUs
1423 can be controlled through /sys/devices/system/cpu.
1426 bool "Use local timer interrupts"
1429 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1431 Enable support for local timers on SMP platforms, rather then the
1432 legacy IPI broadcast method. Local timers allows the system
1433 accounting to be spread across the timer interval, preventing a
1434 "thundering herd" at every timer tick.
1436 source kernel/Kconfig.preempt
1440 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1441 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1442 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1443 default AT91_TIMER_HZ if ARCH_AT91
1444 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1447 config THUMB2_KERNEL
1448 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1449 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1451 select ARM_ASM_UNIFIED
1453 By enabling this option, the kernel will be compiled in
1454 Thumb-2 mode. A compiler/assembler that understand the unified
1455 ARM-Thumb syntax is needed.
1459 config THUMB2_AVOID_R_ARM_THM_JUMP11
1460 bool "Work around buggy Thumb-2 short branch relocations in gas"
1461 depends on THUMB2_KERNEL && MODULES
1464 Various binutils versions can resolve Thumb-2 branches to
1465 locally-defined, preemptible global symbols as short-range "b.n"
1466 branch instructions.
1468 This is a problem, because there's no guarantee the final
1469 destination of the symbol, or any candidate locations for a
1470 trampoline, are within range of the branch. For this reason, the
1471 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1472 relocation in modules at all, and it makes little sense to add
1475 The symptom is that the kernel fails with an "unsupported
1476 relocation" error when loading some modules.
1478 Until fixed tools are available, passing
1479 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1480 code which hits this problem, at the cost of a bit of extra runtime
1481 stack usage in some cases.
1483 The problem is described in more detail at:
1484 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1486 Only Thumb-2 kernels are affected.
1488 Unless you are sure your tools don't have this problem, say Y.
1490 config ARM_ASM_UNIFIED
1494 bool "Use the ARM EABI to compile the kernel"
1496 This option allows for the kernel to be compiled using the latest
1497 ARM ABI (aka EABI). This is only useful if you are using a user
1498 space environment that is also compiled with EABI.
1500 Since there are major incompatibilities between the legacy ABI and
1501 EABI, especially with regard to structure member alignment, this
1502 option also changes the kernel syscall calling convention to
1503 disambiguate both ABIs and allow for backward compatibility support
1504 (selected with CONFIG_OABI_COMPAT).
1506 To use this you need GCC version 4.0.0 or later.
1509 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1510 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1513 This option preserves the old syscall interface along with the
1514 new (ARM EABI) one. It also provides a compatibility layer to
1515 intercept syscalls that have structure arguments which layout
1516 in memory differs between the legacy ABI and the new ARM EABI
1517 (only for non "thumb" binaries). This option adds a tiny
1518 overhead to all syscalls and produces a slightly larger kernel.
1519 If you know you'll be using only pure EABI user space then you
1520 can say N here. If this option is not selected and you attempt
1521 to execute a legacy ABI binary then the result will be
1522 UNPREDICTABLE (in fact it can be predicted that it won't work
1523 at all). If in doubt say Y.
1525 config ARCH_HAS_HOLES_MEMORYMODEL
1528 config ARCH_SPARSEMEM_ENABLE
1531 config ARCH_SPARSEMEM_DEFAULT
1532 def_bool ARCH_SPARSEMEM_ENABLE
1534 config ARCH_SELECT_MEMORY_MODEL
1535 def_bool ARCH_SPARSEMEM_ENABLE
1538 bool "High Memory Support (EXPERIMENTAL)"
1539 depends on MMU && EXPERIMENTAL
1541 The address space of ARM processors is only 4 Gigabytes large
1542 and it has to accommodate user address space, kernel address
1543 space as well as some memory mapped IO. That means that, if you
1544 have a large amount of physical memory and/or IO, not all of the
1545 memory can be "permanently mapped" by the kernel. The physical
1546 memory that is not permanently mapped is called "high memory".
1548 Depending on the selected kernel/user memory split, minimum
1549 vmalloc space and actual amount of RAM, you may not need this
1550 option which should result in a slightly faster kernel.
1555 bool "Allocate 2nd-level pagetables from highmem"
1558 config HW_PERF_EVENTS
1559 bool "Enable hardware performance counter support for perf events"
1560 depends on PERF_EVENTS && CPU_HAS_PMU
1563 Enable hardware performance counter support for perf events. If
1564 disabled, perf events will use software events only.
1568 config FORCE_MAX_ZONEORDER
1569 int "Maximum zone order" if ARCH_SHMOBILE
1570 range 11 64 if ARCH_SHMOBILE
1571 default "9" if SA1111
1574 The kernel memory allocator divides physically contiguous memory
1575 blocks into "zones", where each zone is a power of two number of
1576 pages. This option selects the largest power of two that the kernel
1577 keeps in the memory allocator. If you need to allocate very large
1578 blocks of physically contiguous memory, then you may need to
1579 increase this value.
1581 This config option is actually maximum order plus one. For example,
1582 a value of 11 means that the largest free memory block is 2^10 pages.
1585 bool "Timer and CPU usage LEDs"
1586 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1587 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1588 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1589 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1590 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1591 ARCH_AT91 || ARCH_DAVINCI || \
1592 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1594 If you say Y here, the LEDs on your machine will be used
1595 to provide useful information about your current system status.
1597 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1598 be able to select which LEDs are active using the options below. If
1599 you are compiling a kernel for the EBSA-110 or the LART however, the
1600 red LED will simply flash regularly to indicate that the system is
1601 still functional. It is safe to say Y here if you have a CATS
1602 system, but the driver will do nothing.
1605 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1606 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1607 || MACH_OMAP_PERSEUS2
1609 depends on !GENERIC_CLOCKEVENTS
1610 default y if ARCH_EBSA110
1612 If you say Y here, one of the system LEDs (the green one on the
1613 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1614 will flash regularly to indicate that the system is still
1615 operational. This is mainly useful to kernel hackers who are
1616 debugging unstable kernels.
1618 The LART uses the same LED for both Timer LED and CPU usage LED
1619 functions. You may choose to use both, but the Timer LED function
1620 will overrule the CPU usage LED.
1623 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1625 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1626 || MACH_OMAP_PERSEUS2
1629 If you say Y here, the red LED will be used to give a good real
1630 time indication of CPU usage, by lighting whenever the idle task
1631 is not currently executing.
1633 The LART uses the same LED for both Timer LED and CPU usage LED
1634 functions. You may choose to use both, but the Timer LED function
1635 will overrule the CPU usage LED.
1637 config ALIGNMENT_TRAP
1639 depends on CPU_CP15_MMU
1640 default y if !ARCH_EBSA110
1641 select HAVE_PROC_CPU if PROC_FS
1643 ARM processors cannot fetch/store information which is not
1644 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1645 address divisible by 4. On 32-bit ARM processors, these non-aligned
1646 fetch/store instructions will be emulated in software if you say
1647 here, which has a severe performance impact. This is necessary for
1648 correct operation of some network protocols. With an IP-only
1649 configuration it is safe to say N, otherwise say Y.
1651 config UACCESS_WITH_MEMCPY
1652 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1653 depends on MMU && EXPERIMENTAL
1654 default y if CPU_FEROCEON
1656 Implement faster copy_to_user and clear_user methods for CPU
1657 cores where a 8-word STM instruction give significantly higher
1658 memory write throughput than a sequence of individual 32bit stores.
1660 A possible side effect is a slight increase in scheduling latency
1661 between threads sharing the same address space if they invoke
1662 such copy operations with large buffers.
1664 However, if the CPU data cache is using a write-allocate mode,
1665 this option is unlikely to provide any performance gain.
1669 prompt "Enable seccomp to safely compute untrusted bytecode"
1671 This kernel feature is useful for number crunching applications
1672 that may need to compute untrusted bytecode during their
1673 execution. By using pipes or other transports made available to
1674 the process as file descriptors supporting the read/write
1675 syscalls, it's possible to isolate those applications in
1676 their own address space using seccomp. Once seccomp is
1677 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1678 and the task is only allowed to execute a few safe syscalls
1679 defined by each seccomp mode.
1681 config CC_STACKPROTECTOR
1682 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1683 depends on EXPERIMENTAL
1685 This option turns on the -fstack-protector GCC feature. This
1686 feature puts, at the beginning of functions, a canary value on
1687 the stack just before the return address, and validates
1688 the value just before actually returning. Stack based buffer
1689 overflows (that need to overwrite this return address) now also
1690 overwrite the canary, which gets detected and the attack is then
1691 neutralized via a kernel panic.
1692 This feature requires gcc version 4.2 or above.
1694 config DEPRECATED_PARAM_STRUCT
1695 bool "Provide old way to pass kernel parameters"
1697 This was deprecated in 2001 and announced to live on for 5 years.
1698 Some old boot loaders still use this way.
1704 # Compressed boot loader in ROM. Yes, we really want to ask about
1705 # TEXT and BSS so we preserve their values in the config files.
1706 config ZBOOT_ROM_TEXT
1707 hex "Compressed ROM boot loader base address"
1710 The physical address at which the ROM-able zImage is to be
1711 placed in the target. Platforms which normally make use of
1712 ROM-able zImage formats normally set this to a suitable
1713 value in their defconfig file.
1715 If ZBOOT_ROM is not enabled, this has no effect.
1717 config ZBOOT_ROM_BSS
1718 hex "Compressed ROM boot loader BSS address"
1721 The base address of an area of read/write memory in the target
1722 for the ROM-able zImage which must be available while the
1723 decompressor is running. It must be large enough to hold the
1724 entire decompressed kernel plus an additional 128 KiB.
1725 Platforms which normally make use of ROM-able zImage formats
1726 normally set this to a suitable value in their defconfig file.
1728 If ZBOOT_ROM is not enabled, this has no effect.
1731 bool "Compressed boot loader in ROM/flash"
1732 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1734 Say Y here if you intend to execute your compressed kernel image
1735 (zImage) directly from ROM or flash. If unsure, say N.
1737 config ZBOOT_ROM_MMCIF
1738 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1739 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1741 Say Y here to include experimental MMCIF loading code in the
1742 ROM-able zImage. With this enabled it is possible to write the
1743 the ROM-able zImage kernel image to an MMC card and boot the
1744 kernel straight from the reset vector. At reset the processor
1745 Mask ROM will load the first part of the the ROM-able zImage
1746 which in turn loads the rest the kernel image to RAM using the
1747 MMCIF hardware block.
1750 string "Default kernel command string"
1753 On some architectures (EBSA110 and CATS), there is currently no way
1754 for the boot loader to pass arguments to the kernel. For these
1755 architectures, you should supply some command-line options at build
1756 time by entering them here. As a minimum, you should specify the
1757 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1759 config CMDLINE_FORCE
1760 bool "Always use the default kernel command string"
1761 depends on CMDLINE != ""
1763 Always use the default kernel command string, even if the boot
1764 loader passes other arguments to the kernel.
1765 This is useful if you cannot or don't want to change the
1766 command-line options your boot loader passes to the kernel.
1771 bool "Kernel Execute-In-Place from ROM"
1772 depends on !ZBOOT_ROM
1774 Execute-In-Place allows the kernel to run from non-volatile storage
1775 directly addressable by the CPU, such as NOR flash. This saves RAM
1776 space since the text section of the kernel is not loaded from flash
1777 to RAM. Read-write sections, such as the data section and stack,
1778 are still copied to RAM. The XIP kernel is not compressed since
1779 it has to run directly from flash, so it will take more space to
1780 store it. The flash address used to link the kernel object files,
1781 and for storing it, is configuration dependent. Therefore, if you
1782 say Y here, you must know the proper physical address where to
1783 store the kernel image depending on your own flash memory usage.
1785 Also note that the make target becomes "make xipImage" rather than
1786 "make zImage" or "make Image". The final kernel binary to put in
1787 ROM memory will be arch/arm/boot/xipImage.
1791 config XIP_PHYS_ADDR
1792 hex "XIP Kernel Physical Location"
1793 depends on XIP_KERNEL
1794 default "0x00080000"
1796 This is the physical address in your flash memory the kernel will
1797 be linked for and stored to. This address is dependent on your
1801 bool "Kexec system call (EXPERIMENTAL)"
1802 depends on EXPERIMENTAL
1804 kexec is a system call that implements the ability to shutdown your
1805 current kernel, and to start another kernel. It is like a reboot
1806 but it is independent of the system firmware. And like a reboot
1807 you can start any kernel with it, not just Linux.
1809 It is an ongoing process to be certain the hardware in a machine
1810 is properly shutdown, so do not be surprised if this code does not
1811 initially work for you. It may help to enable device hotplugging
1815 bool "Export atags in procfs"
1819 Should the atags used to boot the kernel be exported in an "atags"
1820 file in procfs. Useful with kexec.
1823 bool "Build kdump crash kernel (EXPERIMENTAL)"
1824 depends on EXPERIMENTAL
1826 Generate crash dump after being started by kexec. This should
1827 be normally only set in special crash dump kernels which are
1828 loaded in the main kernel with kexec-tools into a specially
1829 reserved region and then later executed after a crash by
1830 kdump/kexec. The crash dump kernel must be compiled to a
1831 memory address not used by the main kernel
1833 For more details see Documentation/kdump/kdump.txt
1835 config AUTO_ZRELADDR
1836 bool "Auto calculation of the decompressed kernel image address"
1837 depends on !ZBOOT_ROM && !ARCH_U300
1839 ZRELADDR is the physical address where the decompressed kernel
1840 image will be placed. If AUTO_ZRELADDR is selected, the address
1841 will be determined at run-time by masking the current IP with
1842 0xf8000000. This assumes the zImage being placed in the first 128MB
1843 from start of memory.
1847 menu "CPU Power Management"
1851 source "drivers/cpufreq/Kconfig"
1854 tristate "CPUfreq driver for i.MX CPUs"
1855 depends on ARCH_MXC && CPU_FREQ
1857 This enables the CPUfreq driver for i.MX CPUs.
1859 config CPU_FREQ_SA1100
1862 config CPU_FREQ_SA1110
1865 config CPU_FREQ_INTEGRATOR
1866 tristate "CPUfreq driver for ARM Integrator CPUs"
1867 depends on ARCH_INTEGRATOR && CPU_FREQ
1870 This enables the CPUfreq driver for ARM Integrator CPUs.
1872 For details, take a look at <file:Documentation/cpu-freq>.
1878 depends on CPU_FREQ && ARCH_PXA && PXA25x
1880 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1882 config CPU_FREQ_S3C64XX
1883 bool "CPUfreq support for Samsung S3C64XX CPUs"
1884 depends on CPU_FREQ && CPU_S3C6410
1889 Internal configuration node for common cpufreq on Samsung SoC
1891 config CPU_FREQ_S3C24XX
1892 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1893 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1896 This enables the CPUfreq driver for the Samsung S3C24XX family
1899 For details, take a look at <file:Documentation/cpu-freq>.
1903 config CPU_FREQ_S3C24XX_PLL
1904 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1905 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1907 Compile in support for changing the PLL frequency from the
1908 S3C24XX series CPUfreq driver. The PLL takes time to settle
1909 after a frequency change, so by default it is not enabled.
1911 This also means that the PLL tables for the selected CPU(s) will
1912 be built which may increase the size of the kernel image.
1914 config CPU_FREQ_S3C24XX_DEBUG
1915 bool "Debug CPUfreq Samsung driver core"
1916 depends on CPU_FREQ_S3C24XX
1918 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1920 config CPU_FREQ_S3C24XX_IODEBUG
1921 bool "Debug CPUfreq Samsung driver IO timing"
1922 depends on CPU_FREQ_S3C24XX
1924 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1926 config CPU_FREQ_S3C24XX_DEBUGFS
1927 bool "Export debugfs for CPUFreq"
1928 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1930 Export status information via debugfs.
1934 source "drivers/cpuidle/Kconfig"
1938 menu "Floating point emulation"
1940 comment "At least one emulation must be selected"
1943 bool "NWFPE math emulation"
1944 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1946 Say Y to include the NWFPE floating point emulator in the kernel.
1947 This is necessary to run most binaries. Linux does not currently
1948 support floating point hardware so you need to say Y here even if
1949 your machine has an FPA or floating point co-processor podule.
1951 You may say N here if you are going to load the Acorn FPEmulator
1952 early in the bootup.
1955 bool "Support extended precision"
1956 depends on FPE_NWFPE
1958 Say Y to include 80-bit support in the kernel floating-point
1959 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1960 Note that gcc does not generate 80-bit operations by default,
1961 so in most cases this option only enlarges the size of the
1962 floating point emulator without any good reason.
1964 You almost surely want to say N here.
1967 bool "FastFPE math emulation (EXPERIMENTAL)"
1968 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1970 Say Y here to include the FAST floating point emulator in the kernel.
1971 This is an experimental much faster emulator which now also has full
1972 precision for the mantissa. It does not support any exceptions.
1973 It is very simple, and approximately 3-6 times faster than NWFPE.
1975 It should be sufficient for most programs. It may be not suitable
1976 for scientific calculations, but you have to check this for yourself.
1977 If you do not feel you need a faster FP emulation you should better
1981 bool "VFP-format floating point maths"
1982 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1984 Say Y to include VFP support code in the kernel. This is needed
1985 if your hardware includes a VFP unit.
1987 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1988 release notes and additional status information.
1990 Say N if your target does not have VFP hardware.
1998 bool "Advanced SIMD (NEON) Extension support"
1999 depends on VFPv3 && CPU_V7
2001 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2006 menu "Userspace binary formats"
2008 source "fs/Kconfig.binfmt"
2011 tristate "RISC OS personality"
2014 Say Y here to include the kernel code necessary if you want to run
2015 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2016 experimental; if this sounds frightening, say N and sleep in peace.
2017 You can also say M here to compile this support as a module (which
2018 will be called arthur).
2022 menu "Power management options"
2024 source "kernel/power/Kconfig"
2026 config ARCH_SUSPEND_POSSIBLE
2027 depends on !ARCH_S5P64X0 && !ARCH_S5P6442
2028 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2029 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2034 source "net/Kconfig"
2036 source "drivers/Kconfig"
2040 source "arch/arm/Kconfig.debug"
2042 source "security/Kconfig"
2044 source "crypto/Kconfig"
2046 source "lib/Kconfig"