5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt translation functions at runtime according to
201 the position of the kernel in system memory.
203 This can only be used with non-XIP with MMU kernels where
204 the base of physical memory is at a 16MB boundary.
206 config ARM_PATCH_PHYS_VIRT_16BIT
208 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
210 source "init/Kconfig"
212 source "kernel/Kconfig.freezer"
217 bool "MMU-based Paged Memory Management Support"
220 Select if you want MMU-based virtualised addressing space
221 support by paged memory management. If unsure, say 'Y'.
224 # The "ARM system type" choice list is ordered alphabetically by option
225 # text. Please add new entries in the option alphabetic order.
228 prompt "ARM system type"
229 default ARCH_VERSATILE
231 config ARCH_INTEGRATOR
232 bool "ARM Ltd. Integrator family"
234 select ARCH_HAS_CPUFREQ
237 select GENERIC_CLOCKEVENTS
238 select PLAT_VERSATILE
239 select PLAT_VERSATILE_FPGA_IRQ
241 Support for ARM's Integrator platform.
244 bool "ARM Ltd. RealView family"
248 select GENERIC_CLOCKEVENTS
249 select ARCH_WANT_OPTIONAL_GPIOLIB
250 select PLAT_VERSATILE
251 select PLAT_VERSATILE_CLCD
252 select ARM_TIMER_SP804
253 select GPIO_PL061 if GPIOLIB
255 This enables support for ARM Ltd RealView boards.
257 config ARCH_VERSATILE
258 bool "ARM Ltd. Versatile family"
263 select GENERIC_CLOCKEVENTS
264 select ARCH_WANT_OPTIONAL_GPIOLIB
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_CLCD
267 select PLAT_VERSATILE_FPGA_IRQ
268 select ARM_TIMER_SP804
270 This enables support for ARM Ltd Versatile board.
273 bool "ARM Ltd. Versatile Express family"
274 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select ARM_TIMER_SP804
278 select GENERIC_CLOCKEVENTS
280 select HAVE_PATA_PLATFORM
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_CLCD
285 This enables support for the ARM Ltd Versatile Express boards.
289 select ARCH_REQUIRE_GPIOLIB
292 This enables support for systems based on the Atmel AT91RM9200,
293 AT91SAM9 and AT91CAP9 processors.
296 bool "Broadcom BCMRING"
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 Support for Broadcom's BCMRing platform.
307 bool "Cirrus Logic CLPS711x/EP721x-based"
309 select ARCH_USES_GETTIMEOFFSET
311 Support for Cirrus Logic 711x/721x based boards.
314 bool "Cavium Networks CNS3XXX family"
316 select GENERIC_CLOCKEVENTS
318 select MIGHT_HAVE_PCI
319 select PCI_DOMAINS if PCI
321 Support for Cavium Networks CNS3XXX platform.
324 bool "Cortina Systems Gemini"
326 select ARCH_REQUIRE_GPIOLIB
327 select ARCH_USES_GETTIMEOFFSET
329 Support for the Cortina Systems Gemini family SoCs
336 select ARCH_USES_GETTIMEOFFSET
338 This is an evaluation board for the StrongARM processor available
339 from Digital. It has limited hardware on-board, including an
340 Ethernet interface, two PCMCIA sockets, two serial ports and a
349 select ARCH_REQUIRE_GPIOLIB
350 select ARCH_HAS_HOLES_MEMORYMODEL
351 select ARCH_USES_GETTIMEOFFSET
353 This enables support for the Cirrus EP93xx series of CPUs.
355 config ARCH_FOOTBRIDGE
359 select GENERIC_CLOCKEVENTS
361 Support for systems based on the DC21285 companion chip
362 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
365 bool "Freescale MXC/iMX-based"
366 select GENERIC_CLOCKEVENTS
367 select ARCH_REQUIRE_GPIOLIB
369 select HAVE_SCHED_CLOCK
371 Support for Freescale MXC/iMX-based family of processors
374 bool "Freescale MXS-based"
375 select GENERIC_CLOCKEVENTS
376 select ARCH_REQUIRE_GPIOLIB
379 Support for Freescale MXS-based family of processors
382 bool "Freescale STMP3xxx"
385 select ARCH_REQUIRE_GPIOLIB
386 select GENERIC_CLOCKEVENTS
387 select USB_ARCH_HAS_EHCI
389 Support for systems based on the Freescale 3xxx CPUs.
392 bool "Hilscher NetX based"
395 select GENERIC_CLOCKEVENTS
397 This enables support for systems based on the Hilscher NetX Soc
400 bool "Hynix HMS720x-based"
403 select ARCH_USES_GETTIMEOFFSET
405 This enables support for systems based on the Hynix HMS720x
413 select ARCH_SUPPORTS_MSI
416 Support for Intel's IOP13XX (XScale) family of processors.
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's 80219 and IOP32X (XScale) family of
435 select ARCH_REQUIRE_GPIOLIB
437 Support for Intel's IOP33X (XScale) family of processors.
444 select ARCH_USES_GETTIMEOFFSET
446 Support for Intel's IXP23xx (XScale) family of processors.
449 bool "IXP2400/2800-based"
453 select ARCH_USES_GETTIMEOFFSET
455 Support for Intel's IXP2400/2800 (XScale) family of processors.
462 select GENERIC_CLOCKEVENTS
463 select HAVE_SCHED_CLOCK
464 select MIGHT_HAVE_PCI
465 select DMABOUNCE if PCI
467 Support for Intel's IXP4XX (XScale) family of processors.
473 select ARCH_REQUIRE_GPIOLIB
474 select GENERIC_CLOCKEVENTS
477 Support for the Marvell Dove SoC 88AP510
480 bool "Marvell Kirkwood"
483 select ARCH_REQUIRE_GPIOLIB
484 select GENERIC_CLOCKEVENTS
487 Support for the following Marvell Kirkwood series SoCs:
488 88F6180, 88F6192 and 88F6281.
491 bool "Marvell Loki (88RC8480)"
493 select GENERIC_CLOCKEVENTS
496 Support for the Marvell Loki (88RC8480) SoC.
501 select ARCH_REQUIRE_GPIOLIB
504 select USB_ARCH_HAS_OHCI
507 select GENERIC_CLOCKEVENTS
509 Support for the NXP LPC32XX family of processors
512 bool "Marvell MV78xx0"
515 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
519 Support for the following Marvell MV78xx0 series SoCs:
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 Support for the following Marvell Orion 5x series SoCs:
532 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
533 Orion-2 (5281), Orion-1-90 (6183).
536 bool "Marvell PXA168/910/MMP2"
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
541 select HAVE_SCHED_CLOCK
546 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
549 bool "Micrel/Kendin KS8695"
551 select ARCH_REQUIRE_GPIOLIB
552 select ARCH_USES_GETTIMEOFFSET
554 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
555 System-on-Chip devices.
558 bool "NetSilicon NS9xxx"
561 select GENERIC_CLOCKEVENTS
564 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
567 <http://www.digi.com/products/microprocessors/index.jsp>
570 bool "Nuvoton W90X900 CPU"
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
576 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
577 At present, the w90x900 has been renamed nuc900, regarding
578 the ARM series product line, you can login the following
579 link address to know more.
581 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
582 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
585 bool "Nuvoton NUC93X CPU"
589 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
590 low-power and high performance MPEG-4/JPEG multimedia controller chip.
596 select GENERIC_CLOCKEVENTS
599 select HAVE_SCHED_CLOCK
600 select ARCH_HAS_BARRIERS if CACHE_L2X0
601 select ARCH_HAS_CPUFREQ
603 This enables support for NVIDIA Tegra based systems (Tegra APX,
604 Tegra 6xx and Tegra 2 series).
607 bool "Philips Nexperia PNX4008 Mobile"
610 select ARCH_USES_GETTIMEOFFSET
612 This enables support for Philips PNX4008 mobile platform.
615 bool "PXA2xx/PXA3xx-based"
618 select ARCH_HAS_CPUFREQ
620 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS
622 select HAVE_SCHED_CLOCK
627 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
632 select GENERIC_CLOCKEVENTS
633 select ARCH_REQUIRE_GPIOLIB
636 Support for Qualcomm MSM/QSD based systems. This runs on the
637 apps processor of the MSM/QSD and depends on a shared memory
638 interface to the modem processor which runs the baseband
639 stack and controls some vital subsystems
640 (clock and power control, etc).
643 bool "Renesas SH-Mobile / R-Mobile"
646 select GENERIC_CLOCKEVENTS
649 select MULTI_IRQ_HANDLER
651 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
658 select ARCH_MAY_HAVE_PC_FDC
659 select HAVE_PATA_PLATFORM
662 select ARCH_SPARSEMEM_ENABLE
663 select ARCH_USES_GETTIMEOFFSET
665 On the Acorn Risc-PC, Linux can support the internal IDE disk and
666 CD-ROM interface, serial and parallel port, and the floppy drive.
672 select ARCH_SPARSEMEM_ENABLE
674 select ARCH_HAS_CPUFREQ
676 select GENERIC_CLOCKEVENTS
678 select HAVE_SCHED_CLOCK
680 select ARCH_REQUIRE_GPIOLIB
682 Support for StrongARM 11x0 based boards.
685 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
687 select ARCH_HAS_CPUFREQ
689 select ARCH_USES_GETTIMEOFFSET
690 select HAVE_S3C2410_I2C if I2C
692 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
693 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
694 the Samsung SMDK2410 development board (and derivatives).
696 Note, the S3C2416 and the S3C2450 are so close that they even share
697 the same SoC ID code. This means that there is no separate machine
698 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
701 bool "Samsung S3C64XX"
707 select ARCH_USES_GETTIMEOFFSET
708 select ARCH_HAS_CPUFREQ
709 select ARCH_REQUIRE_GPIOLIB
710 select SAMSUNG_CLKSRC
711 select SAMSUNG_IRQ_VIC_TIMER
712 select SAMSUNG_IRQ_UART
713 select S3C_GPIO_TRACK
714 select S3C_GPIO_PULL_UPDOWN
715 select S3C_GPIO_CFG_S3C24XX
716 select S3C_GPIO_CFG_S3C64XX
718 select USB_ARCH_HAS_OHCI
719 select SAMSUNG_GPIOLIB_4BIT
720 select HAVE_S3C2410_I2C if I2C
721 select HAVE_S3C2410_WATCHDOG if WATCHDOG
723 Samsung S3C64XX series based systems
726 bool "Samsung S5P6440 S5P6450"
730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
731 select GENERIC_CLOCKEVENTS
732 select HAVE_SCHED_CLOCK
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C_RTC if RTC_CLASS
736 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
740 bool "Samsung S5PC100"
744 select ARM_L1_CACHE_SHIFT_6
745 select ARCH_USES_GETTIMEOFFSET
746 select HAVE_S3C2410_I2C if I2C
747 select HAVE_S3C_RTC if RTC_CLASS
748 select HAVE_S3C2410_WATCHDOG if WATCHDOG
750 Samsung S5PC100 series based systems
753 bool "Samsung S5PV210/S5PC110"
755 select ARCH_SPARSEMEM_ENABLE
758 select ARM_L1_CACHE_SHIFT_6
759 select ARCH_HAS_CPUFREQ
760 select GENERIC_CLOCKEVENTS
761 select HAVE_SCHED_CLOCK
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C_RTC if RTC_CLASS
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 Samsung S5PV210/S5PC110 series based systems
769 bool "Samsung EXYNOS4"
771 select ARCH_SPARSEMEM_ENABLE
774 select ARCH_HAS_CPUFREQ
775 select GENERIC_CLOCKEVENTS
776 select HAVE_S3C_RTC if RTC_CLASS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 Samsung EXYNOS4 series based systems
789 select ARCH_USES_GETTIMEOFFSET
791 Support for the StrongARM based Digital DNARD machine, also known
792 as "Shark" (<http://www.shark-linux.de/shark.html>).
795 bool "Telechips TCC ARM926-based systems"
799 select GENERIC_CLOCKEVENTS
801 Support for Telechips TCC ARM926-based systems.
804 bool "ST-Ericsson U300 Series"
807 select HAVE_SCHED_CLOCK
811 select GENERIC_CLOCKEVENTS
815 Support for ST-Ericsson U300 series mobile platforms.
818 bool "ST-Ericsson U8500 Series"
821 select GENERIC_CLOCKEVENTS
823 select ARCH_REQUIRE_GPIOLIB
824 select ARCH_HAS_CPUFREQ
826 Support for ST-Ericsson's Ux500 architecture
829 bool "STMicroelectronics Nomadik"
834 select GENERIC_CLOCKEVENTS
835 select ARCH_REQUIRE_GPIOLIB
837 Support for the Nomadik platform by ST-Ericsson
841 select GENERIC_CLOCKEVENTS
842 select ARCH_REQUIRE_GPIOLIB
846 select GENERIC_ALLOCATOR
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 Support for TI's DaVinci platform.
854 select ARCH_REQUIRE_GPIOLIB
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_SCHED_CLOCK
858 select ARCH_HAS_HOLES_MEMORYMODEL
860 Support for TI's OMAP platform (OMAP1/2/3/4).
865 select ARCH_REQUIRE_GPIOLIB
867 select GENERIC_CLOCKEVENTS
870 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
873 bool "VIA/WonderMedia 85xx"
876 select ARCH_HAS_CPUFREQ
877 select GENERIC_CLOCKEVENTS
878 select ARCH_REQUIRE_GPIOLIB
881 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
885 # This is sorted alphabetically by mach-* pathname. However, plat-*
886 # Kconfigs may be included either alphabetically (according to the
887 # plat- suffix) or along side the corresponding mach-* source.
889 source "arch/arm/mach-at91/Kconfig"
891 source "arch/arm/mach-bcmring/Kconfig"
893 source "arch/arm/mach-clps711x/Kconfig"
895 source "arch/arm/mach-cns3xxx/Kconfig"
897 source "arch/arm/mach-davinci/Kconfig"
899 source "arch/arm/mach-dove/Kconfig"
901 source "arch/arm/mach-ep93xx/Kconfig"
903 source "arch/arm/mach-footbridge/Kconfig"
905 source "arch/arm/mach-gemini/Kconfig"
907 source "arch/arm/mach-h720x/Kconfig"
909 source "arch/arm/mach-integrator/Kconfig"
911 source "arch/arm/mach-iop32x/Kconfig"
913 source "arch/arm/mach-iop33x/Kconfig"
915 source "arch/arm/mach-iop13xx/Kconfig"
917 source "arch/arm/mach-ixp4xx/Kconfig"
919 source "arch/arm/mach-ixp2000/Kconfig"
921 source "arch/arm/mach-ixp23xx/Kconfig"
923 source "arch/arm/mach-kirkwood/Kconfig"
925 source "arch/arm/mach-ks8695/Kconfig"
927 source "arch/arm/mach-loki/Kconfig"
929 source "arch/arm/mach-lpc32xx/Kconfig"
931 source "arch/arm/mach-msm/Kconfig"
933 source "arch/arm/mach-mv78xx0/Kconfig"
935 source "arch/arm/plat-mxc/Kconfig"
937 source "arch/arm/mach-mxs/Kconfig"
939 source "arch/arm/mach-netx/Kconfig"
941 source "arch/arm/mach-nomadik/Kconfig"
942 source "arch/arm/plat-nomadik/Kconfig"
944 source "arch/arm/mach-ns9xxx/Kconfig"
946 source "arch/arm/mach-nuc93x/Kconfig"
948 source "arch/arm/plat-omap/Kconfig"
950 source "arch/arm/mach-omap1/Kconfig"
952 source "arch/arm/mach-omap2/Kconfig"
954 source "arch/arm/mach-orion5x/Kconfig"
956 source "arch/arm/mach-pxa/Kconfig"
957 source "arch/arm/plat-pxa/Kconfig"
959 source "arch/arm/mach-mmp/Kconfig"
961 source "arch/arm/mach-realview/Kconfig"
963 source "arch/arm/mach-sa1100/Kconfig"
965 source "arch/arm/plat-samsung/Kconfig"
966 source "arch/arm/plat-s3c24xx/Kconfig"
967 source "arch/arm/plat-s5p/Kconfig"
969 source "arch/arm/plat-spear/Kconfig"
971 source "arch/arm/plat-tcc/Kconfig"
974 source "arch/arm/mach-s3c2400/Kconfig"
975 source "arch/arm/mach-s3c2410/Kconfig"
976 source "arch/arm/mach-s3c2412/Kconfig"
977 source "arch/arm/mach-s3c2416/Kconfig"
978 source "arch/arm/mach-s3c2440/Kconfig"
979 source "arch/arm/mach-s3c2443/Kconfig"
983 source "arch/arm/mach-s3c64xx/Kconfig"
986 source "arch/arm/mach-s5p64x0/Kconfig"
988 source "arch/arm/mach-s5pc100/Kconfig"
990 source "arch/arm/mach-s5pv210/Kconfig"
992 source "arch/arm/mach-exynos4/Kconfig"
994 source "arch/arm/mach-shmobile/Kconfig"
996 source "arch/arm/plat-stmp3xxx/Kconfig"
998 source "arch/arm/mach-tegra/Kconfig"
1000 source "arch/arm/mach-u300/Kconfig"
1002 source "arch/arm/mach-ux500/Kconfig"
1004 source "arch/arm/mach-versatile/Kconfig"
1006 source "arch/arm/mach-vexpress/Kconfig"
1007 source "arch/arm/plat-versatile/Kconfig"
1009 source "arch/arm/mach-vt8500/Kconfig"
1011 source "arch/arm/mach-w90x900/Kconfig"
1013 # Definitions to make life easier
1019 select GENERIC_CLOCKEVENTS
1020 select HAVE_SCHED_CLOCK
1024 select HAVE_SCHED_CLOCK
1029 config PLAT_VERSATILE
1032 config ARM_TIMER_SP804
1035 source arch/arm/mm/Kconfig
1038 bool "Enable iWMMXt support"
1039 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1040 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1042 Enable support for iWMMXt context switching at run time if
1043 running on a CPU that supports it.
1045 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1048 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1052 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1053 (!ARCH_OMAP3 || OMAP3_EMU)
1057 config MULTI_IRQ_HANDLER
1060 Allow each machine to specify it's own IRQ handler at run time.
1063 source "arch/arm/Kconfig-nommu"
1066 config ARM_ERRATA_411920
1067 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1068 depends on CPU_V6 || CPU_V6K
1070 Invalidation of the Instruction Cache operation can
1071 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1072 It does not affect the MPCore. This option enables the ARM Ltd.
1073 recommended workaround.
1075 config ARM_ERRATA_430973
1076 bool "ARM errata: Stale prediction on replaced interworking branch"
1079 This option enables the workaround for the 430973 Cortex-A8
1080 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1081 interworking branch is replaced with another code sequence at the
1082 same virtual address, whether due to self-modifying code or virtual
1083 to physical address re-mapping, Cortex-A8 does not recover from the
1084 stale interworking branch prediction. This results in Cortex-A8
1085 executing the new code sequence in the incorrect ARM or Thumb state.
1086 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1087 and also flushes the branch target cache at every context switch.
1088 Note that setting specific bits in the ACTLR register may not be
1089 available in non-secure mode.
1091 config ARM_ERRATA_458693
1092 bool "ARM errata: Processor deadlock when a false hazard is created"
1095 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1096 erratum. For very specific sequences of memory operations, it is
1097 possible for a hazard condition intended for a cache line to instead
1098 be incorrectly associated with a different cache line. This false
1099 hazard might then cause a processor deadlock. The workaround enables
1100 the L1 caching of the NEON accesses and disables the PLD instruction
1101 in the ACTLR register. Note that setting specific bits in the ACTLR
1102 register may not be available in non-secure mode.
1104 config ARM_ERRATA_460075
1105 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1108 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1109 erratum. Any asynchronous access to the L2 cache may encounter a
1110 situation in which recent store transactions to the L2 cache are lost
1111 and overwritten with stale memory contents from external memory. The
1112 workaround disables the write-allocate mode for the L2 cache via the
1113 ACTLR register. Note that setting specific bits in the ACTLR register
1114 may not be available in non-secure mode.
1116 config ARM_ERRATA_742230
1117 bool "ARM errata: DMB operation may be faulty"
1118 depends on CPU_V7 && SMP
1120 This option enables the workaround for the 742230 Cortex-A9
1121 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1122 between two write operations may not ensure the correct visibility
1123 ordering of the two writes. This workaround sets a specific bit in
1124 the diagnostic register of the Cortex-A9 which causes the DMB
1125 instruction to behave as a DSB, ensuring the correct behaviour of
1128 config ARM_ERRATA_742231
1129 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1130 depends on CPU_V7 && SMP
1132 This option enables the workaround for the 742231 Cortex-A9
1133 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1134 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1135 accessing some data located in the same cache line, may get corrupted
1136 data due to bad handling of the address hazard when the line gets
1137 replaced from one of the CPUs at the same time as another CPU is
1138 accessing it. This workaround sets specific bits in the diagnostic
1139 register of the Cortex-A9 which reduces the linefill issuing
1140 capabilities of the processor.
1142 config PL310_ERRATA_588369
1143 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1144 depends on CACHE_L2X0
1146 The PL310 L2 cache controller implements three types of Clean &
1147 Invalidate maintenance operations: by Physical Address
1148 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1149 They are architecturally defined to behave as the execution of a
1150 clean operation followed immediately by an invalidate operation,
1151 both performing to the same memory location. This functionality
1152 is not correctly implemented in PL310 as clean lines are not
1153 invalidated as a result of these operations.
1155 config ARM_ERRATA_720789
1156 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1157 depends on CPU_V7 && SMP
1159 This option enables the workaround for the 720789 Cortex-A9 (prior to
1160 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1161 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1162 As a consequence of this erratum, some TLB entries which should be
1163 invalidated are not, resulting in an incoherency in the system page
1164 tables. The workaround changes the TLB flushing routines to invalidate
1165 entries regardless of the ASID.
1167 config PL310_ERRATA_727915
1168 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1169 depends on CACHE_L2X0
1171 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1172 operation (offset 0x7FC). This operation runs in background so that
1173 PL310 can handle normal accesses while it is in progress. Under very
1174 rare circumstances, due to this erratum, write data can be lost when
1175 PL310 treats a cacheable write transaction during a Clean &
1176 Invalidate by Way operation.
1178 config ARM_ERRATA_743622
1179 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1182 This option enables the workaround for the 743622 Cortex-A9
1183 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1184 optimisation in the Cortex-A9 Store Buffer may lead to data
1185 corruption. This workaround sets a specific bit in the diagnostic
1186 register of the Cortex-A9 which disables the Store Buffer
1187 optimisation, preventing the defect from occurring. This has no
1188 visible impact on the overall performance or power consumption of the
1191 config ARM_ERRATA_751472
1192 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1193 depends on CPU_V7 && SMP
1195 This option enables the workaround for the 751472 Cortex-A9 (prior
1196 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1197 completion of a following broadcasted operation if the second
1198 operation is received by a CPU before the ICIALLUIS has completed,
1199 potentially leading to corrupted entries in the cache or TLB.
1201 config ARM_ERRATA_753970
1202 bool "ARM errata: cache sync operation may be faulty"
1203 depends on CACHE_PL310
1205 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1207 Under some condition the effect of cache sync operation on
1208 the store buffer still remains when the operation completes.
1209 This means that the store buffer is always asked to drain and
1210 this prevents it from merging any further writes. The workaround
1211 is to replace the normal offset of cache sync operation (0x730)
1212 by another offset targeting an unmapped PL310 register 0x740.
1213 This has the same effect as the cache sync operation: store buffer
1214 drain and waiting for all buffers empty.
1216 config ARM_ERRATA_754322
1217 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1220 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1221 r3p*) erratum. A speculative memory access may cause a page table walk
1222 which starts prior to an ASID switch but completes afterwards. This
1223 can populate the micro-TLB with a stale entry which may be hit with
1224 the new ASID. This workaround places two dsb instructions in the mm
1225 switching code so that no page table walks can cross the ASID switch.
1227 config ARM_ERRATA_754327
1228 bool "ARM errata: no automatic Store Buffer drain"
1229 depends on CPU_V7 && SMP
1231 This option enables the workaround for the 754327 Cortex-A9 (prior to
1232 r2p0) erratum. The Store Buffer does not have any automatic draining
1233 mechanism and therefore a livelock may occur if an external agent
1234 continuously polls a memory location waiting to observe an update.
1235 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1236 written polling loops from denying visibility of updates to memory.
1240 source "arch/arm/common/Kconfig"
1250 Find out whether you have ISA slots on your motherboard. ISA is the
1251 name of a bus system, i.e. the way the CPU talks to the other stuff
1252 inside your box. Other bus systems are PCI, EISA, MicroChannel
1253 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1254 newer boards don't support it. If you have ISA, say Y, otherwise N.
1256 # Select ISA DMA controller support
1261 # Select ISA DMA interface
1266 bool "PCI support" if MIGHT_HAVE_PCI
1268 Find out whether you have a PCI motherboard. PCI is the name of a
1269 bus system, i.e. the way the CPU talks to the other stuff inside
1270 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1271 VESA. If you have PCI, say Y, otherwise N.
1277 config PCI_NANOENGINE
1278 bool "BSE nanoEngine PCI support"
1279 depends on SA1100_NANOENGINE
1281 Enable PCI on the BSE nanoEngine board.
1286 # Select the host bridge type
1287 config PCI_HOST_VIA82C505
1289 depends on PCI && ARCH_SHARK
1292 config PCI_HOST_ITE8152
1294 depends on PCI && MACH_ARMCORE
1298 source "drivers/pci/Kconfig"
1300 source "drivers/pcmcia/Kconfig"
1304 menu "Kernel Features"
1306 source "kernel/time/Kconfig"
1309 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1310 depends on EXPERIMENTAL
1311 depends on CPU_V6K || CPU_V7
1312 depends on GENERIC_CLOCKEVENTS
1313 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1314 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1315 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1316 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1317 select USE_GENERIC_SMP_HELPERS
1318 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1320 This enables support for systems with more than one CPU. If you have
1321 a system with only one CPU, like most personal computers, say N. If
1322 you have a system with more than one CPU, say Y.
1324 If you say N here, the kernel will run on single and multiprocessor
1325 machines, but will use only one CPU of a multiprocessor machine. If
1326 you say Y here, the kernel will run on many, but not all, single
1327 processor machines. On a single processor machine, the kernel will
1328 run faster if you say N here.
1330 See also <file:Documentation/i386/IO-APIC.txt>,
1331 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1332 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1334 If you don't know what to do here, say N.
1337 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1338 depends on EXPERIMENTAL
1339 depends on SMP && !XIP_KERNEL
1342 SMP kernels contain instructions which fail on non-SMP processors.
1343 Enabling this option allows the kernel to modify itself to make
1344 these instructions safe. Disabling it allows about 1K of space
1347 If you don't know what to do here, say Y.
1353 This option enables support for the ARM system coherency unit
1360 This options enables support for the ARM timer and watchdog unit
1363 prompt "Memory split"
1366 Select the desired split between kernel and user memory.
1368 If you are not absolutely sure what you are doing, leave this
1372 bool "3G/1G user/kernel split"
1374 bool "2G/2G user/kernel split"
1376 bool "1G/3G user/kernel split"
1381 default 0x40000000 if VMSPLIT_1G
1382 default 0x80000000 if VMSPLIT_2G
1386 int "Maximum number of CPUs (2-32)"
1392 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1393 depends on SMP && HOTPLUG && EXPERIMENTAL
1394 depends on !ARCH_MSM
1396 Say Y here to experiment with turning CPUs off and on. CPUs
1397 can be controlled through /sys/devices/system/cpu.
1400 bool "Use local timer interrupts"
1403 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1405 Enable support for local timers on SMP platforms, rather then the
1406 legacy IPI broadcast method. Local timers allows the system
1407 accounting to be spread across the timer interval, preventing a
1408 "thundering herd" at every timer tick.
1410 source kernel/Kconfig.preempt
1414 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1415 ARCH_S5PV210 || ARCH_EXYNOS4
1416 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1417 default AT91_TIMER_HZ if ARCH_AT91
1418 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1421 config THUMB2_KERNEL
1422 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1423 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1425 select ARM_ASM_UNIFIED
1427 By enabling this option, the kernel will be compiled in
1428 Thumb-2 mode. A compiler/assembler that understand the unified
1429 ARM-Thumb syntax is needed.
1433 config THUMB2_AVOID_R_ARM_THM_JUMP11
1434 bool "Work around buggy Thumb-2 short branch relocations in gas"
1435 depends on THUMB2_KERNEL && MODULES
1438 Various binutils versions can resolve Thumb-2 branches to
1439 locally-defined, preemptible global symbols as short-range "b.n"
1440 branch instructions.
1442 This is a problem, because there's no guarantee the final
1443 destination of the symbol, or any candidate locations for a
1444 trampoline, are within range of the branch. For this reason, the
1445 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1446 relocation in modules at all, and it makes little sense to add
1449 The symptom is that the kernel fails with an "unsupported
1450 relocation" error when loading some modules.
1452 Until fixed tools are available, passing
1453 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1454 code which hits this problem, at the cost of a bit of extra runtime
1455 stack usage in some cases.
1457 The problem is described in more detail at:
1458 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1460 Only Thumb-2 kernels are affected.
1462 Unless you are sure your tools don't have this problem, say Y.
1464 config ARM_ASM_UNIFIED
1468 bool "Use the ARM EABI to compile the kernel"
1470 This option allows for the kernel to be compiled using the latest
1471 ARM ABI (aka EABI). This is only useful if you are using a user
1472 space environment that is also compiled with EABI.
1474 Since there are major incompatibilities between the legacy ABI and
1475 EABI, especially with regard to structure member alignment, this
1476 option also changes the kernel syscall calling convention to
1477 disambiguate both ABIs and allow for backward compatibility support
1478 (selected with CONFIG_OABI_COMPAT).
1480 To use this you need GCC version 4.0.0 or later.
1483 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1484 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1487 This option preserves the old syscall interface along with the
1488 new (ARM EABI) one. It also provides a compatibility layer to
1489 intercept syscalls that have structure arguments which layout
1490 in memory differs between the legacy ABI and the new ARM EABI
1491 (only for non "thumb" binaries). This option adds a tiny
1492 overhead to all syscalls and produces a slightly larger kernel.
1493 If you know you'll be using only pure EABI user space then you
1494 can say N here. If this option is not selected and you attempt
1495 to execute a legacy ABI binary then the result will be
1496 UNPREDICTABLE (in fact it can be predicted that it won't work
1497 at all). If in doubt say Y.
1499 config ARCH_HAS_HOLES_MEMORYMODEL
1502 config ARCH_SPARSEMEM_ENABLE
1505 config ARCH_SPARSEMEM_DEFAULT
1506 def_bool ARCH_SPARSEMEM_ENABLE
1508 config ARCH_SELECT_MEMORY_MODEL
1509 def_bool ARCH_SPARSEMEM_ENABLE
1512 bool "High Memory Support (EXPERIMENTAL)"
1513 depends on MMU && EXPERIMENTAL
1515 The address space of ARM processors is only 4 Gigabytes large
1516 and it has to accommodate user address space, kernel address
1517 space as well as some memory mapped IO. That means that, if you
1518 have a large amount of physical memory and/or IO, not all of the
1519 memory can be "permanently mapped" by the kernel. The physical
1520 memory that is not permanently mapped is called "high memory".
1522 Depending on the selected kernel/user memory split, minimum
1523 vmalloc space and actual amount of RAM, you may not need this
1524 option which should result in a slightly faster kernel.
1529 bool "Allocate 2nd-level pagetables from highmem"
1532 config HW_PERF_EVENTS
1533 bool "Enable hardware performance counter support for perf events"
1534 depends on PERF_EVENTS && CPU_HAS_PMU
1537 Enable hardware performance counter support for perf events. If
1538 disabled, perf events will use software events only.
1542 config FORCE_MAX_ZONEORDER
1543 int "Maximum zone order" if ARCH_SHMOBILE
1544 range 11 64 if ARCH_SHMOBILE
1545 default "9" if SA1111
1548 The kernel memory allocator divides physically contiguous memory
1549 blocks into "zones", where each zone is a power of two number of
1550 pages. This option selects the largest power of two that the kernel
1551 keeps in the memory allocator. If you need to allocate very large
1552 blocks of physically contiguous memory, then you may need to
1553 increase this value.
1555 This config option is actually maximum order plus one. For example,
1556 a value of 11 means that the largest free memory block is 2^10 pages.
1559 bool "Timer and CPU usage LEDs"
1560 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1561 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1562 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1563 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1564 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1565 ARCH_AT91 || ARCH_DAVINCI || \
1566 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1568 If you say Y here, the LEDs on your machine will be used
1569 to provide useful information about your current system status.
1571 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1572 be able to select which LEDs are active using the options below. If
1573 you are compiling a kernel for the EBSA-110 or the LART however, the
1574 red LED will simply flash regularly to indicate that the system is
1575 still functional. It is safe to say Y here if you have a CATS
1576 system, but the driver will do nothing.
1579 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1580 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1581 || MACH_OMAP_PERSEUS2
1583 depends on !GENERIC_CLOCKEVENTS
1584 default y if ARCH_EBSA110
1586 If you say Y here, one of the system LEDs (the green one on the
1587 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1588 will flash regularly to indicate that the system is still
1589 operational. This is mainly useful to kernel hackers who are
1590 debugging unstable kernels.
1592 The LART uses the same LED for both Timer LED and CPU usage LED
1593 functions. You may choose to use both, but the Timer LED function
1594 will overrule the CPU usage LED.
1597 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1599 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1600 || MACH_OMAP_PERSEUS2
1603 If you say Y here, the red LED will be used to give a good real
1604 time indication of CPU usage, by lighting whenever the idle task
1605 is not currently executing.
1607 The LART uses the same LED for both Timer LED and CPU usage LED
1608 functions. You may choose to use both, but the Timer LED function
1609 will overrule the CPU usage LED.
1611 config ALIGNMENT_TRAP
1613 depends on CPU_CP15_MMU
1614 default y if !ARCH_EBSA110
1615 select HAVE_PROC_CPU if PROC_FS
1617 ARM processors cannot fetch/store information which is not
1618 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1619 address divisible by 4. On 32-bit ARM processors, these non-aligned
1620 fetch/store instructions will be emulated in software if you say
1621 here, which has a severe performance impact. This is necessary for
1622 correct operation of some network protocols. With an IP-only
1623 configuration it is safe to say N, otherwise say Y.
1625 config UACCESS_WITH_MEMCPY
1626 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1627 depends on MMU && EXPERIMENTAL
1628 default y if CPU_FEROCEON
1630 Implement faster copy_to_user and clear_user methods for CPU
1631 cores where a 8-word STM instruction give significantly higher
1632 memory write throughput than a sequence of individual 32bit stores.
1634 A possible side effect is a slight increase in scheduling latency
1635 between threads sharing the same address space if they invoke
1636 such copy operations with large buffers.
1638 However, if the CPU data cache is using a write-allocate mode,
1639 this option is unlikely to provide any performance gain.
1643 prompt "Enable seccomp to safely compute untrusted bytecode"
1645 This kernel feature is useful for number crunching applications
1646 that may need to compute untrusted bytecode during their
1647 execution. By using pipes or other transports made available to
1648 the process as file descriptors supporting the read/write
1649 syscalls, it's possible to isolate those applications in
1650 their own address space using seccomp. Once seccomp is
1651 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1652 and the task is only allowed to execute a few safe syscalls
1653 defined by each seccomp mode.
1655 config CC_STACKPROTECTOR
1656 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1657 depends on EXPERIMENTAL
1659 This option turns on the -fstack-protector GCC feature. This
1660 feature puts, at the beginning of functions, a canary value on
1661 the stack just before the return address, and validates
1662 the value just before actually returning. Stack based buffer
1663 overflows (that need to overwrite this return address) now also
1664 overwrite the canary, which gets detected and the attack is then
1665 neutralized via a kernel panic.
1666 This feature requires gcc version 4.2 or above.
1668 config DEPRECATED_PARAM_STRUCT
1669 bool "Provide old way to pass kernel parameters"
1671 This was deprecated in 2001 and announced to live on for 5 years.
1672 Some old boot loaders still use this way.
1678 # Compressed boot loader in ROM. Yes, we really want to ask about
1679 # TEXT and BSS so we preserve their values in the config files.
1680 config ZBOOT_ROM_TEXT
1681 hex "Compressed ROM boot loader base address"
1684 The physical address at which the ROM-able zImage is to be
1685 placed in the target. Platforms which normally make use of
1686 ROM-able zImage formats normally set this to a suitable
1687 value in their defconfig file.
1689 If ZBOOT_ROM is not enabled, this has no effect.
1691 config ZBOOT_ROM_BSS
1692 hex "Compressed ROM boot loader BSS address"
1695 The base address of an area of read/write memory in the target
1696 for the ROM-able zImage which must be available while the
1697 decompressor is running. It must be large enough to hold the
1698 entire decompressed kernel plus an additional 128 KiB.
1699 Platforms which normally make use of ROM-able zImage formats
1700 normally set this to a suitable value in their defconfig file.
1702 If ZBOOT_ROM is not enabled, this has no effect.
1705 bool "Compressed boot loader in ROM/flash"
1706 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1708 Say Y here if you intend to execute your compressed kernel image
1709 (zImage) directly from ROM or flash. If unsure, say N.
1711 config ZBOOT_ROM_MMCIF
1712 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1713 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1715 Say Y here to include experimental MMCIF loading code in the
1716 ROM-able zImage. With this enabled it is possible to write the
1717 the ROM-able zImage kernel image to an MMC card and boot the
1718 kernel straight from the reset vector. At reset the processor
1719 Mask ROM will load the first part of the the ROM-able zImage
1720 which in turn loads the rest the kernel image to RAM using the
1721 MMCIF hardware block.
1724 string "Default kernel command string"
1727 On some architectures (EBSA110 and CATS), there is currently no way
1728 for the boot loader to pass arguments to the kernel. For these
1729 architectures, you should supply some command-line options at build
1730 time by entering them here. As a minimum, you should specify the
1731 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1733 config CMDLINE_FORCE
1734 bool "Always use the default kernel command string"
1735 depends on CMDLINE != ""
1737 Always use the default kernel command string, even if the boot
1738 loader passes other arguments to the kernel.
1739 This is useful if you cannot or don't want to change the
1740 command-line options your boot loader passes to the kernel.
1745 bool "Kernel Execute-In-Place from ROM"
1746 depends on !ZBOOT_ROM
1748 Execute-In-Place allows the kernel to run from non-volatile storage
1749 directly addressable by the CPU, such as NOR flash. This saves RAM
1750 space since the text section of the kernel is not loaded from flash
1751 to RAM. Read-write sections, such as the data section and stack,
1752 are still copied to RAM. The XIP kernel is not compressed since
1753 it has to run directly from flash, so it will take more space to
1754 store it. The flash address used to link the kernel object files,
1755 and for storing it, is configuration dependent. Therefore, if you
1756 say Y here, you must know the proper physical address where to
1757 store the kernel image depending on your own flash memory usage.
1759 Also note that the make target becomes "make xipImage" rather than
1760 "make zImage" or "make Image". The final kernel binary to put in
1761 ROM memory will be arch/arm/boot/xipImage.
1765 config XIP_PHYS_ADDR
1766 hex "XIP Kernel Physical Location"
1767 depends on XIP_KERNEL
1768 default "0x00080000"
1770 This is the physical address in your flash memory the kernel will
1771 be linked for and stored to. This address is dependent on your
1775 bool "Kexec system call (EXPERIMENTAL)"
1776 depends on EXPERIMENTAL
1778 kexec is a system call that implements the ability to shutdown your
1779 current kernel, and to start another kernel. It is like a reboot
1780 but it is independent of the system firmware. And like a reboot
1781 you can start any kernel with it, not just Linux.
1783 It is an ongoing process to be certain the hardware in a machine
1784 is properly shutdown, so do not be surprised if this code does not
1785 initially work for you. It may help to enable device hotplugging
1789 bool "Export atags in procfs"
1793 Should the atags used to boot the kernel be exported in an "atags"
1794 file in procfs. Useful with kexec.
1797 bool "Build kdump crash kernel (EXPERIMENTAL)"
1798 depends on EXPERIMENTAL
1800 Generate crash dump after being started by kexec. This should
1801 be normally only set in special crash dump kernels which are
1802 loaded in the main kernel with kexec-tools into a specially
1803 reserved region and then later executed after a crash by
1804 kdump/kexec. The crash dump kernel must be compiled to a
1805 memory address not used by the main kernel
1807 For more details see Documentation/kdump/kdump.txt
1809 config AUTO_ZRELADDR
1810 bool "Auto calculation of the decompressed kernel image address"
1811 depends on !ZBOOT_ROM && !ARCH_U300
1813 ZRELADDR is the physical address where the decompressed kernel
1814 image will be placed. If AUTO_ZRELADDR is selected, the address
1815 will be determined at run-time by masking the current IP with
1816 0xf8000000. This assumes the zImage being placed in the first 128MB
1817 from start of memory.
1821 menu "CPU Power Management"
1825 source "drivers/cpufreq/Kconfig"
1828 tristate "CPUfreq driver for i.MX CPUs"
1829 depends on ARCH_MXC && CPU_FREQ
1831 This enables the CPUfreq driver for i.MX CPUs.
1833 config CPU_FREQ_SA1100
1836 config CPU_FREQ_SA1110
1839 config CPU_FREQ_INTEGRATOR
1840 tristate "CPUfreq driver for ARM Integrator CPUs"
1841 depends on ARCH_INTEGRATOR && CPU_FREQ
1844 This enables the CPUfreq driver for ARM Integrator CPUs.
1846 For details, take a look at <file:Documentation/cpu-freq>.
1852 depends on CPU_FREQ && ARCH_PXA && PXA25x
1854 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1856 config CPU_FREQ_S3C64XX
1857 bool "CPUfreq support for Samsung S3C64XX CPUs"
1858 depends on CPU_FREQ && CPU_S3C6410
1863 Internal configuration node for common cpufreq on Samsung SoC
1865 config CPU_FREQ_S3C24XX
1866 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1867 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1870 This enables the CPUfreq driver for the Samsung S3C24XX family
1873 For details, take a look at <file:Documentation/cpu-freq>.
1877 config CPU_FREQ_S3C24XX_PLL
1878 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1879 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1881 Compile in support for changing the PLL frequency from the
1882 S3C24XX series CPUfreq driver. The PLL takes time to settle
1883 after a frequency change, so by default it is not enabled.
1885 This also means that the PLL tables for the selected CPU(s) will
1886 be built which may increase the size of the kernel image.
1888 config CPU_FREQ_S3C24XX_DEBUG
1889 bool "Debug CPUfreq Samsung driver core"
1890 depends on CPU_FREQ_S3C24XX
1892 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1894 config CPU_FREQ_S3C24XX_IODEBUG
1895 bool "Debug CPUfreq Samsung driver IO timing"
1896 depends on CPU_FREQ_S3C24XX
1898 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1900 config CPU_FREQ_S3C24XX_DEBUGFS
1901 bool "Export debugfs for CPUFreq"
1902 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1904 Export status information via debugfs.
1908 source "drivers/cpuidle/Kconfig"
1912 menu "Floating point emulation"
1914 comment "At least one emulation must be selected"
1917 bool "NWFPE math emulation"
1918 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1920 Say Y to include the NWFPE floating point emulator in the kernel.
1921 This is necessary to run most binaries. Linux does not currently
1922 support floating point hardware so you need to say Y here even if
1923 your machine has an FPA or floating point co-processor podule.
1925 You may say N here if you are going to load the Acorn FPEmulator
1926 early in the bootup.
1929 bool "Support extended precision"
1930 depends on FPE_NWFPE
1932 Say Y to include 80-bit support in the kernel floating-point
1933 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1934 Note that gcc does not generate 80-bit operations by default,
1935 so in most cases this option only enlarges the size of the
1936 floating point emulator without any good reason.
1938 You almost surely want to say N here.
1941 bool "FastFPE math emulation (EXPERIMENTAL)"
1942 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1944 Say Y here to include the FAST floating point emulator in the kernel.
1945 This is an experimental much faster emulator which now also has full
1946 precision for the mantissa. It does not support any exceptions.
1947 It is very simple, and approximately 3-6 times faster than NWFPE.
1949 It should be sufficient for most programs. It may be not suitable
1950 for scientific calculations, but you have to check this for yourself.
1951 If you do not feel you need a faster FP emulation you should better
1955 bool "VFP-format floating point maths"
1956 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1958 Say Y to include VFP support code in the kernel. This is needed
1959 if your hardware includes a VFP unit.
1961 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1962 release notes and additional status information.
1964 Say N if your target does not have VFP hardware.
1972 bool "Advanced SIMD (NEON) Extension support"
1973 depends on VFPv3 && CPU_V7
1975 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1980 menu "Userspace binary formats"
1982 source "fs/Kconfig.binfmt"
1985 tristate "RISC OS personality"
1988 Say Y here to include the kernel code necessary if you want to run
1989 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1990 experimental; if this sounds frightening, say N and sleep in peace.
1991 You can also say M here to compile this support as a module (which
1992 will be called arthur).
1996 menu "Power management options"
1998 source "kernel/power/Kconfig"
2000 config ARCH_SUSPEND_POSSIBLE
2001 depends on !ARCH_S5P64X0
2002 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2003 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2008 source "net/Kconfig"
2010 source "drivers/Kconfig"
2014 source "arch/arm/Kconfig.debug"
2016 source "security/Kconfig"
2018 source "crypto/Kconfig"
2020 source "lib/Kconfig"