5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
68 select GENERIC_ALLOCATOR
79 The Extended Industry Standard Architecture (EISA) bus was
80 developed as an open alternative to the IBM MicroChannel bus.
82 The EISA bus provided some of the features of the IBM MicroChannel
83 bus while maintaining backward compatibility with cards made for
84 the older ISA bus. The EISA bus saw limited use between 1988 and
85 1995 when it was made obsolete by the PCI bus.
87 Say Y here if you are building a kernel for an EISA-based machine.
97 MicroChannel Architecture is found in some IBM PS/2 machines and
98 laptops. It is a bus system similar to PCI or ISA. See
99 <file:Documentation/mca.txt> (and especially the web page given
100 there) before attempting to build an MCA bus kernel.
102 config STACKTRACE_SUPPORT
106 config HAVE_LATENCYTOP_SUPPORT
111 config LOCKDEP_SUPPORT
115 config TRACE_IRQFLAGS_SUPPORT
119 config HARDIRQS_SW_RESEND
123 config GENERIC_IRQ_PROBE
127 config GENERIC_LOCKBREAK
130 depends on SMP && PREEMPT
132 config RWSEM_GENERIC_SPINLOCK
136 config RWSEM_XCHGADD_ALGORITHM
139 config ARCH_HAS_ILOG2_U32
142 config ARCH_HAS_ILOG2_U64
145 config ARCH_HAS_CPUFREQ
148 Internal node to signify that the ARCH has CPUFREQ support
149 and that the relevant menu configurations are displayed for
152 config ARCH_HAS_CPU_IDLE_WAIT
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config GENERIC_ISA_DMA
181 config ARM_L1_CACHE_SHIFT_6
184 Setting ARM L1 cache line size to 64 Bytes.
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 source "init/Kconfig"
196 source "kernel/Kconfig.freezer"
201 bool "MMU-based Paged Memory Management Support"
204 Select if you want MMU-based virtualised addressing space
205 support by paged memory management. If unsure, say 'Y'.
208 # The "ARM system type" choice list is ordered alphabetically by option
209 # text. Please add new entries in the option alphabetic order.
212 prompt "ARM system type"
213 default ARCH_VERSATILE
216 bool "Agilent AAEC-2000 based"
220 select ARCH_USES_GETTIMEOFFSET
222 This enables support for systems based on the Agilent AAEC-2000
224 config ARCH_INTEGRATOR
225 bool "ARM Ltd. Integrator family"
227 select ARCH_HAS_CPUFREQ
230 select GENERIC_CLOCKEVENTS
231 select PLAT_VERSATILE
233 Support for ARM's Integrator platform.
236 bool "ARM Ltd. RealView family"
239 select HAVE_SCHED_CLOCK
241 select GENERIC_CLOCKEVENTS
242 select ARCH_WANT_OPTIONAL_GPIOLIB
243 select PLAT_VERSATILE
244 select ARM_TIMER_SP804
245 select GPIO_PL061 if GPIOLIB
247 This enables support for ARM Ltd RealView boards.
249 config ARCH_VERSATILE
250 bool "ARM Ltd. Versatile family"
254 select HAVE_SCHED_CLOCK
256 select GENERIC_CLOCKEVENTS
257 select ARCH_WANT_OPTIONAL_GPIOLIB
258 select PLAT_VERSATILE
259 select ARM_TIMER_SP804
261 This enables support for ARM Ltd Versatile board.
264 bool "ARM Ltd. Versatile Express family"
265 select ARCH_WANT_OPTIONAL_GPIOLIB
267 select ARM_TIMER_SP804
269 select GENERIC_CLOCKEVENTS
271 select HAVE_SCHED_CLOCK
273 select PLAT_VERSATILE
275 This enables support for the ARM Ltd Versatile Express boards.
279 select ARCH_REQUIRE_GPIOLIB
282 This enables support for systems based on the Atmel AT91RM9200,
283 AT91SAM9 and AT91CAP9 processors.
286 bool "Broadcom BCMRING"
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
294 Support for Broadcom's BCMRing platform.
297 bool "Cirrus Logic CLPS711x/EP721x-based"
299 select ARCH_USES_GETTIMEOFFSET
301 Support for Cirrus Logic 711x/721x based boards.
304 bool "Cavium Networks CNS3XXX family"
306 select GENERIC_CLOCKEVENTS
308 select MIGHT_HAVE_PCI
309 select PCI_DOMAINS if PCI
311 Support for Cavium Networks CNS3XXX platform.
314 bool "Cortina Systems Gemini"
316 select ARCH_REQUIRE_GPIOLIB
317 select ARCH_USES_GETTIMEOFFSET
319 Support for the Cortina Systems Gemini family SoCs
326 select ARCH_USES_GETTIMEOFFSET
328 This is an evaluation board for the StrongARM processor available
329 from Digital. It has limited hardware on-board, including an
330 Ethernet interface, two PCMCIA sockets, two serial ports and a
339 select ARCH_REQUIRE_GPIOLIB
340 select ARCH_HAS_HOLES_MEMORYMODEL
341 select ARCH_USES_GETTIMEOFFSET
343 This enables support for the Cirrus EP93xx series of CPUs.
345 config ARCH_FOOTBRIDGE
349 select ARCH_USES_GETTIMEOFFSET
351 Support for systems based on the DC21285 companion chip
352 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
355 bool "Freescale MXC/iMX-based"
356 select GENERIC_CLOCKEVENTS
357 select ARCH_REQUIRE_GPIOLIB
360 Support for Freescale MXC/iMX-based family of processors
363 bool "Freescale MXS-based"
364 select GENERIC_CLOCKEVENTS
365 select ARCH_REQUIRE_GPIOLIB
368 Support for Freescale MXS-based family of processors
371 bool "Freescale STMP3xxx"
374 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
376 select USB_ARCH_HAS_EHCI
378 Support for systems based on the Freescale 3xxx CPUs.
381 bool "Hilscher NetX based"
384 select GENERIC_CLOCKEVENTS
386 This enables support for systems based on the Hilscher NetX Soc
389 bool "Hynix HMS720x-based"
392 select ARCH_USES_GETTIMEOFFSET
394 This enables support for systems based on the Hynix HMS720x
402 select ARCH_SUPPORTS_MSI
405 Support for Intel's IOP13XX (XScale) family of processors.
413 select ARCH_REQUIRE_GPIOLIB
415 Support for Intel's 80219 and IOP32X (XScale) family of
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's IOP33X (XScale) family of processors.
433 select ARCH_USES_GETTIMEOFFSET
435 Support for Intel's IXP23xx (XScale) family of processors.
438 bool "IXP2400/2800-based"
442 select ARCH_USES_GETTIMEOFFSET
444 Support for Intel's IXP2400/2800 (XScale) family of processors.
451 select GENERIC_CLOCKEVENTS
452 select HAVE_SCHED_CLOCK
453 select MIGHT_HAVE_PCI
454 select DMABOUNCE if PCI
456 Support for Intel's IXP4XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
462 select GENERIC_CLOCKEVENTS
465 Support for the Marvell Dove SoC 88AP510
468 bool "Marvell Kirkwood"
471 select ARCH_REQUIRE_GPIOLIB
472 select GENERIC_CLOCKEVENTS
475 Support for the following Marvell Kirkwood series SoCs:
476 88F6180, 88F6192 and 88F6281.
479 bool "Marvell Loki (88RC8480)"
481 select GENERIC_CLOCKEVENTS
484 Support for the Marvell Loki (88RC8480) SoC.
489 select ARCH_REQUIRE_GPIOLIB
492 select USB_ARCH_HAS_OHCI
495 select GENERIC_CLOCKEVENTS
497 Support for the NXP LPC32XX family of processors
500 bool "Marvell MV78xx0"
503 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
507 Support for the following Marvell MV78xx0 series SoCs:
515 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
519 Support for the following Marvell Orion 5x series SoCs:
520 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
521 Orion-2 (5281), Orion-1-90 (6183).
524 bool "Marvell PXA168/910/MMP2"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select HAVE_SCHED_CLOCK
534 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
537 bool "Micrel/Kendin KS8695"
539 select ARCH_REQUIRE_GPIOLIB
540 select ARCH_USES_GETTIMEOFFSET
542 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
543 System-on-Chip devices.
546 bool "NetSilicon NS9xxx"
549 select GENERIC_CLOCKEVENTS
552 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
555 <http://www.digi.com/products/microprocessors/index.jsp>
558 bool "Nuvoton W90X900 CPU"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
565 At present, the w90x900 has been renamed nuc900, regarding
566 the ARM series product line, you can login the following
567 link address to know more.
569 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
570 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
573 bool "Nuvoton NUC93X CPU"
577 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
578 low-power and high performance MPEG-4/JPEG multimedia controller chip.
584 select GENERIC_CLOCKEVENTS
587 select HAVE_SCHED_CLOCK
588 select ARCH_HAS_BARRIERS if CACHE_L2X0
589 select ARCH_HAS_CPUFREQ
591 This enables support for NVIDIA Tegra based systems (Tegra APX,
592 Tegra 6xx and Tegra 2 series).
595 bool "Philips Nexperia PNX4008 Mobile"
598 select ARCH_USES_GETTIMEOFFSET
600 This enables support for Philips PNX4008 mobile platform.
603 bool "PXA2xx/PXA3xx-based"
606 select ARCH_HAS_CPUFREQ
608 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select HAVE_SCHED_CLOCK
615 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
620 select GENERIC_CLOCKEVENTS
621 select ARCH_REQUIRE_GPIOLIB
623 Support for Qualcomm MSM/QSD based systems. This runs on the
624 apps processor of the MSM/QSD and depends on a shared memory
625 interface to the modem processor which runs the baseband
626 stack and controls some vital subsystems
627 (clock and power control, etc).
630 bool "Renesas SH-Mobile / R-Mobile"
633 select GENERIC_CLOCKEVENTS
636 select MULTI_IRQ_HANDLER
638 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
645 select ARCH_MAY_HAVE_PC_FDC
646 select HAVE_PATA_PLATFORM
649 select ARCH_SPARSEMEM_ENABLE
650 select ARCH_USES_GETTIMEOFFSET
652 On the Acorn Risc-PC, Linux can support the internal IDE disk and
653 CD-ROM interface, serial and parallel port, and the floppy drive.
659 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_HAS_CPUFREQ
663 select GENERIC_CLOCKEVENTS
665 select HAVE_SCHED_CLOCK
667 select ARCH_REQUIRE_GPIOLIB
669 Support for StrongARM 11x0 based boards.
672 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
674 select ARCH_HAS_CPUFREQ
676 select ARCH_USES_GETTIMEOFFSET
677 select HAVE_S3C2410_I2C if I2C
679 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
680 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
681 the Samsung SMDK2410 development board (and derivatives).
683 Note, the S3C2416 and the S3C2450 are so close that they even share
684 the same SoC ID code. This means that there is no seperate machine
685 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
688 bool "Samsung S3C64XX"
694 select ARCH_USES_GETTIMEOFFSET
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
697 select SAMSUNG_CLKSRC
698 select SAMSUNG_IRQ_VIC_TIMER
699 select SAMSUNG_IRQ_UART
700 select S3C_GPIO_TRACK
701 select S3C_GPIO_PULL_UPDOWN
702 select S3C_GPIO_CFG_S3C24XX
703 select S3C_GPIO_CFG_S3C64XX
705 select USB_ARCH_HAS_OHCI
706 select SAMSUNG_GPIOLIB_4BIT
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 Samsung S3C64XX series based systems
713 bool "Samsung S5P6440 S5P6450"
717 select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 select ARCH_USES_GETTIMEOFFSET
719 select HAVE_S3C2410_I2C if I2C
720 select HAVE_S3C_RTC if RTC_CLASS
722 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
726 bool "Samsung S5P6442"
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 Samsung S5P6442 CPU based systems
736 bool "Samsung S5PC100"
740 select ARM_L1_CACHE_SHIFT_6
741 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_S3C2410_I2C if I2C
743 select HAVE_S3C_RTC if RTC_CLASS
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 Samsung S5PC100 series based systems
749 bool "Samsung S5PV210/S5PC110"
751 select ARCH_SPARSEMEM_ENABLE
754 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_HAS_CPUFREQ
756 select ARCH_USES_GETTIMEOFFSET
757 select HAVE_S3C2410_I2C if I2C
758 select HAVE_S3C_RTC if RTC_CLASS
759 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 Samsung S5PV210/S5PC110 series based systems
764 bool "Samsung S5PV310/S5PC210"
766 select ARCH_SPARSEMEM_ENABLE
769 select ARCH_HAS_CPUFREQ
770 select GENERIC_CLOCKEVENTS
771 select HAVE_S3C_RTC if RTC_CLASS
772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 Samsung S5PV310 series based systems
784 select ARCH_USES_GETTIMEOFFSET
786 Support for the StrongARM based Digital DNARD machine, also known
787 as "Shark" (<http://www.shark-linux.de/shark.html>).
790 bool "Telechips TCC ARM926-based systems"
794 select GENERIC_CLOCKEVENTS
796 Support for Telechips TCC ARM926-based systems.
801 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
802 select ARCH_USES_GETTIMEOFFSET
804 Say Y here for systems based on one of the Sharp LH7A40X
805 System on a Chip processors. These CPUs include an ARM922T
806 core with a wide array of integrated devices for
807 hand-held and low-power applications.
810 bool "ST-Ericsson U300 Series"
813 select HAVE_SCHED_CLOCK
817 select GENERIC_CLOCKEVENTS
821 Support for ST-Ericsson U300 series mobile platforms.
824 bool "ST-Ericsson U8500 Series"
827 select GENERIC_CLOCKEVENTS
829 select ARCH_REQUIRE_GPIOLIB
830 select ARCH_HAS_CPUFREQ
832 Support for ST-Ericsson's Ux500 architecture
835 bool "STMicroelectronics Nomadik"
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
843 Support for the Nomadik platform by ST-Ericsson
847 select GENERIC_CLOCKEVENTS
848 select ARCH_REQUIRE_GPIOLIB
852 select GENERIC_ALLOCATOR
853 select ARCH_HAS_HOLES_MEMORYMODEL
855 Support for TI's DaVinci platform.
860 select ARCH_REQUIRE_GPIOLIB
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_SCHED_CLOCK
864 select ARCH_HAS_HOLES_MEMORYMODEL
866 Support for TI's OMAP platform (OMAP1/2/3/4).
871 select ARCH_REQUIRE_GPIOLIB
873 select GENERIC_CLOCKEVENTS
876 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
881 # This is sorted alphabetically by mach-* pathname. However, plat-*
882 # Kconfigs may be included either alphabetically (according to the
883 # plat- suffix) or along side the corresponding mach-* source.
885 source "arch/arm/mach-aaec2000/Kconfig"
887 source "arch/arm/mach-at91/Kconfig"
889 source "arch/arm/mach-bcmring/Kconfig"
891 source "arch/arm/mach-clps711x/Kconfig"
893 source "arch/arm/mach-cns3xxx/Kconfig"
895 source "arch/arm/mach-davinci/Kconfig"
897 source "arch/arm/mach-dove/Kconfig"
899 source "arch/arm/mach-ep93xx/Kconfig"
901 source "arch/arm/mach-footbridge/Kconfig"
903 source "arch/arm/mach-gemini/Kconfig"
905 source "arch/arm/mach-h720x/Kconfig"
907 source "arch/arm/mach-integrator/Kconfig"
909 source "arch/arm/mach-iop32x/Kconfig"
911 source "arch/arm/mach-iop33x/Kconfig"
913 source "arch/arm/mach-iop13xx/Kconfig"
915 source "arch/arm/mach-ixp4xx/Kconfig"
917 source "arch/arm/mach-ixp2000/Kconfig"
919 source "arch/arm/mach-ixp23xx/Kconfig"
921 source "arch/arm/mach-kirkwood/Kconfig"
923 source "arch/arm/mach-ks8695/Kconfig"
925 source "arch/arm/mach-lh7a40x/Kconfig"
927 source "arch/arm/mach-loki/Kconfig"
929 source "arch/arm/mach-lpc32xx/Kconfig"
931 source "arch/arm/mach-msm/Kconfig"
933 source "arch/arm/mach-mv78xx0/Kconfig"
935 source "arch/arm/plat-mxc/Kconfig"
937 source "arch/arm/mach-mxs/Kconfig"
939 source "arch/arm/mach-netx/Kconfig"
941 source "arch/arm/mach-nomadik/Kconfig"
942 source "arch/arm/plat-nomadik/Kconfig"
944 source "arch/arm/mach-ns9xxx/Kconfig"
946 source "arch/arm/mach-nuc93x/Kconfig"
948 source "arch/arm/plat-omap/Kconfig"
950 source "arch/arm/mach-omap1/Kconfig"
952 source "arch/arm/mach-omap2/Kconfig"
954 source "arch/arm/mach-orion5x/Kconfig"
956 source "arch/arm/mach-pxa/Kconfig"
957 source "arch/arm/plat-pxa/Kconfig"
959 source "arch/arm/mach-mmp/Kconfig"
961 source "arch/arm/mach-realview/Kconfig"
963 source "arch/arm/mach-sa1100/Kconfig"
965 source "arch/arm/plat-samsung/Kconfig"
966 source "arch/arm/plat-s3c24xx/Kconfig"
967 source "arch/arm/plat-s5p/Kconfig"
969 source "arch/arm/plat-spear/Kconfig"
971 source "arch/arm/plat-tcc/Kconfig"
974 source "arch/arm/mach-s3c2400/Kconfig"
975 source "arch/arm/mach-s3c2410/Kconfig"
976 source "arch/arm/mach-s3c2412/Kconfig"
977 source "arch/arm/mach-s3c2416/Kconfig"
978 source "arch/arm/mach-s3c2440/Kconfig"
979 source "arch/arm/mach-s3c2443/Kconfig"
983 source "arch/arm/mach-s3c64xx/Kconfig"
986 source "arch/arm/mach-s5p64x0/Kconfig"
988 source "arch/arm/mach-s5p6442/Kconfig"
990 source "arch/arm/mach-s5pc100/Kconfig"
992 source "arch/arm/mach-s5pv210/Kconfig"
994 source "arch/arm/mach-s5pv310/Kconfig"
996 source "arch/arm/mach-shmobile/Kconfig"
998 source "arch/arm/plat-stmp3xxx/Kconfig"
1000 source "arch/arm/mach-tegra/Kconfig"
1002 source "arch/arm/mach-u300/Kconfig"
1004 source "arch/arm/mach-ux500/Kconfig"
1006 source "arch/arm/mach-versatile/Kconfig"
1008 source "arch/arm/mach-vexpress/Kconfig"
1010 source "arch/arm/mach-w90x900/Kconfig"
1012 # Definitions to make life easier
1018 select GENERIC_CLOCKEVENTS
1019 select HAVE_SCHED_CLOCK
1023 select HAVE_SCHED_CLOCK
1028 config PLAT_VERSATILE
1031 config ARM_TIMER_SP804
1034 source arch/arm/mm/Kconfig
1037 bool "Enable iWMMXt support"
1038 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1039 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1041 Enable support for iWMMXt context switching at run time if
1042 running on a CPU that supports it.
1044 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1047 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1051 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1052 (!ARCH_OMAP3 || OMAP3_EMU)
1056 config MULTI_IRQ_HANDLER
1059 Allow each machine to specify it's own IRQ handler at run time.
1062 source "arch/arm/Kconfig-nommu"
1065 config ARM_ERRATA_411920
1066 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1069 Invalidation of the Instruction Cache operation can
1070 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1071 It does not affect the MPCore. This option enables the ARM Ltd.
1072 recommended workaround.
1074 config ARM_ERRATA_430973
1075 bool "ARM errata: Stale prediction on replaced interworking branch"
1078 This option enables the workaround for the 430973 Cortex-A8
1079 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1080 interworking branch is replaced with another code sequence at the
1081 same virtual address, whether due to self-modifying code or virtual
1082 to physical address re-mapping, Cortex-A8 does not recover from the
1083 stale interworking branch prediction. This results in Cortex-A8
1084 executing the new code sequence in the incorrect ARM or Thumb state.
1085 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1086 and also flushes the branch target cache at every context switch.
1087 Note that setting specific bits in the ACTLR register may not be
1088 available in non-secure mode.
1090 config ARM_ERRATA_458693
1091 bool "ARM errata: Processor deadlock when a false hazard is created"
1094 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1095 erratum. For very specific sequences of memory operations, it is
1096 possible for a hazard condition intended for a cache line to instead
1097 be incorrectly associated with a different cache line. This false
1098 hazard might then cause a processor deadlock. The workaround enables
1099 the L1 caching of the NEON accesses and disables the PLD instruction
1100 in the ACTLR register. Note that setting specific bits in the ACTLR
1101 register may not be available in non-secure mode.
1103 config ARM_ERRATA_460075
1104 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1107 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1108 erratum. Any asynchronous access to the L2 cache may encounter a
1109 situation in which recent store transactions to the L2 cache are lost
1110 and overwritten with stale memory contents from external memory. The
1111 workaround disables the write-allocate mode for the L2 cache via the
1112 ACTLR register. Note that setting specific bits in the ACTLR register
1113 may not be available in non-secure mode.
1115 config ARM_ERRATA_742230
1116 bool "ARM errata: DMB operation may be faulty"
1117 depends on CPU_V7 && SMP
1119 This option enables the workaround for the 742230 Cortex-A9
1120 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1121 between two write operations may not ensure the correct visibility
1122 ordering of the two writes. This workaround sets a specific bit in
1123 the diagnostic register of the Cortex-A9 which causes the DMB
1124 instruction to behave as a DSB, ensuring the correct behaviour of
1127 config ARM_ERRATA_742231
1128 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1129 depends on CPU_V7 && SMP
1131 This option enables the workaround for the 742231 Cortex-A9
1132 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1133 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1134 accessing some data located in the same cache line, may get corrupted
1135 data due to bad handling of the address hazard when the line gets
1136 replaced from one of the CPUs at the same time as another CPU is
1137 accessing it. This workaround sets specific bits in the diagnostic
1138 register of the Cortex-A9 which reduces the linefill issuing
1139 capabilities of the processor.
1141 config PL310_ERRATA_588369
1142 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1143 depends on CACHE_L2X0 && ARCH_OMAP4
1145 The PL310 L2 cache controller implements three types of Clean &
1146 Invalidate maintenance operations: by Physical Address
1147 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1148 They are architecturally defined to behave as the execution of a
1149 clean operation followed immediately by an invalidate operation,
1150 both performing to the same memory location. This functionality
1151 is not correctly implemented in PL310 as clean lines are not
1152 invalidated as a result of these operations. Note that this errata
1153 uses Texas Instrument's secure monitor api.
1155 config ARM_ERRATA_720789
1156 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1157 depends on CPU_V7 && SMP
1159 This option enables the workaround for the 720789 Cortex-A9 (prior to
1160 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1161 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1162 As a consequence of this erratum, some TLB entries which should be
1163 invalidated are not, resulting in an incoherency in the system page
1164 tables. The workaround changes the TLB flushing routines to invalidate
1165 entries regardless of the ASID.
1167 config ARM_ERRATA_743622
1168 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1171 This option enables the workaround for the 743622 Cortex-A9
1172 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1173 optimisation in the Cortex-A9 Store Buffer may lead to data
1174 corruption. This workaround sets a specific bit in the diagnostic
1175 register of the Cortex-A9 which disables the Store Buffer
1176 optimisation, preventing the defect from occurring. This has no
1177 visible impact on the overall performance or power consumption of the
1180 config ARM_ERRATA_751472
1181 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1182 depends on CPU_V7 && SMP
1184 This option enables the workaround for the 751472 Cortex-A9 (prior
1185 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1186 completion of a following broadcasted operation if the second
1187 operation is received by a CPU before the ICIALLUIS has completed,
1188 potentially leading to corrupted entries in the cache or TLB.
1190 config ARM_ERRATA_753970
1191 bool "ARM errata: cache sync operation may be faulty"
1192 depends on CACHE_PL310
1194 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1196 Under some condition the effect of cache sync operation on
1197 the store buffer still remains when the operation completes.
1198 This means that the store buffer is always asked to drain and
1199 this prevents it from merging any further writes. The workaround
1200 is to replace the normal offset of cache sync operation (0x730)
1201 by another offset targeting an unmapped PL310 register 0x740.
1202 This has the same effect as the cache sync operation: store buffer
1203 drain and waiting for all buffers empty.
1205 config ARM_ERRATA_754322
1206 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1209 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1210 r3p*) erratum. A speculative memory access may cause a page table walk
1211 which starts prior to an ASID switch but completes afterwards. This
1212 can populate the micro-TLB with a stale entry which may be hit with
1213 the new ASID. This workaround places two dsb instructions in the mm
1214 switching code so that no page table walks can cross the ASID switch.
1216 config ARM_ERRATA_754327
1217 bool "ARM errata: no automatic Store Buffer drain"
1218 depends on CPU_V7 && SMP
1220 This option enables the workaround for the 754327 Cortex-A9 (prior to
1221 r2p0) erratum. The Store Buffer does not have any automatic draining
1222 mechanism and therefore a livelock may occur if an external agent
1223 continuously polls a memory location waiting to observe an update.
1224 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1225 written polling loops from denying visibility of updates to memory.
1229 source "arch/arm/common/Kconfig"
1239 Find out whether you have ISA slots on your motherboard. ISA is the
1240 name of a bus system, i.e. the way the CPU talks to the other stuff
1241 inside your box. Other bus systems are PCI, EISA, MicroChannel
1242 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1243 newer boards don't support it. If you have ISA, say Y, otherwise N.
1245 # Select ISA DMA controller support
1250 # Select ISA DMA interface
1255 bool "PCI support" if MIGHT_HAVE_PCI
1257 Find out whether you have a PCI motherboard. PCI is the name of a
1258 bus system, i.e. the way the CPU talks to the other stuff inside
1259 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1260 VESA. If you have PCI, say Y, otherwise N.
1266 config PCI_NANOENGINE
1267 bool "BSE nanoEngine PCI support"
1268 depends on SA1100_NANOENGINE
1270 Enable PCI on the BSE nanoEngine board.
1275 # Select the host bridge type
1276 config PCI_HOST_VIA82C505
1278 depends on PCI && ARCH_SHARK
1281 config PCI_HOST_ITE8152
1283 depends on PCI && MACH_ARMCORE
1287 source "drivers/pci/Kconfig"
1289 source "drivers/pcmcia/Kconfig"
1293 menu "Kernel Features"
1295 source "kernel/time/Kconfig"
1298 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1299 depends on EXPERIMENTAL
1300 depends on GENERIC_CLOCKEVENTS
1301 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1302 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1303 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1304 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1305 select USE_GENERIC_SMP_HELPERS
1306 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1308 This enables support for systems with more than one CPU. If you have
1309 a system with only one CPU, like most personal computers, say N. If
1310 you have a system with more than one CPU, say Y.
1312 If you say N here, the kernel will run on single and multiprocessor
1313 machines, but will use only one CPU of a multiprocessor machine. If
1314 you say Y here, the kernel will run on many, but not all, single
1315 processor machines. On a single processor machine, the kernel will
1316 run faster if you say N here.
1318 See also <file:Documentation/i386/IO-APIC.txt>,
1319 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1320 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1322 If you don't know what to do here, say N.
1325 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1326 depends on EXPERIMENTAL
1327 depends on SMP && !XIP_KERNEL
1330 SMP kernels contain instructions which fail on non-SMP processors.
1331 Enabling this option allows the kernel to modify itself to make
1332 these instructions safe. Disabling it allows about 1K of space
1335 If you don't know what to do here, say Y.
1341 This option enables support for the ARM system coherency unit
1348 This options enables support for the ARM timer and watchdog unit
1351 prompt "Memory split"
1354 Select the desired split between kernel and user memory.
1356 If you are not absolutely sure what you are doing, leave this
1360 bool "3G/1G user/kernel split"
1362 bool "2G/2G user/kernel split"
1364 bool "1G/3G user/kernel split"
1369 default 0x40000000 if VMSPLIT_1G
1370 default 0x80000000 if VMSPLIT_2G
1374 int "Maximum number of CPUs (2-32)"
1380 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1381 depends on SMP && HOTPLUG && EXPERIMENTAL
1382 depends on !ARCH_MSM
1384 Say Y here to experiment with turning CPUs off and on. CPUs
1385 can be controlled through /sys/devices/system/cpu.
1388 bool "Use local timer interrupts"
1391 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1393 Enable support for local timers on SMP platforms, rather then the
1394 legacy IPI broadcast method. Local timers allows the system
1395 accounting to be spread across the timer interval, preventing a
1396 "thundering herd" at every timer tick.
1398 source kernel/Kconfig.preempt
1402 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1403 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1404 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1405 default AT91_TIMER_HZ if ARCH_AT91
1406 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1409 config THUMB2_KERNEL
1410 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1411 depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
1413 select ARM_ASM_UNIFIED
1415 By enabling this option, the kernel will be compiled in
1416 Thumb-2 mode. A compiler/assembler that understand the unified
1417 ARM-Thumb syntax is needed.
1421 config ARM_ASM_UNIFIED
1425 bool "Use the ARM EABI to compile the kernel"
1427 This option allows for the kernel to be compiled using the latest
1428 ARM ABI (aka EABI). This is only useful if you are using a user
1429 space environment that is also compiled with EABI.
1431 Since there are major incompatibilities between the legacy ABI and
1432 EABI, especially with regard to structure member alignment, this
1433 option also changes the kernel syscall calling convention to
1434 disambiguate both ABIs and allow for backward compatibility support
1435 (selected with CONFIG_OABI_COMPAT).
1437 To use this you need GCC version 4.0.0 or later.
1440 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1441 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1444 This option preserves the old syscall interface along with the
1445 new (ARM EABI) one. It also provides a compatibility layer to
1446 intercept syscalls that have structure arguments which layout
1447 in memory differs between the legacy ABI and the new ARM EABI
1448 (only for non "thumb" binaries). This option adds a tiny
1449 overhead to all syscalls and produces a slightly larger kernel.
1450 If you know you'll be using only pure EABI user space then you
1451 can say N here. If this option is not selected and you attempt
1452 to execute a legacy ABI binary then the result will be
1453 UNPREDICTABLE (in fact it can be predicted that it won't work
1454 at all). If in doubt say Y.
1456 config ARCH_HAS_HOLES_MEMORYMODEL
1459 config ARCH_SPARSEMEM_ENABLE
1462 config ARCH_SPARSEMEM_DEFAULT
1463 def_bool ARCH_SPARSEMEM_ENABLE
1465 config ARCH_SELECT_MEMORY_MODEL
1466 def_bool ARCH_SPARSEMEM_ENABLE
1469 bool "High Memory Support (EXPERIMENTAL)"
1470 depends on MMU && EXPERIMENTAL
1472 The address space of ARM processors is only 4 Gigabytes large
1473 and it has to accommodate user address space, kernel address
1474 space as well as some memory mapped IO. That means that, if you
1475 have a large amount of physical memory and/or IO, not all of the
1476 memory can be "permanently mapped" by the kernel. The physical
1477 memory that is not permanently mapped is called "high memory".
1479 Depending on the selected kernel/user memory split, minimum
1480 vmalloc space and actual amount of RAM, you may not need this
1481 option which should result in a slightly faster kernel.
1486 bool "Allocate 2nd-level pagetables from highmem"
1488 depends on !OUTER_CACHE
1490 config HW_PERF_EVENTS
1491 bool "Enable hardware performance counter support for perf events"
1492 depends on PERF_EVENTS && CPU_HAS_PMU
1495 Enable hardware performance counter support for perf events. If
1496 disabled, perf events will use software events only.
1500 config FORCE_MAX_ZONEORDER
1501 int "Maximum zone order" if ARCH_SHMOBILE
1502 range 11 64 if ARCH_SHMOBILE
1503 default "9" if SA1111
1506 The kernel memory allocator divides physically contiguous memory
1507 blocks into "zones", where each zone is a power of two number of
1508 pages. This option selects the largest power of two that the kernel
1509 keeps in the memory allocator. If you need to allocate very large
1510 blocks of physically contiguous memory, then you may need to
1511 increase this value.
1513 This config option is actually maximum order plus one. For example,
1514 a value of 11 means that the largest free memory block is 2^10 pages.
1517 bool "Timer and CPU usage LEDs"
1518 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1519 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1520 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1521 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1522 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1523 ARCH_AT91 || ARCH_DAVINCI || \
1524 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1526 If you say Y here, the LEDs on your machine will be used
1527 to provide useful information about your current system status.
1529 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1530 be able to select which LEDs are active using the options below. If
1531 you are compiling a kernel for the EBSA-110 or the LART however, the
1532 red LED will simply flash regularly to indicate that the system is
1533 still functional. It is safe to say Y here if you have a CATS
1534 system, but the driver will do nothing.
1537 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1538 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1539 || MACH_OMAP_PERSEUS2
1541 depends on !GENERIC_CLOCKEVENTS
1542 default y if ARCH_EBSA110
1544 If you say Y here, one of the system LEDs (the green one on the
1545 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1546 will flash regularly to indicate that the system is still
1547 operational. This is mainly useful to kernel hackers who are
1548 debugging unstable kernels.
1550 The LART uses the same LED for both Timer LED and CPU usage LED
1551 functions. You may choose to use both, but the Timer LED function
1552 will overrule the CPU usage LED.
1555 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1557 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1558 || MACH_OMAP_PERSEUS2
1561 If you say Y here, the red LED will be used to give a good real
1562 time indication of CPU usage, by lighting whenever the idle task
1563 is not currently executing.
1565 The LART uses the same LED for both Timer LED and CPU usage LED
1566 functions. You may choose to use both, but the Timer LED function
1567 will overrule the CPU usage LED.
1569 config ALIGNMENT_TRAP
1571 depends on CPU_CP15_MMU
1572 default y if !ARCH_EBSA110
1573 select HAVE_PROC_CPU if PROC_FS
1575 ARM processors cannot fetch/store information which is not
1576 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1577 address divisible by 4. On 32-bit ARM processors, these non-aligned
1578 fetch/store instructions will be emulated in software if you say
1579 here, which has a severe performance impact. This is necessary for
1580 correct operation of some network protocols. With an IP-only
1581 configuration it is safe to say N, otherwise say Y.
1583 config UACCESS_WITH_MEMCPY
1584 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1585 depends on MMU && EXPERIMENTAL
1586 default y if CPU_FEROCEON
1588 Implement faster copy_to_user and clear_user methods for CPU
1589 cores where a 8-word STM instruction give significantly higher
1590 memory write throughput than a sequence of individual 32bit stores.
1592 A possible side effect is a slight increase in scheduling latency
1593 between threads sharing the same address space if they invoke
1594 such copy operations with large buffers.
1596 However, if the CPU data cache is using a write-allocate mode,
1597 this option is unlikely to provide any performance gain.
1601 prompt "Enable seccomp to safely compute untrusted bytecode"
1603 This kernel feature is useful for number crunching applications
1604 that may need to compute untrusted bytecode during their
1605 execution. By using pipes or other transports made available to
1606 the process as file descriptors supporting the read/write
1607 syscalls, it's possible to isolate those applications in
1608 their own address space using seccomp. Once seccomp is
1609 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1610 and the task is only allowed to execute a few safe syscalls
1611 defined by each seccomp mode.
1613 config CC_STACKPROTECTOR
1614 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1615 depends on EXPERIMENTAL
1617 This option turns on the -fstack-protector GCC feature. This
1618 feature puts, at the beginning of functions, a canary value on
1619 the stack just before the return address, and validates
1620 the value just before actually returning. Stack based buffer
1621 overflows (that need to overwrite this return address) now also
1622 overwrite the canary, which gets detected and the attack is then
1623 neutralized via a kernel panic.
1624 This feature requires gcc version 4.2 or above.
1626 config DEPRECATED_PARAM_STRUCT
1627 bool "Provide old way to pass kernel parameters"
1629 This was deprecated in 2001 and announced to live on for 5 years.
1630 Some old boot loaders still use this way.
1636 # Compressed boot loader in ROM. Yes, we really want to ask about
1637 # TEXT and BSS so we preserve their values in the config files.
1638 config ZBOOT_ROM_TEXT
1639 hex "Compressed ROM boot loader base address"
1642 The physical address at which the ROM-able zImage is to be
1643 placed in the target. Platforms which normally make use of
1644 ROM-able zImage formats normally set this to a suitable
1645 value in their defconfig file.
1647 If ZBOOT_ROM is not enabled, this has no effect.
1649 config ZBOOT_ROM_BSS
1650 hex "Compressed ROM boot loader BSS address"
1653 The base address of an area of read/write memory in the target
1654 for the ROM-able zImage which must be available while the
1655 decompressor is running. It must be large enough to hold the
1656 entire decompressed kernel plus an additional 128 KiB.
1657 Platforms which normally make use of ROM-able zImage formats
1658 normally set this to a suitable value in their defconfig file.
1660 If ZBOOT_ROM is not enabled, this has no effect.
1663 bool "Compressed boot loader in ROM/flash"
1664 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1666 Say Y here if you intend to execute your compressed kernel image
1667 (zImage) directly from ROM or flash. If unsure, say N.
1670 string "Default kernel command string"
1673 On some architectures (EBSA110 and CATS), there is currently no way
1674 for the boot loader to pass arguments to the kernel. For these
1675 architectures, you should supply some command-line options at build
1676 time by entering them here. As a minimum, you should specify the
1677 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1679 config CMDLINE_FORCE
1680 bool "Always use the default kernel command string"
1681 depends on CMDLINE != ""
1683 Always use the default kernel command string, even if the boot
1684 loader passes other arguments to the kernel.
1685 This is useful if you cannot or don't want to change the
1686 command-line options your boot loader passes to the kernel.
1691 bool "Kernel Execute-In-Place from ROM"
1692 depends on !ZBOOT_ROM
1694 Execute-In-Place allows the kernel to run from non-volatile storage
1695 directly addressable by the CPU, such as NOR flash. This saves RAM
1696 space since the text section of the kernel is not loaded from flash
1697 to RAM. Read-write sections, such as the data section and stack,
1698 are still copied to RAM. The XIP kernel is not compressed since
1699 it has to run directly from flash, so it will take more space to
1700 store it. The flash address used to link the kernel object files,
1701 and for storing it, is configuration dependent. Therefore, if you
1702 say Y here, you must know the proper physical address where to
1703 store the kernel image depending on your own flash memory usage.
1705 Also note that the make target becomes "make xipImage" rather than
1706 "make zImage" or "make Image". The final kernel binary to put in
1707 ROM memory will be arch/arm/boot/xipImage.
1711 config XIP_PHYS_ADDR
1712 hex "XIP Kernel Physical Location"
1713 depends on XIP_KERNEL
1714 default "0x00080000"
1716 This is the physical address in your flash memory the kernel will
1717 be linked for and stored to. This address is dependent on your
1721 bool "Kexec system call (EXPERIMENTAL)"
1722 depends on EXPERIMENTAL
1724 kexec is a system call that implements the ability to shutdown your
1725 current kernel, and to start another kernel. It is like a reboot
1726 but it is independent of the system firmware. And like a reboot
1727 you can start any kernel with it, not just Linux.
1729 It is an ongoing process to be certain the hardware in a machine
1730 is properly shutdown, so do not be surprised if this code does not
1731 initially work for you. It may help to enable device hotplugging
1735 bool "Export atags in procfs"
1739 Should the atags used to boot the kernel be exported in an "atags"
1740 file in procfs. Useful with kexec.
1743 bool "Build kdump crash kernel (EXPERIMENTAL)"
1744 depends on EXPERIMENTAL
1746 Generate crash dump after being started by kexec. This should
1747 be normally only set in special crash dump kernels which are
1748 loaded in the main kernel with kexec-tools into a specially
1749 reserved region and then later executed after a crash by
1750 kdump/kexec. The crash dump kernel must be compiled to a
1751 memory address not used by the main kernel
1753 For more details see Documentation/kdump/kdump.txt
1755 config AUTO_ZRELADDR
1756 bool "Auto calculation of the decompressed kernel image address"
1757 depends on !ZBOOT_ROM && !ARCH_U300
1759 ZRELADDR is the physical address where the decompressed kernel
1760 image will be placed. If AUTO_ZRELADDR is selected, the address
1761 will be determined at run-time by masking the current IP with
1762 0xf8000000. This assumes the zImage being placed in the first 128MB
1763 from start of memory.
1767 menu "CPU Power Management"
1771 source "drivers/cpufreq/Kconfig"
1774 tristate "CPUfreq driver for i.MX CPUs"
1775 depends on ARCH_MXC && CPU_FREQ
1777 This enables the CPUfreq driver for i.MX CPUs.
1779 config CPU_FREQ_SA1100
1782 config CPU_FREQ_SA1110
1785 config CPU_FREQ_INTEGRATOR
1786 tristate "CPUfreq driver for ARM Integrator CPUs"
1787 depends on ARCH_INTEGRATOR && CPU_FREQ
1790 This enables the CPUfreq driver for ARM Integrator CPUs.
1792 For details, take a look at <file:Documentation/cpu-freq>.
1798 depends on CPU_FREQ && ARCH_PXA && PXA25x
1800 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1802 config CPU_FREQ_S3C64XX
1803 bool "CPUfreq support for Samsung S3C64XX CPUs"
1804 depends on CPU_FREQ && CPU_S3C6410
1809 Internal configuration node for common cpufreq on Samsung SoC
1811 config CPU_FREQ_S3C24XX
1812 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1813 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1816 This enables the CPUfreq driver for the Samsung S3C24XX family
1819 For details, take a look at <file:Documentation/cpu-freq>.
1823 config CPU_FREQ_S3C24XX_PLL
1824 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1825 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1827 Compile in support for changing the PLL frequency from the
1828 S3C24XX series CPUfreq driver. The PLL takes time to settle
1829 after a frequency change, so by default it is not enabled.
1831 This also means that the PLL tables for the selected CPU(s) will
1832 be built which may increase the size of the kernel image.
1834 config CPU_FREQ_S3C24XX_DEBUG
1835 bool "Debug CPUfreq Samsung driver core"
1836 depends on CPU_FREQ_S3C24XX
1838 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1840 config CPU_FREQ_S3C24XX_IODEBUG
1841 bool "Debug CPUfreq Samsung driver IO timing"
1842 depends on CPU_FREQ_S3C24XX
1844 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1846 config CPU_FREQ_S3C24XX_DEBUGFS
1847 bool "Export debugfs for CPUFreq"
1848 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1850 Export status information via debugfs.
1854 source "drivers/cpuidle/Kconfig"
1858 menu "Floating point emulation"
1860 comment "At least one emulation must be selected"
1863 bool "NWFPE math emulation"
1864 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1866 Say Y to include the NWFPE floating point emulator in the kernel.
1867 This is necessary to run most binaries. Linux does not currently
1868 support floating point hardware so you need to say Y here even if
1869 your machine has an FPA or floating point co-processor podule.
1871 You may say N here if you are going to load the Acorn FPEmulator
1872 early in the bootup.
1875 bool "Support extended precision"
1876 depends on FPE_NWFPE
1878 Say Y to include 80-bit support in the kernel floating-point
1879 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1880 Note that gcc does not generate 80-bit operations by default,
1881 so in most cases this option only enlarges the size of the
1882 floating point emulator without any good reason.
1884 You almost surely want to say N here.
1887 bool "FastFPE math emulation (EXPERIMENTAL)"
1888 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1890 Say Y here to include the FAST floating point emulator in the kernel.
1891 This is an experimental much faster emulator which now also has full
1892 precision for the mantissa. It does not support any exceptions.
1893 It is very simple, and approximately 3-6 times faster than NWFPE.
1895 It should be sufficient for most programs. It may be not suitable
1896 for scientific calculations, but you have to check this for yourself.
1897 If you do not feel you need a faster FP emulation you should better
1901 bool "VFP-format floating point maths"
1902 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1904 Say Y to include VFP support code in the kernel. This is needed
1905 if your hardware includes a VFP unit.
1907 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1908 release notes and additional status information.
1910 Say N if your target does not have VFP hardware.
1918 bool "Advanced SIMD (NEON) Extension support"
1919 depends on VFPv3 && CPU_V7
1921 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1926 menu "Userspace binary formats"
1928 source "fs/Kconfig.binfmt"
1931 tristate "RISC OS personality"
1934 Say Y here to include the kernel code necessary if you want to run
1935 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1936 experimental; if this sounds frightening, say N and sleep in peace.
1937 You can also say M here to compile this support as a module (which
1938 will be called arthur).
1942 menu "Power management options"
1944 source "kernel/power/Kconfig"
1946 config ARCH_SUSPEND_POSSIBLE
1951 source "net/Kconfig"
1953 source "drivers/Kconfig"
1957 source "arch/arm/Kconfig.debug"
1959 source "security/Kconfig"
1961 source "crypto/Kconfig"
1963 source "lib/Kconfig"