5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
199 depends on EXPERIMENTAL
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary, or theoretically 64K
209 for the MSM machine class.
211 config ARM_PATCH_PHYS_VIRT_16BIT
213 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
215 This option extends the physical to virtual translation patching
216 to allow physical memory down to a theoretical minimum of 64K
219 source "init/Kconfig"
221 source "kernel/Kconfig.freezer"
226 bool "MMU-based Paged Memory Management Support"
229 Select if you want MMU-based virtualised addressing space
230 support by paged memory management. If unsure, say 'Y'.
233 # The "ARM system type" choice list is ordered alphabetically by option
234 # text. Please add new entries in the option alphabetic order.
237 prompt "ARM system type"
238 default ARCH_VERSATILE
240 config ARCH_INTEGRATOR
241 bool "ARM Ltd. Integrator family"
243 select ARCH_HAS_CPUFREQ
245 select HAVE_MACH_CLKDEV
247 select GENERIC_CLOCKEVENTS
248 select PLAT_VERSATILE
249 select PLAT_VERSATILE_FPGA_IRQ
251 Support for ARM's Integrator platform.
254 bool "ARM Ltd. RealView family"
257 select HAVE_MACH_CLKDEV
259 select GENERIC_CLOCKEVENTS
260 select ARCH_WANT_OPTIONAL_GPIOLIB
261 select PLAT_VERSATILE
262 select PLAT_VERSATILE_CLCD
263 select ARM_TIMER_SP804
264 select GPIO_PL061 if GPIOLIB
266 This enables support for ARM Ltd RealView boards.
268 config ARCH_VERSATILE
269 bool "ARM Ltd. Versatile family"
273 select HAVE_MACH_CLKDEV
275 select GENERIC_CLOCKEVENTS
276 select ARCH_WANT_OPTIONAL_GPIOLIB
277 select PLAT_VERSATILE
278 select PLAT_VERSATILE_CLCD
279 select PLAT_VERSATILE_FPGA_IRQ
280 select ARM_TIMER_SP804
282 This enables support for ARM Ltd Versatile board.
285 bool "ARM Ltd. Versatile Express family"
286 select ARCH_WANT_OPTIONAL_GPIOLIB
288 select ARM_TIMER_SP804
290 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
293 select HAVE_PATA_PLATFORM
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
298 This enables support for the ARM Ltd Versatile Express boards.
302 select ARCH_REQUIRE_GPIOLIB
305 select ARM_PATCH_PHYS_VIRT if MMU
307 This enables support for systems based on the Atmel AT91RM9200,
308 AT91SAM9 and AT91CAP9 processors.
311 bool "Broadcom BCMRING"
315 select ARM_TIMER_SP804
317 select GENERIC_CLOCKEVENTS
318 select ARCH_WANT_OPTIONAL_GPIOLIB
320 Support for Broadcom's BCMRing platform.
323 bool "Cirrus Logic CLPS711x/EP721x-based"
325 select ARCH_USES_GETTIMEOFFSET
327 Support for Cirrus Logic 711x/721x based boards.
330 bool "Cavium Networks CNS3XXX family"
332 select GENERIC_CLOCKEVENTS
334 select MIGHT_HAVE_PCI
335 select PCI_DOMAINS if PCI
337 Support for Cavium Networks CNS3XXX platform.
340 bool "Cortina Systems Gemini"
342 select ARCH_REQUIRE_GPIOLIB
343 select ARCH_USES_GETTIMEOFFSET
345 Support for the Cortina Systems Gemini family SoCs
348 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
352 select GENERIC_CLOCKEVENTS
354 select GENERIC_IRQ_CHIP
358 Support for CSR SiRFSoC ARM Cortex A9 Platform
365 select ARCH_USES_GETTIMEOFFSET
367 This is an evaluation board for the StrongARM processor available
368 from Digital. It has limited hardware on-board, including an
369 Ethernet interface, two PCMCIA sockets, two serial ports and a
378 select ARCH_REQUIRE_GPIOLIB
379 select ARCH_HAS_HOLES_MEMORYMODEL
380 select ARCH_USES_GETTIMEOFFSET
382 This enables support for the Cirrus EP93xx series of CPUs.
384 config ARCH_FOOTBRIDGE
388 select GENERIC_CLOCKEVENTS
390 Support for systems based on the DC21285 companion chip
391 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
394 bool "Freescale MXC/iMX-based"
395 select GENERIC_CLOCKEVENTS
396 select ARCH_REQUIRE_GPIOLIB
399 select HAVE_SCHED_CLOCK
401 Support for Freescale MXC/iMX-based family of processors
404 bool "Freescale MXS-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
410 Support for Freescale MXS-based family of processors
413 bool "Hilscher NetX based"
417 select GENERIC_CLOCKEVENTS
419 This enables support for systems based on the Hilscher NetX Soc
422 bool "Hynix HMS720x-based"
425 select ARCH_USES_GETTIMEOFFSET
427 This enables support for systems based on the Hynix HMS720x
435 select ARCH_SUPPORTS_MSI
438 Support for Intel's IOP13XX (XScale) family of processors.
446 select ARCH_REQUIRE_GPIOLIB
448 Support for Intel's 80219 and IOP32X (XScale) family of
457 select ARCH_REQUIRE_GPIOLIB
459 Support for Intel's IOP33X (XScale) family of processors.
466 select ARCH_USES_GETTIMEOFFSET
468 Support for Intel's IXP23xx (XScale) family of processors.
471 bool "IXP2400/2800-based"
475 select ARCH_USES_GETTIMEOFFSET
477 Support for Intel's IXP2400/2800 (XScale) family of processors.
485 select GENERIC_CLOCKEVENTS
486 select HAVE_SCHED_CLOCK
487 select MIGHT_HAVE_PCI
488 select DMABOUNCE if PCI
490 Support for Intel's IXP4XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Dove SoC 88AP510
503 bool "Marvell Kirkwood"
506 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
510 Support for the following Marvell Kirkwood series SoCs:
511 88F6180, 88F6192 and 88F6281.
517 select ARCH_REQUIRE_GPIOLIB
520 select USB_ARCH_HAS_OHCI
523 select GENERIC_CLOCKEVENTS
525 Support for the NXP LPC32XX family of processors
528 bool "Marvell MV78xx0"
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 Support for the following Marvell MV78xx0 series SoCs:
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select HAVE_SCHED_CLOCK
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 bool "Micrel/Kendin KS8695"
567 select ARCH_REQUIRE_GPIOLIB
568 select ARCH_USES_GETTIMEOFFSET
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
590 bool "Nuvoton NUC93X CPU"
594 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
595 low-power and high performance MPEG-4/JPEG multimedia controller chip.
602 select GENERIC_CLOCKEVENTS
605 select HAVE_SCHED_CLOCK
606 select ARCH_HAS_BARRIERS if CACHE_L2X0
607 select ARCH_HAS_CPUFREQ
609 This enables support for NVIDIA Tegra based systems (Tegra APX,
610 Tegra 6xx and Tegra 2 series).
613 bool "Philips Nexperia PNX4008 Mobile"
616 select ARCH_USES_GETTIMEOFFSET
618 This enables support for Philips PNX4008 mobile platform.
621 bool "PXA2xx/PXA3xx-based"
624 select ARCH_HAS_CPUFREQ
627 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
629 select HAVE_SCHED_CLOCK
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
639 select GENERIC_CLOCKEVENTS
640 select ARCH_REQUIRE_GPIOLIB
643 Support for Qualcomm MSM/QSD based systems. This runs on the
644 apps processor of the MSM/QSD and depends on a shared memory
645 interface to the modem processor which runs the baseband
646 stack and controls some vital subsystems
647 (clock and power control, etc).
650 bool "Renesas SH-Mobile / R-Mobile"
653 select HAVE_MACH_CLKDEV
654 select GENERIC_CLOCKEVENTS
657 select MULTI_IRQ_HANDLER
658 select PM_GENERIC_DOMAINS if PM
660 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
667 select ARCH_MAY_HAVE_PC_FDC
668 select HAVE_PATA_PLATFORM
671 select ARCH_SPARSEMEM_ENABLE
672 select ARCH_USES_GETTIMEOFFSET
674 On the Acorn Risc-PC, Linux can support the internal IDE disk and
675 CD-ROM interface, serial and parallel port, and the floppy drive.
682 select ARCH_SPARSEMEM_ENABLE
684 select ARCH_HAS_CPUFREQ
686 select GENERIC_CLOCKEVENTS
688 select HAVE_SCHED_CLOCK
690 select ARCH_REQUIRE_GPIOLIB
692 Support for StrongARM 11x0 based boards.
695 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
697 select ARCH_HAS_CPUFREQ
700 select ARCH_USES_GETTIMEOFFSET
701 select HAVE_S3C2410_I2C if I2C
703 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
704 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
705 the Samsung SMDK2410 development board (and derivatives).
707 Note, the S3C2416 and the S3C2450 are so close that they even share
708 the same SoC ID code. This means that there is no separate machine
709 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
712 bool "Samsung S3C64XX"
719 select ARCH_USES_GETTIMEOFFSET
720 select ARCH_HAS_CPUFREQ
721 select ARCH_REQUIRE_GPIOLIB
722 select SAMSUNG_CLKSRC
723 select SAMSUNG_IRQ_VIC_TIMER
724 select SAMSUNG_IRQ_UART
725 select S3C_GPIO_TRACK
726 select S3C_GPIO_PULL_UPDOWN
727 select S3C_GPIO_CFG_S3C24XX
728 select S3C_GPIO_CFG_S3C64XX
730 select USB_ARCH_HAS_OHCI
731 select SAMSUNG_GPIOLIB_4BIT
732 select HAVE_S3C2410_I2C if I2C
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 Samsung S3C64XX series based systems
738 bool "Samsung S5P6440 S5P6450"
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
745 select GENERIC_CLOCKEVENTS
746 select HAVE_SCHED_CLOCK
747 select HAVE_S3C2410_I2C if I2C
748 select HAVE_S3C_RTC if RTC_CLASS
750 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
754 bool "Samsung S5PC100"
759 select ARM_L1_CACHE_SHIFT_6
760 select ARCH_USES_GETTIMEOFFSET
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C_RTC if RTC_CLASS
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 Samsung S5PC100 series based systems
768 bool "Samsung S5PV210/S5PC110"
770 select ARCH_SPARSEMEM_ENABLE
775 select ARM_L1_CACHE_SHIFT_6
776 select ARCH_HAS_CPUFREQ
777 select GENERIC_CLOCKEVENTS
778 select HAVE_SCHED_CLOCK
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C_RTC if RTC_CLASS
781 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 Samsung S5PV210/S5PC110 series based systems
786 bool "Samsung EXYNOS4"
788 select ARCH_SPARSEMEM_ENABLE
792 select ARCH_HAS_CPUFREQ
793 select GENERIC_CLOCKEVENTS
794 select HAVE_S3C_RTC if RTC_CLASS
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 Samsung EXYNOS4 series based systems
807 select ARCH_USES_GETTIMEOFFSET
809 Support for the StrongARM based Digital DNARD machine, also known
810 as "Shark" (<http://www.shark-linux.de/shark.html>).
813 bool "Telechips TCC ARM926-based systems"
818 select GENERIC_CLOCKEVENTS
820 Support for Telechips TCC ARM926-based systems.
823 bool "ST-Ericsson U300 Series"
827 select HAVE_SCHED_CLOCK
831 select GENERIC_CLOCKEVENTS
833 select HAVE_MACH_CLKDEV
836 Support for ST-Ericsson U300 series mobile platforms.
839 bool "ST-Ericsson U8500 Series"
842 select GENERIC_CLOCKEVENTS
844 select ARCH_REQUIRE_GPIOLIB
845 select ARCH_HAS_CPUFREQ
847 Support for ST-Ericsson's Ux500 architecture
850 bool "STMicroelectronics Nomadik"
855 select GENERIC_CLOCKEVENTS
856 select ARCH_REQUIRE_GPIOLIB
858 Support for the Nomadik platform by ST-Ericsson
862 select GENERIC_CLOCKEVENTS
863 select ARCH_REQUIRE_GPIOLIB
867 select GENERIC_ALLOCATOR
868 select GENERIC_IRQ_CHIP
869 select ARCH_HAS_HOLES_MEMORYMODEL
871 Support for TI's DaVinci platform.
876 select ARCH_REQUIRE_GPIOLIB
877 select ARCH_HAS_CPUFREQ
879 select GENERIC_CLOCKEVENTS
880 select HAVE_SCHED_CLOCK
881 select ARCH_HAS_HOLES_MEMORYMODEL
883 Support for TI's OMAP platform (OMAP1/2/3/4).
888 select ARCH_REQUIRE_GPIOLIB
891 select GENERIC_CLOCKEVENTS
894 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
897 bool "VIA/WonderMedia 85xx"
900 select ARCH_HAS_CPUFREQ
901 select GENERIC_CLOCKEVENTS
902 select ARCH_REQUIRE_GPIOLIB
905 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
908 bool "Xilinx Zynq ARM Cortex A9 Platform"
911 select GENERIC_CLOCKEVENTS
918 Support for Xilinx Zynq ARM Cortex A9 Platform
922 # This is sorted alphabetically by mach-* pathname. However, plat-*
923 # Kconfigs may be included either alphabetically (according to the
924 # plat- suffix) or along side the corresponding mach-* source.
926 source "arch/arm/mach-at91/Kconfig"
928 source "arch/arm/mach-bcmring/Kconfig"
930 source "arch/arm/mach-clps711x/Kconfig"
932 source "arch/arm/mach-cns3xxx/Kconfig"
934 source "arch/arm/mach-davinci/Kconfig"
936 source "arch/arm/mach-dove/Kconfig"
938 source "arch/arm/mach-ep93xx/Kconfig"
940 source "arch/arm/mach-footbridge/Kconfig"
942 source "arch/arm/mach-gemini/Kconfig"
944 source "arch/arm/mach-h720x/Kconfig"
946 source "arch/arm/mach-integrator/Kconfig"
948 source "arch/arm/mach-iop32x/Kconfig"
950 source "arch/arm/mach-iop33x/Kconfig"
952 source "arch/arm/mach-iop13xx/Kconfig"
954 source "arch/arm/mach-ixp4xx/Kconfig"
956 source "arch/arm/mach-ixp2000/Kconfig"
958 source "arch/arm/mach-ixp23xx/Kconfig"
960 source "arch/arm/mach-kirkwood/Kconfig"
962 source "arch/arm/mach-ks8695/Kconfig"
964 source "arch/arm/mach-lpc32xx/Kconfig"
966 source "arch/arm/mach-msm/Kconfig"
968 source "arch/arm/mach-mv78xx0/Kconfig"
970 source "arch/arm/plat-mxc/Kconfig"
972 source "arch/arm/mach-mxs/Kconfig"
974 source "arch/arm/mach-netx/Kconfig"
976 source "arch/arm/mach-nomadik/Kconfig"
977 source "arch/arm/plat-nomadik/Kconfig"
979 source "arch/arm/mach-nuc93x/Kconfig"
981 source "arch/arm/plat-omap/Kconfig"
983 source "arch/arm/mach-omap1/Kconfig"
985 source "arch/arm/mach-omap2/Kconfig"
987 source "arch/arm/mach-orion5x/Kconfig"
989 source "arch/arm/mach-pxa/Kconfig"
990 source "arch/arm/plat-pxa/Kconfig"
992 source "arch/arm/mach-mmp/Kconfig"
994 source "arch/arm/mach-realview/Kconfig"
996 source "arch/arm/mach-sa1100/Kconfig"
998 source "arch/arm/plat-samsung/Kconfig"
999 source "arch/arm/plat-s3c24xx/Kconfig"
1000 source "arch/arm/plat-s5p/Kconfig"
1002 source "arch/arm/plat-spear/Kconfig"
1004 source "arch/arm/plat-tcc/Kconfig"
1007 source "arch/arm/mach-s3c2410/Kconfig"
1008 source "arch/arm/mach-s3c2412/Kconfig"
1009 source "arch/arm/mach-s3c2416/Kconfig"
1010 source "arch/arm/mach-s3c2440/Kconfig"
1011 source "arch/arm/mach-s3c2443/Kconfig"
1015 source "arch/arm/mach-s3c64xx/Kconfig"
1018 source "arch/arm/mach-s5p64x0/Kconfig"
1020 source "arch/arm/mach-s5pc100/Kconfig"
1022 source "arch/arm/mach-s5pv210/Kconfig"
1024 source "arch/arm/mach-exynos4/Kconfig"
1026 source "arch/arm/mach-shmobile/Kconfig"
1028 source "arch/arm/mach-tegra/Kconfig"
1030 source "arch/arm/mach-u300/Kconfig"
1032 source "arch/arm/mach-ux500/Kconfig"
1034 source "arch/arm/mach-versatile/Kconfig"
1036 source "arch/arm/mach-vexpress/Kconfig"
1037 source "arch/arm/plat-versatile/Kconfig"
1039 source "arch/arm/mach-vt8500/Kconfig"
1041 source "arch/arm/mach-w90x900/Kconfig"
1043 # Definitions to make life easier
1049 select GENERIC_CLOCKEVENTS
1050 select HAVE_SCHED_CLOCK
1055 select GENERIC_IRQ_CHIP
1056 select HAVE_SCHED_CLOCK
1061 config PLAT_VERSATILE
1064 config ARM_TIMER_SP804
1068 source arch/arm/mm/Kconfig
1071 bool "Enable iWMMXt support"
1072 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1073 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1075 Enable support for iWMMXt context switching at run time if
1076 running on a CPU that supports it.
1078 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1081 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1085 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1086 (!ARCH_OMAP3 || OMAP3_EMU)
1090 config MULTI_IRQ_HANDLER
1093 Allow each machine to specify it's own IRQ handler at run time.
1096 source "arch/arm/Kconfig-nommu"
1099 config ARM_ERRATA_411920
1100 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1101 depends on CPU_V6 || CPU_V6K
1103 Invalidation of the Instruction Cache operation can
1104 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1105 It does not affect the MPCore. This option enables the ARM Ltd.
1106 recommended workaround.
1108 config ARM_ERRATA_430973
1109 bool "ARM errata: Stale prediction on replaced interworking branch"
1112 This option enables the workaround for the 430973 Cortex-A8
1113 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1114 interworking branch is replaced with another code sequence at the
1115 same virtual address, whether due to self-modifying code or virtual
1116 to physical address re-mapping, Cortex-A8 does not recover from the
1117 stale interworking branch prediction. This results in Cortex-A8
1118 executing the new code sequence in the incorrect ARM or Thumb state.
1119 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1120 and also flushes the branch target cache at every context switch.
1121 Note that setting specific bits in the ACTLR register may not be
1122 available in non-secure mode.
1124 config ARM_ERRATA_458693
1125 bool "ARM errata: Processor deadlock when a false hazard is created"
1128 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1129 erratum. For very specific sequences of memory operations, it is
1130 possible for a hazard condition intended for a cache line to instead
1131 be incorrectly associated with a different cache line. This false
1132 hazard might then cause a processor deadlock. The workaround enables
1133 the L1 caching of the NEON accesses and disables the PLD instruction
1134 in the ACTLR register. Note that setting specific bits in the ACTLR
1135 register may not be available in non-secure mode.
1137 config ARM_ERRATA_460075
1138 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1141 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1142 erratum. Any asynchronous access to the L2 cache may encounter a
1143 situation in which recent store transactions to the L2 cache are lost
1144 and overwritten with stale memory contents from external memory. The
1145 workaround disables the write-allocate mode for the L2 cache via the
1146 ACTLR register. Note that setting specific bits in the ACTLR register
1147 may not be available in non-secure mode.
1149 config ARM_ERRATA_742230
1150 bool "ARM errata: DMB operation may be faulty"
1151 depends on CPU_V7 && SMP
1153 This option enables the workaround for the 742230 Cortex-A9
1154 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1155 between two write operations may not ensure the correct visibility
1156 ordering of the two writes. This workaround sets a specific bit in
1157 the diagnostic register of the Cortex-A9 which causes the DMB
1158 instruction to behave as a DSB, ensuring the correct behaviour of
1161 config ARM_ERRATA_742231
1162 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1163 depends on CPU_V7 && SMP
1165 This option enables the workaround for the 742231 Cortex-A9
1166 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1167 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1168 accessing some data located in the same cache line, may get corrupted
1169 data due to bad handling of the address hazard when the line gets
1170 replaced from one of the CPUs at the same time as another CPU is
1171 accessing it. This workaround sets specific bits in the diagnostic
1172 register of the Cortex-A9 which reduces the linefill issuing
1173 capabilities of the processor.
1175 config PL310_ERRATA_588369
1176 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1177 depends on CACHE_L2X0
1179 The PL310 L2 cache controller implements three types of Clean &
1180 Invalidate maintenance operations: by Physical Address
1181 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1182 They are architecturally defined to behave as the execution of a
1183 clean operation followed immediately by an invalidate operation,
1184 both performing to the same memory location. This functionality
1185 is not correctly implemented in PL310 as clean lines are not
1186 invalidated as a result of these operations.
1188 config ARM_ERRATA_720789
1189 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1190 depends on CPU_V7 && SMP
1192 This option enables the workaround for the 720789 Cortex-A9 (prior to
1193 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1194 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1195 As a consequence of this erratum, some TLB entries which should be
1196 invalidated are not, resulting in an incoherency in the system page
1197 tables. The workaround changes the TLB flushing routines to invalidate
1198 entries regardless of the ASID.
1200 config PL310_ERRATA_727915
1201 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1202 depends on CACHE_L2X0
1204 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1205 operation (offset 0x7FC). This operation runs in background so that
1206 PL310 can handle normal accesses while it is in progress. Under very
1207 rare circumstances, due to this erratum, write data can be lost when
1208 PL310 treats a cacheable write transaction during a Clean &
1209 Invalidate by Way operation.
1211 config ARM_ERRATA_743622
1212 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1215 This option enables the workaround for the 743622 Cortex-A9
1216 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1217 optimisation in the Cortex-A9 Store Buffer may lead to data
1218 corruption. This workaround sets a specific bit in the diagnostic
1219 register of the Cortex-A9 which disables the Store Buffer
1220 optimisation, preventing the defect from occurring. This has no
1221 visible impact on the overall performance or power consumption of the
1224 config ARM_ERRATA_751472
1225 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1226 depends on CPU_V7 && SMP
1228 This option enables the workaround for the 751472 Cortex-A9 (prior
1229 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1230 completion of a following broadcasted operation if the second
1231 operation is received by a CPU before the ICIALLUIS has completed,
1232 potentially leading to corrupted entries in the cache or TLB.
1234 config ARM_ERRATA_753970
1235 bool "ARM errata: cache sync operation may be faulty"
1236 depends on CACHE_PL310
1238 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1240 Under some condition the effect of cache sync operation on
1241 the store buffer still remains when the operation completes.
1242 This means that the store buffer is always asked to drain and
1243 this prevents it from merging any further writes. The workaround
1244 is to replace the normal offset of cache sync operation (0x730)
1245 by another offset targeting an unmapped PL310 register 0x740.
1246 This has the same effect as the cache sync operation: store buffer
1247 drain and waiting for all buffers empty.
1249 config ARM_ERRATA_754322
1250 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1253 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1254 r3p*) erratum. A speculative memory access may cause a page table walk
1255 which starts prior to an ASID switch but completes afterwards. This
1256 can populate the micro-TLB with a stale entry which may be hit with
1257 the new ASID. This workaround places two dsb instructions in the mm
1258 switching code so that no page table walks can cross the ASID switch.
1260 config ARM_ERRATA_754327
1261 bool "ARM errata: no automatic Store Buffer drain"
1262 depends on CPU_V7 && SMP
1264 This option enables the workaround for the 754327 Cortex-A9 (prior to
1265 r2p0) erratum. The Store Buffer does not have any automatic draining
1266 mechanism and therefore a livelock may occur if an external agent
1267 continuously polls a memory location waiting to observe an update.
1268 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1269 written polling loops from denying visibility of updates to memory.
1273 source "arch/arm/common/Kconfig"
1283 Find out whether you have ISA slots on your motherboard. ISA is the
1284 name of a bus system, i.e. the way the CPU talks to the other stuff
1285 inside your box. Other bus systems are PCI, EISA, MicroChannel
1286 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1287 newer boards don't support it. If you have ISA, say Y, otherwise N.
1289 # Select ISA DMA controller support
1294 # Select ISA DMA interface
1299 bool "PCI support" if MIGHT_HAVE_PCI
1301 Find out whether you have a PCI motherboard. PCI is the name of a
1302 bus system, i.e. the way the CPU talks to the other stuff inside
1303 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1304 VESA. If you have PCI, say Y, otherwise N.
1310 config PCI_NANOENGINE
1311 bool "BSE nanoEngine PCI support"
1312 depends on SA1100_NANOENGINE
1314 Enable PCI on the BSE nanoEngine board.
1319 # Select the host bridge type
1320 config PCI_HOST_VIA82C505
1322 depends on PCI && ARCH_SHARK
1325 config PCI_HOST_ITE8152
1327 depends on PCI && MACH_ARMCORE
1331 source "drivers/pci/Kconfig"
1333 source "drivers/pcmcia/Kconfig"
1337 menu "Kernel Features"
1339 source "kernel/time/Kconfig"
1342 bool "Symmetric Multi-Processing"
1343 depends on CPU_V6K || CPU_V7
1344 depends on GENERIC_CLOCKEVENTS
1345 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1346 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1347 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1348 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1349 select USE_GENERIC_SMP_HELPERS
1350 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1352 This enables support for systems with more than one CPU. If you have
1353 a system with only one CPU, like most personal computers, say N. If
1354 you have a system with more than one CPU, say Y.
1356 If you say N here, the kernel will run on single and multiprocessor
1357 machines, but will use only one CPU of a multiprocessor machine. If
1358 you say Y here, the kernel will run on many, but not all, single
1359 processor machines. On a single processor machine, the kernel will
1360 run faster if you say N here.
1362 See also <file:Documentation/i386/IO-APIC.txt>,
1363 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1364 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1366 If you don't know what to do here, say N.
1369 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1370 depends on EXPERIMENTAL
1371 depends on SMP && !XIP_KERNEL
1374 SMP kernels contain instructions which fail on non-SMP processors.
1375 Enabling this option allows the kernel to modify itself to make
1376 these instructions safe. Disabling it allows about 1K of space
1379 If you don't know what to do here, say Y.
1384 This option enables support for the ARM system coherency unit
1391 This options enables support for the ARM timer and watchdog unit
1394 prompt "Memory split"
1397 Select the desired split between kernel and user memory.
1399 If you are not absolutely sure what you are doing, leave this
1403 bool "3G/1G user/kernel split"
1405 bool "2G/2G user/kernel split"
1407 bool "1G/3G user/kernel split"
1412 default 0x40000000 if VMSPLIT_1G
1413 default 0x80000000 if VMSPLIT_2G
1417 int "Maximum number of CPUs (2-32)"
1423 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1424 depends on SMP && HOTPLUG && EXPERIMENTAL
1426 Say Y here to experiment with turning CPUs off and on. CPUs
1427 can be controlled through /sys/devices/system/cpu.
1430 bool "Use local timer interrupts"
1433 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1435 Enable support for local timers on SMP platforms, rather then the
1436 legacy IPI broadcast method. Local timers allows the system
1437 accounting to be spread across the timer interval, preventing a
1438 "thundering herd" at every timer tick.
1440 source kernel/Kconfig.preempt
1444 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1445 ARCH_S5PV210 || ARCH_EXYNOS4
1446 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1447 default AT91_TIMER_HZ if ARCH_AT91
1448 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1451 config THUMB2_KERNEL
1452 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1453 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1455 select ARM_ASM_UNIFIED
1457 By enabling this option, the kernel will be compiled in
1458 Thumb-2 mode. A compiler/assembler that understand the unified
1459 ARM-Thumb syntax is needed.
1463 config THUMB2_AVOID_R_ARM_THM_JUMP11
1464 bool "Work around buggy Thumb-2 short branch relocations in gas"
1465 depends on THUMB2_KERNEL && MODULES
1468 Various binutils versions can resolve Thumb-2 branches to
1469 locally-defined, preemptible global symbols as short-range "b.n"
1470 branch instructions.
1472 This is a problem, because there's no guarantee the final
1473 destination of the symbol, or any candidate locations for a
1474 trampoline, are within range of the branch. For this reason, the
1475 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1476 relocation in modules at all, and it makes little sense to add
1479 The symptom is that the kernel fails with an "unsupported
1480 relocation" error when loading some modules.
1482 Until fixed tools are available, passing
1483 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1484 code which hits this problem, at the cost of a bit of extra runtime
1485 stack usage in some cases.
1487 The problem is described in more detail at:
1488 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1490 Only Thumb-2 kernels are affected.
1492 Unless you are sure your tools don't have this problem, say Y.
1494 config ARM_ASM_UNIFIED
1498 bool "Use the ARM EABI to compile the kernel"
1500 This option allows for the kernel to be compiled using the latest
1501 ARM ABI (aka EABI). This is only useful if you are using a user
1502 space environment that is also compiled with EABI.
1504 Since there are major incompatibilities between the legacy ABI and
1505 EABI, especially with regard to structure member alignment, this
1506 option also changes the kernel syscall calling convention to
1507 disambiguate both ABIs and allow for backward compatibility support
1508 (selected with CONFIG_OABI_COMPAT).
1510 To use this you need GCC version 4.0.0 or later.
1513 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1514 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1517 This option preserves the old syscall interface along with the
1518 new (ARM EABI) one. It also provides a compatibility layer to
1519 intercept syscalls that have structure arguments which layout
1520 in memory differs between the legacy ABI and the new ARM EABI
1521 (only for non "thumb" binaries). This option adds a tiny
1522 overhead to all syscalls and produces a slightly larger kernel.
1523 If you know you'll be using only pure EABI user space then you
1524 can say N here. If this option is not selected and you attempt
1525 to execute a legacy ABI binary then the result will be
1526 UNPREDICTABLE (in fact it can be predicted that it won't work
1527 at all). If in doubt say Y.
1529 config ARCH_HAS_HOLES_MEMORYMODEL
1532 config ARCH_SPARSEMEM_ENABLE
1535 config ARCH_SPARSEMEM_DEFAULT
1536 def_bool ARCH_SPARSEMEM_ENABLE
1538 config ARCH_SELECT_MEMORY_MODEL
1539 def_bool ARCH_SPARSEMEM_ENABLE
1541 config HAVE_ARCH_PFN_VALID
1542 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1545 bool "High Memory Support"
1548 The address space of ARM processors is only 4 Gigabytes large
1549 and it has to accommodate user address space, kernel address
1550 space as well as some memory mapped IO. That means that, if you
1551 have a large amount of physical memory and/or IO, not all of the
1552 memory can be "permanently mapped" by the kernel. The physical
1553 memory that is not permanently mapped is called "high memory".
1555 Depending on the selected kernel/user memory split, minimum
1556 vmalloc space and actual amount of RAM, you may not need this
1557 option which should result in a slightly faster kernel.
1562 bool "Allocate 2nd-level pagetables from highmem"
1565 config HW_PERF_EVENTS
1566 bool "Enable hardware performance counter support for perf events"
1567 depends on PERF_EVENTS && CPU_HAS_PMU
1570 Enable hardware performance counter support for perf events. If
1571 disabled, perf events will use software events only.
1575 config FORCE_MAX_ZONEORDER
1576 int "Maximum zone order" if ARCH_SHMOBILE
1577 range 11 64 if ARCH_SHMOBILE
1578 default "9" if SA1111
1581 The kernel memory allocator divides physically contiguous memory
1582 blocks into "zones", where each zone is a power of two number of
1583 pages. This option selects the largest power of two that the kernel
1584 keeps in the memory allocator. If you need to allocate very large
1585 blocks of physically contiguous memory, then you may need to
1586 increase this value.
1588 This config option is actually maximum order plus one. For example,
1589 a value of 11 means that the largest free memory block is 2^10 pages.
1592 bool "Timer and CPU usage LEDs"
1593 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1594 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1595 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1596 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1597 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1598 ARCH_AT91 || ARCH_DAVINCI || \
1599 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1601 If you say Y here, the LEDs on your machine will be used
1602 to provide useful information about your current system status.
1604 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1605 be able to select which LEDs are active using the options below. If
1606 you are compiling a kernel for the EBSA-110 or the LART however, the
1607 red LED will simply flash regularly to indicate that the system is
1608 still functional. It is safe to say Y here if you have a CATS
1609 system, but the driver will do nothing.
1612 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1613 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1614 || MACH_OMAP_PERSEUS2
1616 depends on !GENERIC_CLOCKEVENTS
1617 default y if ARCH_EBSA110
1619 If you say Y here, one of the system LEDs (the green one on the
1620 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1621 will flash regularly to indicate that the system is still
1622 operational. This is mainly useful to kernel hackers who are
1623 debugging unstable kernels.
1625 The LART uses the same LED for both Timer LED and CPU usage LED
1626 functions. You may choose to use both, but the Timer LED function
1627 will overrule the CPU usage LED.
1630 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1632 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1633 || MACH_OMAP_PERSEUS2
1636 If you say Y here, the red LED will be used to give a good real
1637 time indication of CPU usage, by lighting whenever the idle task
1638 is not currently executing.
1640 The LART uses the same LED for both Timer LED and CPU usage LED
1641 functions. You may choose to use both, but the Timer LED function
1642 will overrule the CPU usage LED.
1644 config ALIGNMENT_TRAP
1646 depends on CPU_CP15_MMU
1647 default y if !ARCH_EBSA110
1648 select HAVE_PROC_CPU if PROC_FS
1650 ARM processors cannot fetch/store information which is not
1651 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1652 address divisible by 4. On 32-bit ARM processors, these non-aligned
1653 fetch/store instructions will be emulated in software if you say
1654 here, which has a severe performance impact. This is necessary for
1655 correct operation of some network protocols. With an IP-only
1656 configuration it is safe to say N, otherwise say Y.
1658 config UACCESS_WITH_MEMCPY
1659 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1660 depends on MMU && EXPERIMENTAL
1661 default y if CPU_FEROCEON
1663 Implement faster copy_to_user and clear_user methods for CPU
1664 cores where a 8-word STM instruction give significantly higher
1665 memory write throughput than a sequence of individual 32bit stores.
1667 A possible side effect is a slight increase in scheduling latency
1668 between threads sharing the same address space if they invoke
1669 such copy operations with large buffers.
1671 However, if the CPU data cache is using a write-allocate mode,
1672 this option is unlikely to provide any performance gain.
1676 prompt "Enable seccomp to safely compute untrusted bytecode"
1678 This kernel feature is useful for number crunching applications
1679 that may need to compute untrusted bytecode during their
1680 execution. By using pipes or other transports made available to
1681 the process as file descriptors supporting the read/write
1682 syscalls, it's possible to isolate those applications in
1683 their own address space using seccomp. Once seccomp is
1684 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1685 and the task is only allowed to execute a few safe syscalls
1686 defined by each seccomp mode.
1688 config CC_STACKPROTECTOR
1689 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1690 depends on EXPERIMENTAL
1692 This option turns on the -fstack-protector GCC feature. This
1693 feature puts, at the beginning of functions, a canary value on
1694 the stack just before the return address, and validates
1695 the value just before actually returning. Stack based buffer
1696 overflows (that need to overwrite this return address) now also
1697 overwrite the canary, which gets detected and the attack is then
1698 neutralized via a kernel panic.
1699 This feature requires gcc version 4.2 or above.
1701 config DEPRECATED_PARAM_STRUCT
1702 bool "Provide old way to pass kernel parameters"
1704 This was deprecated in 2001 and announced to live on for 5 years.
1705 Some old boot loaders still use this way.
1712 bool "Flattened Device Tree support"
1714 select OF_EARLY_FLATTREE
1716 Include support for flattened device tree machine descriptions.
1718 # Compressed boot loader in ROM. Yes, we really want to ask about
1719 # TEXT and BSS so we preserve their values in the config files.
1720 config ZBOOT_ROM_TEXT
1721 hex "Compressed ROM boot loader base address"
1724 The physical address at which the ROM-able zImage is to be
1725 placed in the target. Platforms which normally make use of
1726 ROM-able zImage formats normally set this to a suitable
1727 value in their defconfig file.
1729 If ZBOOT_ROM is not enabled, this has no effect.
1731 config ZBOOT_ROM_BSS
1732 hex "Compressed ROM boot loader BSS address"
1735 The base address of an area of read/write memory in the target
1736 for the ROM-able zImage which must be available while the
1737 decompressor is running. It must be large enough to hold the
1738 entire decompressed kernel plus an additional 128 KiB.
1739 Platforms which normally make use of ROM-able zImage formats
1740 normally set this to a suitable value in their defconfig file.
1742 If ZBOOT_ROM is not enabled, this has no effect.
1745 bool "Compressed boot loader in ROM/flash"
1746 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1748 Say Y here if you intend to execute your compressed kernel image
1749 (zImage) directly from ROM or flash. If unsure, say N.
1752 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1753 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1754 default ZBOOT_ROM_NONE
1756 Include experimental SD/MMC loading code in the ROM-able zImage.
1757 With this enabled it is possible to write the the ROM-able zImage
1758 kernel image to an MMC or SD card and boot the kernel straight
1759 from the reset vector. At reset the processor Mask ROM will load
1760 the first part of the the ROM-able zImage which in turn loads the
1761 rest the kernel image to RAM.
1763 config ZBOOT_ROM_NONE
1764 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1766 Do not load image from SD or MMC
1768 config ZBOOT_ROM_MMCIF
1769 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1771 Load image from MMCIF hardware block.
1773 config ZBOOT_ROM_SH_MOBILE_SDHI
1774 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1776 Load image from SDHI hardware block
1781 string "Default kernel command string"
1784 On some architectures (EBSA110 and CATS), there is currently no way
1785 for the boot loader to pass arguments to the kernel. For these
1786 architectures, you should supply some command-line options at build
1787 time by entering them here. As a minimum, you should specify the
1788 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1791 prompt "Kernel command line type" if CMDLINE != ""
1792 default CMDLINE_FROM_BOOTLOADER
1794 config CMDLINE_FROM_BOOTLOADER
1795 bool "Use bootloader kernel arguments if available"
1797 Uses the command-line options passed by the boot loader. If
1798 the boot loader doesn't provide any, the default kernel command
1799 string provided in CMDLINE will be used.
1801 config CMDLINE_EXTEND
1802 bool "Extend bootloader kernel arguments"
1804 The command-line arguments provided by the boot loader will be
1805 appended to the default kernel command string.
1807 config CMDLINE_FORCE
1808 bool "Always use the default kernel command string"
1810 Always use the default kernel command string, even if the boot
1811 loader passes other arguments to the kernel.
1812 This is useful if you cannot or don't want to change the
1813 command-line options your boot loader passes to the kernel.
1817 bool "Kernel Execute-In-Place from ROM"
1818 depends on !ZBOOT_ROM
1820 Execute-In-Place allows the kernel to run from non-volatile storage
1821 directly addressable by the CPU, such as NOR flash. This saves RAM
1822 space since the text section of the kernel is not loaded from flash
1823 to RAM. Read-write sections, such as the data section and stack,
1824 are still copied to RAM. The XIP kernel is not compressed since
1825 it has to run directly from flash, so it will take more space to
1826 store it. The flash address used to link the kernel object files,
1827 and for storing it, is configuration dependent. Therefore, if you
1828 say Y here, you must know the proper physical address where to
1829 store the kernel image depending on your own flash memory usage.
1831 Also note that the make target becomes "make xipImage" rather than
1832 "make zImage" or "make Image". The final kernel binary to put in
1833 ROM memory will be arch/arm/boot/xipImage.
1837 config XIP_PHYS_ADDR
1838 hex "XIP Kernel Physical Location"
1839 depends on XIP_KERNEL
1840 default "0x00080000"
1842 This is the physical address in your flash memory the kernel will
1843 be linked for and stored to. This address is dependent on your
1847 bool "Kexec system call (EXPERIMENTAL)"
1848 depends on EXPERIMENTAL
1850 kexec is a system call that implements the ability to shutdown your
1851 current kernel, and to start another kernel. It is like a reboot
1852 but it is independent of the system firmware. And like a reboot
1853 you can start any kernel with it, not just Linux.
1855 It is an ongoing process to be certain the hardware in a machine
1856 is properly shutdown, so do not be surprised if this code does not
1857 initially work for you. It may help to enable device hotplugging
1861 bool "Export atags in procfs"
1865 Should the atags used to boot the kernel be exported in an "atags"
1866 file in procfs. Useful with kexec.
1869 bool "Build kdump crash kernel (EXPERIMENTAL)"
1870 depends on EXPERIMENTAL
1872 Generate crash dump after being started by kexec. This should
1873 be normally only set in special crash dump kernels which are
1874 loaded in the main kernel with kexec-tools into a specially
1875 reserved region and then later executed after a crash by
1876 kdump/kexec. The crash dump kernel must be compiled to a
1877 memory address not used by the main kernel
1879 For more details see Documentation/kdump/kdump.txt
1881 config AUTO_ZRELADDR
1882 bool "Auto calculation of the decompressed kernel image address"
1883 depends on !ZBOOT_ROM && !ARCH_U300
1885 ZRELADDR is the physical address where the decompressed kernel
1886 image will be placed. If AUTO_ZRELADDR is selected, the address
1887 will be determined at run-time by masking the current IP with
1888 0xf8000000. This assumes the zImage being placed in the first 128MB
1889 from start of memory.
1893 menu "CPU Power Management"
1897 source "drivers/cpufreq/Kconfig"
1900 tristate "CPUfreq driver for i.MX CPUs"
1901 depends on ARCH_MXC && CPU_FREQ
1903 This enables the CPUfreq driver for i.MX CPUs.
1905 config CPU_FREQ_SA1100
1908 config CPU_FREQ_SA1110
1911 config CPU_FREQ_INTEGRATOR
1912 tristate "CPUfreq driver for ARM Integrator CPUs"
1913 depends on ARCH_INTEGRATOR && CPU_FREQ
1916 This enables the CPUfreq driver for ARM Integrator CPUs.
1918 For details, take a look at <file:Documentation/cpu-freq>.
1924 depends on CPU_FREQ && ARCH_PXA && PXA25x
1926 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1931 Internal configuration node for common cpufreq on Samsung SoC
1933 config CPU_FREQ_S3C24XX
1934 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1935 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1938 This enables the CPUfreq driver for the Samsung S3C24XX family
1941 For details, take a look at <file:Documentation/cpu-freq>.
1945 config CPU_FREQ_S3C24XX_PLL
1946 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1947 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1949 Compile in support for changing the PLL frequency from the
1950 S3C24XX series CPUfreq driver. The PLL takes time to settle
1951 after a frequency change, so by default it is not enabled.
1953 This also means that the PLL tables for the selected CPU(s) will
1954 be built which may increase the size of the kernel image.
1956 config CPU_FREQ_S3C24XX_DEBUG
1957 bool "Debug CPUfreq Samsung driver core"
1958 depends on CPU_FREQ_S3C24XX
1960 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1962 config CPU_FREQ_S3C24XX_IODEBUG
1963 bool "Debug CPUfreq Samsung driver IO timing"
1964 depends on CPU_FREQ_S3C24XX
1966 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1968 config CPU_FREQ_S3C24XX_DEBUGFS
1969 bool "Export debugfs for CPUFreq"
1970 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1972 Export status information via debugfs.
1976 source "drivers/cpuidle/Kconfig"
1980 menu "Floating point emulation"
1982 comment "At least one emulation must be selected"
1985 bool "NWFPE math emulation"
1986 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1988 Say Y to include the NWFPE floating point emulator in the kernel.
1989 This is necessary to run most binaries. Linux does not currently
1990 support floating point hardware so you need to say Y here even if
1991 your machine has an FPA or floating point co-processor podule.
1993 You may say N here if you are going to load the Acorn FPEmulator
1994 early in the bootup.
1997 bool "Support extended precision"
1998 depends on FPE_NWFPE
2000 Say Y to include 80-bit support in the kernel floating-point
2001 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2002 Note that gcc does not generate 80-bit operations by default,
2003 so in most cases this option only enlarges the size of the
2004 floating point emulator without any good reason.
2006 You almost surely want to say N here.
2009 bool "FastFPE math emulation (EXPERIMENTAL)"
2010 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2012 Say Y here to include the FAST floating point emulator in the kernel.
2013 This is an experimental much faster emulator which now also has full
2014 precision for the mantissa. It does not support any exceptions.
2015 It is very simple, and approximately 3-6 times faster than NWFPE.
2017 It should be sufficient for most programs. It may be not suitable
2018 for scientific calculations, but you have to check this for yourself.
2019 If you do not feel you need a faster FP emulation you should better
2023 bool "VFP-format floating point maths"
2024 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2026 Say Y to include VFP support code in the kernel. This is needed
2027 if your hardware includes a VFP unit.
2029 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2030 release notes and additional status information.
2032 Say N if your target does not have VFP hardware.
2040 bool "Advanced SIMD (NEON) Extension support"
2041 depends on VFPv3 && CPU_V7
2043 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2048 menu "Userspace binary formats"
2050 source "fs/Kconfig.binfmt"
2053 tristate "RISC OS personality"
2056 Say Y here to include the kernel code necessary if you want to run
2057 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2058 experimental; if this sounds frightening, say N and sleep in peace.
2059 You can also say M here to compile this support as a module (which
2060 will be called arthur).
2064 menu "Power management options"
2066 source "kernel/power/Kconfig"
2068 config ARCH_SUSPEND_POSSIBLE
2069 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2070 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2071 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2076 source "net/Kconfig"
2078 source "drivers/Kconfig"
2082 source "arch/arm/Kconfig.debug"
2084 source "security/Kconfig"
2086 source "crypto/Kconfig"
2088 source "lib/Kconfig"