8 select SYS_SUPPORTS_APM_EMULATION
9 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
10 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
13 select HAVE_KRETPROBES if (HAVE_KPROBES)
14 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
15 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
16 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
17 select HAVE_GENERIC_DMA_COHERENT
18 select HAVE_KERNEL_GZIP
19 select HAVE_KERNEL_LZO
20 select HAVE_KERNEL_LZMA
22 select HAVE_PERF_EVENTS
23 select PERF_USE_VMALLOC
24 select HAVE_REGS_AND_STACK_ACCESS_API
25 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
27 The ARM series is a line of low-power-consumption RISC chip designs
28 licensed by ARM Ltd and targeted at embedded applications and
29 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
30 manufactured, but legacy ARM-based PC hardware remains popular in
31 Europe. There is an ARM Linux project with a web page at
32 <http://www.arm.linux.org.uk/>.
37 config SYS_SUPPORTS_APM_EMULATION
43 config ARCH_USES_GETTIMEOFFSET
47 config GENERIC_CLOCKEVENTS
50 config GENERIC_CLOCKEVENTS_BROADCAST
52 depends on GENERIC_CLOCKEVENTS
57 select GENERIC_ALLOCATOR
68 The Extended Industry Standard Architecture (EISA) bus was
69 developed as an open alternative to the IBM MicroChannel bus.
71 The EISA bus provided some of the features of the IBM MicroChannel
72 bus while maintaining backward compatibility with cards made for
73 the older ISA bus. The EISA bus saw limited use between 1988 and
74 1995 when it was made obsolete by the PCI bus.
76 Say Y here if you are building a kernel for an EISA-based machine.
86 MicroChannel Architecture is found in some IBM PS/2 machines and
87 laptops. It is a bus system similar to PCI or ISA. See
88 <file:Documentation/mca.txt> (and especially the web page given
89 there) before attempting to build an MCA bus kernel.
91 config GENERIC_HARDIRQS
95 config STACKTRACE_SUPPORT
99 config HAVE_LATENCYTOP_SUPPORT
104 config LOCKDEP_SUPPORT
108 config TRACE_IRQFLAGS_SUPPORT
112 config HARDIRQS_SW_RESEND
116 config GENERIC_IRQ_PROBE
120 config GENERIC_LOCKBREAK
123 depends on SMP && PREEMPT
125 config RWSEM_GENERIC_SPINLOCK
129 config RWSEM_XCHGADD_ALGORITHM
132 config ARCH_HAS_ILOG2_U32
135 config ARCH_HAS_ILOG2_U64
138 config ARCH_HAS_CPUFREQ
141 Internal node to signify that the ARCH has CPUFREQ support
142 and that the relevant menu configurations are displayed for
145 config ARCH_HAS_CPU_IDLE_WAIT
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config GENERIC_ISA_DMA
174 config GENERIC_HARDIRQS_NO__DO_IRQ
177 config ARM_L1_CACHE_SHIFT_6
180 Setting ARM L1 cache line size to 64 Bytes.
184 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
185 default DRAM_BASE if REMAP_VECTORS_TO_RAM
188 The base address of exception vectors.
190 source "init/Kconfig"
192 source "kernel/Kconfig.freezer"
197 bool "MMU-based Paged Memory Management Support"
200 Select if you want MMU-based virtualised addressing space
201 support by paged memory management. If unsure, say 'Y'.
204 # The "ARM system type" choice list is ordered alphabetically by option
205 # text. Please add new entries in the option alphabetic order.
208 prompt "ARM system type"
209 default ARCH_VERSATILE
212 bool "Agilent AAEC-2000 based"
216 select ARCH_USES_GETTIMEOFFSET
218 This enables support for systems based on the Agilent AAEC-2000
220 config ARCH_INTEGRATOR
221 bool "ARM Ltd. Integrator family"
223 select ARCH_HAS_CPUFREQ
226 select GENERIC_CLOCKEVENTS
227 select PLAT_VERSATILE
229 Support for ARM's Integrator platform.
232 bool "ARM Ltd. RealView family"
236 select GENERIC_CLOCKEVENTS
237 select ARCH_WANT_OPTIONAL_GPIOLIB
238 select PLAT_VERSATILE
239 select ARM_TIMER_SP804
240 select GPIO_PL061 if GPIOLIB
242 This enables support for ARM Ltd RealView boards.
244 config ARCH_VERSATILE
245 bool "ARM Ltd. Versatile family"
250 select GENERIC_CLOCKEVENTS
251 select ARCH_WANT_OPTIONAL_GPIOLIB
252 select PLAT_VERSATILE
253 select ARM_TIMER_SP804
255 This enables support for ARM Ltd Versatile board.
258 bool "ARM Ltd. Versatile Express family"
259 select ARCH_WANT_OPTIONAL_GPIOLIB
261 select ARM_TIMER_SP804
263 select GENERIC_CLOCKEVENTS
266 select PLAT_VERSATILE
268 This enables support for the ARM Ltd Versatile Express boards.
272 select ARCH_REQUIRE_GPIOLIB
275 This enables support for systems based on the Atmel AT91RM9200,
276 AT91SAM9 and AT91CAP9 processors.
279 bool "Broadcom BCMRING"
284 select GENERIC_CLOCKEVENTS
285 select ARCH_WANT_OPTIONAL_GPIOLIB
287 Support for Broadcom's BCMRing platform.
290 bool "Cirrus Logic CLPS711x/EP721x-based"
292 select ARCH_USES_GETTIMEOFFSET
294 Support for Cirrus Logic 711x/721x based boards.
297 bool "Cavium Networks CNS3XXX family"
299 select GENERIC_CLOCKEVENTS
301 select PCI_DOMAINS if PCI
303 Support for Cavium Networks CNS3XXX platform.
306 bool "Cortina Systems Gemini"
308 select ARCH_REQUIRE_GPIOLIB
309 select ARCH_USES_GETTIMEOFFSET
311 Support for the Cortina Systems Gemini family SoCs
318 select ARCH_USES_GETTIMEOFFSET
320 This is an evaluation board for the StrongARM processor available
321 from Digital. It has limited hardware on-board, including an
322 Ethernet interface, two PCMCIA sockets, two serial ports and a
331 select ARCH_REQUIRE_GPIOLIB
332 select ARCH_HAS_HOLES_MEMORYMODEL
333 select ARCH_USES_GETTIMEOFFSET
335 This enables support for the Cirrus EP93xx series of CPUs.
337 config ARCH_FOOTBRIDGE
341 select ARCH_USES_GETTIMEOFFSET
343 Support for systems based on the DC21285 companion chip
344 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
347 bool "Freescale MXC/iMX-based"
348 select GENERIC_CLOCKEVENTS
349 select ARCH_REQUIRE_GPIOLIB
352 Support for Freescale MXC/iMX-based family of processors
355 bool "Freescale STMP3xxx"
358 select ARCH_REQUIRE_GPIOLIB
359 select GENERIC_CLOCKEVENTS
360 select USB_ARCH_HAS_EHCI
362 Support for systems based on the Freescale 3xxx CPUs.
365 bool "Hilscher NetX based"
368 select GENERIC_CLOCKEVENTS
370 This enables support for systems based on the Hilscher NetX Soc
373 bool "Hynix HMS720x-based"
376 select ARCH_USES_GETTIMEOFFSET
378 This enables support for systems based on the Hynix HMS720x
386 select ARCH_SUPPORTS_MSI
389 Support for Intel's IOP13XX (XScale) family of processors.
397 select ARCH_REQUIRE_GPIOLIB
399 Support for Intel's 80219 and IOP32X (XScale) family of
408 select ARCH_REQUIRE_GPIOLIB
410 Support for Intel's IOP33X (XScale) family of processors.
417 select ARCH_USES_GETTIMEOFFSET
419 Support for Intel's IXP23xx (XScale) family of processors.
422 bool "IXP2400/2800-based"
426 select ARCH_USES_GETTIMEOFFSET
428 Support for Intel's IXP2400/2800 (XScale) family of processors.
435 select GENERIC_CLOCKEVENTS
436 select DMABOUNCE if PCI
438 Support for Intel's IXP4XX (XScale) family of processors.
443 select ARCH_REQUIRE_GPIOLIB
444 select GENERIC_CLOCKEVENTS
447 Support for the Marvell Dove SoC 88AP510
450 bool "Marvell Kirkwood"
453 select ARCH_REQUIRE_GPIOLIB
454 select GENERIC_CLOCKEVENTS
457 Support for the following Marvell Kirkwood series SoCs:
458 88F6180, 88F6192 and 88F6281.
461 bool "Marvell Loki (88RC8480)"
463 select GENERIC_CLOCKEVENTS
466 Support for the Marvell Loki (88RC8480) SoC.
471 select ARCH_REQUIRE_GPIOLIB
474 select USB_ARCH_HAS_OHCI
477 select GENERIC_CLOCKEVENTS
479 Support for the NXP LPC32XX family of processors
482 bool "Marvell MV78xx0"
485 select ARCH_REQUIRE_GPIOLIB
486 select GENERIC_CLOCKEVENTS
489 Support for the following Marvell MV78xx0 series SoCs:
497 select ARCH_REQUIRE_GPIOLIB
498 select GENERIC_CLOCKEVENTS
501 Support for the following Marvell Orion 5x series SoCs:
502 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
503 Orion-2 (5281), Orion-1-90 (6183).
506 bool "Marvell PXA168/910/MMP2"
508 select ARCH_REQUIRE_GPIOLIB
510 select GENERIC_CLOCKEVENTS
515 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
518 bool "Micrel/Kendin KS8695"
520 select ARCH_REQUIRE_GPIOLIB
521 select ARCH_USES_GETTIMEOFFSET
523 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
524 System-on-Chip devices.
527 bool "NetSilicon NS9xxx"
530 select GENERIC_CLOCKEVENTS
533 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
536 <http://www.digi.com/products/microprocessors/index.jsp>
539 bool "Nuvoton W90X900 CPU"
541 select ARCH_REQUIRE_GPIOLIB
543 select GENERIC_CLOCKEVENTS
545 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
546 At present, the w90x900 has been renamed nuc900, regarding
547 the ARM series product line, you can login the following
548 link address to know more.
550 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
551 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
554 bool "Nuvoton NUC93X CPU"
558 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
559 low-power and high performance MPEG-4/JPEG multimedia controller chip.
564 select GENERIC_CLOCKEVENTS
568 select ARCH_HAS_BARRIERS if CACHE_L2X0
569 select ARCH_HAS_CPUFREQ
571 This enables support for NVIDIA Tegra based systems (Tegra APX,
572 Tegra 6xx and Tegra 2 series).
575 bool "Philips Nexperia PNX4008 Mobile"
578 select ARCH_USES_GETTIMEOFFSET
580 This enables support for Philips PNX4008 mobile platform.
583 bool "PXA2xx/PXA3xx-based"
586 select ARCH_HAS_CPUFREQ
588 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
594 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
599 select GENERIC_CLOCKEVENTS
600 select ARCH_REQUIRE_GPIOLIB
602 Support for Qualcomm MSM/QSD based systems. This runs on the
603 apps processor of the MSM/QSD and depends on a shared memory
604 interface to the modem processor which runs the baseband
605 stack and controls some vital subsystems
606 (clock and power control, etc).
609 bool "Renesas SH-Mobile / R-Mobile"
612 select GENERIC_CLOCKEVENTS
616 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
623 select ARCH_MAY_HAVE_PC_FDC
624 select HAVE_PATA_PLATFORM
627 select ARCH_SPARSEMEM_ENABLE
628 select ARCH_USES_GETTIMEOFFSET
630 On the Acorn Risc-PC, Linux can support the internal IDE disk and
631 CD-ROM interface, serial and parallel port, and the floppy drive.
637 select ARCH_SPARSEMEM_ENABLE
639 select ARCH_HAS_CPUFREQ
641 select GENERIC_CLOCKEVENTS
644 select ARCH_REQUIRE_GPIOLIB
646 Support for StrongARM 11x0 based boards.
649 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
651 select ARCH_HAS_CPUFREQ
653 select ARCH_USES_GETTIMEOFFSET
654 select HAVE_S3C2410_I2C if I2C
656 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
657 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
658 the Samsung SMDK2410 development board (and derivatives).
660 Note, the S3C2416 and the S3C2450 are so close that they even share
661 the same SoC ID code. This means that there is no seperate machine
662 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
665 bool "Samsung S3C64XX"
671 select ARCH_USES_GETTIMEOFFSET
672 select ARCH_HAS_CPUFREQ
673 select ARCH_REQUIRE_GPIOLIB
674 select SAMSUNG_CLKSRC
675 select SAMSUNG_IRQ_VIC_TIMER
676 select SAMSUNG_IRQ_UART
677 select S3C_GPIO_TRACK
678 select S3C_GPIO_PULL_UPDOWN
679 select S3C_GPIO_CFG_S3C24XX
680 select S3C_GPIO_CFG_S3C64XX
682 select USB_ARCH_HAS_OHCI
683 select SAMSUNG_GPIOLIB_4BIT
684 select HAVE_S3C2410_I2C if I2C
685 select HAVE_S3C2410_WATCHDOG if WATCHDOG
687 Samsung S3C64XX series based systems
690 bool "Samsung S5P6440 S5P6450"
694 select HAVE_S3C2410_WATCHDOG if WATCHDOG
695 select ARCH_USES_GETTIMEOFFSET
696 select HAVE_S3C2410_I2C if I2C
697 select HAVE_S3C_RTC if RTC_CLASS
699 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
703 bool "Samsung S5P6442"
707 select ARCH_USES_GETTIMEOFFSET
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 Samsung S5P6442 CPU based systems
713 bool "Samsung S5PC100"
717 select ARM_L1_CACHE_SHIFT_6
718 select ARCH_USES_GETTIMEOFFSET
719 select HAVE_S3C2410_I2C if I2C
720 select HAVE_S3C_RTC if RTC_CLASS
721 select HAVE_S3C2410_WATCHDOG if WATCHDOG
723 Samsung S5PC100 series based systems
726 bool "Samsung S5PV210/S5PC110"
728 select ARCH_SPARSEMEM_ENABLE
731 select ARM_L1_CACHE_SHIFT_6
732 select ARCH_HAS_CPUFREQ
733 select ARCH_USES_GETTIMEOFFSET
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C_RTC if RTC_CLASS
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 Samsung S5PV210/S5PC110 series based systems
741 bool "Samsung S5PV310/S5PC210"
743 select ARCH_SPARSEMEM_ENABLE
746 select GENERIC_CLOCKEVENTS
747 select HAVE_S3C_RTC if RTC_CLASS
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 Samsung S5PV310 series based systems
760 select ARCH_USES_GETTIMEOFFSET
762 Support for the StrongARM based Digital DNARD machine, also known
763 as "Shark" (<http://www.shark-linux.de/shark.html>).
766 bool "Telechips TCC ARM926-based systems"
770 select GENERIC_CLOCKEVENTS
772 Support for Telechips TCC ARM926-based systems.
777 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
778 select ARCH_USES_GETTIMEOFFSET
780 Say Y here for systems based on one of the Sharp LH7A40X
781 System on a Chip processors. These CPUs include an ARM922T
782 core with a wide array of integrated devices for
783 hand-held and low-power applications.
786 bool "ST-Ericsson U300 Series"
792 select GENERIC_CLOCKEVENTS
796 Support for ST-Ericsson U300 series mobile platforms.
799 bool "ST-Ericsson U8500 Series"
802 select GENERIC_CLOCKEVENTS
804 select ARCH_REQUIRE_GPIOLIB
806 Support for ST-Ericsson's Ux500 architecture
809 bool "STMicroelectronics Nomadik"
814 select GENERIC_CLOCKEVENTS
815 select ARCH_REQUIRE_GPIOLIB
817 Support for the Nomadik platform by ST-Ericsson
821 select GENERIC_CLOCKEVENTS
822 select ARCH_REQUIRE_GPIOLIB
826 select GENERIC_ALLOCATOR
827 select ARCH_HAS_HOLES_MEMORYMODEL
829 Support for TI's DaVinci platform.
834 select ARCH_REQUIRE_GPIOLIB
835 select ARCH_HAS_CPUFREQ
836 select GENERIC_CLOCKEVENTS
837 select ARCH_HAS_HOLES_MEMORYMODEL
839 Support for TI's OMAP platform (OMAP1/2/3/4).
844 select ARCH_REQUIRE_GPIOLIB
846 select GENERIC_CLOCKEVENTS
849 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
854 # This is sorted alphabetically by mach-* pathname. However, plat-*
855 # Kconfigs may be included either alphabetically (according to the
856 # plat- suffix) or along side the corresponding mach-* source.
858 source "arch/arm/mach-aaec2000/Kconfig"
860 source "arch/arm/mach-at91/Kconfig"
862 source "arch/arm/mach-bcmring/Kconfig"
864 source "arch/arm/mach-clps711x/Kconfig"
866 source "arch/arm/mach-cns3xxx/Kconfig"
868 source "arch/arm/mach-davinci/Kconfig"
870 source "arch/arm/mach-dove/Kconfig"
872 source "arch/arm/mach-ep93xx/Kconfig"
874 source "arch/arm/mach-footbridge/Kconfig"
876 source "arch/arm/mach-gemini/Kconfig"
878 source "arch/arm/mach-h720x/Kconfig"
880 source "arch/arm/mach-integrator/Kconfig"
882 source "arch/arm/mach-iop32x/Kconfig"
884 source "arch/arm/mach-iop33x/Kconfig"
886 source "arch/arm/mach-iop13xx/Kconfig"
888 source "arch/arm/mach-ixp4xx/Kconfig"
890 source "arch/arm/mach-ixp2000/Kconfig"
892 source "arch/arm/mach-ixp23xx/Kconfig"
894 source "arch/arm/mach-kirkwood/Kconfig"
896 source "arch/arm/mach-ks8695/Kconfig"
898 source "arch/arm/mach-lh7a40x/Kconfig"
900 source "arch/arm/mach-loki/Kconfig"
902 source "arch/arm/mach-lpc32xx/Kconfig"
904 source "arch/arm/mach-msm/Kconfig"
906 source "arch/arm/mach-mv78xx0/Kconfig"
908 source "arch/arm/plat-mxc/Kconfig"
910 source "arch/arm/mach-netx/Kconfig"
912 source "arch/arm/mach-nomadik/Kconfig"
913 source "arch/arm/plat-nomadik/Kconfig"
915 source "arch/arm/mach-ns9xxx/Kconfig"
917 source "arch/arm/mach-nuc93x/Kconfig"
919 source "arch/arm/plat-omap/Kconfig"
921 source "arch/arm/mach-omap1/Kconfig"
923 source "arch/arm/mach-omap2/Kconfig"
925 source "arch/arm/mach-orion5x/Kconfig"
927 source "arch/arm/mach-pxa/Kconfig"
928 source "arch/arm/plat-pxa/Kconfig"
930 source "arch/arm/mach-mmp/Kconfig"
932 source "arch/arm/mach-realview/Kconfig"
934 source "arch/arm/mach-sa1100/Kconfig"
936 source "arch/arm/plat-samsung/Kconfig"
937 source "arch/arm/plat-s3c24xx/Kconfig"
938 source "arch/arm/plat-s5p/Kconfig"
940 source "arch/arm/plat-spear/Kconfig"
942 source "arch/arm/plat-tcc/Kconfig"
945 source "arch/arm/mach-s3c2400/Kconfig"
946 source "arch/arm/mach-s3c2410/Kconfig"
947 source "arch/arm/mach-s3c2412/Kconfig"
948 source "arch/arm/mach-s3c2416/Kconfig"
949 source "arch/arm/mach-s3c2440/Kconfig"
950 source "arch/arm/mach-s3c2443/Kconfig"
954 source "arch/arm/mach-s3c64xx/Kconfig"
957 source "arch/arm/mach-s5p64x0/Kconfig"
959 source "arch/arm/mach-s5p6442/Kconfig"
961 source "arch/arm/mach-s5pc100/Kconfig"
963 source "arch/arm/mach-s5pv210/Kconfig"
965 source "arch/arm/mach-s5pv310/Kconfig"
967 source "arch/arm/mach-shmobile/Kconfig"
969 source "arch/arm/plat-stmp3xxx/Kconfig"
971 source "arch/arm/mach-tegra/Kconfig"
973 source "arch/arm/mach-u300/Kconfig"
975 source "arch/arm/mach-ux500/Kconfig"
977 source "arch/arm/mach-versatile/Kconfig"
979 source "arch/arm/mach-vexpress/Kconfig"
981 source "arch/arm/mach-w90x900/Kconfig"
983 # Definitions to make life easier
989 select GENERIC_CLOCKEVENTS
997 config PLAT_VERSATILE
1000 config ARM_TIMER_SP804
1003 source arch/arm/mm/Kconfig
1006 bool "Enable iWMMXt support"
1007 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
1008 default y if PXA27x || PXA3xx || ARCH_MMP
1010 Enable support for iWMMXt context switching at run time if
1011 running on a CPU that supports it.
1013 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1016 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1020 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1021 (!ARCH_OMAP3 || OMAP3_EMU)
1026 source "arch/arm/Kconfig-nommu"
1029 config ARM_ERRATA_411920
1030 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1033 Invalidation of the Instruction Cache operation can
1034 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1035 It does not affect the MPCore. This option enables the ARM Ltd.
1036 recommended workaround.
1038 config ARM_ERRATA_430973
1039 bool "ARM errata: Stale prediction on replaced interworking branch"
1042 This option enables the workaround for the 430973 Cortex-A8
1043 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1044 interworking branch is replaced with another code sequence at the
1045 same virtual address, whether due to self-modifying code or virtual
1046 to physical address re-mapping, Cortex-A8 does not recover from the
1047 stale interworking branch prediction. This results in Cortex-A8
1048 executing the new code sequence in the incorrect ARM or Thumb state.
1049 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1050 and also flushes the branch target cache at every context switch.
1051 Note that setting specific bits in the ACTLR register may not be
1052 available in non-secure mode.
1054 config ARM_ERRATA_458693
1055 bool "ARM errata: Processor deadlock when a false hazard is created"
1058 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1059 erratum. For very specific sequences of memory operations, it is
1060 possible for a hazard condition intended for a cache line to instead
1061 be incorrectly associated with a different cache line. This false
1062 hazard might then cause a processor deadlock. The workaround enables
1063 the L1 caching of the NEON accesses and disables the PLD instruction
1064 in the ACTLR register. Note that setting specific bits in the ACTLR
1065 register may not be available in non-secure mode.
1067 config ARM_ERRATA_460075
1068 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1071 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1072 erratum. Any asynchronous access to the L2 cache may encounter a
1073 situation in which recent store transactions to the L2 cache are lost
1074 and overwritten with stale memory contents from external memory. The
1075 workaround disables the write-allocate mode for the L2 cache via the
1076 ACTLR register. Note that setting specific bits in the ACTLR register
1077 may not be available in non-secure mode.
1079 config ARM_ERRATA_742230
1080 bool "ARM errata: DMB operation may be faulty"
1081 depends on CPU_V7 && SMP
1083 This option enables the workaround for the 742230 Cortex-A9
1084 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1085 between two write operations may not ensure the correct visibility
1086 ordering of the two writes. This workaround sets a specific bit in
1087 the diagnostic register of the Cortex-A9 which causes the DMB
1088 instruction to behave as a DSB, ensuring the correct behaviour of
1091 config ARM_ERRATA_742231
1092 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1093 depends on CPU_V7 && SMP
1095 This option enables the workaround for the 742231 Cortex-A9
1096 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1097 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1098 accessing some data located in the same cache line, may get corrupted
1099 data due to bad handling of the address hazard when the line gets
1100 replaced from one of the CPUs at the same time as another CPU is
1101 accessing it. This workaround sets specific bits in the diagnostic
1102 register of the Cortex-A9 which reduces the linefill issuing
1103 capabilities of the processor.
1105 config PL310_ERRATA_588369
1106 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1107 depends on CACHE_L2X0 && ARCH_OMAP4
1109 The PL310 L2 cache controller implements three types of Clean &
1110 Invalidate maintenance operations: by Physical Address
1111 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1112 They are architecturally defined to behave as the execution of a
1113 clean operation followed immediately by an invalidate operation,
1114 both performing to the same memory location. This functionality
1115 is not correctly implemented in PL310 as clean lines are not
1116 invalidated as a result of these operations. Note that this errata
1117 uses Texas Instrument's secure monitor api.
1119 config ARM_ERRATA_720789
1120 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1121 depends on CPU_V7 && SMP
1123 This option enables the workaround for the 720789 Cortex-A9 (prior to
1124 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1125 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1126 As a consequence of this erratum, some TLB entries which should be
1127 invalidated are not, resulting in an incoherency in the system page
1128 tables. The workaround changes the TLB flushing routines to invalidate
1129 entries regardless of the ASID.
1131 config ARM_ERRATA_743622
1132 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1135 This option enables the workaround for the 743622 Cortex-A9
1136 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1137 optimisation in the Cortex-A9 Store Buffer may lead to data
1138 corruption. This workaround sets a specific bit in the diagnostic
1139 register of the Cortex-A9 which disables the Store Buffer
1140 optimisation, preventing the defect from occurring. This has no
1141 visible impact on the overall performance or power consumption of the
1146 source "arch/arm/common/Kconfig"
1156 Find out whether you have ISA slots on your motherboard. ISA is the
1157 name of a bus system, i.e. the way the CPU talks to the other stuff
1158 inside your box. Other bus systems are PCI, EISA, MicroChannel
1159 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1160 newer boards don't support it. If you have ISA, say Y, otherwise N.
1162 # Select ISA DMA controller support
1167 # Select ISA DMA interface
1172 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
1174 Find out whether you have a PCI motherboard. PCI is the name of a
1175 bus system, i.e. the way the CPU talks to the other stuff inside
1176 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1177 VESA. If you have PCI, say Y, otherwise N.
1186 # Select the host bridge type
1187 config PCI_HOST_VIA82C505
1189 depends on PCI && ARCH_SHARK
1192 config PCI_HOST_ITE8152
1194 depends on PCI && MACH_ARMCORE
1198 source "drivers/pci/Kconfig"
1200 source "drivers/pcmcia/Kconfig"
1204 menu "Kernel Features"
1206 source "kernel/time/Kconfig"
1209 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1210 depends on EXPERIMENTAL
1211 depends on GENERIC_CLOCKEVENTS
1212 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1213 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
1214 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
1215 select USE_GENERIC_SMP_HELPERS
1218 This enables support for systems with more than one CPU. If you have
1219 a system with only one CPU, like most personal computers, say N. If
1220 you have a system with more than one CPU, say Y.
1222 If you say N here, the kernel will run on single and multiprocessor
1223 machines, but will use only one CPU of a multiprocessor machine. If
1224 you say Y here, the kernel will run on many, but not all, single
1225 processor machines. On a single processor machine, the kernel will
1226 run faster if you say N here.
1228 See also <file:Documentation/i386/IO-APIC.txt>,
1229 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1230 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1232 If you don't know what to do here, say N.
1235 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1236 depends on EXPERIMENTAL
1237 depends on SMP && !XIP && !THUMB2_KERNEL
1240 SMP kernels contain instructions which fail on non-SMP processors.
1241 Enabling this option allows the kernel to modify itself to make
1242 these instructions safe. Disabling it allows about 1K of space
1245 If you don't know what to do here, say Y.
1251 This option enables support for the ARM system coherency unit
1257 This options enables support for the ARM timer and watchdog unit
1260 prompt "Memory split"
1263 Select the desired split between kernel and user memory.
1265 If you are not absolutely sure what you are doing, leave this
1269 bool "3G/1G user/kernel split"
1271 bool "2G/2G user/kernel split"
1273 bool "1G/3G user/kernel split"
1278 default 0x40000000 if VMSPLIT_1G
1279 default 0x80000000 if VMSPLIT_2G
1283 int "Maximum number of CPUs (2-32)"
1289 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1290 depends on SMP && HOTPLUG && EXPERIMENTAL
1292 Say Y here to experiment with turning CPUs off and on. CPUs
1293 can be controlled through /sys/devices/system/cpu.
1296 bool "Use local timer interrupts"
1301 Enable support for local timers on SMP platforms, rather then the
1302 legacy IPI broadcast method. Local timers allows the system
1303 accounting to be spread across the timer interval, preventing a
1304 "thundering herd" at every timer tick.
1306 source kernel/Kconfig.preempt
1310 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1311 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1312 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1313 default AT91_TIMER_HZ if ARCH_AT91
1314 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1317 config THUMB2_KERNEL
1318 bool "Compile the kernel in Thumb-2 mode"
1319 depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
1321 select ARM_ASM_UNIFIED
1323 By enabling this option, the kernel will be compiled in
1324 Thumb-2 mode. A compiler/assembler that understand the unified
1325 ARM-Thumb syntax is needed.
1329 config ARM_ASM_UNIFIED
1333 bool "Use the ARM EABI to compile the kernel"
1335 This option allows for the kernel to be compiled using the latest
1336 ARM ABI (aka EABI). This is only useful if you are using a user
1337 space environment that is also compiled with EABI.
1339 Since there are major incompatibilities between the legacy ABI and
1340 EABI, especially with regard to structure member alignment, this
1341 option also changes the kernel syscall calling convention to
1342 disambiguate both ABIs and allow for backward compatibility support
1343 (selected with CONFIG_OABI_COMPAT).
1345 To use this you need GCC version 4.0.0 or later.
1348 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1349 depends on AEABI && EXPERIMENTAL
1352 This option preserves the old syscall interface along with the
1353 new (ARM EABI) one. It also provides a compatibility layer to
1354 intercept syscalls that have structure arguments which layout
1355 in memory differs between the legacy ABI and the new ARM EABI
1356 (only for non "thumb" binaries). This option adds a tiny
1357 overhead to all syscalls and produces a slightly larger kernel.
1358 If you know you'll be using only pure EABI user space then you
1359 can say N here. If this option is not selected and you attempt
1360 to execute a legacy ABI binary then the result will be
1361 UNPREDICTABLE (in fact it can be predicted that it won't work
1362 at all). If in doubt say Y.
1364 config ARCH_HAS_HOLES_MEMORYMODEL
1367 config ARCH_SPARSEMEM_ENABLE
1370 config ARCH_SPARSEMEM_DEFAULT
1371 def_bool ARCH_SPARSEMEM_ENABLE
1373 config ARCH_SELECT_MEMORY_MODEL
1374 def_bool ARCH_SPARSEMEM_ENABLE
1377 bool "High Memory Support (EXPERIMENTAL)"
1378 depends on MMU && EXPERIMENTAL
1380 The address space of ARM processors is only 4 Gigabytes large
1381 and it has to accommodate user address space, kernel address
1382 space as well as some memory mapped IO. That means that, if you
1383 have a large amount of physical memory and/or IO, not all of the
1384 memory can be "permanently mapped" by the kernel. The physical
1385 memory that is not permanently mapped is called "high memory".
1387 Depending on the selected kernel/user memory split, minimum
1388 vmalloc space and actual amount of RAM, you may not need this
1389 option which should result in a slightly faster kernel.
1394 bool "Allocate 2nd-level pagetables from highmem"
1396 depends on !OUTER_CACHE
1398 config HW_PERF_EVENTS
1399 bool "Enable hardware performance counter support for perf events"
1400 depends on PERF_EVENTS && CPU_HAS_PMU
1403 Enable hardware performance counter support for perf events. If
1404 disabled, perf events will use software events only.
1409 This enables support for sparse irqs. This is useful in general
1410 as most CPUs have a fairly sparse array of IRQ vectors, which
1411 the irq_desc then maps directly on to. Systems with a high
1412 number of off-chip IRQs will want to treat this as
1413 experimental until they have been independently verified.
1417 config FORCE_MAX_ZONEORDER
1418 int "Maximum zone order" if ARCH_SHMOBILE
1419 range 11 64 if ARCH_SHMOBILE
1420 default "9" if SA1111
1423 The kernel memory allocator divides physically contiguous memory
1424 blocks into "zones", where each zone is a power of two number of
1425 pages. This option selects the largest power of two that the kernel
1426 keeps in the memory allocator. If you need to allocate very large
1427 blocks of physically contiguous memory, then you may need to
1428 increase this value.
1430 This config option is actually maximum order plus one. For example,
1431 a value of 11 means that the largest free memory block is 2^10 pages.
1434 bool "Timer and CPU usage LEDs"
1435 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1436 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1437 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1438 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1439 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1440 ARCH_AT91 || ARCH_DAVINCI || \
1441 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1443 If you say Y here, the LEDs on your machine will be used
1444 to provide useful information about your current system status.
1446 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1447 be able to select which LEDs are active using the options below. If
1448 you are compiling a kernel for the EBSA-110 or the LART however, the
1449 red LED will simply flash regularly to indicate that the system is
1450 still functional. It is safe to say Y here if you have a CATS
1451 system, but the driver will do nothing.
1454 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1455 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1456 || MACH_OMAP_PERSEUS2
1458 depends on !GENERIC_CLOCKEVENTS
1459 default y if ARCH_EBSA110
1461 If you say Y here, one of the system LEDs (the green one on the
1462 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1463 will flash regularly to indicate that the system is still
1464 operational. This is mainly useful to kernel hackers who are
1465 debugging unstable kernels.
1467 The LART uses the same LED for both Timer LED and CPU usage LED
1468 functions. You may choose to use both, but the Timer LED function
1469 will overrule the CPU usage LED.
1472 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1474 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1475 || MACH_OMAP_PERSEUS2
1478 If you say Y here, the red LED will be used to give a good real
1479 time indication of CPU usage, by lighting whenever the idle task
1480 is not currently executing.
1482 The LART uses the same LED for both Timer LED and CPU usage LED
1483 functions. You may choose to use both, but the Timer LED function
1484 will overrule the CPU usage LED.
1486 config ALIGNMENT_TRAP
1488 depends on CPU_CP15_MMU
1489 default y if !ARCH_EBSA110
1490 select HAVE_PROC_CPU if PROC_FS
1492 ARM processors cannot fetch/store information which is not
1493 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1494 address divisible by 4. On 32-bit ARM processors, these non-aligned
1495 fetch/store instructions will be emulated in software if you say
1496 here, which has a severe performance impact. This is necessary for
1497 correct operation of some network protocols. With an IP-only
1498 configuration it is safe to say N, otherwise say Y.
1500 config UACCESS_WITH_MEMCPY
1501 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1502 depends on MMU && EXPERIMENTAL
1503 default y if CPU_FEROCEON
1505 Implement faster copy_to_user and clear_user methods for CPU
1506 cores where a 8-word STM instruction give significantly higher
1507 memory write throughput than a sequence of individual 32bit stores.
1509 A possible side effect is a slight increase in scheduling latency
1510 between threads sharing the same address space if they invoke
1511 such copy operations with large buffers.
1513 However, if the CPU data cache is using a write-allocate mode,
1514 this option is unlikely to provide any performance gain.
1518 prompt "Enable seccomp to safely compute untrusted bytecode"
1520 This kernel feature is useful for number crunching applications
1521 that may need to compute untrusted bytecode during their
1522 execution. By using pipes or other transports made available to
1523 the process as file descriptors supporting the read/write
1524 syscalls, it's possible to isolate those applications in
1525 their own address space using seccomp. Once seccomp is
1526 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1527 and the task is only allowed to execute a few safe syscalls
1528 defined by each seccomp mode.
1530 config CC_STACKPROTECTOR
1531 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1533 This option turns on the -fstack-protector GCC feature. This
1534 feature puts, at the beginning of functions, a canary value on
1535 the stack just before the return address, and validates
1536 the value just before actually returning. Stack based buffer
1537 overflows (that need to overwrite this return address) now also
1538 overwrite the canary, which gets detected and the attack is then
1539 neutralized via a kernel panic.
1540 This feature requires gcc version 4.2 or above.
1542 config DEPRECATED_PARAM_STRUCT
1543 bool "Provide old way to pass kernel parameters"
1545 This was deprecated in 2001 and announced to live on for 5 years.
1546 Some old boot loaders still use this way.
1552 # Compressed boot loader in ROM. Yes, we really want to ask about
1553 # TEXT and BSS so we preserve their values in the config files.
1554 config ZBOOT_ROM_TEXT
1555 hex "Compressed ROM boot loader base address"
1558 The physical address at which the ROM-able zImage is to be
1559 placed in the target. Platforms which normally make use of
1560 ROM-able zImage formats normally set this to a suitable
1561 value in their defconfig file.
1563 If ZBOOT_ROM is not enabled, this has no effect.
1565 config ZBOOT_ROM_BSS
1566 hex "Compressed ROM boot loader BSS address"
1569 The base address of an area of read/write memory in the target
1570 for the ROM-able zImage which must be available while the
1571 decompressor is running. It must be large enough to hold the
1572 entire decompressed kernel plus an additional 128 KiB.
1573 Platforms which normally make use of ROM-able zImage formats
1574 normally set this to a suitable value in their defconfig file.
1576 If ZBOOT_ROM is not enabled, this has no effect.
1579 bool "Compressed boot loader in ROM/flash"
1580 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1582 Say Y here if you intend to execute your compressed kernel image
1583 (zImage) directly from ROM or flash. If unsure, say N.
1586 string "Default kernel command string"
1589 On some architectures (EBSA110 and CATS), there is currently no way
1590 for the boot loader to pass arguments to the kernel. For these
1591 architectures, you should supply some command-line options at build
1592 time by entering them here. As a minimum, you should specify the
1593 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1595 config CMDLINE_FORCE
1596 bool "Always use the default kernel command string"
1597 depends on CMDLINE != ""
1599 Always use the default kernel command string, even if the boot
1600 loader passes other arguments to the kernel.
1601 This is useful if you cannot or don't want to change the
1602 command-line options your boot loader passes to the kernel.
1607 bool "Kernel Execute-In-Place from ROM"
1608 depends on !ZBOOT_ROM
1610 Execute-In-Place allows the kernel to run from non-volatile storage
1611 directly addressable by the CPU, such as NOR flash. This saves RAM
1612 space since the text section of the kernel is not loaded from flash
1613 to RAM. Read-write sections, such as the data section and stack,
1614 are still copied to RAM. The XIP kernel is not compressed since
1615 it has to run directly from flash, so it will take more space to
1616 store it. The flash address used to link the kernel object files,
1617 and for storing it, is configuration dependent. Therefore, if you
1618 say Y here, you must know the proper physical address where to
1619 store the kernel image depending on your own flash memory usage.
1621 Also note that the make target becomes "make xipImage" rather than
1622 "make zImage" or "make Image". The final kernel binary to put in
1623 ROM memory will be arch/arm/boot/xipImage.
1627 config XIP_PHYS_ADDR
1628 hex "XIP Kernel Physical Location"
1629 depends on XIP_KERNEL
1630 default "0x00080000"
1632 This is the physical address in your flash memory the kernel will
1633 be linked for and stored to. This address is dependent on your
1637 bool "Kexec system call (EXPERIMENTAL)"
1638 depends on EXPERIMENTAL
1640 kexec is a system call that implements the ability to shutdown your
1641 current kernel, and to start another kernel. It is like a reboot
1642 but it is independent of the system firmware. And like a reboot
1643 you can start any kernel with it, not just Linux.
1645 It is an ongoing process to be certain the hardware in a machine
1646 is properly shutdown, so do not be surprised if this code does not
1647 initially work for you. It may help to enable device hotplugging
1651 bool "Export atags in procfs"
1655 Should the atags used to boot the kernel be exported in an "atags"
1656 file in procfs. Useful with kexec.
1658 config AUTO_ZRELADDR
1659 bool "Auto calculation of the decompressed kernel image address"
1660 depends on !ZBOOT_ROM && !ARCH_U300
1662 ZRELADDR is the physical address where the decompressed kernel
1663 image will be placed. If AUTO_ZRELADDR is selected, the address
1664 will be determined at run-time by masking the current IP with
1665 0xf8000000. This assumes the zImage being placed in the first 128MB
1666 from start of memory.
1670 menu "CPU Power Management"
1674 source "drivers/cpufreq/Kconfig"
1677 tristate "CPUfreq driver for i.MX CPUs"
1678 depends on ARCH_MXC && CPU_FREQ
1680 This enables the CPUfreq driver for i.MX CPUs.
1682 config CPU_FREQ_SA1100
1685 config CPU_FREQ_SA1110
1688 config CPU_FREQ_INTEGRATOR
1689 tristate "CPUfreq driver for ARM Integrator CPUs"
1690 depends on ARCH_INTEGRATOR && CPU_FREQ
1693 This enables the CPUfreq driver for ARM Integrator CPUs.
1695 For details, take a look at <file:Documentation/cpu-freq>.
1701 depends on CPU_FREQ && ARCH_PXA && PXA25x
1703 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1705 config CPU_FREQ_S3C64XX
1706 bool "CPUfreq support for Samsung S3C64XX CPUs"
1707 depends on CPU_FREQ && CPU_S3C6410
1712 Internal configuration node for common cpufreq on Samsung SoC
1714 config CPU_FREQ_S3C24XX
1715 bool "CPUfreq driver for Samsung S3C24XX series CPUs"
1716 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1719 This enables the CPUfreq driver for the Samsung S3C24XX family
1722 For details, take a look at <file:Documentation/cpu-freq>.
1726 config CPU_FREQ_S3C24XX_PLL
1727 bool "Support CPUfreq changing of PLL frequency"
1728 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1730 Compile in support for changing the PLL frequency from the
1731 S3C24XX series CPUfreq driver. The PLL takes time to settle
1732 after a frequency change, so by default it is not enabled.
1734 This also means that the PLL tables for the selected CPU(s) will
1735 be built which may increase the size of the kernel image.
1737 config CPU_FREQ_S3C24XX_DEBUG
1738 bool "Debug CPUfreq Samsung driver core"
1739 depends on CPU_FREQ_S3C24XX
1741 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1743 config CPU_FREQ_S3C24XX_IODEBUG
1744 bool "Debug CPUfreq Samsung driver IO timing"
1745 depends on CPU_FREQ_S3C24XX
1747 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1749 config CPU_FREQ_S3C24XX_DEBUGFS
1750 bool "Export debugfs for CPUFreq"
1751 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1753 Export status information via debugfs.
1757 source "drivers/cpuidle/Kconfig"
1761 menu "Floating point emulation"
1763 comment "At least one emulation must be selected"
1766 bool "NWFPE math emulation"
1767 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1769 Say Y to include the NWFPE floating point emulator in the kernel.
1770 This is necessary to run most binaries. Linux does not currently
1771 support floating point hardware so you need to say Y here even if
1772 your machine has an FPA or floating point co-processor podule.
1774 You may say N here if you are going to load the Acorn FPEmulator
1775 early in the bootup.
1778 bool "Support extended precision"
1779 depends on FPE_NWFPE
1781 Say Y to include 80-bit support in the kernel floating-point
1782 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1783 Note that gcc does not generate 80-bit operations by default,
1784 so in most cases this option only enlarges the size of the
1785 floating point emulator without any good reason.
1787 You almost surely want to say N here.
1790 bool "FastFPE math emulation (EXPERIMENTAL)"
1791 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1793 Say Y here to include the FAST floating point emulator in the kernel.
1794 This is an experimental much faster emulator which now also has full
1795 precision for the mantissa. It does not support any exceptions.
1796 It is very simple, and approximately 3-6 times faster than NWFPE.
1798 It should be sufficient for most programs. It may be not suitable
1799 for scientific calculations, but you have to check this for yourself.
1800 If you do not feel you need a faster FP emulation you should better
1804 bool "VFP-format floating point maths"
1805 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1807 Say Y to include VFP support code in the kernel. This is needed
1808 if your hardware includes a VFP unit.
1810 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1811 release notes and additional status information.
1813 Say N if your target does not have VFP hardware.
1821 bool "Advanced SIMD (NEON) Extension support"
1822 depends on VFPv3 && CPU_V7
1824 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1829 menu "Userspace binary formats"
1831 source "fs/Kconfig.binfmt"
1834 tristate "RISC OS personality"
1837 Say Y here to include the kernel code necessary if you want to run
1838 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1839 experimental; if this sounds frightening, say N and sleep in peace.
1840 You can also say M here to compile this support as a module (which
1841 will be called arthur).
1845 menu "Power management options"
1847 source "kernel/power/Kconfig"
1849 config ARCH_SUSPEND_POSSIBLE
1854 source "net/Kconfig"
1856 source "drivers/Kconfig"
1860 source "arch/arm/Kconfig.debug"
1862 source "security/Kconfig"
1864 source "crypto/Kconfig"
1866 source "lib/Kconfig"