2 * linux/arch/alpha/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
14 * "A Kernel Model for Precision Timekeeping" by Dave Mills
15 * 1997-01-09 Adrian Sun
16 * use interval timer if CONFIG_RTC=y
17 * 1997-10-29 John Bowman (bowman@math.ualberta.ca)
18 * fixed tick loss calculation in timer_interrupt
19 * (round system clock to nearest tick instead of truncating)
20 * fixed algorithm in time_init for getting time from CMOS clock
21 * 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
22 * fixed algorithm in do_gettimeofday() for calculating the precise time
23 * from processor cycle counter (now taking lost_ticks into account)
24 * 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
25 * Fixed time_init to be aware of epoches != 1900. This prevents
26 * booting up in 2048 for me;) Code is stolen from rtc.c.
27 * 2003-06-03 R. Scott Bailey <scott.bailey@eds.com>
28 * Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/param.h>
35 #include <linux/string.h>
37 #include <linux/delay.h>
38 #include <linux/ioport.h>
39 #include <linux/irq.h>
40 #include <linux/interrupt.h>
41 #include <linux/init.h>
42 #include <linux/bcd.h>
43 #include <linux/profile.h>
45 #include <asm/uaccess.h>
47 #include <asm/hwrpb.h>
48 #include <asm/8253pit.h>
51 #include <linux/mc146818rtc.h>
52 #include <linux/time.h>
53 #include <linux/timex.h>
58 static int set_rtc_mmss(unsigned long);
60 DEFINE_SPINLOCK(rtc_lock);
61 EXPORT_SYMBOL(rtc_lock);
63 #define TICK_SIZE (tick_nsec / 1000)
66 * Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
67 * by 48 gives us 16 bits for HZ while keeping the accuracy good even
68 * for large CPU clock rates.
72 /* lump static variables together for more efficient access: */
74 /* cycle counter last time it got invoked */
76 /* ticks/cycle * 2^48 */
77 unsigned long scaled_ticks_per_cycle;
78 /* partial unused tick */
79 unsigned long partial_tick;
82 unsigned long est_cycle_freq;
85 static inline __u32 rpcc(void)
88 asm volatile ("rpcc %0" : "=r"(result));
92 int update_persistent_clock(struct timespec now)
94 return set_rtc_mmss(now.tv_sec);
97 void read_persistent_clock(struct timespec *ts)
99 unsigned int year, mon, day, hour, min, sec, epoch;
101 sec = CMOS_READ(RTC_SECONDS);
102 min = CMOS_READ(RTC_MINUTES);
103 hour = CMOS_READ(RTC_HOURS);
104 day = CMOS_READ(RTC_DAY_OF_MONTH);
105 mon = CMOS_READ(RTC_MONTH);
106 year = CMOS_READ(RTC_YEAR);
108 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
111 hour = bcd2bin(hour);
114 year = bcd2bin(year);
117 /* PC-like is standard; used for year >= 70 */
121 else if (year >= 20 && year < 48)
124 else if (year >= 48 && year < 70)
125 /* Digital UNIX epoch */
128 printk(KERN_INFO "Using epoch = %d\n", epoch);
130 if ((year += epoch) < 1970)
133 ts->tv_sec = mktime(year, mon, day, hour, min, sec);
139 * timer_interrupt() needs to keep up the real-time clock,
140 * as well as call the "do_timer()" routine every clocktick
142 irqreturn_t timer_interrupt(int irq, void *dev)
149 /* Not SMP, do kernel PC profiling here. */
150 profile_tick(CPU_PROFILING);
153 write_seqlock(&xtime_lock);
156 * Calculate how many ticks have passed since the last update,
157 * including any previous partial leftover. Save any resulting
158 * fraction for the next pass.
161 delta = now - state.last_time;
162 state.last_time = now;
163 delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
164 state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
165 nticks = delta >> FIX_SHIFT;
170 write_sequnlock(&xtime_lock);
174 update_process_times(user_mode(get_irq_regs()));
181 common_init_rtc(void)
185 /* Reset periodic interrupt frequency. */
186 x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
187 /* Test includes known working values on various platforms
188 where 0x26 is wrong; we refuse to change those. */
189 if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
190 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
191 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
194 /* Turn on periodic interrupts. */
195 x = CMOS_READ(RTC_CONTROL);
196 if (!(x & RTC_PIE)) {
197 printk("Turning on RTC interrupts.\n");
199 x &= ~(RTC_AIE | RTC_UIE);
200 CMOS_WRITE(x, RTC_CONTROL);
202 (void) CMOS_READ(RTC_INTR_FLAGS);
204 outb(0x36, 0x43); /* pit counter 0: system timer */
208 outb(0xb6, 0x43); /* pit counter 2: speaker */
215 unsigned int common_get_rtc_time(struct rtc_time *time)
217 return __get_rtc_time(time);
220 int common_set_rtc_time(struct rtc_time *time)
222 return __set_rtc_time(time);
225 /* Validate a computed cycle counter result against the known bounds for
226 the given processor core. There's too much brokenness in the way of
227 timing hardware for any one method to work everywhere. :-(
229 Return 0 if the result cannot be trusted, otherwise return the argument. */
231 static unsigned long __init
232 validate_cc_value(unsigned long cc)
234 static struct bounds {
235 unsigned int min, max;
236 } cpu_hz[] __initdata = {
237 [EV3_CPU] = { 50000000, 200000000 }, /* guess */
238 [EV4_CPU] = { 100000000, 300000000 },
239 [LCA4_CPU] = { 100000000, 300000000 }, /* guess */
240 [EV45_CPU] = { 200000000, 300000000 },
241 [EV5_CPU] = { 250000000, 433000000 },
242 [EV56_CPU] = { 333000000, 667000000 },
243 [PCA56_CPU] = { 400000000, 600000000 }, /* guess */
244 [PCA57_CPU] = { 500000000, 600000000 }, /* guess */
245 [EV6_CPU] = { 466000000, 600000000 },
246 [EV67_CPU] = { 600000000, 750000000 },
247 [EV68AL_CPU] = { 750000000, 940000000 },
248 [EV68CB_CPU] = { 1000000000, 1333333333 },
249 /* None of the following are shipping as of 2001-11-01. */
250 [EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */
251 [EV69_CPU] = { 1000000000, 1700000000 }, /* guess */
252 [EV7_CPU] = { 800000000, 1400000000 }, /* guess */
253 [EV79_CPU] = { 1000000000, 2000000000 }, /* guess */
256 /* Allow for some drift in the crystal. 10MHz is more than enough. */
257 const unsigned int deviation = 10000000;
259 struct percpu_struct *cpu;
262 cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
263 index = cpu->type & 0xffffffff;
265 /* If index out of bounds, no way to validate. */
266 if (index >= ARRAY_SIZE(cpu_hz))
269 /* If index contains no data, no way to validate. */
270 if (cpu_hz[index].max == 0)
273 if (cc < cpu_hz[index].min - deviation
274 || cc > cpu_hz[index].max + deviation)
282 * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
286 #define CALIBRATE_LATCH 0xffff
287 #define TIMEOUT_COUNT 0x100000
289 static unsigned long __init
290 calibrate_cc_with_pit(void)
294 /* Set the Gate high, disable speaker */
295 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
298 * Now let's take care of CTC channel 2
300 * Set the Gate high, program CTC channel 2 for mode 0,
301 * (interrupt on terminal count mode), binary count,
302 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
304 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
305 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
306 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
311 } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
314 /* Error: ECTCNEVERSET or ECPUTOOFAST. */
315 if (count <= 1 || count == TIMEOUT_COUNT)
318 return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
321 /* The Linux interpretation of the CMOS clock register contents:
322 When the Update-In-Progress (UIP) flag goes from 1 to 0, the
323 RTC registers show the second which has precisely just started.
324 Let's hope other operating systems interpret the RTC the same way. */
326 static unsigned long __init
327 rpcc_after_update_in_progress(void)
329 do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
330 do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
338 unsigned int cc1, cc2;
339 unsigned long cycle_freq, tolerance;
342 /* Calibrate CPU clock -- attempt #1. */
344 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
348 /* Calibrate CPU clock -- attempt #2. */
349 if (!est_cycle_freq) {
350 cc1 = rpcc_after_update_in_progress();
351 cc2 = rpcc_after_update_in_progress();
352 est_cycle_freq = validate_cc_value(cc2 - cc1);
356 cycle_freq = hwrpb->cycle_freq;
357 if (est_cycle_freq) {
358 /* If the given value is within 250 PPM of what we calculated,
359 accept it. Otherwise, use what we found. */
360 tolerance = cycle_freq / 4000;
361 diff = cycle_freq - est_cycle_freq;
364 if ((unsigned long)diff > tolerance) {
365 cycle_freq = est_cycle_freq;
366 printk("HWRPB cycle frequency bogus. "
367 "Estimated %lu Hz\n", cycle_freq);
371 } else if (! validate_cc_value (cycle_freq)) {
372 printk("HWRPB cycle frequency bogus, "
373 "and unable to estimate a proper value!\n");
376 /* From John Bowman <bowman@math.ualberta.ca>: allow the values
377 to settle, as the Update-In-Progress bit going low isn't good
378 enough on some hardware. 2ms is our guess; we haven't found
379 bogomips yet, but this is close on a 500Mhz box. */
384 extern void __you_loose (void);
388 state.last_time = cc1;
389 state.scaled_ticks_per_cycle
390 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
391 state.partial_tick = 0L;
393 /* Startup the timer source. */
398 * Use the cycle counter to estimate an displacement from the last time
399 * tick. Unfortunately the Alpha designers made only the low 32-bits of
400 * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz
401 * part. So we can't do the "find absolute time in terms of cycles" thing
402 * that the other ports do.
404 u32 arch_gettimeoffset(void)
407 /* Until and unless we figure out how to get cpu cycle counters
408 in sync and keep them there, we can't use the rpcc tricks. */
411 unsigned long delta_cycles, delta_usec, partial_tick;
413 delta_cycles = rpcc() - state.last_time;
414 partial_tick = state.partial_tick;
416 * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks)
417 * = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks)
418 * = cycles * (s_t_p_c) * 15625 / (2**42 * ticks)
420 * which, given a 600MHz cycle and a 1024Hz tick, has a
421 * dynamic range of about 1.7e17, which is less than the
422 * 1.8e19 in an unsigned long, so we are safe from overflow.
424 * Round, but with .5 up always, since .5 to even is harder
425 * with no clear gain.
428 delta_usec = (delta_cycles * state.scaled_ticks_per_cycle
429 + partial_tick) * 15625;
430 delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
431 return delta_usec * 1000;
436 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
437 * called 500 ms after the second nowtime has started, because when
438 * nowtime is written into the registers of the CMOS clock, it will
439 * jump to the next second precisely 500 ms later. Check the Motorola
440 * MC146818A or Dallas DS12887 data sheet for details.
442 * BUG: This routine does not handle hour overflow properly; it just
443 * sets the minutes. Usually you won't notice until after reboot!
448 set_rtc_mmss(unsigned long nowtime)
451 int real_seconds, real_minutes, cmos_minutes;
452 unsigned char save_control, save_freq_select;
454 /* irq are locally disabled here */
455 spin_lock(&rtc_lock);
456 /* Tell the clock it's being set */
457 save_control = CMOS_READ(RTC_CONTROL);
458 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
460 /* Stop and reset prescaler */
461 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
462 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
464 cmos_minutes = CMOS_READ(RTC_MINUTES);
465 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
466 cmos_minutes = bcd2bin(cmos_minutes);
469 * since we're only adjusting minutes and seconds,
470 * don't interfere with hour overflow. This avoids
471 * messing with unknown time zones but requires your
472 * RTC not to be off by more than 15 minutes
474 real_seconds = nowtime % 60;
475 real_minutes = nowtime / 60;
476 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
477 /* correct for half hour time zone */
482 if (abs(real_minutes - cmos_minutes) < 30) {
483 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
484 real_seconds = bin2bcd(real_seconds);
485 real_minutes = bin2bcd(real_minutes);
487 CMOS_WRITE(real_seconds,RTC_SECONDS);
488 CMOS_WRITE(real_minutes,RTC_MINUTES);
491 "set_rtc_mmss: can't update from %d to %d\n",
492 cmos_minutes, real_minutes);
496 /* The following flags have to be released exactly in this order,
497 * otherwise the DS12887 (popular MC146818A clone with integrated
498 * battery and quartz) will not reset the oscillator and will not
499 * update precisely 500 ms later. You won't find this mentioned in
500 * the Dallas Semiconductor data sheets, but who believes data
501 * sheets anyway ... -- Markus Kuhn
503 CMOS_WRITE(save_control, RTC_CONTROL);
504 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
505 spin_unlock(&rtc_lock);