2 * linux/arch/alpha/kernel/sys_nautilus.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1998 Richard Henderson
6 * Copyright (C) 1999 Alpha Processor, Inc.,
7 * (David Daniel, Stig Telfer, Soohoon Lee)
9 * Code supporting NAUTILUS systems.
12 * NAUTILUS has the following I/O features:
14 * a) Driven by AMD 751 aka IRONGATE (northbridge):
18 * b) Driven by ALI M1543C (southbridge)
21 * 1 dual drive capable FDD controller
23 * 1 ECP/EPP/SP parallel port
27 #include <linux/kernel.h>
28 #include <linux/types.h>
30 #include <linux/sched.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/reboot.h>
34 #include <linux/bootmem.h>
35 #include <linux/bitops.h>
37 #include <asm/ptrace.h>
38 #include <asm/system.h>
41 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/core_irongate.h>
46 #include <asm/hwrpb.h>
47 #include <asm/tlbflush.h>
53 #include "machvec_impl.h"
57 nautilus_init_irq(void)
59 if (alpha_using_srm) {
60 alpha_mv.device_interrupt = srm_device_interrupt;
64 common_init_isa_dma();
68 nautilus_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
70 /* Preserve the IRQ set up by the console. */
73 /* UP1500: AGP INTA is actually routed to IRQ 5, not IRQ 10 as
74 console reports. Check the device id of AGP bridge to distinguish
75 UP1500 from UP1000/1100. Note: 'pin' is 2 due to bridge swizzle. */
76 if (slot == 1 && pin == 2 &&
77 dev->bus->self && dev->bus->self->device == 0x700f)
79 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
84 nautilus_kill_arch(int mode)
86 struct pci_bus *bus = pci_isa_hose->bus;
91 case LINUX_REBOOT_CMD_RESTART:
92 if (! alpha_using_srm) {
94 pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
95 pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80);
102 case LINUX_REBOOT_CMD_POWER_OFF:
104 off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */
105 pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
108 off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */
109 pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
112 outw(0xffff, pmuport); /* Clear pending events. */
113 outw(off, pmuport + 4);
119 /* Perform analysis of a machine check that arrived from the system (NMI) */
122 naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
123 struct pt_regs *regs)
125 printk("PC %lx RA %lx\n", regs->pc, regs->r26);
126 irongate_pci_clr_err();
129 /* Machine checks can come from two sources - those on the CPU and those
130 in the system. They are analysed separately but all starts here. */
133 nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
137 /* Now for some analysis. Machine checks fall into two classes --
138 those picked up by the system, and those picked up by the CPU.
139 Add to that the two levels of severity - correctable or not. */
141 if (vector == SCB_Q_SYSMCHK
142 && ((IRONGATE0->dramms & 0x300) == 0x300)) {
143 unsigned long nmi_ctl;
152 /* Write again clears error bits. */
153 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
157 /* Write again clears error bits. */
158 IRONGATE0->dramms = IRONGATE0->dramms;
168 if (vector == SCB_Q_SYSERR)
169 mchk_class = "Correctable";
170 else if (vector == SCB_Q_SYSMCHK)
171 mchk_class = "Fatal";
173 ev6_machine_check(vector, la_ptr);
177 printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
178 "[%s System Machine Check (NMI)]\n",
181 naut_sys_machine_check(vector, la_ptr, get_irq_regs());
183 /* Tell the PALcode to clear the machine check */
189 extern void free_reserved_mem(void *, void *);
190 extern void pcibios_claim_one_bus(struct pci_bus *);
192 static struct resource irongate_io = {
193 .name = "Irongate PCI IO",
194 .flags = IORESOURCE_IO,
196 static struct resource irongate_mem = {
197 .name = "Irongate PCI MEM",
198 .flags = IORESOURCE_MEM,
202 nautilus_init_pci(void)
204 struct pci_controller *hose = hose_head;
206 struct pci_dev *irongate;
207 unsigned long bus_align, bus_size, pci_mem;
208 unsigned long memtop = max_low_pfn << PAGE_SHIFT;
210 /* Scan our single hose. */
211 bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
213 pcibios_claim_one_bus(bus);
215 irongate = pci_get_bus_and_slot(0, 0);
216 bus->self = irongate;
217 bus->resource[0] = &irongate_io;
218 bus->resource[1] = &irongate_mem;
220 pci_bus_size_bridges(bus);
223 bus->resource[0]->start = 0;
224 bus->resource[0]->end = 0xffff;
226 /* Set up PCI memory range - limit is hardwired to 0xffffffff,
227 base must be at aligned to 16Mb. */
228 bus_align = bus->resource[1]->start;
229 bus_size = bus->resource[1]->end + 1 - bus_align;
230 if (bus_align < 0x1000000UL)
231 bus_align = 0x1000000UL;
233 pci_mem = (0x100000000UL - bus_size) & -bus_align;
235 bus->resource[1]->start = pci_mem;
236 bus->resource[1]->end = 0xffffffffUL;
237 if (request_resource(&iomem_resource, bus->resource[1]) < 0)
238 printk(KERN_ERR "Failed to request MEM on hose 0\n");
240 if (pci_mem < memtop)
242 if (memtop > alpha_mv.min_mem_address) {
243 free_reserved_mem(__va(alpha_mv.min_mem_address),
245 printk("nautilus_init_pci: %ldk freed\n",
246 (memtop - alpha_mv.min_mem_address) >> 10);
249 if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */
250 IRONGATE0->pci_mem = pci_mem;
252 pci_bus_assign_resources(bus);
254 /* pci_common_swizzle() relies on bus->self being NULL
255 for the root bus, so just clear it. */
257 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
264 struct alpha_machine_vector nautilus_mv __initmv = {
265 .vector_name = "Nautilus",
269 .machine_check = nautilus_machine_check,
270 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
271 .min_io_address = DEFAULT_IO_BASE,
272 .min_mem_address = IRONGATE_DEFAULT_MEM_BASE,
275 .device_interrupt = isa_device_interrupt,
277 .init_arch = irongate_init_arch,
278 .init_irq = nautilus_init_irq,
279 .init_rtc = common_init_rtc,
280 .init_pci = nautilus_init_pci,
281 .kill_arch = nautilus_kill_arch,
282 .pci_map_irq = nautilus_map_irq,
283 .pci_swizzle = common_swizzle,