1 * UART (Universal Asynchronous Receiver/Transmitter)
11 - "nvidia,tegra20-uart"
13 - "ralink,rt2880-uart"
14 - "ibm,qpace-nwp-serial"
17 - "altr,16550-FIFO128"
20 - "serial" if the port type is unknown.
21 - reg : offset and length of the register set for the device.
22 - interrupts : should contain uart interrupt.
23 - clock-frequency : the input clock frequency for the UART
25 clocks phandle to refer to the clk used as per Documentation/devicetree
26 /bindings/clock/clock-bindings.txt
29 - current-speed : the current active speed of the UART.
30 - reg-offset : offset to apply to the mapbase from the start of the registers.
31 - reg-shift : quantity to shift the register offsets by.
32 - reg-io-width : the size (in bytes) of the IO accesses that should be
33 performed on the device. There are some systems that require 32-bit
34 accesses to the UART (e.g. TI davinci).
35 - used-by-rtas : set to indicate that the port is in use by the OpenFirmware
36 RTAS and should not be registered.
37 - no-loopback-test: set to indicate that the port does not implements loopback
39 - fifo-size: the fifo size of the UART.
40 - auto-flow-control: one way to enable automatic flow control support. The
41 driver is allowed to detect support for the capability even without this
47 Freescale DUART is very similar to the PC16552D (and to a
48 pair of NS16550A), albeit with some nonstandard behavior such as
49 erratum A-004737 (relating to incorrect BRK handling).
51 Represents a single port that is compatible with the DUART found
52 on many Freescale chips (examples include mpc8349, mpc8548,
53 mpc8641d, p4080 and ls2085a).
58 compatible = "ns8250";
59 reg = <0x80230000 0x100>;
60 clock-frequency = <3686400>;