Documentation/devicetree/bindings/phy/phy-miphy28lp.txt

   1 STMicroelectronics STi MIPHY28LP PHY binding
   2 ============================================
   3
   4 This binding describes a miphy device that is used to control PHY hardware
   5 for SATA, PCIe or USB3.
   6
   7 Required properties (controller (parent) node):
   8 - compatible    : Should be "st,miphy28lp-phy".
   9 - st,syscfg     : Should be a phandle of the system configuration register group
  10                   which contain the SATA, PCIe or USB3 mode setting bits.
  11
  12 Required nodes  :  A sub-node is required for each channel the controller
  13                    provides. Address range information including the usual
  14                    'reg' and 'reg-names' properties are used inside these
  15                    nodes to describe the controller's topology. These nodes
  16                    are translated by the driver's .xlate() function.
  17
  18 Required properties (port (child) node):
  19 - #phy-cells    : Should be 1 (See second example)
  20                   Cell after port phandle is device type from:
  21                         - PHY_TYPE_SATA
  22                         - PHY_TYPE_PCI
  23                         - PHY_TYPE_USB3
  24 - reg           : Address and length of the register set for the device.
  25 - reg-names     : The names of the register addresses corresponding to the registers
  26                   filled in "reg". It can also contain the offset of the system configuration
  27                   registers used as glue-logic to setup the device for SATA/PCIe or USB3
  28                   devices.
  29 - resets        : phandle to the parent reset controller.
  30 - reset-names   : Associated name must be "miphy-sw-rst".
  31
  32 Optional properties (port (child) node):
  33 - st,osc-rdy            : to check the MIPHY0_OSC_RDY status in the glue-logic. This
  34                           is not available in all the MiPHY. For example, for STiH407, only the
  35                           MiPHY0 has this bit.
  36 - st,osc-force-ext      : to select the external oscillator. This can change from
  37                           different MiPHY inside the same SoC.
  38 - st,sata_gen           : to select which SATA_SPDMODE has to be set in the SATA system config
  39                           register.
  40 - st,px_rx_pol_inv      : to invert polarity of RXn/RXp (respectively negative line and positive
  41                           line).
  42 - st,scc-on             : enable ssc to reduce effects of EMI (only for sata or PCIe).
  43 - st,tx-impedance-comp  : to compensate tx impedance avoiding out of range values.
  44
  45 example:
  46
  47                 miphy28lp_phy: miphy28lp@9b22000 {
  48                         compatible = "st,miphy28lp-phy";
  49                         st,syscfg = <&syscfg_core>;
  50                         #address-cells  = <1>;
  51                         #size-cells     = <1>;
  52                         ranges;
  53
  54                         phy_port0: port@9b22000 {
  55                                 reg = <0x9b22000 0xff>,
  56                                       <0x9b09000 0xff>,
  57                                       <0x9b04000 0xff>,
  58                                       <0x114 0x4>, /* sysctrl MiPHY cntrl */
  59                                       <0x818 0x4>, /* sysctrl MiPHY status*/
  60                                       <0xe0  0x4>, /* sysctrl PCIe */
  61                                       <0xec  0x4>; /* sysctrl SATA */
  62                                 reg-names = "sata-up",
  63                                             "pcie-up",
  64                                             "pipew",
  65                                             "miphy-ctrl-glue",
  66                                             "miphy-status-glue",
  67                                             "pcie-glue",
  68                                             "sata-glue";
  69                                 #phy-cells = <1>;
  70                                 st,osc-rdy;
  71                                 reset-names = "miphy-sw-rst";
  72                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
  73                         };
  74
  75                         phy_port1: port@9b2a000 {
  76                                 reg = <0x9b2a000 0xff>,
  77                                       <0x9b19000 0xff>,
  78                                       <0x9b14000 0xff>,
  79                                       <0x118 0x4>,
  80                                       <0x81c 0x4>,
  81                                       <0xe4  0x4>,
  82                                       <0xf0  0x4>;
  83                                 reg-names = "sata-up",
  84                                             "pcie-up",
  85                                             "pipew",
  86                                             "miphy-ctrl-glue",
  87                                             "miphy-status-glue",
  88                                             "pcie-glue",
  89                                             "sata-glue";
  90                                 #phy-cells = <1>;
  91                                 st,osc-force-ext;
  92                                 reset-names = "miphy-sw-rst";
  93                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
  94                         };
  95
  96                         phy_port2: port@8f95000 {
  97                                 reg = <0x8f95000 0xff>,
  98                                       <0x8f90000 0xff>,
  99                                       <0x11c 0x4>,
 100                                       <0x820 0x4>;
 101                                 reg-names = "pipew",
 102                                     "usb3-up",
 103                                     "miphy-ctrl-glue",
 104                                     "miphy-status-glue";
 105                                 #phy-cells = <1>;
 106                                 reset-names = "miphy-sw-rst";
 107                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 108                         };
 109                 };
 110
 111
 112 Specifying phy control of devices
 113 =================================
 114
 115 Device nodes should specify the configuration required in their "phys"
 116 property, containing a phandle to the miphy device node and an index
 117 specifying which configuration to use, as described in phy-bindings.txt.
 118
 119 example:
 120                 sata0: sata@9b20000  {
 121                         ...
 122                         phys            = <&phy_port0 PHY_TYPE_SATA>;
 123                         ...
 124                 };
 125
 126 Macro definitions for the supported miphy configuration can be found in:
 127
 128 include/dt-bindings/phy/phy-miphy28lp.h