recipes/linux/omap3-pandora-kernel/mru-make-dpll4-m4-ck-programmable.diff

   1 From: Mans Rullgard <mans@mansr.com>
   2 Date: Fri, 29 Aug 2008 01:52:42 +0000 (+0100)
   3 Subject: OMAP: Make dpll4_m4_ck programmable with clk_set_rate()
   4 X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=feab5b628c06619196044c15d9d2a113df173eee
   5
   6 OMAP: Make dpll4_m4_ck programmable with clk_set_rate()
   7
   8 Filling the set_rate and round_rate fields of dpll4_m4_ck makes
   9 this clock programmable through clk_set_rate().  This is needed
  10 to give omapfb control over the dss1_alwon_fck rate.
  11
  12 Signed-off-by: Mans Rullgard <mans@mansr.com>
  13 ---
  14
  15 diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
  16 index 41f91f8..9c8e0c8 100644
  17 --- a/arch/arm/mach-omap2/clock34xx.h
  18 +++ b/arch/arm/mach-omap2/clock34xx.h
  19 @@ -877,6 +877,8 @@ static struct clk dpll4_m4_ck = {
  20                                 PARENT_CONTROLS_CLOCK,
  21         .clkdm          = { .name = "dpll4_clkdm" },
  22         .recalc         = &omap2_clksel_recalc,
  23 +       .set_rate       = &omap2_clksel_set_rate,
  24 +       .round_rate     = &omap2_clksel_round_rate,
  25  };
  26
  27  /* The PWRDN bit is apparently only available on 3430ES2 and above */