2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
35 #include <plat/mcbsp.h>
36 #include "omap-mcbsp.h"
39 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
42 xhandler_get, xhandler_put) \
43 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
44 .info = omap_mcbsp_st_info_volsw, \
45 .get = xhandler_get, .put = xhandler_put, \
46 .private_value = (unsigned long) &(struct soc_mixer_control) \
47 {.min = xmin, .max = xmax} }
49 struct omap_mcbsp_data {
51 struct omap_mcbsp_reg_cfg regs;
54 * Flags indicating is the bus already activated and configured by
63 struct snd_pcm_substream *substream;
66 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
69 * Stream DMA parameters. DMA request line and port address are set runtime
70 * since they are different between OMAP1 and later OMAPs
72 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
74 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
76 struct snd_soc_pcm_runtime *rtd = substream->private_data;
77 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
78 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
79 struct omap_pcm_dma_data *dma_data;
80 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
83 dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
85 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
86 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
88 * Configure McBSP threshold based on either:
89 * packet_size, when the sDMA is in packet mode, or
90 * based on the period size.
92 if (dma_data->packet_size)
93 words = dma_data->packet_size;
95 words = snd_pcm_lib_period_bytes(substream) /
96 (mcbsp_data->wlen / 8);
100 /* Configure McBSP internal buffer usage */
101 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
102 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
104 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
107 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
108 struct snd_pcm_hw_rule *rule)
110 struct snd_interval *buffer_size = hw_param_interval(params,
111 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
112 struct snd_interval *channels = hw_param_interval(params,
113 SNDRV_PCM_HW_PARAM_CHANNELS);
114 struct omap_mcbsp_data *mcbsp_data = rule->private;
115 struct snd_pcm_substream *substream = mcbsp_data->substream;
116 struct snd_interval frames;
119 snd_interval_any(&frames);
120 size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
122 frames.min = size / channels->min;
125 if (substream && substream->pnd_hack_params.frames_min > 0
126 && substream->pnd_hack_params.frames_max
127 >= substream->pnd_hack_params.frames_min)
129 frames.min = substream->pnd_hack_params.frames_min;
130 frames.max = substream->pnd_hack_params.frames_max;
133 return snd_interval_refine(buffer_size, &frames);
136 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
137 struct snd_soc_dai *cpu_dai)
139 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
140 int bus_id = mcbsp_data->bus_id;
143 if (!cpu_dai->active) {
144 err = omap_mcbsp_request(bus_id);
145 mcbsp_data->substream = substream;
149 * OMAP3 McBSP FIFO is word structured.
150 * McBSP2 has 1024 + 256 = 1280 word long buffer,
151 * McBSP1,3,4,5 has 128 word long buffer
152 * This means that the size of the FIFO depends on the sample format.
153 * For example on McBSP3:
154 * 16bit samples: size is 128 * 2 = 256 bytes
155 * 32bit samples: size is 128 * 4 = 512 bytes
156 * It is simpler to place constraint for buffer and period based on
158 * McBSP3 as example again (16 or 32 bit samples):
159 * 1 channel (mono): size is 128 frames (128 words)
160 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
161 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
163 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
165 * Rule for the buffer size. We should not allow
166 * smaller buffer than the FIFO size to avoid underruns
168 snd_pcm_hw_rule_add(substream->runtime, 0,
169 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
170 omap_mcbsp_hwrule_min_buffersize,
172 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
174 /* Make sure, that the period size is always even */
175 snd_pcm_hw_constraint_step(substream->runtime, 0,
176 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
182 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
183 struct snd_soc_dai *cpu_dai)
185 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
187 if (!cpu_dai->active) {
188 omap_mcbsp_free(mcbsp_data->bus_id);
189 mcbsp_data->configured = 0;
191 /* undo pandora hack */
192 mcbsp_data->substream = NULL;
193 substream->pnd_hack_params.frames_min = 0;
194 substream->pnd_hack_params.frames_max = 0;
198 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
199 struct snd_soc_dai *cpu_dai)
201 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
202 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
205 case SNDRV_PCM_TRIGGER_START:
206 case SNDRV_PCM_TRIGGER_RESUME:
207 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
208 mcbsp_data->active++;
209 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
212 case SNDRV_PCM_TRIGGER_STOP:
213 case SNDRV_PCM_TRIGGER_SUSPEND:
214 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
215 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
216 mcbsp_data->active--;
225 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
226 struct snd_pcm_substream *substream,
227 struct snd_soc_dai *dai)
229 struct snd_soc_pcm_runtime *rtd = substream->private_data;
230 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
231 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
233 snd_pcm_sframes_t delay;
235 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
236 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
238 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
241 * Divide the used locations with the channel count to get the
242 * FIFO usage in samples (don't care about partial samples in the
245 delay = fifo_use / substream->runtime->channels;
250 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
251 struct snd_pcm_hw_params *params,
252 struct snd_soc_dai *cpu_dai)
254 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
255 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
256 struct omap_pcm_dma_data *dma_data;
257 int dma, bus_id = mcbsp_data->bus_id;
258 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
261 unsigned int format, div, framesize, master;
263 dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
265 dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream);
266 port = omap_mcbsp_dma_reg_params(bus_id, substream->stream);
268 switch (params_format(params)) {
269 case SNDRV_PCM_FORMAT_S16_LE:
270 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
273 case SNDRV_PCM_FORMAT_S32_LE:
274 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
280 if (cpu_is_omap34xx()) {
281 dma_data->set_threshold = omap_mcbsp_set_threshold;
282 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
283 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
284 MCBSP_DMA_MODE_THRESHOLD) {
285 int period_words, max_thrsh;
287 period_words = params_period_bytes(params) / (wlen / 8);
288 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
289 max_thrsh = omap_mcbsp_get_max_tx_threshold(
292 max_thrsh = omap_mcbsp_get_max_rx_threshold(
295 * If the period contains less or equal number of words,
296 * we are using the original threshold mode setup:
297 * McBSP threshold = sDMA frame size = period_size
298 * Otherwise we switch to sDMA packet mode:
299 * McBSP threshold = sDMA packet size
300 * sDMA frame size = period size
302 if (period_words > max_thrsh) {
306 * Look for the biggest threshold value, which
307 * divides the period size evenly.
309 divider = period_words / max_thrsh;
310 if (period_words % max_thrsh)
312 while (period_words % divider &&
313 divider < period_words)
315 if (divider == period_words)
318 pkt_size = period_words / divider;
319 sync_mode = OMAP_DMA_SYNC_PACKET;
321 sync_mode = OMAP_DMA_SYNC_FRAME;
326 dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
327 dma_data->dma_req = dma;
328 dma_data->port_addr = port;
329 dma_data->sync_mode = sync_mode;
330 dma_data->packet_size = pkt_size;
332 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
335 if (mcbsp_data->configured) {
336 /* McBSP already configured by another stream */
341 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
342 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
343 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
344 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
345 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
346 wpf = channels = params_channels(params);
347 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
348 format == SND_SOC_DAIFMT_LEFT_J)) {
349 /* Use dual-phase frames */
350 regs->rcr2 |= RPHASE;
351 regs->xcr2 |= XPHASE;
352 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
354 regs->rcr2 |= RFRLEN2(wpf - 1);
355 regs->xcr2 |= XFRLEN2(wpf - 1);
358 regs->rcr1 |= RFRLEN1(wpf - 1);
359 regs->xcr1 |= XFRLEN1(wpf - 1);
361 switch (params_format(params)) {
362 case SNDRV_PCM_FORMAT_S16_LE:
363 /* Set word lengths */
364 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
365 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
366 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
367 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
369 case SNDRV_PCM_FORMAT_S32_LE:
370 /* Set word lengths */
371 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
372 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
373 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
374 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
377 /* Unsupported PCM format */
381 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
382 * by _counting_ BCLKs. Calculate frame size in BCLKs */
383 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
384 if (master == SND_SOC_DAIFMT_CBS_CFS) {
385 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
386 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
388 if (framesize < wlen * channels) {
389 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
390 "channels\n", __func__);
394 framesize = wlen * channels;
396 /* Set FS period and length in terms of bit clock periods */
397 regs->srgr2 &= ~FPER(0xfff);
398 regs->srgr1 &= ~FWID(0xff);
400 case SND_SOC_DAIFMT_I2S:
401 case SND_SOC_DAIFMT_LEFT_J:
402 regs->srgr2 |= FPER(framesize - 1);
403 regs->srgr1 |= FWID((framesize >> 1) - 1);
405 case SND_SOC_DAIFMT_DSP_A:
406 case SND_SOC_DAIFMT_DSP_B:
407 regs->srgr2 |= FPER(framesize - 1);
408 regs->srgr1 |= FWID(0);
412 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
413 mcbsp_data->wlen = wlen;
414 mcbsp_data->configured = 1;
420 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
421 * cache is initialized here
423 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
426 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
427 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
430 if (mcbsp_data->configured)
433 mcbsp_data->fmt = fmt;
434 memset(regs, 0, sizeof(*regs));
435 /* Generic McBSP register settings */
436 regs->spcr2 |= XINTM(3) | FREE;
437 regs->spcr1 |= RINTM(3);
438 /* RFIG and XFIG are not defined in 34xx */
439 if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
443 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
444 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
445 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
448 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
449 case SND_SOC_DAIFMT_I2S:
450 /* 1-bit data delay */
451 regs->rcr2 |= RDATDLY(1);
452 regs->xcr2 |= XDATDLY(1);
454 case SND_SOC_DAIFMT_LEFT_J:
455 /* 0-bit data delay */
456 regs->rcr2 |= RDATDLY(0);
457 regs->xcr2 |= XDATDLY(0);
458 regs->spcr1 |= RJUST(2);
459 /* Invert FS polarity configuration */
462 case SND_SOC_DAIFMT_DSP_A:
463 /* 1-bit data delay */
464 regs->rcr2 |= RDATDLY(1);
465 regs->xcr2 |= XDATDLY(1);
466 /* Invert FS polarity configuration */
469 case SND_SOC_DAIFMT_DSP_B:
470 /* 0-bit data delay */
471 regs->rcr2 |= RDATDLY(0);
472 regs->xcr2 |= XDATDLY(0);
473 /* Invert FS polarity configuration */
477 /* Unsupported data format */
481 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
482 case SND_SOC_DAIFMT_CBS_CFS:
483 /* McBSP master. Set FS and bit clocks as outputs */
484 regs->pcr0 |= FSXM | FSRM |
486 /* Sample rate generator drives the FS */
489 case SND_SOC_DAIFMT_CBM_CFM:
493 /* Unsupported master/slave configuration */
497 /* Set bit clock (CLKX/CLKR) and FS polarities */
498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499 case SND_SOC_DAIFMT_NB_NF:
502 * FS active low. TX data driven on falling edge of bit clock
503 * and RX data sampled on rising edge of bit clock.
505 regs->pcr0 |= FSXP | FSRP |
508 case SND_SOC_DAIFMT_NB_IF:
509 regs->pcr0 |= CLKXP | CLKRP;
511 case SND_SOC_DAIFMT_IB_NF:
512 regs->pcr0 |= FSXP | FSRP;
514 case SND_SOC_DAIFMT_IB_IF:
520 regs->pcr0 ^= FSXP | FSRP;
525 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
528 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
529 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
531 if (div_id != OMAP_MCBSP_CLKGDV)
534 mcbsp_data->clk_div = div;
535 regs->srgr1 &= ~CLKGDV(0xff);
536 regs->srgr1 |= CLKGDV(div - 1);
541 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
542 int clk_id, unsigned int freq,
545 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
546 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
549 if (mcbsp_data->active) {
550 if (freq == mcbsp_data->in_freq)
556 /* The McBSP signal muxing functions are only available on McBSP1 */
557 if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR ||
558 clk_id == OMAP_MCBSP_CLKR_SRC_CLKX ||
559 clk_id == OMAP_MCBSP_FSR_SRC_FSR ||
560 clk_id == OMAP_MCBSP_FSR_SRC_FSX)
561 if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0)
564 mcbsp_data->in_freq = freq;
565 regs->srgr2 &= ~CLKSM;
566 regs->pcr0 &= ~SCLKME;
569 case OMAP_MCBSP_SYSCLK_CLK:
570 regs->srgr2 |= CLKSM;
572 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
573 if (cpu_class_is_omap1()) {
577 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
578 MCBSP_CLKS_PRCM_SRC);
580 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
581 if (cpu_class_is_omap1()) {
585 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
589 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
590 regs->srgr2 |= CLKSM;
591 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
592 regs->pcr0 |= SCLKME;
596 case OMAP_MCBSP_CLKR_SRC_CLKR:
597 if (cpu_class_is_omap1())
599 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR);
601 case OMAP_MCBSP_CLKR_SRC_CLKX:
602 if (cpu_class_is_omap1())
604 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX);
606 case OMAP_MCBSP_FSR_SRC_FSR:
607 if (cpu_class_is_omap1())
609 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR);
611 case OMAP_MCBSP_FSR_SRC_FSX:
612 if (cpu_class_is_omap1())
614 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX);
624 * We have to be sure there is more than FIFO size worth of data ready
625 * before starting, or else we get underflow right after start.
626 * XXX: To make realtime streaming work, setting this to fifo+period
627 * as DMA uses period boundaries, there must be enough data at those.
629 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
630 struct snd_soc_dai *cpu_dai)
632 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
633 struct snd_pcm_runtime *runtime = substream->runtime;
636 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
639 size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
640 size /= substream->runtime->channels;
642 size += bytes_to_frames(runtime, snd_pcm_lib_period_bytes(substream));
644 if (runtime->start_threshold < size) {
645 runtime->start_threshold = size;
646 if (runtime->start_threshold > runtime->buffer_size)
647 runtime->start_threshold = runtime->buffer_size;
653 static struct snd_soc_dai_ops mcbsp_dai_ops = {
654 .startup = omap_mcbsp_dai_startup,
655 .shutdown = omap_mcbsp_dai_shutdown,
656 .trigger = omap_mcbsp_dai_trigger,
657 .delay = omap_mcbsp_dai_delay,
658 .hw_params = omap_mcbsp_dai_hw_params,
659 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
660 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
661 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
662 .prepare = omap_mcbsp_dai_prepare,
665 static int mcbsp_dai_probe(struct snd_soc_dai *dai)
667 mcbsp_data[dai->id].bus_id = dai->id;
668 snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id);
672 static struct snd_soc_dai_driver omap_mcbsp_dai = {
673 .probe = mcbsp_dai_probe,
677 .rates = OMAP_MCBSP_RATES,
678 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
683 .rates = OMAP_MCBSP_RATES,
684 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
686 .ops = &mcbsp_dai_ops,
689 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
690 struct snd_ctl_elem_info *uinfo)
692 struct soc_mixer_control *mc =
693 (struct soc_mixer_control *)kcontrol->private_value;
697 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
699 uinfo->value.integer.min = min;
700 uinfo->value.integer.max = max;
704 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
706 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
707 struct snd_ctl_elem_value *uc) \
709 struct soc_mixer_control *mc = \
710 (struct soc_mixer_control *)kc->private_value; \
713 int val = uc->value.integer.value[0]; \
715 if (val < min || val > max) \
718 /* OMAP McBSP implementation uses index values 0..4 */ \
719 return omap_st_set_chgain((id)-1, channel, val); \
722 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
724 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
725 struct snd_ctl_elem_value *uc) \
729 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
732 uc->value.integer.value[0] = chgain; \
736 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
737 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
738 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
739 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
740 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
741 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
742 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
743 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
745 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
746 struct snd_ctl_elem_value *ucontrol)
748 struct soc_mixer_control *mc =
749 (struct soc_mixer_control *)kcontrol->private_value;
750 u8 value = ucontrol->value.integer.value[0];
752 if (value == omap_st_is_enabled(mc->reg))
756 omap_st_enable(mc->reg);
758 omap_st_disable(mc->reg);
763 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
764 struct snd_ctl_elem_value *ucontrol)
766 struct soc_mixer_control *mc =
767 (struct soc_mixer_control *)kcontrol->private_value;
769 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
773 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
774 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
775 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
776 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
778 omap_mcbsp2_get_st_ch0_volume,
779 omap_mcbsp2_set_st_ch0_volume),
780 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
782 omap_mcbsp2_get_st_ch1_volume,
783 omap_mcbsp2_set_st_ch1_volume),
786 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
787 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
788 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
789 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
791 omap_mcbsp3_get_st_ch0_volume,
792 omap_mcbsp3_set_st_ch0_volume),
793 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
795 omap_mcbsp3_get_st_ch1_volume,
796 omap_mcbsp3_set_st_ch1_volume),
799 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
801 if (!cpu_is_omap34xx())
805 case 1: /* McBSP 2 */
806 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
807 ARRAY_SIZE(omap_mcbsp2_st_controls));
808 case 2: /* McBSP 3 */
809 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
810 ARRAY_SIZE(omap_mcbsp3_st_controls));
817 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
819 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
821 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
824 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
826 snd_soc_unregister_dai(&pdev->dev);
830 static struct platform_driver asoc_mcbsp_driver = {
832 .name = "omap-mcbsp-dai",
833 .owner = THIS_MODULE,
836 .probe = asoc_mcbsp_probe,
837 .remove = __devexit_p(asoc_mcbsp_remove),
840 static int __init snd_omap_mcbsp_init(void)
842 return platform_driver_register(&asoc_mcbsp_driver);
844 module_init(snd_omap_mcbsp_init);
846 static void __exit snd_omap_mcbsp_exit(void)
848 platform_driver_unregister(&asoc_mcbsp_driver);
850 module_exit(snd_omap_mcbsp_exit);
852 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
853 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
854 MODULE_LICENSE("GPL");