2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/module.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/asoundef.h>
38 #include <sound/initval.h>
42 /* note, two last pcis should be equal, it is not a bug */
44 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
47 MODULE_LICENSE("GPL");
48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
52 "{RME,Digi96/8 PAD}}");
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
58 module_param_array(index, int, NULL, 0444);
59 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60 module_param_array(id, charp, NULL, 0444);
61 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62 module_param_array(enable, bool, NULL, 0444);
63 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
66 * Defines for RME Digi96 series, from internal RME reference documents
70 #define RME96_SPDIF_NCHANNELS 2
72 /* Playback and capture buffer size */
73 #define RME96_BUFFER_SIZE 0x10000
76 #define RME96_IO_SIZE 0x60000
79 #define RME96_IO_PLAY_BUFFER 0x0
80 #define RME96_IO_REC_BUFFER 0x10000
81 #define RME96_IO_CONTROL_REGISTER 0x20000
82 #define RME96_IO_ADDITIONAL_REG 0x20004
83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85 #define RME96_IO_SET_PLAY_POS 0x40000
86 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
87 #define RME96_IO_SET_REC_POS 0x50000
88 #define RME96_IO_RESET_REC_POS 0x5FFFC
89 #define RME96_IO_GET_PLAY_POS 0x20000
90 #define RME96_IO_GET_REC_POS 0x30000
92 /* Write control register bits */
93 #define RME96_WCR_START (1 << 0)
94 #define RME96_WCR_START_2 (1 << 1)
95 #define RME96_WCR_GAIN_0 (1 << 2)
96 #define RME96_WCR_GAIN_1 (1 << 3)
97 #define RME96_WCR_MODE24 (1 << 4)
98 #define RME96_WCR_MODE24_2 (1 << 5)
99 #define RME96_WCR_BM (1 << 6)
100 #define RME96_WCR_BM_2 (1 << 7)
101 #define RME96_WCR_ADAT (1 << 8)
102 #define RME96_WCR_FREQ_0 (1 << 9)
103 #define RME96_WCR_FREQ_1 (1 << 10)
104 #define RME96_WCR_DS (1 << 11)
105 #define RME96_WCR_PRO (1 << 12)
106 #define RME96_WCR_EMP (1 << 13)
107 #define RME96_WCR_SEL (1 << 14)
108 #define RME96_WCR_MASTER (1 << 15)
109 #define RME96_WCR_PD (1 << 16)
110 #define RME96_WCR_INP_0 (1 << 17)
111 #define RME96_WCR_INP_1 (1 << 18)
112 #define RME96_WCR_THRU_0 (1 << 19)
113 #define RME96_WCR_THRU_1 (1 << 20)
114 #define RME96_WCR_THRU_2 (1 << 21)
115 #define RME96_WCR_THRU_3 (1 << 22)
116 #define RME96_WCR_THRU_4 (1 << 23)
117 #define RME96_WCR_THRU_5 (1 << 24)
118 #define RME96_WCR_THRU_6 (1 << 25)
119 #define RME96_WCR_THRU_7 (1 << 26)
120 #define RME96_WCR_DOLBY (1 << 27)
121 #define RME96_WCR_MONITOR_0 (1 << 28)
122 #define RME96_WCR_MONITOR_1 (1 << 29)
123 #define RME96_WCR_ISEL (1 << 30)
124 #define RME96_WCR_IDIS (1 << 31)
126 #define RME96_WCR_BITPOS_GAIN_0 2
127 #define RME96_WCR_BITPOS_GAIN_1 3
128 #define RME96_WCR_BITPOS_FREQ_0 9
129 #define RME96_WCR_BITPOS_FREQ_1 10
130 #define RME96_WCR_BITPOS_INP_0 17
131 #define RME96_WCR_BITPOS_INP_1 18
132 #define RME96_WCR_BITPOS_MONITOR_0 28
133 #define RME96_WCR_BITPOS_MONITOR_1 29
135 /* Read control register bits */
136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137 #define RME96_RCR_IRQ_2 (1 << 16)
138 #define RME96_RCR_T_OUT (1 << 17)
139 #define RME96_RCR_DEV_ID_0 (1 << 21)
140 #define RME96_RCR_DEV_ID_1 (1 << 22)
141 #define RME96_RCR_LOCK (1 << 23)
142 #define RME96_RCR_VERF (1 << 26)
143 #define RME96_RCR_F0 (1 << 27)
144 #define RME96_RCR_F1 (1 << 28)
145 #define RME96_RCR_F2 (1 << 29)
146 #define RME96_RCR_AUTOSYNC (1 << 30)
147 #define RME96_RCR_IRQ (1 << 31)
149 #define RME96_RCR_BITPOS_F0 27
150 #define RME96_RCR_BITPOS_F1 28
151 #define RME96_RCR_BITPOS_F2 29
153 /* Additional register bits */
154 #define RME96_AR_WSEL (1 << 0)
155 #define RME96_AR_ANALOG (1 << 1)
156 #define RME96_AR_FREQPAD_0 (1 << 2)
157 #define RME96_AR_FREQPAD_1 (1 << 3)
158 #define RME96_AR_FREQPAD_2 (1 << 4)
159 #define RME96_AR_PD2 (1 << 5)
160 #define RME96_AR_DAC_EN (1 << 6)
161 #define RME96_AR_CLATCH (1 << 7)
162 #define RME96_AR_CCLK (1 << 8)
163 #define RME96_AR_CDATA (1 << 9)
165 #define RME96_AR_BITPOS_F0 2
166 #define RME96_AR_BITPOS_F1 3
167 #define RME96_AR_BITPOS_F2 4
170 #define RME96_MONITOR_TRACKS_1_2 0
171 #define RME96_MONITOR_TRACKS_3_4 1
172 #define RME96_MONITOR_TRACKS_5_6 2
173 #define RME96_MONITOR_TRACKS_7_8 3
176 #define RME96_ATTENUATION_0 0
177 #define RME96_ATTENUATION_6 1
178 #define RME96_ATTENUATION_12 2
179 #define RME96_ATTENUATION_18 3
182 #define RME96_INPUT_OPTICAL 0
183 #define RME96_INPUT_COAXIAL 1
184 #define RME96_INPUT_INTERNAL 2
185 #define RME96_INPUT_XLR 3
186 #define RME96_INPUT_ANALOG 4
189 #define RME96_CLOCKMODE_SLAVE 0
190 #define RME96_CLOCKMODE_MASTER 1
191 #define RME96_CLOCKMODE_WORDCLOCK 2
193 /* Block sizes in bytes */
194 #define RME96_SMALL_BLOCK_SIZE 2048
195 #define RME96_LARGE_BLOCK_SIZE 8192
198 #define RME96_AD1852_VOL_BITS 14
199 #define RME96_AD1855_VOL_BITS 10
206 void __iomem *iobase;
208 u32 wcreg; /* cached write control register value */
209 u32 wcreg_spdif; /* S/PDIF setup */
210 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
211 u32 rcreg; /* cached read control register value */
212 u32 areg; /* cached additional register value */
213 u16 vol[2]; /* cached volume of analog output */
215 u8 rev; /* card revision number */
217 struct snd_pcm_substream *playback_substream;
218 struct snd_pcm_substream *capture_substream;
220 int playback_frlog; /* log2 of framesize */
223 size_t playback_periodsize; /* in bytes, zero if not used */
224 size_t capture_periodsize; /* in bytes, zero if not used */
226 struct snd_card *card;
227 struct snd_pcm *spdif_pcm;
228 struct snd_pcm *adat_pcm;
230 struct snd_kcontrol *spdif_ctl;
233 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
234 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
235 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
236 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
237 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
241 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
245 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
246 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
247 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
248 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
249 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
250 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
251 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
254 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
257 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
260 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
264 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
267 static snd_pcm_uframes_t
268 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
270 static snd_pcm_uframes_t
271 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
273 static void __devinit
274 snd_rme96_proc_init(struct rme96 *rme96);
277 snd_rme96_create_switches(struct snd_card *card,
278 struct rme96 *rme96);
281 snd_rme96_getinputtype(struct rme96 *rme96);
283 static inline unsigned int
284 snd_rme96_playback_ptr(struct rme96 *rme96)
286 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
287 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
290 static inline unsigned int
291 snd_rme96_capture_ptr(struct rme96 *rme96)
293 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
294 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
298 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
299 int channel, /* not used (interleaved data) */
300 snd_pcm_uframes_t pos,
301 snd_pcm_uframes_t count)
303 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
304 count <<= rme96->playback_frlog;
305 pos <<= rme96->playback_frlog;
306 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
312 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
313 int channel, /* not used (interleaved data) */
314 snd_pcm_uframes_t pos,
316 snd_pcm_uframes_t count)
318 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
319 count <<= rme96->playback_frlog;
320 pos <<= rme96->playback_frlog;
321 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
327 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
328 int channel, /* not used (interleaved data) */
329 snd_pcm_uframes_t pos,
331 snd_pcm_uframes_t count)
333 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
334 count <<= rme96->capture_frlog;
335 pos <<= rme96->capture_frlog;
336 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
342 * Digital output capabilities (S/PDIF)
344 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
346 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
347 SNDRV_PCM_INFO_MMAP_VALID |
348 SNDRV_PCM_INFO_INTERLEAVED |
349 SNDRV_PCM_INFO_PAUSE),
350 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
351 SNDRV_PCM_FMTBIT_S32_LE),
352 .rates = (SNDRV_PCM_RATE_32000 |
353 SNDRV_PCM_RATE_44100 |
354 SNDRV_PCM_RATE_48000 |
355 SNDRV_PCM_RATE_64000 |
356 SNDRV_PCM_RATE_88200 |
357 SNDRV_PCM_RATE_96000),
362 .buffer_bytes_max = RME96_BUFFER_SIZE,
363 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
364 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
365 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
366 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
371 * Digital input capabilities (S/PDIF)
373 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
375 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
376 SNDRV_PCM_INFO_MMAP_VALID |
377 SNDRV_PCM_INFO_INTERLEAVED |
378 SNDRV_PCM_INFO_PAUSE),
379 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
380 SNDRV_PCM_FMTBIT_S32_LE),
381 .rates = (SNDRV_PCM_RATE_32000 |
382 SNDRV_PCM_RATE_44100 |
383 SNDRV_PCM_RATE_48000 |
384 SNDRV_PCM_RATE_64000 |
385 SNDRV_PCM_RATE_88200 |
386 SNDRV_PCM_RATE_96000),
391 .buffer_bytes_max = RME96_BUFFER_SIZE,
392 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
393 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
394 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
395 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
400 * Digital output capabilities (ADAT)
402 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
404 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
405 SNDRV_PCM_INFO_MMAP_VALID |
406 SNDRV_PCM_INFO_INTERLEAVED |
407 SNDRV_PCM_INFO_PAUSE),
408 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
409 SNDRV_PCM_FMTBIT_S32_LE),
410 .rates = (SNDRV_PCM_RATE_44100 |
411 SNDRV_PCM_RATE_48000),
416 .buffer_bytes_max = RME96_BUFFER_SIZE,
417 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
418 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
419 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
420 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
425 * Digital input capabilities (ADAT)
427 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
429 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
430 SNDRV_PCM_INFO_MMAP_VALID |
431 SNDRV_PCM_INFO_INTERLEAVED |
432 SNDRV_PCM_INFO_PAUSE),
433 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
434 SNDRV_PCM_FMTBIT_S32_LE),
435 .rates = (SNDRV_PCM_RATE_44100 |
436 SNDRV_PCM_RATE_48000),
441 .buffer_bytes_max = RME96_BUFFER_SIZE,
442 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
443 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
444 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
445 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
450 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
451 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
452 * on the falling edge of CCLK and be stable on the rising edge. The rising
453 * edge of CLATCH after the last data bit clocks in the whole data word.
454 * A fast processor could probably drive the SPI interface faster than the
455 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
456 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
458 * NOTE: increased delay from 1 to 10, since there where problems setting
462 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
466 for (i = 0; i < 16; i++) {
468 rme96->areg |= RME96_AR_CDATA;
470 rme96->areg &= ~RME96_AR_CDATA;
472 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
473 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
475 rme96->areg |= RME96_AR_CCLK;
476 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
480 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
481 rme96->areg |= RME96_AR_CLATCH;
482 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
484 rme96->areg &= ~RME96_AR_CLATCH;
485 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
489 snd_rme96_apply_dac_volume(struct rme96 *rme96)
491 if (RME96_DAC_IS_1852(rme96)) {
492 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
493 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
494 } else if (RME96_DAC_IS_1855(rme96)) {
495 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
496 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
501 snd_rme96_reset_dac(struct rme96 *rme96)
503 writel(rme96->wcreg | RME96_WCR_PD,
504 rme96->iobase + RME96_IO_CONTROL_REGISTER);
505 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
509 snd_rme96_getmontracks(struct rme96 *rme96)
511 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
512 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
516 snd_rme96_setmontracks(struct rme96 *rme96,
520 rme96->wcreg |= RME96_WCR_MONITOR_0;
522 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
525 rme96->wcreg |= RME96_WCR_MONITOR_1;
527 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
529 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
534 snd_rme96_getattenuation(struct rme96 *rme96)
536 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
537 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
541 snd_rme96_setattenuation(struct rme96 *rme96,
544 switch (attenuation) {
546 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
550 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
554 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
558 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
564 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
569 snd_rme96_capture_getrate(struct rme96 *rme96,
575 if (rme96->areg & RME96_AR_ANALOG) {
576 /* Analog input, overrides S/PDIF setting */
577 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
578 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
592 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
595 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
596 if (rme96->rcreg & RME96_RCR_LOCK) {
599 if (rme96->rcreg & RME96_RCR_T_OUT) {
605 if (rme96->rcreg & RME96_RCR_VERF) {
610 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
611 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
612 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
616 if (rme96->rcreg & RME96_RCR_T_OUT) {
620 case 3: return 96000;
621 case 4: return 88200;
622 case 5: return 48000;
623 case 6: return 44100;
624 case 7: return 32000;
632 snd_rme96_playback_getrate(struct rme96 *rme96)
636 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
637 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
638 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
643 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
644 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
658 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
662 snd_rme96_playback_setrate(struct rme96 *rme96,
667 ds = rme96->wcreg & RME96_WCR_DS;
670 rme96->wcreg &= ~RME96_WCR_DS;
671 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
675 rme96->wcreg &= ~RME96_WCR_DS;
676 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
680 rme96->wcreg &= ~RME96_WCR_DS;
681 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
685 rme96->wcreg |= RME96_WCR_DS;
686 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
690 rme96->wcreg |= RME96_WCR_DS;
691 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
695 rme96->wcreg |= RME96_WCR_DS;
696 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
702 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
703 (ds && !(rme96->wcreg & RME96_WCR_DS)))
705 /* change to/from double-speed: reset the DAC (if available) */
706 snd_rme96_reset_dac(rme96);
707 return 1; /* need to restore volume */
709 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
715 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
720 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
721 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
724 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
725 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
728 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
729 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
732 if (rme96->rev < 4) {
735 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
736 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
739 if (rme96->rev < 4) {
742 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
743 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
746 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
747 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
752 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
757 snd_rme96_setclockmode(struct rme96 *rme96,
761 case RME96_CLOCKMODE_SLAVE:
763 rme96->wcreg &= ~RME96_WCR_MASTER;
764 rme96->areg &= ~RME96_AR_WSEL;
766 case RME96_CLOCKMODE_MASTER:
768 rme96->wcreg |= RME96_WCR_MASTER;
769 rme96->areg &= ~RME96_AR_WSEL;
771 case RME96_CLOCKMODE_WORDCLOCK:
772 /* Word clock is a master mode */
773 rme96->wcreg |= RME96_WCR_MASTER;
774 rme96->areg |= RME96_AR_WSEL;
779 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
780 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
785 snd_rme96_getclockmode(struct rme96 *rme96)
787 if (rme96->areg & RME96_AR_WSEL) {
788 return RME96_CLOCKMODE_WORDCLOCK;
790 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
791 RME96_CLOCKMODE_SLAVE;
795 snd_rme96_setinputtype(struct rme96 *rme96,
801 case RME96_INPUT_OPTICAL:
802 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
805 case RME96_INPUT_COAXIAL:
806 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
809 case RME96_INPUT_INTERNAL:
810 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
813 case RME96_INPUT_XLR:
814 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
815 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
816 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
819 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
822 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
825 case RME96_INPUT_ANALOG:
826 if (!RME96_HAS_ANALOG_IN(rme96)) {
829 rme96->areg |= RME96_AR_ANALOG;
830 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
831 if (rme96->rev < 4) {
833 * Revision less than 004 does not support 64 and
836 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
837 snd_rme96_capture_analog_setrate(rme96, 44100);
839 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
840 snd_rme96_capture_analog_setrate(rme96, 32000);
847 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
848 rme96->areg &= ~RME96_AR_ANALOG;
849 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
851 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
856 snd_rme96_getinputtype(struct rme96 *rme96)
858 if (rme96->areg & RME96_AR_ANALOG) {
859 return RME96_INPUT_ANALOG;
861 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
862 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
866 snd_rme96_setframelog(struct rme96 *rme96,
872 if (n_channels == 2) {
875 /* assume 8 channels */
879 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
880 rme96->playback_frlog = frlog;
882 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
883 rme96->capture_frlog = frlog;
888 snd_rme96_playback_setformat(struct rme96 *rme96,
892 case SNDRV_PCM_FORMAT_S16_LE:
893 rme96->wcreg &= ~RME96_WCR_MODE24;
895 case SNDRV_PCM_FORMAT_S32_LE:
896 rme96->wcreg |= RME96_WCR_MODE24;
901 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
906 snd_rme96_capture_setformat(struct rme96 *rme96,
910 case SNDRV_PCM_FORMAT_S16_LE:
911 rme96->wcreg &= ~RME96_WCR_MODE24_2;
913 case SNDRV_PCM_FORMAT_S32_LE:
914 rme96->wcreg |= RME96_WCR_MODE24_2;
919 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
924 snd_rme96_set_period_properties(struct rme96 *rme96,
927 switch (period_bytes) {
928 case RME96_LARGE_BLOCK_SIZE:
929 rme96->wcreg &= ~RME96_WCR_ISEL;
931 case RME96_SMALL_BLOCK_SIZE:
932 rme96->wcreg |= RME96_WCR_ISEL;
938 rme96->wcreg &= ~RME96_WCR_IDIS;
939 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
943 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
944 struct snd_pcm_hw_params *params)
946 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
947 struct snd_pcm_runtime *runtime = substream->runtime;
948 int err, rate, dummy;
949 bool apply_dac_volume = false;
951 runtime->dma_area = (void __force *)(rme96->iobase +
952 RME96_IO_PLAY_BUFFER);
953 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
954 runtime->dma_bytes = RME96_BUFFER_SIZE;
956 spin_lock_irq(&rme96->lock);
957 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
958 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
959 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
962 if ((int)params_rate(params) != rate) {
967 err = snd_rme96_playback_setrate(rme96, params_rate(params));
970 apply_dac_volume = err > 0; /* need to restore volume later? */
973 err = snd_rme96_playback_setformat(rme96, params_format(params));
976 snd_rme96_setframelog(rme96, params_channels(params), 1);
977 if (rme96->capture_periodsize != 0) {
978 if (params_period_size(params) << rme96->playback_frlog !=
979 rme96->capture_periodsize)
985 rme96->playback_periodsize =
986 params_period_size(params) << rme96->playback_frlog;
987 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
989 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
990 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
991 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
996 spin_unlock_irq(&rme96->lock);
997 if (apply_dac_volume) {
998 usleep_range(3000, 10000);
999 snd_rme96_apply_dac_volume(rme96);
1006 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1007 struct snd_pcm_hw_params *params)
1009 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1010 struct snd_pcm_runtime *runtime = substream->runtime;
1011 int err, isadat, rate;
1013 runtime->dma_area = (void __force *)(rme96->iobase +
1014 RME96_IO_REC_BUFFER);
1015 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1016 runtime->dma_bytes = RME96_BUFFER_SIZE;
1018 spin_lock_irq(&rme96->lock);
1019 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1020 spin_unlock_irq(&rme96->lock);
1023 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1024 if ((err = snd_rme96_capture_analog_setrate(rme96,
1025 params_rate(params))) < 0)
1027 spin_unlock_irq(&rme96->lock);
1030 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1031 if ((int)params_rate(params) != rate) {
1032 spin_unlock_irq(&rme96->lock);
1035 if ((isadat && runtime->hw.channels_min == 2) ||
1036 (!isadat && runtime->hw.channels_min == 8))
1038 spin_unlock_irq(&rme96->lock);
1042 snd_rme96_setframelog(rme96, params_channels(params), 0);
1043 if (rme96->playback_periodsize != 0) {
1044 if (params_period_size(params) << rme96->capture_frlog !=
1045 rme96->playback_periodsize)
1047 spin_unlock_irq(&rme96->lock);
1051 rme96->capture_periodsize =
1052 params_period_size(params) << rme96->capture_frlog;
1053 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1054 spin_unlock_irq(&rme96->lock);
1060 snd_rme96_playback_start(struct rme96 *rme96,
1064 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1067 rme96->wcreg |= RME96_WCR_START;
1068 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1072 snd_rme96_capture_start(struct rme96 *rme96,
1076 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1079 rme96->wcreg |= RME96_WCR_START_2;
1080 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1084 snd_rme96_playback_stop(struct rme96 *rme96)
1087 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1088 * the hardware will not stop generating interrupts
1090 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1091 if (rme96->rcreg & RME96_RCR_IRQ) {
1092 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1094 rme96->wcreg &= ~RME96_WCR_START;
1095 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1099 snd_rme96_capture_stop(struct rme96 *rme96)
1101 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1102 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1103 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1105 rme96->wcreg &= ~RME96_WCR_START_2;
1106 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1110 snd_rme96_interrupt(int irq,
1113 struct rme96 *rme96 = (struct rme96 *)dev_id;
1115 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1116 /* fastpath out, to ease interrupt sharing */
1117 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1118 (rme96->rcreg & RME96_RCR_IRQ_2)))
1123 if (rme96->rcreg & RME96_RCR_IRQ) {
1125 snd_pcm_period_elapsed(rme96->playback_substream);
1126 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1128 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1130 snd_pcm_period_elapsed(rme96->capture_substream);
1131 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1136 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1138 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1139 .count = ARRAY_SIZE(period_bytes),
1140 .list = period_bytes,
1145 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1146 struct snd_pcm_runtime *runtime)
1150 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1151 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1152 if ((size = rme96->playback_periodsize) != 0 ||
1153 (size = rme96->capture_periodsize) != 0)
1154 snd_pcm_hw_constraint_minmax(runtime,
1155 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1158 snd_pcm_hw_constraint_list(runtime, 0,
1159 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1160 &hw_constraints_period_bytes);
1164 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1167 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1168 struct snd_pcm_runtime *runtime = substream->runtime;
1170 spin_lock_irq(&rme96->lock);
1171 if (rme96->playback_substream != NULL) {
1172 spin_unlock_irq(&rme96->lock);
1175 rme96->wcreg &= ~RME96_WCR_ADAT;
1176 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1177 rme96->playback_substream = substream;
1178 spin_unlock_irq(&rme96->lock);
1180 runtime->hw = snd_rme96_playback_spdif_info;
1181 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1182 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1183 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1186 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1187 runtime->hw.rate_min = rate;
1188 runtime->hw.rate_max = rate;
1190 rme96_set_buffer_size_constraint(rme96, runtime);
1192 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1193 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1194 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1195 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1200 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1203 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1204 struct snd_pcm_runtime *runtime = substream->runtime;
1206 runtime->hw = snd_rme96_capture_spdif_info;
1207 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1208 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1213 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1214 runtime->hw.rate_min = rate;
1215 runtime->hw.rate_max = rate;
1218 spin_lock_irq(&rme96->lock);
1219 if (rme96->capture_substream != NULL) {
1220 spin_unlock_irq(&rme96->lock);
1223 rme96->capture_substream = substream;
1224 spin_unlock_irq(&rme96->lock);
1226 rme96_set_buffer_size_constraint(rme96, runtime);
1231 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1234 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1235 struct snd_pcm_runtime *runtime = substream->runtime;
1237 spin_lock_irq(&rme96->lock);
1238 if (rme96->playback_substream != NULL) {
1239 spin_unlock_irq(&rme96->lock);
1242 rme96->wcreg |= RME96_WCR_ADAT;
1243 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1244 rme96->playback_substream = substream;
1245 spin_unlock_irq(&rme96->lock);
1247 runtime->hw = snd_rme96_playback_adat_info;
1248 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1249 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1250 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1253 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1254 runtime->hw.rate_min = rate;
1255 runtime->hw.rate_max = rate;
1257 rme96_set_buffer_size_constraint(rme96, runtime);
1262 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1265 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1266 struct snd_pcm_runtime *runtime = substream->runtime;
1268 runtime->hw = snd_rme96_capture_adat_info;
1269 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1270 /* makes no sense to use analog input. Note that analog
1271 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1274 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1278 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1279 runtime->hw.rate_min = rate;
1280 runtime->hw.rate_max = rate;
1283 spin_lock_irq(&rme96->lock);
1284 if (rme96->capture_substream != NULL) {
1285 spin_unlock_irq(&rme96->lock);
1288 rme96->capture_substream = substream;
1289 spin_unlock_irq(&rme96->lock);
1291 rme96_set_buffer_size_constraint(rme96, runtime);
1296 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1298 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1301 spin_lock_irq(&rme96->lock);
1302 if (RME96_ISPLAYING(rme96)) {
1303 snd_rme96_playback_stop(rme96);
1305 rme96->playback_substream = NULL;
1306 rme96->playback_periodsize = 0;
1307 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1308 spin_unlock_irq(&rme96->lock);
1310 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1311 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1312 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1318 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1320 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1322 spin_lock_irq(&rme96->lock);
1323 if (RME96_ISRECORDING(rme96)) {
1324 snd_rme96_capture_stop(rme96);
1326 rme96->capture_substream = NULL;
1327 rme96->capture_periodsize = 0;
1328 spin_unlock_irq(&rme96->lock);
1333 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1335 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1337 spin_lock_irq(&rme96->lock);
1338 if (RME96_ISPLAYING(rme96)) {
1339 snd_rme96_playback_stop(rme96);
1341 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1342 spin_unlock_irq(&rme96->lock);
1347 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1349 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1351 spin_lock_irq(&rme96->lock);
1352 if (RME96_ISRECORDING(rme96)) {
1353 snd_rme96_capture_stop(rme96);
1355 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1356 spin_unlock_irq(&rme96->lock);
1361 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1364 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1367 case SNDRV_PCM_TRIGGER_START:
1368 if (!RME96_ISPLAYING(rme96)) {
1369 if (substream != rme96->playback_substream) {
1372 snd_rme96_playback_start(rme96, 0);
1376 case SNDRV_PCM_TRIGGER_STOP:
1377 if (RME96_ISPLAYING(rme96)) {
1378 if (substream != rme96->playback_substream) {
1381 snd_rme96_playback_stop(rme96);
1385 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1386 if (RME96_ISPLAYING(rme96)) {
1387 snd_rme96_playback_stop(rme96);
1391 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1392 if (!RME96_ISPLAYING(rme96)) {
1393 snd_rme96_playback_start(rme96, 1);
1404 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1407 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1410 case SNDRV_PCM_TRIGGER_START:
1411 if (!RME96_ISRECORDING(rme96)) {
1412 if (substream != rme96->capture_substream) {
1415 snd_rme96_capture_start(rme96, 0);
1419 case SNDRV_PCM_TRIGGER_STOP:
1420 if (RME96_ISRECORDING(rme96)) {
1421 if (substream != rme96->capture_substream) {
1424 snd_rme96_capture_stop(rme96);
1428 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1429 if (RME96_ISRECORDING(rme96)) {
1430 snd_rme96_capture_stop(rme96);
1434 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1435 if (!RME96_ISRECORDING(rme96)) {
1436 snd_rme96_capture_start(rme96, 1);
1447 static snd_pcm_uframes_t
1448 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1450 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1451 return snd_rme96_playback_ptr(rme96);
1454 static snd_pcm_uframes_t
1455 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1457 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1458 return snd_rme96_capture_ptr(rme96);
1461 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1462 .open = snd_rme96_playback_spdif_open,
1463 .close = snd_rme96_playback_close,
1464 .ioctl = snd_pcm_lib_ioctl,
1465 .hw_params = snd_rme96_playback_hw_params,
1466 .prepare = snd_rme96_playback_prepare,
1467 .trigger = snd_rme96_playback_trigger,
1468 .pointer = snd_rme96_playback_pointer,
1469 .copy = snd_rme96_playback_copy,
1470 .silence = snd_rme96_playback_silence,
1471 .mmap = snd_pcm_lib_mmap_iomem,
1474 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1475 .open = snd_rme96_capture_spdif_open,
1476 .close = snd_rme96_capture_close,
1477 .ioctl = snd_pcm_lib_ioctl,
1478 .hw_params = snd_rme96_capture_hw_params,
1479 .prepare = snd_rme96_capture_prepare,
1480 .trigger = snd_rme96_capture_trigger,
1481 .pointer = snd_rme96_capture_pointer,
1482 .copy = snd_rme96_capture_copy,
1483 .mmap = snd_pcm_lib_mmap_iomem,
1486 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1487 .open = snd_rme96_playback_adat_open,
1488 .close = snd_rme96_playback_close,
1489 .ioctl = snd_pcm_lib_ioctl,
1490 .hw_params = snd_rme96_playback_hw_params,
1491 .prepare = snd_rme96_playback_prepare,
1492 .trigger = snd_rme96_playback_trigger,
1493 .pointer = snd_rme96_playback_pointer,
1494 .copy = snd_rme96_playback_copy,
1495 .silence = snd_rme96_playback_silence,
1496 .mmap = snd_pcm_lib_mmap_iomem,
1499 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1500 .open = snd_rme96_capture_adat_open,
1501 .close = snd_rme96_capture_close,
1502 .ioctl = snd_pcm_lib_ioctl,
1503 .hw_params = snd_rme96_capture_hw_params,
1504 .prepare = snd_rme96_capture_prepare,
1505 .trigger = snd_rme96_capture_trigger,
1506 .pointer = snd_rme96_capture_pointer,
1507 .copy = snd_rme96_capture_copy,
1508 .mmap = snd_pcm_lib_mmap_iomem,
1512 snd_rme96_free(void *private_data)
1514 struct rme96 *rme96 = (struct rme96 *)private_data;
1516 if (rme96 == NULL) {
1519 if (rme96->irq >= 0) {
1520 snd_rme96_playback_stop(rme96);
1521 snd_rme96_capture_stop(rme96);
1522 rme96->areg &= ~RME96_AR_DAC_EN;
1523 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1524 free_irq(rme96->irq, (void *)rme96);
1527 if (rme96->iobase) {
1528 iounmap(rme96->iobase);
1529 rme96->iobase = NULL;
1532 pci_release_regions(rme96->pci);
1535 pci_disable_device(rme96->pci);
1539 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1541 struct rme96 *rme96 = pcm->private_data;
1542 rme96->spdif_pcm = NULL;
1546 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1548 struct rme96 *rme96 = pcm->private_data;
1549 rme96->adat_pcm = NULL;
1552 static int __devinit
1553 snd_rme96_create(struct rme96 *rme96)
1555 struct pci_dev *pci = rme96->pci;
1559 spin_lock_init(&rme96->lock);
1561 if ((err = pci_enable_device(pci)) < 0)
1564 if ((err = pci_request_regions(pci, "RME96")) < 0)
1566 rme96->port = pci_resource_start(rme96->pci, 0);
1568 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1569 if (!rme96->iobase) {
1570 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1574 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1575 KBUILD_MODNAME, rme96)) {
1576 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1579 rme96->irq = pci->irq;
1581 /* read the card's revision number */
1582 pci_read_config_byte(pci, 8, &rme96->rev);
1584 /* set up ALSA pcm device for S/PDIF */
1585 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1586 1, 1, &rme96->spdif_pcm)) < 0)
1590 rme96->spdif_pcm->private_data = rme96;
1591 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1592 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1593 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1594 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1596 rme96->spdif_pcm->info_flags = 0;
1598 /* set up ALSA pcm device for ADAT */
1599 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1600 /* ADAT is not available on the base model */
1601 rme96->adat_pcm = NULL;
1603 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1604 1, 1, &rme96->adat_pcm)) < 0)
1608 rme96->adat_pcm->private_data = rme96;
1609 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1610 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1611 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1612 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1614 rme96->adat_pcm->info_flags = 0;
1617 rme96->playback_periodsize = 0;
1618 rme96->capture_periodsize = 0;
1620 /* make sure playback/capture is stopped, if by some reason active */
1621 snd_rme96_playback_stop(rme96);
1622 snd_rme96_capture_stop(rme96);
1624 /* set default values in registers */
1626 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1627 RME96_WCR_SEL | /* normal playback */
1628 RME96_WCR_MASTER | /* set to master clock mode */
1629 RME96_WCR_INP_0; /* set coaxial input */
1631 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1633 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1634 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1637 writel(rme96->areg | RME96_AR_PD2,
1638 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1639 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1641 /* reset and enable the DAC (order is important). */
1642 snd_rme96_reset_dac(rme96);
1643 rme96->areg |= RME96_AR_DAC_EN;
1644 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1646 /* reset playback and record buffer pointers */
1647 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1648 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1651 rme96->vol[0] = rme96->vol[1] = 0;
1652 if (RME96_HAS_ANALOG_OUT(rme96)) {
1653 snd_rme96_apply_dac_volume(rme96);
1656 /* init switch interface */
1657 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1661 /* init proc interface */
1662 snd_rme96_proc_init(rme96);
1672 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1675 struct rme96 *rme96 = entry->private_data;
1677 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1679 snd_iprintf(buffer, rme96->card->longname);
1680 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1682 snd_iprintf(buffer, "\nGeneral settings\n");
1683 if (rme96->wcreg & RME96_WCR_IDIS) {
1684 snd_iprintf(buffer, " period size: N/A (interrupts "
1686 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1687 snd_iprintf(buffer, " period size: 2048 bytes\n");
1689 snd_iprintf(buffer, " period size: 8192 bytes\n");
1691 snd_iprintf(buffer, "\nInput settings\n");
1692 switch (snd_rme96_getinputtype(rme96)) {
1693 case RME96_INPUT_OPTICAL:
1694 snd_iprintf(buffer, " input: optical");
1696 case RME96_INPUT_COAXIAL:
1697 snd_iprintf(buffer, " input: coaxial");
1699 case RME96_INPUT_INTERNAL:
1700 snd_iprintf(buffer, " input: internal");
1702 case RME96_INPUT_XLR:
1703 snd_iprintf(buffer, " input: XLR");
1705 case RME96_INPUT_ANALOG:
1706 snd_iprintf(buffer, " input: analog");
1709 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1710 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1713 snd_iprintf(buffer, " (8 channels)\n");
1715 snd_iprintf(buffer, " (2 channels)\n");
1717 snd_iprintf(buffer, " sample rate: %d Hz\n",
1718 snd_rme96_capture_getrate(rme96, &n));
1720 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1721 snd_iprintf(buffer, " sample format: 24 bit\n");
1723 snd_iprintf(buffer, " sample format: 16 bit\n");
1726 snd_iprintf(buffer, "\nOutput settings\n");
1727 if (rme96->wcreg & RME96_WCR_SEL) {
1728 snd_iprintf(buffer, " output signal: normal playback\n");
1730 snd_iprintf(buffer, " output signal: same as input\n");
1732 snd_iprintf(buffer, " sample rate: %d Hz\n",
1733 snd_rme96_playback_getrate(rme96));
1734 if (rme96->wcreg & RME96_WCR_MODE24) {
1735 snd_iprintf(buffer, " sample format: 24 bit\n");
1737 snd_iprintf(buffer, " sample format: 16 bit\n");
1739 if (rme96->areg & RME96_AR_WSEL) {
1740 snd_iprintf(buffer, " sample clock source: word clock\n");
1741 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1742 snd_iprintf(buffer, " sample clock source: internal\n");
1743 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1744 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1745 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1746 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1748 snd_iprintf(buffer, " sample clock source: autosync\n");
1750 if (rme96->wcreg & RME96_WCR_PRO) {
1751 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1753 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1755 if (rme96->wcreg & RME96_WCR_EMP) {
1756 snd_iprintf(buffer, " emphasis: on\n");
1758 snd_iprintf(buffer, " emphasis: off\n");
1760 if (rme96->wcreg & RME96_WCR_DOLBY) {
1761 snd_iprintf(buffer, " non-audio (dolby): on\n");
1763 snd_iprintf(buffer, " non-audio (dolby): off\n");
1765 if (RME96_HAS_ANALOG_IN(rme96)) {
1766 snd_iprintf(buffer, "\nAnalog output settings\n");
1767 switch (snd_rme96_getmontracks(rme96)) {
1768 case RME96_MONITOR_TRACKS_1_2:
1769 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1771 case RME96_MONITOR_TRACKS_3_4:
1772 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1774 case RME96_MONITOR_TRACKS_5_6:
1775 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1777 case RME96_MONITOR_TRACKS_7_8:
1778 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1781 switch (snd_rme96_getattenuation(rme96)) {
1782 case RME96_ATTENUATION_0:
1783 snd_iprintf(buffer, " attenuation: 0 dB\n");
1785 case RME96_ATTENUATION_6:
1786 snd_iprintf(buffer, " attenuation: -6 dB\n");
1788 case RME96_ATTENUATION_12:
1789 snd_iprintf(buffer, " attenuation: -12 dB\n");
1791 case RME96_ATTENUATION_18:
1792 snd_iprintf(buffer, " attenuation: -18 dB\n");
1795 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1796 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1800 static void __devinit
1801 snd_rme96_proc_init(struct rme96 *rme96)
1803 struct snd_info_entry *entry;
1805 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1806 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1813 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1816 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1818 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1820 spin_lock_irq(&rme96->lock);
1821 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1822 spin_unlock_irq(&rme96->lock);
1826 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1828 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1832 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1833 spin_lock_irq(&rme96->lock);
1834 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1835 change = val != rme96->wcreg;
1837 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1838 spin_unlock_irq(&rme96->lock);
1843 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1845 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1846 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1847 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1849 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1851 switch (rme96->pci->device) {
1852 case PCI_DEVICE_ID_RME_DIGI96:
1853 case PCI_DEVICE_ID_RME_DIGI96_8:
1854 uinfo->value.enumerated.items = 3;
1856 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1857 uinfo->value.enumerated.items = 4;
1859 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1860 if (rme96->rev > 4) {
1862 uinfo->value.enumerated.items = 4;
1863 texts[3] = _texts[4]; /* Analog instead of XLR */
1866 uinfo->value.enumerated.items = 5;
1873 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1874 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1876 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1880 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1882 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1883 unsigned int items = 3;
1885 spin_lock_irq(&rme96->lock);
1886 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1888 switch (rme96->pci->device) {
1889 case PCI_DEVICE_ID_RME_DIGI96:
1890 case PCI_DEVICE_ID_RME_DIGI96_8:
1893 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1896 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1897 if (rme96->rev > 4) {
1898 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1899 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1900 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1911 if (ucontrol->value.enumerated.item[0] >= items) {
1912 ucontrol->value.enumerated.item[0] = items - 1;
1915 spin_unlock_irq(&rme96->lock);
1919 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1921 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1923 int change, items = 3;
1925 switch (rme96->pci->device) {
1926 case PCI_DEVICE_ID_RME_DIGI96:
1927 case PCI_DEVICE_ID_RME_DIGI96_8:
1930 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1933 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1934 if (rme96->rev > 4) {
1944 val = ucontrol->value.enumerated.item[0] % items;
1946 /* special case for PST */
1947 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1948 if (val == RME96_INPUT_XLR) {
1949 val = RME96_INPUT_ANALOG;
1953 spin_lock_irq(&rme96->lock);
1954 change = (int)val != snd_rme96_getinputtype(rme96);
1955 snd_rme96_setinputtype(rme96, val);
1956 spin_unlock_irq(&rme96->lock);
1961 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1963 static char *texts[3] = { "AutoSync", "Internal", "Word" };
1965 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1967 uinfo->value.enumerated.items = 3;
1968 if (uinfo->value.enumerated.item > 2) {
1969 uinfo->value.enumerated.item = 2;
1971 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1975 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1977 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1979 spin_lock_irq(&rme96->lock);
1980 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1981 spin_unlock_irq(&rme96->lock);
1985 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1987 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1991 val = ucontrol->value.enumerated.item[0] % 3;
1992 spin_lock_irq(&rme96->lock);
1993 change = (int)val != snd_rme96_getclockmode(rme96);
1994 snd_rme96_setclockmode(rme96, val);
1995 spin_unlock_irq(&rme96->lock);
2000 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2002 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2004 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2006 uinfo->value.enumerated.items = 4;
2007 if (uinfo->value.enumerated.item > 3) {
2008 uinfo->value.enumerated.item = 3;
2010 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2014 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2016 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2018 spin_lock_irq(&rme96->lock);
2019 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2020 spin_unlock_irq(&rme96->lock);
2024 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2026 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2030 val = ucontrol->value.enumerated.item[0] % 4;
2031 spin_lock_irq(&rme96->lock);
2033 change = (int)val != snd_rme96_getattenuation(rme96);
2034 snd_rme96_setattenuation(rme96, val);
2035 spin_unlock_irq(&rme96->lock);
2040 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2042 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2044 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2046 uinfo->value.enumerated.items = 4;
2047 if (uinfo->value.enumerated.item > 3) {
2048 uinfo->value.enumerated.item = 3;
2050 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2054 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2056 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2058 spin_lock_irq(&rme96->lock);
2059 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2060 spin_unlock_irq(&rme96->lock);
2064 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2066 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2070 val = ucontrol->value.enumerated.item[0] % 4;
2071 spin_lock_irq(&rme96->lock);
2072 change = (int)val != snd_rme96_getmontracks(rme96);
2073 snd_rme96_setmontracks(rme96, val);
2074 spin_unlock_irq(&rme96->lock);
2078 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2081 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2082 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2083 if (val & RME96_WCR_PRO)
2084 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2086 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2090 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2092 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2093 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2094 if (val & RME96_WCR_PRO)
2095 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2097 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2100 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2102 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2107 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2109 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2111 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2115 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2117 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2121 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2122 spin_lock_irq(&rme96->lock);
2123 change = val != rme96->wcreg_spdif;
2124 rme96->wcreg_spdif = val;
2125 spin_unlock_irq(&rme96->lock);
2129 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2131 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2136 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2138 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2140 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2144 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2146 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2150 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2151 spin_lock_irq(&rme96->lock);
2152 change = val != rme96->wcreg_spdif_stream;
2153 rme96->wcreg_spdif_stream = val;
2154 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2155 rme96->wcreg |= val;
2156 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2157 spin_unlock_irq(&rme96->lock);
2161 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2163 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2168 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2170 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2175 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2177 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2179 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2181 uinfo->value.integer.min = 0;
2182 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2187 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2189 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2191 spin_lock_irq(&rme96->lock);
2192 u->value.integer.value[0] = rme96->vol[0];
2193 u->value.integer.value[1] = rme96->vol[1];
2194 spin_unlock_irq(&rme96->lock);
2200 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2202 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2204 unsigned int vol, maxvol;
2207 if (!RME96_HAS_ANALOG_OUT(rme96))
2209 maxvol = RME96_185X_MAX_OUT(rme96);
2210 spin_lock_irq(&rme96->lock);
2211 vol = u->value.integer.value[0];
2212 if (vol != rme96->vol[0] && vol <= maxvol) {
2213 rme96->vol[0] = vol;
2216 vol = u->value.integer.value[1];
2217 if (vol != rme96->vol[1] && vol <= maxvol) {
2218 rme96->vol[1] = vol;
2222 snd_rme96_apply_dac_volume(rme96);
2223 spin_unlock_irq(&rme96->lock);
2228 static struct snd_kcontrol_new snd_rme96_controls[] = {
2230 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2231 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2232 .info = snd_rme96_control_spdif_info,
2233 .get = snd_rme96_control_spdif_get,
2234 .put = snd_rme96_control_spdif_put
2237 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2238 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2239 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2240 .info = snd_rme96_control_spdif_stream_info,
2241 .get = snd_rme96_control_spdif_stream_get,
2242 .put = snd_rme96_control_spdif_stream_put
2245 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2246 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2247 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2248 .info = snd_rme96_control_spdif_mask_info,
2249 .get = snd_rme96_control_spdif_mask_get,
2250 .private_value = IEC958_AES0_NONAUDIO |
2251 IEC958_AES0_PROFESSIONAL |
2252 IEC958_AES0_CON_EMPHASIS
2255 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2256 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2257 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2258 .info = snd_rme96_control_spdif_mask_info,
2259 .get = snd_rme96_control_spdif_mask_get,
2260 .private_value = IEC958_AES0_NONAUDIO |
2261 IEC958_AES0_PROFESSIONAL |
2262 IEC958_AES0_PRO_EMPHASIS
2265 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2266 .name = "Input Connector",
2267 .info = snd_rme96_info_inputtype_control,
2268 .get = snd_rme96_get_inputtype_control,
2269 .put = snd_rme96_put_inputtype_control
2272 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2273 .name = "Loopback Input",
2274 .info = snd_rme96_info_loopback_control,
2275 .get = snd_rme96_get_loopback_control,
2276 .put = snd_rme96_put_loopback_control
2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2280 .name = "Sample Clock Source",
2281 .info = snd_rme96_info_clockmode_control,
2282 .get = snd_rme96_get_clockmode_control,
2283 .put = snd_rme96_put_clockmode_control
2286 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2287 .name = "Monitor Tracks",
2288 .info = snd_rme96_info_montracks_control,
2289 .get = snd_rme96_get_montracks_control,
2290 .put = snd_rme96_put_montracks_control
2293 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2294 .name = "Attenuation",
2295 .info = snd_rme96_info_attenuation_control,
2296 .get = snd_rme96_get_attenuation_control,
2297 .put = snd_rme96_put_attenuation_control
2300 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2301 .name = "DAC Playback Volume",
2302 .info = snd_rme96_dac_volume_info,
2303 .get = snd_rme96_dac_volume_get,
2304 .put = snd_rme96_dac_volume_put
2309 snd_rme96_create_switches(struct snd_card *card,
2310 struct rme96 *rme96)
2313 struct snd_kcontrol *kctl;
2315 for (idx = 0; idx < 7; idx++) {
2316 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2318 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2319 rme96->spdif_ctl = kctl;
2322 if (RME96_HAS_ANALOG_OUT(rme96)) {
2323 for (idx = 7; idx < 10; idx++)
2324 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2332 * Card initialisation
2335 static void snd_rme96_card_free(struct snd_card *card)
2337 snd_rme96_free(card->private_data);
2340 static int __devinit
2341 snd_rme96_probe(struct pci_dev *pci,
2342 const struct pci_device_id *pci_id)
2345 struct rme96 *rme96;
2346 struct snd_card *card;
2350 if (dev >= SNDRV_CARDS) {
2357 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2358 sizeof(struct rme96), &card);
2361 card->private_free = snd_rme96_card_free;
2362 rme96 = card->private_data;
2365 snd_card_set_dev(card, &pci->dev);
2366 if ((err = snd_rme96_create(rme96)) < 0) {
2367 snd_card_free(card);
2371 strcpy(card->driver, "Digi96");
2372 switch (rme96->pci->device) {
2373 case PCI_DEVICE_ID_RME_DIGI96:
2374 strcpy(card->shortname, "RME Digi96");
2376 case PCI_DEVICE_ID_RME_DIGI96_8:
2377 strcpy(card->shortname, "RME Digi96/8");
2379 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2380 strcpy(card->shortname, "RME Digi96/8 PRO");
2382 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2383 pci_read_config_byte(rme96->pci, 8, &val);
2385 strcpy(card->shortname, "RME Digi96/8 PAD");
2387 strcpy(card->shortname, "RME Digi96/8 PST");
2391 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2392 rme96->port, rme96->irq);
2394 if ((err = snd_card_register(card)) < 0) {
2395 snd_card_free(card);
2398 pci_set_drvdata(pci, card);
2403 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2405 snd_card_free(pci_get_drvdata(pci));
2406 pci_set_drvdata(pci, NULL);
2409 static struct pci_driver driver = {
2410 .name = KBUILD_MODNAME,
2411 .id_table = snd_rme96_ids,
2412 .probe = snd_rme96_probe,
2413 .remove = __devexit_p(snd_rme96_remove),
2416 static int __init alsa_card_rme96_init(void)
2418 return pci_register_driver(&driver);
2421 static void __exit alsa_card_rme96_exit(void)
2423 pci_unregister_driver(&driver);
2426 module_init(alsa_card_rme96_init)
2427 module_exit(alsa_card_rme96_exit)