sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53
  54 #ifdef CONFIG_X86
  55 /* for snoop control */
  56 #include <asm/pgtable.h>
  57 #include <asm/cacheflush.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <linux/vgaarb.h>
  62 #include <linux/vga_switcheroo.h>
  63 #include <linux/firmware.h>
  64 #include "hda_codec.h"
  65
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  70 static char *model[SNDRV_CARDS];
  71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  74 static int probe_only[SNDRV_CARDS];
  75 static int jackpoll_ms[SNDRV_CARDS];
  76 static bool single_cmd;
  77 static int enable_msi = -1;
  78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  79 static char *patch[SNDRV_CARDS];
  80 #endif
  81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  84 #endif
  85
  86 module_param_array(index, int, NULL, 0444);
  87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  88 module_param_array(id, charp, NULL, 0444);
  89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  90 module_param_array(enable, bool, NULL, 0444);
  91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  92 module_param_array(model, charp, NULL, 0444);
  93 MODULE_PARM_DESC(model, "Use the given board model.");
  94 module_param_array(position_fix, int, NULL, 0444);
  95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  97 module_param_array(bdl_pos_adj, int, NULL, 0644);
  98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  99 module_param_array(probe_mask, int, NULL, 0444);
 100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 101 module_param_array(probe_only, int, NULL, 0444);
 102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 103 module_param_array(jackpoll_ms, int, NULL, 0444);
 104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 105 module_param(single_cmd, bool, 0444);
 106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 107                  "(for debugging only).");
 108 module_param(enable_msi, bint, 0444);
 109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 111 module_param_array(patch, charp, NULL, 0444);
 112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 113 #endif
 114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 115 module_param_array(beep_mode, bool, NULL, 0444);
 116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 117                             "(0=off, 1=on) (default=1).");
 118 #endif
 119
 120 #ifdef CONFIG_PM
 121 static int param_set_xint(const char *val, const struct kernel_param *kp);
 122 static struct kernel_param_ops param_ops_xint = {
 123         .set = param_set_xint,
 124         .get = param_get_int,
 125 };
 126 #define param_check_xint param_check_int
 127
 128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 129 module_param(power_save, xint, 0644);
 130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 131                  "(in second, 0 = disable).");
 132
 133 /* reset the HD-audio controller in power save mode.
 134  * this may give more power-saving, but will take longer time to
 135  * wake up.
 136  */
 137 static bool power_save_controller = 1;
 138 module_param(power_save_controller, bool, 0644);
 139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 140 #endif /* CONFIG_PM */
 141
 142 static int align_buffer_size = -1;
 143 module_param(align_buffer_size, bint, 0644);
 144 MODULE_PARM_DESC(align_buffer_size,
 145                 "Force buffer and period sizes to be multiple of 128 bytes.");
 146
 147 #ifdef CONFIG_X86
 148 static bool hda_snoop = true;
 149 module_param_named(snoop, hda_snoop, bool, 0444);
 150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 151 #define azx_snoop(chip)         (chip)->snoop
 152 #else
 153 #define hda_snoop               true
 154 #define azx_snoop(chip)         true
 155 #endif
 156
 157
 158 MODULE_LICENSE("GPL");
 159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 160                          "{Intel, ICH6M},"
 161                          "{Intel, ICH7},"
 162                          "{Intel, ESB2},"
 163                          "{Intel, ICH8},"
 164                          "{Intel, ICH9},"
 165                          "{Intel, ICH10},"
 166                          "{Intel, PCH},"
 167                          "{Intel, CPT},"
 168                          "{Intel, PPT},"
 169                          "{Intel, LPT},"
 170                          "{Intel, LPT_LP},"
 171                          "{Intel, HPT},"
 172                          "{Intel, PBG},"
 173                          "{Intel, SCH},"
 174                          "{ATI, SB450},"
 175                          "{ATI, SB600},"
 176                          "{ATI, RS600},"
 177                          "{ATI, RS690},"
 178                          "{ATI, RS780},"
 179                          "{ATI, R600},"
 180                          "{ATI, RV630},"
 181                          "{ATI, RV610},"
 182                          "{ATI, RV670},"
 183                          "{ATI, RV635},"
 184                          "{ATI, RV620},"
 185                          "{ATI, RV770},"
 186                          "{VIA, VT8251},"
 187                          "{VIA, VT8237A},"
 188                          "{SiS, SIS966},"
 189                          "{ULI, M5461}}");
 190 MODULE_DESCRIPTION("Intel HDA driver");
 191
 192 #ifdef CONFIG_SND_VERBOSE_PRINTK
 193 #define SFX     /* nop */
 194 #else
 195 #define SFX     "hda-intel "
 196 #endif
 197
 198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 200 #define SUPPORT_VGA_SWITCHEROO
 201 #endif
 202 #endif
 203
 204
 205 /*
 206  * registers
 207  */
 208 #define ICH6_REG_GCAP                   0x00
 209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 214 #define ICH6_REG_VMIN                   0x02
 215 #define ICH6_REG_VMAJ                   0x03
 216 #define ICH6_REG_OUTPAY                 0x04
 217 #define ICH6_REG_INPAY                  0x06
 218 #define ICH6_REG_GCTL                   0x08
 219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 222 #define ICH6_REG_WAKEEN                 0x0c
 223 #define ICH6_REG_STATESTS               0x0e
 224 #define ICH6_REG_GSTS                   0x10
 225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 226 #define ICH6_REG_INTCTL                 0x20
 227 #define ICH6_REG_INTSTS                 0x24
 228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 230 #define ICH6_REG_SSYNC                  0x38
 231 #define ICH6_REG_CORBLBASE              0x40
 232 #define ICH6_REG_CORBUBASE              0x44
 233 #define ICH6_REG_CORBWP                 0x48
 234 #define ICH6_REG_CORBRP                 0x4a
 235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 236 #define ICH6_REG_CORBCTL                0x4c
 237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 239 #define ICH6_REG_CORBSTS                0x4d
 240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 241 #define ICH6_REG_CORBSIZE               0x4e
 242
 243 #define ICH6_REG_RIRBLBASE              0x50
 244 #define ICH6_REG_RIRBUBASE              0x54
 245 #define ICH6_REG_RIRBWP                 0x58
 246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 247 #define ICH6_REG_RINTCNT                0x5a
 248 #define ICH6_REG_RIRBCTL                0x5c
 249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 252 #define ICH6_REG_RIRBSTS                0x5d
 253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 255 #define ICH6_REG_RIRBSIZE               0x5e
 256
 257 #define ICH6_REG_IC                     0x60
 258 #define ICH6_REG_IR                     0x64
 259 #define ICH6_REG_IRS                    0x68
 260 #define   ICH6_IRS_VALID        (1<<1)
 261 #define   ICH6_IRS_BUSY         (1<<0)
 262
 263 #define ICH6_REG_DPLBASE                0x70
 264 #define ICH6_REG_DPUBASE                0x74
 265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 266
 267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 269
 270 /* stream register offsets from stream base */
 271 #define ICH6_REG_SD_CTL                 0x00
 272 #define ICH6_REG_SD_STS                 0x03
 273 #define ICH6_REG_SD_LPIB                0x04
 274 #define ICH6_REG_SD_CBL                 0x08
 275 #define ICH6_REG_SD_LVI                 0x0c
 276 #define ICH6_REG_SD_FIFOW               0x0e
 277 #define ICH6_REG_SD_FIFOSIZE            0x10
 278 #define ICH6_REG_SD_FORMAT              0x12
 279 #define ICH6_REG_SD_BDLPL               0x18
 280 #define ICH6_REG_SD_BDLPU               0x1c
 281
 282 /* PCI space */
 283 #define ICH6_PCIREG_TCSEL       0x44
 284
 285 /*
 286  * other constants
 287  */
 288
 289 /* max number of SDs */
 290 /* ICH, ATI and VIA have 4 playback and 4 capture */
 291 #define ICH6_NUM_CAPTURE        4
 292 #define ICH6_NUM_PLAYBACK       4
 293
 294 /* ULI has 6 playback and 5 capture */
 295 #define ULI_NUM_CAPTURE         5
 296 #define ULI_NUM_PLAYBACK        6
 297
 298 /* ATI HDMI has 1 playback and 0 capture */
 299 #define ATIHDMI_NUM_CAPTURE     0
 300 #define ATIHDMI_NUM_PLAYBACK    1
 301
 302 /* TERA has 4 playback and 3 capture */
 303 #define TERA_NUM_CAPTURE        3
 304 #define TERA_NUM_PLAYBACK       4
 305
 306 /* this number is statically defined for simplicity */
 307 #define MAX_AZX_DEV             16
 308
 309 /* max number of fragments - we may use more if allocating more pages for BDL */
 310 #define BDL_SIZE                4096
 311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 312 #define AZX_MAX_FRAG            32
 313 /* max buffer size - no h/w limit, you can increase as you like */
 314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 315
 316 /* RIRB int mask: overrun[2], response[0] */
 317 #define RIRB_INT_RESPONSE       0x01
 318 #define RIRB_INT_OVERRUN        0x04
 319 #define RIRB_INT_MASK           0x05
 320
 321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 322 #define AZX_MAX_CODECS          8
 323 #define AZX_DEFAULT_CODECS      4
 324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 325
 326 /* SD_CTL bits */
 327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 333 #define SD_CTL_STREAM_TAG_SHIFT 20
 334
 335 /* SD_CTL and SD_STS */
 336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 340                                  SD_INT_COMPLETE)
 341
 342 /* SD_STS */
 343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 344
 345 /* INTCTL and INTSTS */
 346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 349
 350 /* below are so far hardcoded - should read registers in future */
 351 #define ICH6_MAX_CORB_ENTRIES   256
 352 #define ICH6_MAX_RIRB_ENTRIES   256
 353
 354 /* position fix mode */
 355 enum {
 356         POS_FIX_AUTO,
 357         POS_FIX_LPIB,
 358         POS_FIX_POSBUF,
 359         POS_FIX_VIACOMBO,
 360         POS_FIX_COMBO,
 361 };
 362
 363 /* Defines for ATI HD Audio support in SB450 south bridge */
 364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 366
 367 /* Defines for Nvidia HDA support */
 368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 370 #define NVIDIA_HDA_ISTRM_COH          0x4d
 371 #define NVIDIA_HDA_OSTRM_COH          0x4c
 372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 373
 374 /* Defines for Intel SCH HDA snoop control */
 375 #define INTEL_SCH_HDA_DEVC      0x78
 376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 377
 378 /* Define IN stream 0 FIFO size offset in VIA controller */
 379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 380 /* Define VIA HD Audio Device ID*/
 381 #define VIA_HDAC_DEVICE_ID              0x3288
 382
 383 /* HD Audio class code */
 384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 385
 386 /*
 387  */
 388
 389 struct azx_dev {
 390         struct snd_dma_buffer bdl; /* BDL buffer */
 391         u32 *posbuf;            /* position buffer pointer */
 392
 393         unsigned int bufsize;   /* size of the play buffer in bytes */
 394         unsigned int period_bytes; /* size of the period in bytes */
 395         unsigned int frags;     /* number for period in the play buffer */
 396         unsigned int fifo_size; /* FIFO size */
 397         unsigned long start_wallclk;    /* start + minimum wallclk */
 398         unsigned long period_wallclk;   /* wallclk for period */
 399
 400         void __iomem *sd_addr;  /* stream descriptor pointer */
 401
 402         u32 sd_int_sta_mask;    /* stream int status mask */
 403
 404         /* pcm support */
 405         struct snd_pcm_substream *substream;    /* assigned substream,
 406                                                  * set in PCM open
 407                                                  */
 408         unsigned int format_val;        /* format value to be set in the
 409                                          * controller and the codec
 410                                          */
 411         unsigned char stream_tag;       /* assigned stream */
 412         unsigned char index;            /* stream index */
 413         int assigned_key;               /* last device# key assigned to */
 414
 415         unsigned int opened :1;
 416         unsigned int running :1;
 417         unsigned int irq_pending :1;
 418         unsigned int prepared:1;
 419         unsigned int locked:1;
 420         /*
 421          * For VIA:
 422          *  A flag to ensure DMA position is 0
 423          *  when link position is not greater than FIFO size
 424          */
 425         unsigned int insufficient :1;
 426         unsigned int wc_marked:1;
 427         unsigned int no_period_wakeup:1;
 428
 429         struct timecounter  azx_tc;
 430         struct cyclecounter azx_cc;
 431
 432 #ifdef CONFIG_SND_HDA_DSP_LOADER
 433         struct mutex dsp_mutex;
 434 #endif
 435 };
 436
 437 /* DSP lock helpers */
 438 #ifdef CONFIG_SND_HDA_DSP_LOADER
 439 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
 440 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
 441 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
 442 #define dsp_is_locked(dev)      ((dev)->locked)
 443 #else
 444 #define dsp_lock_init(dev)      do {} while (0)
 445 #define dsp_lock(dev)           do {} while (0)
 446 #define dsp_unlock(dev)         do {} while (0)
 447 #define dsp_is_locked(dev)      0
 448 #endif
 449
 450 /* CORB/RIRB */
 451 struct azx_rb {
 452         u32 *buf;               /* CORB/RIRB buffer
 453                                  * Each CORB entry is 4byte, RIRB is 8byte
 454                                  */
 455         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 456         /* for RIRB */
 457         unsigned short rp, wp;  /* read/write pointers */
 458         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 459         u32 res[AZX_MAX_CODECS];        /* last read value */
 460 };
 461
 462 struct azx_pcm {
 463         struct azx *chip;
 464         struct snd_pcm *pcm;
 465         struct hda_codec *codec;
 466         struct hda_pcm_stream *hinfo[2];
 467         struct list_head list;
 468 };
 469
 470 struct azx {
 471         struct snd_card *card;
 472         struct pci_dev *pci;
 473         int dev_index;
 474
 475         /* chip type specific */
 476         int driver_type;
 477         unsigned int driver_caps;
 478         int playback_streams;
 479         int playback_index_offset;
 480         int capture_streams;
 481         int capture_index_offset;
 482         int num_streams;
 483
 484         /* pci resources */
 485         unsigned long addr;
 486         void __iomem *remap_addr;
 487         int irq;
 488
 489         /* locks */
 490         spinlock_t reg_lock;
 491         struct mutex open_mutex;
 492         struct completion probe_wait;
 493
 494         /* streams (x num_streams) */
 495         struct azx_dev *azx_dev;
 496
 497         /* PCM */
 498         struct list_head pcm_list; /* azx_pcm list */
 499
 500         /* HD codec */
 501         unsigned short codec_mask;
 502         int  codec_probe_mask; /* copied from probe_mask option */
 503         struct hda_bus *bus;
 504         unsigned int beep_mode;
 505
 506         /* CORB/RIRB */
 507         struct azx_rb corb;
 508         struct azx_rb rirb;
 509
 510         /* CORB/RIRB and position buffers */
 511         struct snd_dma_buffer rb;
 512         struct snd_dma_buffer posbuf;
 513
 514 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 515         const struct firmware *fw;
 516 #endif
 517
 518         /* flags */
 519         int position_fix[2]; /* for both playback/capture streams */
 520         int poll_count;
 521         unsigned int running :1;
 522         unsigned int initialized :1;
 523         unsigned int single_cmd :1;
 524         unsigned int polling_mode :1;
 525         unsigned int msi :1;
 526         unsigned int irq_pending_warned :1;
 527         unsigned int probing :1; /* codec probing phase */
 528         unsigned int snoop:1;
 529         unsigned int align_buffer_size:1;
 530         unsigned int region_requested:1;
 531
 532         /* VGA-switcheroo setup */
 533         unsigned int use_vga_switcheroo:1;
 534         unsigned int vga_switcheroo_registered:1;
 535         unsigned int init_failed:1; /* delayed init failed */
 536         unsigned int disabled:1; /* disabled by VGA-switcher */
 537
 538         /* for debugging */
 539         unsigned int last_cmd[AZX_MAX_CODECS];
 540
 541         /* for pending irqs */
 542         struct work_struct irq_pending_work;
 543
 544         /* reboot notifier (for mysterious hangup problem at power-down) */
 545         struct notifier_block reboot_notifier;
 546
 547         /* card list (for power_save trigger) */
 548         struct list_head list;
 549
 550 #ifdef CONFIG_SND_HDA_DSP_LOADER
 551         struct azx_dev saved_azx_dev;
 552 #endif
 553 };
 554
 555 #define CREATE_TRACE_POINTS
 556 #include "hda_intel_trace.h"
 557
 558 /* driver types */
 559 enum {
 560         AZX_DRIVER_ICH,
 561         AZX_DRIVER_PCH,
 562         AZX_DRIVER_SCH,
 563         AZX_DRIVER_ATI,
 564         AZX_DRIVER_ATIHDMI,
 565         AZX_DRIVER_ATIHDMI_NS,
 566         AZX_DRIVER_VIA,
 567         AZX_DRIVER_SIS,
 568         AZX_DRIVER_ULI,
 569         AZX_DRIVER_NVIDIA,
 570         AZX_DRIVER_TERA,
 571         AZX_DRIVER_CTX,
 572         AZX_DRIVER_CTHDA,
 573         AZX_DRIVER_GENERIC,
 574         AZX_NUM_DRIVERS, /* keep this as last entry */
 575 };
 576
 577 /* driver quirks (capabilities) */
 578 /* bits 0-7 are used for indicating driver type */
 579 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 580 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 581 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 582 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 583 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 584 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 585 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 586 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 587 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 588 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 589 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 590 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 591 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 592 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 593 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 594 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 595 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 596 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 597
 598 /* quirks for Intel PCH */
 599 #define AZX_DCAPS_INTEL_PCH_NOPM \
 600         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 601          AZX_DCAPS_COUNT_LPIB_DELAY)
 602
 603 #define AZX_DCAPS_INTEL_PCH \
 604         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 605
 606 /* quirks for ATI SB / AMD Hudson */
 607 #define AZX_DCAPS_PRESET_ATI_SB \
 608         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 609          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 610
 611 /* quirks for ATI/AMD HDMI */
 612 #define AZX_DCAPS_PRESET_ATI_HDMI \
 613         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 614
 615 /* quirks for Nvidia */
 616 #define AZX_DCAPS_PRESET_NVIDIA \
 617         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 618          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
 619
 620 #define AZX_DCAPS_PRESET_CTHDA \
 621         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 622
 623 /*
 624  * VGA-switcher support
 625  */
 626 #ifdef SUPPORT_VGA_SWITCHEROO
 627 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 628 #else
 629 #define use_vga_switcheroo(chip)        0
 630 #endif
 631
 632 static char *driver_short_names[] = {
 633         [AZX_DRIVER_ICH] = "HDA Intel",
 634         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 635         [AZX_DRIVER_SCH] = "HDA Intel MID",
 636         [AZX_DRIVER_ATI] = "HDA ATI SB",
 637         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 638         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 639         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 640         [AZX_DRIVER_SIS] = "HDA SIS966",
 641         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 642         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 643         [AZX_DRIVER_TERA] = "HDA Teradici",
 644         [AZX_DRIVER_CTX] = "HDA Creative",
 645         [AZX_DRIVER_CTHDA] = "HDA Creative",
 646         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 647 };
 648
 649 /*
 650  * macros for easy use
 651  */
 652 #define azx_writel(chip,reg,value) \
 653         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 654 #define azx_readl(chip,reg) \
 655         readl((chip)->remap_addr + ICH6_REG_##reg)
 656 #define azx_writew(chip,reg,value) \
 657         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 658 #define azx_readw(chip,reg) \
 659         readw((chip)->remap_addr + ICH6_REG_##reg)
 660 #define azx_writeb(chip,reg,value) \
 661         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 662 #define azx_readb(chip,reg) \
 663         readb((chip)->remap_addr + ICH6_REG_##reg)
 664
 665 #define azx_sd_writel(dev,reg,value) \
 666         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 667 #define azx_sd_readl(dev,reg) \
 668         readl((dev)->sd_addr + ICH6_REG_##reg)
 669 #define azx_sd_writew(dev,reg,value) \
 670         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 671 #define azx_sd_readw(dev,reg) \
 672         readw((dev)->sd_addr + ICH6_REG_##reg)
 673 #define azx_sd_writeb(dev,reg,value) \
 674         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 675 #define azx_sd_readb(dev,reg) \
 676         readb((dev)->sd_addr + ICH6_REG_##reg)
 677
 678 /* for pcm support */
 679 #define get_azx_dev(substream) (substream->runtime->private_data)
 680
 681 #ifdef CONFIG_X86
 682 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 683 {
 684         int pages;
 685
 686         if (azx_snoop(chip))
 687                 return;
 688         if (!dmab || !dmab->area || !dmab->bytes)
 689                 return;
 690
 691 #ifdef CONFIG_SND_DMA_SGBUF
 692         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 693                 struct snd_sg_buf *sgbuf = dmab->private_data;
 694                 if (on)
 695                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 696                 else
 697                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 698                 return;
 699         }
 700 #endif
 701
 702         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 703         if (on)
 704                 set_memory_wc((unsigned long)dmab->area, pages);
 705         else
 706                 set_memory_wb((unsigned long)dmab->area, pages);
 707 }
 708
 709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 710                                  bool on)
 711 {
 712         __mark_pages_wc(chip, buf, on);
 713 }
 714 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 715                                    struct snd_pcm_substream *substream, bool on)
 716 {
 717         if (azx_dev->wc_marked != on) {
 718                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 719                 azx_dev->wc_marked = on;
 720         }
 721 }
 722 #else
 723 /* NOP for other archs */
 724 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 725                                  bool on)
 726 {
 727 }
 728 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 729                                    struct snd_pcm_substream *substream, bool on)
 730 {
 731 }
 732 #endif
 733
 734 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 735 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 736 /*
 737  * Interface for HD codec
 738  */
 739
 740 /*
 741  * CORB / RIRB interface
 742  */
 743 static int azx_alloc_cmd_io(struct azx *chip)
 744 {
 745         int err;
 746
 747         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 748         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 749                                   snd_dma_pci_data(chip->pci),
 750                                   PAGE_SIZE, &chip->rb);
 751         if (err < 0) {
 752                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
 753                 return err;
 754         }
 755         mark_pages_wc(chip, &chip->rb, true);
 756         return 0;
 757 }
 758
 759 static void azx_init_cmd_io(struct azx *chip)
 760 {
 761         spin_lock_irq(&chip->reg_lock);
 762         /* CORB set up */
 763         chip->corb.addr = chip->rb.addr;
 764         chip->corb.buf = (u32 *)chip->rb.area;
 765         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 766         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 767
 768         /* set the corb size to 256 entries (ULI requires explicitly) */
 769         azx_writeb(chip, CORBSIZE, 0x02);
 770         /* set the corb write pointer to 0 */
 771         azx_writew(chip, CORBWP, 0);
 772         /* reset the corb hw read pointer */
 773         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 774         /* enable corb dma */
 775         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 776
 777         /* RIRB set up */
 778         chip->rirb.addr = chip->rb.addr + 2048;
 779         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 780         chip->rirb.wp = chip->rirb.rp = 0;
 781         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 782         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 783         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 784
 785         /* set the rirb size to 256 entries (ULI requires explicitly) */
 786         azx_writeb(chip, RIRBSIZE, 0x02);
 787         /* reset the rirb hw write pointer */
 788         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 789         /* set N=1, get RIRB response interrupt for new entry */
 790         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 791                 azx_writew(chip, RINTCNT, 0xc0);
 792         else
 793                 azx_writew(chip, RINTCNT, 1);
 794         /* enable rirb dma and response irq */
 795         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 796         spin_unlock_irq(&chip->reg_lock);
 797 }
 798
 799 static void azx_free_cmd_io(struct azx *chip)
 800 {
 801         spin_lock_irq(&chip->reg_lock);
 802         /* disable ringbuffer DMAs */
 803         azx_writeb(chip, RIRBCTL, 0);
 804         azx_writeb(chip, CORBCTL, 0);
 805         spin_unlock_irq(&chip->reg_lock);
 806 }
 807
 808 static unsigned int azx_command_addr(u32 cmd)
 809 {
 810         unsigned int addr = cmd >> 28;
 811
 812         if (addr >= AZX_MAX_CODECS) {
 813                 snd_BUG();
 814                 addr = 0;
 815         }
 816
 817         return addr;
 818 }
 819
 820 static unsigned int azx_response_addr(u32 res)
 821 {
 822         unsigned int addr = res & 0xf;
 823
 824         if (addr >= AZX_MAX_CODECS) {
 825                 snd_BUG();
 826                 addr = 0;
 827         }
 828
 829         return addr;
 830 }
 831
 832 /* send a command */
 833 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 834 {
 835         struct azx *chip = bus->private_data;
 836         unsigned int addr = azx_command_addr(val);
 837         unsigned int wp, rp;
 838
 839         spin_lock_irq(&chip->reg_lock);
 840
 841         /* add command to corb */
 842         wp = azx_readw(chip, CORBWP);
 843         if (wp == 0xffff) {
 844                 /* something wrong, controller likely turned to D3 */
 845                 spin_unlock_irq(&chip->reg_lock);
 846                 return -EIO;
 847         }
 848         wp++;
 849         wp %= ICH6_MAX_CORB_ENTRIES;
 850
 851         rp = azx_readw(chip, CORBRP);
 852         if (wp == rp) {
 853                 /* oops, it's full */
 854                 spin_unlock_irq(&chip->reg_lock);
 855                 return -EAGAIN;
 856         }
 857
 858         chip->rirb.cmds[addr]++;
 859         chip->corb.buf[wp] = cpu_to_le32(val);
 860         azx_writel(chip, CORBWP, wp);
 861
 862         spin_unlock_irq(&chip->reg_lock);
 863
 864         return 0;
 865 }
 866
 867 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 868
 869 /* retrieve RIRB entry - called from interrupt handler */
 870 static void azx_update_rirb(struct azx *chip)
 871 {
 872         unsigned int rp, wp;
 873         unsigned int addr;
 874         u32 res, res_ex;
 875
 876         wp = azx_readw(chip, RIRBWP);
 877         if (wp == 0xffff) {
 878                 /* something wrong, controller likely turned to D3 */
 879                 return;
 880         }
 881
 882         if (wp == chip->rirb.wp)
 883                 return;
 884         chip->rirb.wp = wp;
 885
 886         while (chip->rirb.rp != wp) {
 887                 chip->rirb.rp++;
 888                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 889
 890                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 891                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 892                 res = le32_to_cpu(chip->rirb.buf[rp]);
 893                 addr = azx_response_addr(res_ex);
 894                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 895                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 896                 else if (chip->rirb.cmds[addr]) {
 897                         chip->rirb.res[addr] = res;
 898                         smp_wmb();
 899                         chip->rirb.cmds[addr]--;
 900                 } else
 901                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
 902                                    "last cmd=%#08x\n",
 903                                    pci_name(chip->pci),
 904                                    res, res_ex,
 905                                    chip->last_cmd[addr]);
 906         }
 907 }
 908
 909 /* receive a response */
 910 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 911                                           unsigned int addr)
 912 {
 913         struct azx *chip = bus->private_data;
 914         unsigned long timeout;
 915         unsigned long loopcounter;
 916         int do_poll = 0;
 917
 918  again:
 919         timeout = jiffies + msecs_to_jiffies(1000);
 920
 921         for (loopcounter = 0;; loopcounter++) {
 922                 if (chip->polling_mode || do_poll) {
 923                         spin_lock_irq(&chip->reg_lock);
 924                         azx_update_rirb(chip);
 925                         spin_unlock_irq(&chip->reg_lock);
 926                 }
 927                 if (!chip->rirb.cmds[addr]) {
 928                         smp_rmb();
 929                         bus->rirb_error = 0;
 930
 931                         if (!do_poll)
 932                                 chip->poll_count = 0;
 933                         return chip->rirb.res[addr]; /* the last value */
 934                 }
 935                 if (time_after(jiffies, timeout))
 936                         break;
 937                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 938                         msleep(2); /* temporary workaround */
 939                 else {
 940                         udelay(10);
 941                         cond_resched();
 942                 }
 943         }
 944
 945         if (!bus->no_response_fallback)
 946                 return -1;
 947
 948         if (!chip->polling_mode && chip->poll_count < 2) {
 949                 snd_printdd(SFX "%s: azx_get_response timeout, "
 950                            "polling the codec once: last cmd=0x%08x\n",
 951                            pci_name(chip->pci), chip->last_cmd[addr]);
 952                 do_poll = 1;
 953                 chip->poll_count++;
 954                 goto again;
 955         }
 956
 957
 958         if (!chip->polling_mode) {
 959                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
 960                            "switching to polling mode: last cmd=0x%08x\n",
 961                            pci_name(chip->pci), chip->last_cmd[addr]);
 962                 chip->polling_mode = 1;
 963                 goto again;
 964         }
 965
 966         if (chip->msi) {
 967                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
 968                            "disabling MSI: last cmd=0x%08x\n",
 969                            pci_name(chip->pci), chip->last_cmd[addr]);
 970                 free_irq(chip->irq, chip);
 971                 chip->irq = -1;
 972                 pci_disable_msi(chip->pci);
 973                 chip->msi = 0;
 974                 if (azx_acquire_irq(chip, 1) < 0) {
 975                         bus->rirb_error = 1;
 976                         return -1;
 977                 }
 978                 goto again;
 979         }
 980
 981         if (chip->probing) {
 982                 /* If this critical timeout happens during the codec probing
 983                  * phase, this is likely an access to a non-existing codec
 984                  * slot.  Better to return an error and reset the system.
 985                  */
 986                 return -1;
 987         }
 988
 989         /* a fatal communication error; need either to reset or to fallback
 990          * to the single_cmd mode
 991          */
 992         bus->rirb_error = 1;
 993         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 994                 bus->response_reset = 1;
 995                 return -1; /* give a chance to retry */
 996         }
 997
 998         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 999                    "switching to single_cmd mode: last cmd=0x%08x\n",
1000                    chip->last_cmd[addr]);
1001         chip->single_cmd = 1;
1002         bus->response_reset = 0;
1003         /* release CORB/RIRB */
1004         azx_free_cmd_io(chip);
1005         /* disable unsolicited responses */
1006         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1007         return -1;
1008 }
1009
1010 /*
1011  * Use the single immediate command instead of CORB/RIRB for simplicity
1012  *
1013  * Note: according to Intel, this is not preferred use.  The command was
1014  *       intended for the BIOS only, and may get confused with unsolicited
1015  *       responses.  So, we shouldn't use it for normal operation from the
1016  *       driver.
1017  *       I left the codes, however, for debugging/testing purposes.
1018  */
1019
1020 /* receive a response */
1021 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1022 {
1023         int timeout = 50;
1024
1025         while (timeout--) {
1026                 /* check IRV busy bit */
1027                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1028                         /* reuse rirb.res as the response return value */
1029                         chip->rirb.res[addr] = azx_readl(chip, IR);
1030                         return 0;
1031                 }
1032                 udelay(1);
1033         }
1034         if (printk_ratelimit())
1035                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1036                            pci_name(chip->pci), azx_readw(chip, IRS));
1037         chip->rirb.res[addr] = -1;
1038         return -EIO;
1039 }
1040
1041 /* send a command */
1042 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1043 {
1044         struct azx *chip = bus->private_data;
1045         unsigned int addr = azx_command_addr(val);
1046         int timeout = 50;
1047
1048         bus->rirb_error = 0;
1049         while (timeout--) {
1050                 /* check ICB busy bit */
1051                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1052                         /* Clear IRV valid bit */
1053                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1054                                    ICH6_IRS_VALID);
1055                         azx_writel(chip, IC, val);
1056                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1057                                    ICH6_IRS_BUSY);
1058                         return azx_single_wait_for_response(chip, addr);
1059                 }
1060                 udelay(1);
1061         }
1062         if (printk_ratelimit())
1063                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1064                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1065         return -EIO;
1066 }
1067
1068 /* receive a response */
1069 static unsigned int azx_single_get_response(struct hda_bus *bus,
1070                                             unsigned int addr)
1071 {
1072         struct azx *chip = bus->private_data;
1073         return chip->rirb.res[addr];
1074 }
1075
1076 /*
1077  * The below are the main callbacks from hda_codec.
1078  *
1079  * They are just the skeleton to call sub-callbacks according to the
1080  * current setting of chip->single_cmd.
1081  */
1082
1083 /* send a command */
1084 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1085 {
1086         struct azx *chip = bus->private_data;
1087
1088         if (chip->disabled)
1089                 return 0;
1090         chip->last_cmd[azx_command_addr(val)] = val;
1091         if (chip->single_cmd)
1092                 return azx_single_send_cmd(bus, val);
1093         else
1094                 return azx_corb_send_cmd(bus, val);
1095 }
1096
1097 /* get a response */
1098 static unsigned int azx_get_response(struct hda_bus *bus,
1099                                      unsigned int addr)
1100 {
1101         struct azx *chip = bus->private_data;
1102         if (chip->disabled)
1103                 return 0;
1104         if (chip->single_cmd)
1105                 return azx_single_get_response(bus, addr);
1106         else
1107                 return azx_rirb_get_response(bus, addr);
1108 }
1109
1110 #ifdef CONFIG_PM
1111 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1112 #endif
1113
1114 #ifdef CONFIG_SND_HDA_DSP_LOADER
1115 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1116                                 unsigned int byte_size,
1117                                 struct snd_dma_buffer *bufp);
1118 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1119 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1120                                  struct snd_dma_buffer *dmab);
1121 #endif
1122
1123 /* reset codec link */
1124 static int azx_reset(struct azx *chip, int full_reset)
1125 {
1126         unsigned long timeout;
1127
1128         if (!full_reset)
1129                 goto __skip;
1130
1131         /* clear STATESTS */
1132         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1133
1134         /* reset controller */
1135         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1136
1137         timeout = jiffies + msecs_to_jiffies(100);
1138         while (azx_readb(chip, GCTL) &&
1139                         time_before(jiffies, timeout))
1140                 usleep_range(500, 1000);
1141
1142         /* delay for >= 100us for codec PLL to settle per spec
1143          * Rev 0.9 section 5.5.1
1144          */
1145         usleep_range(500, 1000);
1146
1147         /* Bring controller out of reset */
1148         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1149
1150         timeout = jiffies + msecs_to_jiffies(100);
1151         while (!azx_readb(chip, GCTL) &&
1152                         time_before(jiffies, timeout))
1153                 usleep_range(500, 1000);
1154
1155         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1156         usleep_range(1000, 1200);
1157
1158       __skip:
1159         /* check to see if controller is ready */
1160         if (!azx_readb(chip, GCTL)) {
1161                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1162                 return -EBUSY;
1163         }
1164
1165         /* Accept unsolicited responses */
1166         if (!chip->single_cmd)
1167                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1168                            ICH6_GCTL_UNSOL);
1169
1170         /* detect codecs */
1171         if (!chip->codec_mask) {
1172                 chip->codec_mask = azx_readw(chip, STATESTS);
1173                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1174         }
1175
1176         return 0;
1177 }
1178
1179
1180 /*
1181  * Lowlevel interface
1182  */
1183
1184 /* enable interrupts */
1185 static void azx_int_enable(struct azx *chip)
1186 {
1187         /* enable controller CIE and GIE */
1188         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1189                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1190 }
1191
1192 /* disable interrupts */
1193 static void azx_int_disable(struct azx *chip)
1194 {
1195         int i;
1196
1197         /* disable interrupts in stream descriptor */
1198         for (i = 0; i < chip->num_streams; i++) {
1199                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1200                 azx_sd_writeb(azx_dev, SD_CTL,
1201                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1202         }
1203
1204         /* disable SIE for all streams */
1205         azx_writeb(chip, INTCTL, 0);
1206
1207         /* disable controller CIE and GIE */
1208         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1209                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1210 }
1211
1212 /* clear interrupts */
1213 static void azx_int_clear(struct azx *chip)
1214 {
1215         int i;
1216
1217         /* clear stream status */
1218         for (i = 0; i < chip->num_streams; i++) {
1219                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1220                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1221         }
1222
1223         /* clear STATESTS */
1224         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1225
1226         /* clear rirb status */
1227         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1228
1229         /* clear int status */
1230         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1231 }
1232
1233 /* start a stream */
1234 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1235 {
1236         /*
1237          * Before stream start, initialize parameter
1238          */
1239         azx_dev->insufficient = 1;
1240
1241         /* enable SIE */
1242         azx_writel(chip, INTCTL,
1243                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1244         /* set DMA start and interrupt mask */
1245         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1246                       SD_CTL_DMA_START | SD_INT_MASK);
1247 }
1248
1249 /* stop DMA */
1250 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1251 {
1252         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1253                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1254         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1255 }
1256
1257 /* stop a stream */
1258 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1259 {
1260         azx_stream_clear(chip, azx_dev);
1261         /* disable SIE */
1262         azx_writel(chip, INTCTL,
1263                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1264 }
1265
1266
1267 /*
1268  * reset and start the controller registers
1269  */
1270 static void azx_init_chip(struct azx *chip, int full_reset)
1271 {
1272         if (chip->initialized)
1273                 return;
1274
1275         /* reset controller */
1276         azx_reset(chip, full_reset);
1277
1278         /* initialize interrupts */
1279         azx_int_clear(chip);
1280         azx_int_enable(chip);
1281
1282         /* initialize the codec command I/O */
1283         if (!chip->single_cmd)
1284                 azx_init_cmd_io(chip);
1285
1286         /* program the position buffer */
1287         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1288         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1289
1290         chip->initialized = 1;
1291 }
1292
1293 /*
1294  * initialize the PCI registers
1295  */
1296 /* update bits in a PCI register byte */
1297 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1298                             unsigned char mask, unsigned char val)
1299 {
1300         unsigned char data;
1301
1302         pci_read_config_byte(pci, reg, &data);
1303         data &= ~mask;
1304         data |= (val & mask);
1305         pci_write_config_byte(pci, reg, data);
1306 }
1307
1308 static void azx_init_pci(struct azx *chip)
1309 {
1310         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1311          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1312          * Ensuring these bits are 0 clears playback static on some HD Audio
1313          * codecs.
1314          * The PCI register TCSEL is defined in the Intel manuals.
1315          */
1316         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1317                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1318                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1319         }
1320
1321         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1322          * we need to enable snoop.
1323          */
1324         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1325                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1326                 update_pci_byte(chip->pci,
1327                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1328                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1329         }
1330
1331         /* For NVIDIA HDA, enable snoop */
1332         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1333                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1334                 update_pci_byte(chip->pci,
1335                                 NVIDIA_HDA_TRANSREG_ADDR,
1336                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1337                 update_pci_byte(chip->pci,
1338                                 NVIDIA_HDA_ISTRM_COH,
1339                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1340                 update_pci_byte(chip->pci,
1341                                 NVIDIA_HDA_OSTRM_COH,
1342                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1343         }
1344
1345         /* Enable SCH/PCH snoop if needed */
1346         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1347                 unsigned short snoop;
1348                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1349                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1350                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1351                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1352                         if (!azx_snoop(chip))
1353                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1354                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1355                         pci_read_config_word(chip->pci,
1356                                 INTEL_SCH_HDA_DEVC, &snoop);
1357                 }
1358                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1359                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1360                                 ? "Disabled" : "Enabled");
1361         }
1362 }
1363
1364
1365 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1366
1367 /*
1368  * interrupt handler
1369  */
1370 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1371 {
1372         struct azx *chip = dev_id;
1373         struct azx_dev *azx_dev;
1374         u32 status;
1375         u8 sd_status;
1376         int i, ok;
1377
1378 #ifdef CONFIG_PM_RUNTIME
1379         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1380                 return IRQ_NONE;
1381 #endif
1382
1383         spin_lock(&chip->reg_lock);
1384
1385         if (chip->disabled) {
1386                 spin_unlock(&chip->reg_lock);
1387                 return IRQ_NONE;
1388         }
1389
1390         status = azx_readl(chip, INTSTS);
1391         if (status == 0) {
1392                 spin_unlock(&chip->reg_lock);
1393                 return IRQ_NONE;
1394         }
1395
1396         for (i = 0; i < chip->num_streams; i++) {
1397                 azx_dev = &chip->azx_dev[i];
1398                 if (status & azx_dev->sd_int_sta_mask) {
1399                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1400                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1401                         if (!azx_dev->substream || !azx_dev->running ||
1402                             !(sd_status & SD_INT_COMPLETE))
1403                                 continue;
1404                         /* check whether this IRQ is really acceptable */
1405                         ok = azx_position_ok(chip, azx_dev);
1406                         if (ok == 1) {
1407                                 azx_dev->irq_pending = 0;
1408                                 spin_unlock(&chip->reg_lock);
1409                                 snd_pcm_period_elapsed(azx_dev->substream);
1410                                 spin_lock(&chip->reg_lock);
1411                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1412                                 /* bogus IRQ, process it later */
1413                                 azx_dev->irq_pending = 1;
1414                                 queue_work(chip->bus->workq,
1415                                            &chip->irq_pending_work);
1416                         }
1417                 }
1418         }
1419
1420         /* clear rirb int */
1421         status = azx_readb(chip, RIRBSTS);
1422         if (status & RIRB_INT_MASK) {
1423                 if (status & RIRB_INT_RESPONSE) {
1424                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1425                                 udelay(80);
1426                         azx_update_rirb(chip);
1427                 }
1428                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1429         }
1430
1431 #if 0
1432         /* clear state status int */
1433         if (azx_readb(chip, STATESTS) & 0x04)
1434                 azx_writeb(chip, STATESTS, 0x04);
1435 #endif
1436         spin_unlock(&chip->reg_lock);
1437
1438         return IRQ_HANDLED;
1439 }
1440
1441
1442 /*
1443  * set up a BDL entry
1444  */
1445 static int setup_bdle(struct azx *chip,
1446                       struct snd_dma_buffer *dmab,
1447                       struct azx_dev *azx_dev, u32 **bdlp,
1448                       int ofs, int size, int with_ioc)
1449 {
1450         u32 *bdl = *bdlp;
1451
1452         while (size > 0) {
1453                 dma_addr_t addr;
1454                 int chunk;
1455
1456                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1457                         return -EINVAL;
1458
1459                 addr = snd_sgbuf_get_addr(dmab, ofs);
1460                 /* program the address field of the BDL entry */
1461                 bdl[0] = cpu_to_le32((u32)addr);
1462                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1463                 /* program the size field of the BDL entry */
1464                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1465                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1466                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1467                         u32 remain = 0x1000 - (ofs & 0xfff);
1468                         if (chunk > remain)
1469                                 chunk = remain;
1470                 }
1471                 bdl[2] = cpu_to_le32(chunk);
1472                 /* program the IOC to enable interrupt
1473                  * only when the whole fragment is processed
1474                  */
1475                 size -= chunk;
1476                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1477                 bdl += 4;
1478                 azx_dev->frags++;
1479                 ofs += chunk;
1480         }
1481         *bdlp = bdl;
1482         return ofs;
1483 }
1484
1485 /*
1486  * set up BDL entries
1487  */
1488 static int azx_setup_periods(struct azx *chip,
1489                              struct snd_pcm_substream *substream,
1490                              struct azx_dev *azx_dev)
1491 {
1492         u32 *bdl;
1493         int i, ofs, periods, period_bytes;
1494         int pos_adj;
1495
1496         /* reset BDL address */
1497         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1498         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1499
1500         period_bytes = azx_dev->period_bytes;
1501         periods = azx_dev->bufsize / period_bytes;
1502
1503         /* program the initial BDL entries */
1504         bdl = (u32 *)azx_dev->bdl.area;
1505         ofs = 0;
1506         azx_dev->frags = 0;
1507         pos_adj = bdl_pos_adj[chip->dev_index];
1508         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1509                 struct snd_pcm_runtime *runtime = substream->runtime;
1510                 int pos_align = pos_adj;
1511                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1512                 if (!pos_adj)
1513                         pos_adj = pos_align;
1514                 else
1515                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1516                                 pos_align;
1517                 pos_adj = frames_to_bytes(runtime, pos_adj);
1518                 if (pos_adj >= period_bytes) {
1519                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1520                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1521                         pos_adj = 0;
1522                 } else {
1523                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1524                                          azx_dev,
1525                                          &bdl, ofs, pos_adj, true);
1526                         if (ofs < 0)
1527                                 goto error;
1528                 }
1529         } else
1530                 pos_adj = 0;
1531         for (i = 0; i < periods; i++) {
1532                 if (i == periods - 1 && pos_adj)
1533                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1534                                          azx_dev, &bdl, ofs,
1535                                          period_bytes - pos_adj, 0);
1536                 else
1537                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1538                                          azx_dev, &bdl, ofs,
1539                                          period_bytes,
1540                                          !azx_dev->no_period_wakeup);
1541                 if (ofs < 0)
1542                         goto error;
1543         }
1544         return 0;
1545
1546  error:
1547         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1548                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1549         return -EINVAL;
1550 }
1551
1552 /* reset stream */
1553 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1554 {
1555         unsigned char val;
1556         int timeout;
1557
1558         azx_stream_clear(chip, azx_dev);
1559
1560         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1561                       SD_CTL_STREAM_RESET);
1562         udelay(3);
1563         timeout = 300;
1564         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1565                --timeout)
1566                 ;
1567         val &= ~SD_CTL_STREAM_RESET;
1568         azx_sd_writeb(azx_dev, SD_CTL, val);
1569         udelay(3);
1570
1571         timeout = 300;
1572         /* waiting for hardware to report that the stream is out of reset */
1573         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1574                --timeout)
1575                 ;
1576
1577         /* reset first position - may not be synced with hw at this time */
1578         *azx_dev->posbuf = 0;
1579 }
1580
1581 /*
1582  * set up the SD for streaming
1583  */
1584 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1585 {
1586         unsigned int val;
1587         /* make sure the run bit is zero for SD */
1588         azx_stream_clear(chip, azx_dev);
1589         /* program the stream_tag */
1590         val = azx_sd_readl(azx_dev, SD_CTL);
1591         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1592                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1593         if (!azx_snoop(chip))
1594                 val |= SD_CTL_TRAFFIC_PRIO;
1595         azx_sd_writel(azx_dev, SD_CTL, val);
1596
1597         /* program the length of samples in cyclic buffer */
1598         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1599
1600         /* program the stream format */
1601         /* this value needs to be the same as the one programmed */
1602         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1603
1604         /* program the stream LVI (last valid index) of the BDL */
1605         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1606
1607         /* program the BDL address */
1608         /* lower BDL address */
1609         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1610         /* upper BDL address */
1611         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1612
1613         /* enable the position buffer */
1614         if (chip->position_fix[0] != POS_FIX_LPIB ||
1615             chip->position_fix[1] != POS_FIX_LPIB) {
1616                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1617                         azx_writel(chip, DPLBASE,
1618                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1619         }
1620
1621         /* set the interrupt enable bits in the descriptor control register */
1622         azx_sd_writel(azx_dev, SD_CTL,
1623                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1624
1625         return 0;
1626 }
1627
1628 /*
1629  * Probe the given codec address
1630  */
1631 static int probe_codec(struct azx *chip, int addr)
1632 {
1633         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1634                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1635         unsigned int res;
1636
1637         mutex_lock(&chip->bus->cmd_mutex);
1638         chip->probing = 1;
1639         azx_send_cmd(chip->bus, cmd);
1640         res = azx_get_response(chip->bus, addr);
1641         chip->probing = 0;
1642         mutex_unlock(&chip->bus->cmd_mutex);
1643         if (res == -1)
1644                 return -EIO;
1645         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1646         return 0;
1647 }
1648
1649 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1650                                  struct hda_pcm *cpcm);
1651 static void azx_stop_chip(struct azx *chip);
1652
1653 static void azx_bus_reset(struct hda_bus *bus)
1654 {
1655         struct azx *chip = bus->private_data;
1656
1657         bus->in_reset = 1;
1658         azx_stop_chip(chip);
1659         azx_init_chip(chip, 1);
1660 #ifdef CONFIG_PM
1661         if (chip->initialized) {
1662                 struct azx_pcm *p;
1663                 list_for_each_entry(p, &chip->pcm_list, list)
1664                         snd_pcm_suspend_all(p->pcm);
1665                 snd_hda_suspend(chip->bus);
1666                 snd_hda_resume(chip->bus);
1667         }
1668 #endif
1669         bus->in_reset = 0;
1670 }
1671
1672 static int get_jackpoll_interval(struct azx *chip)
1673 {
1674         int i = jackpoll_ms[chip->dev_index];
1675         unsigned int j;
1676         if (i == 0)
1677                 return 0;
1678         if (i < 50 || i > 60000)
1679                 j = 0;
1680         else
1681                 j = msecs_to_jiffies(i);
1682         if (j == 0)
1683                 snd_printk(KERN_WARNING SFX
1684                            "jackpoll_ms value out of range: %d\n", i);
1685         return j;
1686 }
1687
1688 /*
1689  * Codec initialization
1690  */
1691
1692 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1693 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1694         [AZX_DRIVER_NVIDIA] = 8,
1695         [AZX_DRIVER_TERA] = 1,
1696 };
1697
1698 static int azx_codec_create(struct azx *chip, const char *model)
1699 {
1700         struct hda_bus_template bus_temp;
1701         int c, codecs, err;
1702         int max_slots;
1703
1704         memset(&bus_temp, 0, sizeof(bus_temp));
1705         bus_temp.private_data = chip;
1706         bus_temp.modelname = model;
1707         bus_temp.pci = chip->pci;
1708         bus_temp.ops.command = azx_send_cmd;
1709         bus_temp.ops.get_response = azx_get_response;
1710         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1711         bus_temp.ops.bus_reset = azx_bus_reset;
1712 #ifdef CONFIG_PM
1713         bus_temp.power_save = &power_save;
1714         bus_temp.ops.pm_notify = azx_power_notify;
1715 #endif
1716 #ifdef CONFIG_SND_HDA_DSP_LOADER
1717         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1718         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1719         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1720 #endif
1721
1722         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1723         if (err < 0)
1724                 return err;
1725
1726         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1727                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1728                 chip->bus->needs_damn_long_delay = 1;
1729         }
1730
1731         codecs = 0;
1732         max_slots = azx_max_codecs[chip->driver_type];
1733         if (!max_slots)
1734                 max_slots = AZX_DEFAULT_CODECS;
1735
1736         /* First try to probe all given codec slots */
1737         for (c = 0; c < max_slots; c++) {
1738                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1739                         if (probe_codec(chip, c) < 0) {
1740                                 /* Some BIOSen give you wrong codec addresses
1741                                  * that don't exist
1742                                  */
1743                                 snd_printk(KERN_WARNING SFX
1744                                            "%s: Codec #%d probe error; "
1745                                            "disabling it...\n", pci_name(chip->pci), c);
1746                                 chip->codec_mask &= ~(1 << c);
1747                                 /* More badly, accessing to a non-existing
1748                                  * codec often screws up the controller chip,
1749                                  * and disturbs the further communications.
1750                                  * Thus if an error occurs during probing,
1751                                  * better to reset the controller chip to
1752                                  * get back to the sanity state.
1753                                  */
1754                                 azx_stop_chip(chip);
1755                                 azx_init_chip(chip, 1);
1756                         }
1757                 }
1758         }
1759
1760         /* AMD chipsets often cause the communication stalls upon certain
1761          * sequence like the pin-detection.  It seems that forcing the synced
1762          * access works around the stall.  Grrr...
1763          */
1764         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1765                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1766                         pci_name(chip->pci));
1767                 chip->bus->sync_write = 1;
1768                 chip->bus->allow_bus_reset = 1;
1769         }
1770
1771         /* Then create codec instances */
1772         for (c = 0; c < max_slots; c++) {
1773                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1774                         struct hda_codec *codec;
1775                         err = snd_hda_codec_new(chip->bus, c, &codec);
1776                         if (err < 0)
1777                                 continue;
1778                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1779                         codec->beep_mode = chip->beep_mode;
1780                         codecs++;
1781                 }
1782         }
1783         if (!codecs) {
1784                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1785                 return -ENXIO;
1786         }
1787         return 0;
1788 }
1789
1790 /* configure each codec instance */
1791 static int azx_codec_configure(struct azx *chip)
1792 {
1793         struct hda_codec *codec;
1794         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1795                 snd_hda_codec_configure(codec);
1796         }
1797         return 0;
1798 }
1799
1800
1801 /*
1802  * PCM support
1803  */
1804
1805 /* assign a stream for the PCM */
1806 static inline struct azx_dev *
1807 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1808 {
1809         int dev, i, nums;
1810         struct azx_dev *res = NULL;
1811         /* make a non-zero unique key for the substream */
1812         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1813                 (substream->stream + 1);
1814
1815         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1816                 dev = chip->playback_index_offset;
1817                 nums = chip->playback_streams;
1818         } else {
1819                 dev = chip->capture_index_offset;
1820                 nums = chip->capture_streams;
1821         }
1822         for (i = 0; i < nums; i++, dev++) {
1823                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1824                 dsp_lock(azx_dev);
1825                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1826                         res = azx_dev;
1827                         if (res->assigned_key == key) {
1828                                 res->opened = 1;
1829                                 res->assigned_key = key;
1830                                 dsp_unlock(azx_dev);
1831                                 return azx_dev;
1832                         }
1833                 }
1834                 dsp_unlock(azx_dev);
1835         }
1836         if (res) {
1837                 dsp_lock(res);
1838                 res->opened = 1;
1839                 res->assigned_key = key;
1840                 dsp_unlock(res);
1841         }
1842         return res;
1843 }
1844
1845 /* release the assigned stream */
1846 static inline void azx_release_device(struct azx_dev *azx_dev)
1847 {
1848         azx_dev->opened = 0;
1849 }
1850
1851 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1852 {
1853         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1854         struct snd_pcm_substream *substream = azx_dev->substream;
1855         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1856         struct azx *chip = apcm->chip;
1857
1858         return azx_readl(chip, WALLCLK);
1859 }
1860
1861 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1862                                 bool force, cycle_t last)
1863 {
1864         struct azx_dev *azx_dev = get_azx_dev(substream);
1865         struct timecounter *tc = &azx_dev->azx_tc;
1866         struct cyclecounter *cc = &azx_dev->azx_cc;
1867         u64 nsec;
1868
1869         cc->read = azx_cc_read;
1870         cc->mask = CLOCKSOURCE_MASK(32);
1871
1872         /*
1873          * Converting from 24 MHz to ns means applying a 125/3 factor.
1874          * To avoid any saturation issues in intermediate operations,
1875          * the 125 factor is applied first. The division is applied
1876          * last after reading the timecounter value.
1877          * Applying the 1/3 factor as part of the multiplication
1878          * requires at least 20 bits for a decent precision, however
1879          * overflows occur after about 4 hours or less, not a option.
1880          */
1881
1882         cc->mult = 125; /* saturation after 195 years */
1883         cc->shift = 0;
1884
1885         nsec = 0; /* audio time is elapsed time since trigger */
1886         timecounter_init(tc, cc, nsec);
1887         if (force)
1888                 /*
1889                  * force timecounter to use predefined value,
1890                  * used for synchronized starts
1891                  */
1892                 tc->cycle_last = last;
1893 }
1894
1895 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1896                                 u64 nsec)
1897 {
1898         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1899         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1900         u64 codec_frames, codec_nsecs;
1901
1902         if (!hinfo->ops.get_delay)
1903                 return nsec;
1904
1905         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1906         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1907                               substream->runtime->rate);
1908
1909         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1910                 return nsec + codec_nsecs;
1911
1912         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1913 }
1914
1915 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1916                                 struct timespec *ts)
1917 {
1918         struct azx_dev *azx_dev = get_azx_dev(substream);
1919         u64 nsec;
1920
1921         nsec = timecounter_read(&azx_dev->azx_tc);
1922         nsec = div_u64(nsec, 3); /* can be optimized */
1923         nsec = azx_adjust_codec_delay(substream, nsec);
1924
1925         *ts = ns_to_timespec(nsec);
1926
1927         return 0;
1928 }
1929
1930 static struct snd_pcm_hardware azx_pcm_hw = {
1931         .info =                 (SNDRV_PCM_INFO_MMAP |
1932                                  SNDRV_PCM_INFO_INTERLEAVED |
1933                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1934                                  SNDRV_PCM_INFO_MMAP_VALID |
1935                                  /* No full-resume yet implemented */
1936                                  /* SNDRV_PCM_INFO_RESUME |*/
1937                                  SNDRV_PCM_INFO_PAUSE |
1938                                  SNDRV_PCM_INFO_SYNC_START |
1939                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1940                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1941         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1942         .rates =                SNDRV_PCM_RATE_48000,
1943         .rate_min =             48000,
1944         .rate_max =             48000,
1945         .channels_min =         2,
1946         .channels_max =         2,
1947         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1948         .period_bytes_min =     128,
1949         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1950         .periods_min =          2,
1951         .periods_max =          AZX_MAX_FRAG,
1952         .fifo_size =            0,
1953 };
1954
1955 static int azx_pcm_open(struct snd_pcm_substream *substream)
1956 {
1957         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1958         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1959         struct azx *chip = apcm->chip;
1960         struct azx_dev *azx_dev;
1961         struct snd_pcm_runtime *runtime = substream->runtime;
1962         unsigned long flags;
1963         int err;
1964         int buff_step;
1965
1966         mutex_lock(&chip->open_mutex);
1967         azx_dev = azx_assign_device(chip, substream);
1968         if (azx_dev == NULL) {
1969                 mutex_unlock(&chip->open_mutex);
1970                 return -EBUSY;
1971         }
1972         runtime->hw = azx_pcm_hw;
1973         runtime->hw.channels_min = hinfo->channels_min;
1974         runtime->hw.channels_max = hinfo->channels_max;
1975         runtime->hw.formats = hinfo->formats;
1976         runtime->hw.rates = hinfo->rates;
1977         snd_pcm_limit_hw_rates(runtime);
1978         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1979
1980         /* avoid wrap-around with wall-clock */
1981         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1982                                 20,
1983                                 178000000);
1984
1985         if (chip->align_buffer_size)
1986                 /* constrain buffer sizes to be multiple of 128
1987                    bytes. This is more efficient in terms of memory
1988                    access but isn't required by the HDA spec and
1989                    prevents users from specifying exact period/buffer
1990                    sizes. For example for 44.1kHz, a period size set
1991                    to 20ms will be rounded to 19.59ms. */
1992                 buff_step = 128;
1993         else
1994                 /* Don't enforce steps on buffer sizes, still need to
1995                    be multiple of 4 bytes (HDA spec). Tested on Intel
1996                    HDA controllers, may not work on all devices where
1997                    option needs to be disabled */
1998                 buff_step = 4;
1999
2000         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2001                                    buff_step);
2002         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2003                                    buff_step);
2004         snd_hda_power_up_d3wait(apcm->codec);
2005         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2006         if (err < 0) {
2007                 azx_release_device(azx_dev);
2008                 snd_hda_power_down(apcm->codec);
2009                 mutex_unlock(&chip->open_mutex);
2010                 return err;
2011         }
2012         snd_pcm_limit_hw_rates(runtime);
2013         /* sanity check */
2014         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2015             snd_BUG_ON(!runtime->hw.channels_max) ||
2016             snd_BUG_ON(!runtime->hw.formats) ||
2017             snd_BUG_ON(!runtime->hw.rates)) {
2018                 azx_release_device(azx_dev);
2019                 hinfo->ops.close(hinfo, apcm->codec, substream);
2020                 snd_hda_power_down(apcm->codec);
2021                 mutex_unlock(&chip->open_mutex);
2022                 return -EINVAL;
2023         }
2024
2025         /* disable WALLCLOCK timestamps for capture streams
2026            until we figure out how to handle digital inputs */
2027         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2028                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2029
2030         spin_lock_irqsave(&chip->reg_lock, flags);
2031         azx_dev->substream = substream;
2032         azx_dev->running = 0;
2033         spin_unlock_irqrestore(&chip->reg_lock, flags);
2034
2035         runtime->private_data = azx_dev;
2036         snd_pcm_set_sync(substream);
2037         mutex_unlock(&chip->open_mutex);
2038         return 0;
2039 }
2040
2041 static int azx_pcm_close(struct snd_pcm_substream *substream)
2042 {
2043         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2044         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2045         struct azx *chip = apcm->chip;
2046         struct azx_dev *azx_dev = get_azx_dev(substream);
2047         unsigned long flags;
2048
2049         mutex_lock(&chip->open_mutex);
2050         spin_lock_irqsave(&chip->reg_lock, flags);
2051         azx_dev->substream = NULL;
2052         azx_dev->running = 0;
2053         spin_unlock_irqrestore(&chip->reg_lock, flags);
2054         azx_release_device(azx_dev);
2055         hinfo->ops.close(hinfo, apcm->codec, substream);
2056         snd_hda_power_down(apcm->codec);
2057         mutex_unlock(&chip->open_mutex);
2058         return 0;
2059 }
2060
2061 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2062                              struct snd_pcm_hw_params *hw_params)
2063 {
2064         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2065         struct azx *chip = apcm->chip;
2066         struct azx_dev *azx_dev = get_azx_dev(substream);
2067         int ret;
2068
2069         dsp_lock(azx_dev);
2070         if (dsp_is_locked(azx_dev)) {
2071                 ret = -EBUSY;
2072                 goto unlock;
2073         }
2074
2075         mark_runtime_wc(chip, azx_dev, substream, false);
2076         azx_dev->bufsize = 0;
2077         azx_dev->period_bytes = 0;
2078         azx_dev->format_val = 0;
2079         ret = snd_pcm_lib_malloc_pages(substream,
2080                                         params_buffer_bytes(hw_params));
2081         if (ret < 0)
2082                 goto unlock;
2083         mark_runtime_wc(chip, azx_dev, substream, true);
2084  unlock:
2085         dsp_unlock(azx_dev);
2086         return ret;
2087 }
2088
2089 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2090 {
2091         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2092         struct azx_dev *azx_dev = get_azx_dev(substream);
2093         struct azx *chip = apcm->chip;
2094         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2095
2096         /* reset BDL address */
2097         dsp_lock(azx_dev);
2098         if (!dsp_is_locked(azx_dev)) {
2099                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2100                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2101                 azx_sd_writel(azx_dev, SD_CTL, 0);
2102                 azx_dev->bufsize = 0;
2103                 azx_dev->period_bytes = 0;
2104                 azx_dev->format_val = 0;
2105         }
2106
2107         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2108
2109         mark_runtime_wc(chip, azx_dev, substream, false);
2110         azx_dev->prepared = 0;
2111         dsp_unlock(azx_dev);
2112         return snd_pcm_lib_free_pages(substream);
2113 }
2114
2115 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2116 {
2117         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2118         struct azx *chip = apcm->chip;
2119         struct azx_dev *azx_dev = get_azx_dev(substream);
2120         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2121         struct snd_pcm_runtime *runtime = substream->runtime;
2122         unsigned int bufsize, period_bytes, format_val, stream_tag;
2123         int err;
2124         struct hda_spdif_out *spdif =
2125                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2126         unsigned short ctls = spdif ? spdif->ctls : 0;
2127
2128         dsp_lock(azx_dev);
2129         if (dsp_is_locked(azx_dev)) {
2130                 err = -EBUSY;
2131                 goto unlock;
2132         }
2133
2134         azx_stream_reset(chip, azx_dev);
2135         format_val = snd_hda_calc_stream_format(runtime->rate,
2136                                                 runtime->channels,
2137                                                 runtime->format,
2138                                                 hinfo->maxbps,
2139                                                 ctls);
2140         if (!format_val) {
2141                 snd_printk(KERN_ERR SFX
2142                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2143                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2144                 err = -EINVAL;
2145                 goto unlock;
2146         }
2147
2148         bufsize = snd_pcm_lib_buffer_bytes(substream);
2149         period_bytes = snd_pcm_lib_period_bytes(substream);
2150
2151         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2152                     pci_name(chip->pci), bufsize, format_val);
2153
2154         if (bufsize != azx_dev->bufsize ||
2155             period_bytes != azx_dev->period_bytes ||
2156             format_val != azx_dev->format_val ||
2157             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2158                 azx_dev->bufsize = bufsize;
2159                 azx_dev->period_bytes = period_bytes;
2160                 azx_dev->format_val = format_val;
2161                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2162                 err = azx_setup_periods(chip, substream, azx_dev);
2163                 if (err < 0)
2164                         goto unlock;
2165         }
2166
2167         /* wallclk has 24Mhz clock source */
2168         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2169                                                 runtime->rate) * 1000);
2170         azx_setup_controller(chip, azx_dev);
2171         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2172                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2173         else
2174                 azx_dev->fifo_size = 0;
2175
2176         stream_tag = azx_dev->stream_tag;
2177         /* CA-IBG chips need the playback stream starting from 1 */
2178         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2179             stream_tag > chip->capture_streams)
2180                 stream_tag -= chip->capture_streams;
2181         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2182                                      azx_dev->format_val, substream);
2183
2184  unlock:
2185         if (!err)
2186                 azx_dev->prepared = 1;
2187         dsp_unlock(azx_dev);
2188         return err;
2189 }
2190
2191 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2192 {
2193         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2194         struct azx *chip = apcm->chip;
2195         struct azx_dev *azx_dev;
2196         struct snd_pcm_substream *s;
2197         int rstart = 0, start, nsync = 0, sbits = 0;
2198         int nwait, timeout;
2199
2200         azx_dev = get_azx_dev(substream);
2201         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2202
2203         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2204                 return -EPIPE;
2205
2206         switch (cmd) {
2207         case SNDRV_PCM_TRIGGER_START:
2208                 rstart = 1;
2209         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2210         case SNDRV_PCM_TRIGGER_RESUME:
2211                 start = 1;
2212                 break;
2213         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2214         case SNDRV_PCM_TRIGGER_SUSPEND:
2215         case SNDRV_PCM_TRIGGER_STOP:
2216                 start = 0;
2217                 break;
2218         default:
2219                 return -EINVAL;
2220         }
2221
2222         snd_pcm_group_for_each_entry(s, substream) {
2223                 if (s->pcm->card != substream->pcm->card)
2224                         continue;
2225                 azx_dev = get_azx_dev(s);
2226                 sbits |= 1 << azx_dev->index;
2227                 nsync++;
2228                 snd_pcm_trigger_done(s, substream);
2229         }
2230
2231         spin_lock(&chip->reg_lock);
2232
2233         /* first, set SYNC bits of corresponding streams */
2234         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2235                 azx_writel(chip, OLD_SSYNC,
2236                         azx_readl(chip, OLD_SSYNC) | sbits);
2237         else
2238                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2239
2240         snd_pcm_group_for_each_entry(s, substream) {
2241                 if (s->pcm->card != substream->pcm->card)
2242                         continue;
2243                 azx_dev = get_azx_dev(s);
2244                 if (start) {
2245                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2246                         if (!rstart)
2247                                 azx_dev->start_wallclk -=
2248                                                 azx_dev->period_wallclk;
2249                         azx_stream_start(chip, azx_dev);
2250                 } else {
2251                         azx_stream_stop(chip, azx_dev);
2252                 }
2253                 azx_dev->running = start;
2254         }
2255         spin_unlock(&chip->reg_lock);
2256         if (start) {
2257                 /* wait until all FIFOs get ready */
2258                 for (timeout = 5000; timeout; timeout--) {
2259                         nwait = 0;
2260                         snd_pcm_group_for_each_entry(s, substream) {
2261                                 if (s->pcm->card != substream->pcm->card)
2262                                         continue;
2263                                 azx_dev = get_azx_dev(s);
2264                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2265                                       SD_STS_FIFO_READY))
2266                                         nwait++;
2267                         }
2268                         if (!nwait)
2269                                 break;
2270                         cpu_relax();
2271                 }
2272         } else {
2273                 /* wait until all RUN bits are cleared */
2274                 for (timeout = 5000; timeout; timeout--) {
2275                         nwait = 0;
2276                         snd_pcm_group_for_each_entry(s, substream) {
2277                                 if (s->pcm->card != substream->pcm->card)
2278                                         continue;
2279                                 azx_dev = get_azx_dev(s);
2280                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2281                                     SD_CTL_DMA_START)
2282                                         nwait++;
2283                         }
2284                         if (!nwait)
2285                                 break;
2286                         cpu_relax();
2287                 }
2288         }
2289         spin_lock(&chip->reg_lock);
2290         /* reset SYNC bits */
2291         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2292                 azx_writel(chip, OLD_SSYNC,
2293                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2294         else
2295                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2296         if (start) {
2297                 azx_timecounter_init(substream, 0, 0);
2298                 if (nsync > 1) {
2299                         cycle_t cycle_last;
2300
2301                         /* same start cycle for master and group */
2302                         azx_dev = get_azx_dev(substream);
2303                         cycle_last = azx_dev->azx_tc.cycle_last;
2304
2305                         snd_pcm_group_for_each_entry(s, substream) {
2306                                 if (s->pcm->card != substream->pcm->card)
2307                                         continue;
2308                                 azx_timecounter_init(s, 1, cycle_last);
2309                         }
2310                 }
2311         }
2312         spin_unlock(&chip->reg_lock);
2313         return 0;
2314 }
2315
2316 /* get the current DMA position with correction on VIA chips */
2317 static unsigned int azx_via_get_position(struct azx *chip,
2318                                          struct azx_dev *azx_dev)
2319 {
2320         unsigned int link_pos, mini_pos, bound_pos;
2321         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2322         unsigned int fifo_size;
2323
2324         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2325         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2326                 /* Playback, no problem using link position */
2327                 return link_pos;
2328         }
2329
2330         /* Capture */
2331         /* For new chipset,
2332          * use mod to get the DMA position just like old chipset
2333          */
2334         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2335         mod_dma_pos %= azx_dev->period_bytes;
2336
2337         /* azx_dev->fifo_size can't get FIFO size of in stream.
2338          * Get from base address + offset.
2339          */
2340         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2341
2342         if (azx_dev->insufficient) {
2343                 /* Link position never gather than FIFO size */
2344                 if (link_pos <= fifo_size)
2345                         return 0;
2346
2347                 azx_dev->insufficient = 0;
2348         }
2349
2350         if (link_pos <= fifo_size)
2351                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2352         else
2353                 mini_pos = link_pos - fifo_size;
2354
2355         /* Find nearest previous boudary */
2356         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2357         mod_link_pos = link_pos % azx_dev->period_bytes;
2358         if (mod_link_pos >= fifo_size)
2359                 bound_pos = link_pos - mod_link_pos;
2360         else if (mod_dma_pos >= mod_mini_pos)
2361                 bound_pos = mini_pos - mod_mini_pos;
2362         else {
2363                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2364                 if (bound_pos >= azx_dev->bufsize)
2365                         bound_pos = 0;
2366         }
2367
2368         /* Calculate real DMA position we want */
2369         return bound_pos + mod_dma_pos;
2370 }
2371
2372 static unsigned int azx_get_position(struct azx *chip,
2373                                      struct azx_dev *azx_dev,
2374                                      bool with_check)
2375 {
2376         struct snd_pcm_substream *substream = azx_dev->substream;
2377         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2378         unsigned int pos;
2379         int stream = substream->stream;
2380         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2381         int delay = 0;
2382
2383         switch (chip->position_fix[stream]) {
2384         case POS_FIX_LPIB:
2385                 /* read LPIB */
2386                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2387                 break;
2388         case POS_FIX_VIACOMBO:
2389                 pos = azx_via_get_position(chip, azx_dev);
2390                 break;
2391         default:
2392                 /* use the position buffer */
2393                 pos = le32_to_cpu(*azx_dev->posbuf);
2394                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2395                         if (!pos || pos == (u32)-1) {
2396                                 printk(KERN_WARNING
2397                                        "hda-intel: Invalid position buffer, "
2398                                        "using LPIB read method instead.\n");
2399                                 chip->position_fix[stream] = POS_FIX_LPIB;
2400                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2401                         } else
2402                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2403                 }
2404                 break;
2405         }
2406
2407         if (pos >= azx_dev->bufsize)
2408                 pos = 0;
2409
2410         /* calculate runtime delay from LPIB */
2411         if (substream->runtime &&
2412             chip->position_fix[stream] == POS_FIX_POSBUF &&
2413             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2414                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2415                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2416                         delay = pos - lpib_pos;
2417                 else
2418                         delay = lpib_pos - pos;
2419                 if (delay < 0)
2420                         delay += azx_dev->bufsize;
2421                 if (delay >= azx_dev->period_bytes) {
2422                         snd_printk(KERN_WARNING SFX
2423                                    "%s: Unstable LPIB (%d >= %d); "
2424                                    "disabling LPIB delay counting\n",
2425                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2426                         delay = 0;
2427                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2428                 }
2429                 delay = bytes_to_frames(substream->runtime, delay);
2430         }
2431
2432         if (substream->runtime) {
2433                 if (hinfo->ops.get_delay)
2434                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2435                                                       substream);
2436                 substream->runtime->delay = delay;
2437         }
2438
2439         trace_azx_get_position(chip, azx_dev, pos, delay);
2440         return pos;
2441 }
2442
2443 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2444 {
2445         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2446         struct azx *chip = apcm->chip;
2447         struct azx_dev *azx_dev = get_azx_dev(substream);
2448         return bytes_to_frames(substream->runtime,
2449                                azx_get_position(chip, azx_dev, false));
2450 }
2451
2452 /*
2453  * Check whether the current DMA position is acceptable for updating
2454  * periods.  Returns non-zero if it's OK.
2455  *
2456  * Many HD-audio controllers appear pretty inaccurate about
2457  * the update-IRQ timing.  The IRQ is issued before actually the
2458  * data is processed.  So, we need to process it afterwords in a
2459  * workqueue.
2460  */
2461 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2462 {
2463         u32 wallclk;
2464         unsigned int pos;
2465
2466         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2467         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2468                 return -1;      /* bogus (too early) interrupt */
2469
2470         pos = azx_get_position(chip, azx_dev, true);
2471
2472         if (WARN_ONCE(!azx_dev->period_bytes,
2473                       "hda-intel: zero azx_dev->period_bytes"))
2474                 return -1; /* this shouldn't happen! */
2475         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2476             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2477                 /* NG - it's below the first next period boundary */
2478                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2479         azx_dev->start_wallclk += wallclk;
2480         return 1; /* OK, it's fine */
2481 }
2482
2483 /*
2484  * The work for pending PCM period updates.
2485  */
2486 static void azx_irq_pending_work(struct work_struct *work)
2487 {
2488         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2489         int i, pending, ok;
2490
2491         if (!chip->irq_pending_warned) {
2492                 printk(KERN_WARNING
2493                        "hda-intel: IRQ timing workaround is activated "
2494                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2495                        chip->card->number);
2496                 chip->irq_pending_warned = 1;
2497         }
2498
2499         for (;;) {
2500                 pending = 0;
2501                 spin_lock_irq(&chip->reg_lock);
2502                 for (i = 0; i < chip->num_streams; i++) {
2503                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2504                         if (!azx_dev->irq_pending ||
2505                             !azx_dev->substream ||
2506                             !azx_dev->running)
2507                                 continue;
2508                         ok = azx_position_ok(chip, azx_dev);
2509                         if (ok > 0) {
2510                                 azx_dev->irq_pending = 0;
2511                                 spin_unlock(&chip->reg_lock);
2512                                 snd_pcm_period_elapsed(azx_dev->substream);
2513                                 spin_lock(&chip->reg_lock);
2514                         } else if (ok < 0) {
2515                                 pending = 0;    /* too early */
2516                         } else
2517                                 pending++;
2518                 }
2519                 spin_unlock_irq(&chip->reg_lock);
2520                 if (!pending)
2521                         return;
2522                 msleep(1);
2523         }
2524 }
2525
2526 /* clear irq_pending flags and assure no on-going workq */
2527 static void azx_clear_irq_pending(struct azx *chip)
2528 {
2529         int i;
2530
2531         spin_lock_irq(&chip->reg_lock);
2532         for (i = 0; i < chip->num_streams; i++)
2533                 chip->azx_dev[i].irq_pending = 0;
2534         spin_unlock_irq(&chip->reg_lock);
2535 }
2536
2537 #ifdef CONFIG_X86
2538 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2539                         struct vm_area_struct *area)
2540 {
2541         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2542         struct azx *chip = apcm->chip;
2543         if (!azx_snoop(chip))
2544                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2545         return snd_pcm_lib_default_mmap(substream, area);
2546 }
2547 #else
2548 #define azx_pcm_mmap    NULL
2549 #endif
2550
2551 static struct snd_pcm_ops azx_pcm_ops = {
2552         .open = azx_pcm_open,
2553         .close = azx_pcm_close,
2554         .ioctl = snd_pcm_lib_ioctl,
2555         .hw_params = azx_pcm_hw_params,
2556         .hw_free = azx_pcm_hw_free,
2557         .prepare = azx_pcm_prepare,
2558         .trigger = azx_pcm_trigger,
2559         .pointer = azx_pcm_pointer,
2560         .wall_clock =  azx_get_wallclock_tstamp,
2561         .mmap = azx_pcm_mmap,
2562         .page = snd_pcm_sgbuf_ops_page,
2563 };
2564
2565 static void azx_pcm_free(struct snd_pcm *pcm)
2566 {
2567         struct azx_pcm *apcm = pcm->private_data;
2568         if (apcm) {
2569                 list_del(&apcm->list);
2570                 kfree(apcm);
2571         }
2572 }
2573
2574 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2575
2576 static int
2577 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2578                       struct hda_pcm *cpcm)
2579 {
2580         struct azx *chip = bus->private_data;
2581         struct snd_pcm *pcm;
2582         struct azx_pcm *apcm;
2583         int pcm_dev = cpcm->device;
2584         unsigned int size;
2585         int s, err;
2586
2587         list_for_each_entry(apcm, &chip->pcm_list, list) {
2588                 if (apcm->pcm->device == pcm_dev) {
2589                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2590                                    pci_name(chip->pci), pcm_dev);
2591                         return -EBUSY;
2592                 }
2593         }
2594         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2595                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2596                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2597                           &pcm);
2598         if (err < 0)
2599                 return err;
2600         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2601         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2602         if (apcm == NULL)
2603                 return -ENOMEM;
2604         apcm->chip = chip;
2605         apcm->pcm = pcm;
2606         apcm->codec = codec;
2607         pcm->private_data = apcm;
2608         pcm->private_free = azx_pcm_free;
2609         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2610                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2611         list_add_tail(&apcm->list, &chip->pcm_list);
2612         cpcm->pcm = pcm;
2613         for (s = 0; s < 2; s++) {
2614                 apcm->hinfo[s] = &cpcm->stream[s];
2615                 if (cpcm->stream[s].substreams)
2616                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2617         }
2618         /* buffer pre-allocation */
2619         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2620         if (size > MAX_PREALLOC_SIZE)
2621                 size = MAX_PREALLOC_SIZE;
2622         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2623                                               snd_dma_pci_data(chip->pci),
2624                                               size, MAX_PREALLOC_SIZE);
2625         return 0;
2626 }
2627
2628 /*
2629  * mixer creation - all stuff is implemented in hda module
2630  */
2631 static int azx_mixer_create(struct azx *chip)
2632 {
2633         return snd_hda_build_controls(chip->bus);
2634 }
2635
2636
2637 /*
2638  * initialize SD streams
2639  */
2640 static int azx_init_stream(struct azx *chip)
2641 {
2642         int i;
2643
2644         /* initialize each stream (aka device)
2645          * assign the starting bdl address to each stream (device)
2646          * and initialize
2647          */
2648         for (i = 0; i < chip->num_streams; i++) {
2649                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2650                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2651                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2652                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2653                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2654                 azx_dev->sd_int_sta_mask = 1 << i;
2655                 /* stream tag: must be non-zero and unique */
2656                 azx_dev->index = i;
2657                 azx_dev->stream_tag = i + 1;
2658         }
2659
2660         return 0;
2661 }
2662
2663 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2664 {
2665         if (request_irq(chip->pci->irq, azx_interrupt,
2666                         chip->msi ? 0 : IRQF_SHARED,
2667                         KBUILD_MODNAME, chip)) {
2668                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2669                        "disabling device\n", chip->pci->irq);
2670                 if (do_disconnect)
2671                         snd_card_disconnect(chip->card);
2672                 return -1;
2673         }
2674         chip->irq = chip->pci->irq;
2675         pci_intx(chip->pci, !chip->msi);
2676         return 0;
2677 }
2678
2679
2680 static void azx_stop_chip(struct azx *chip)
2681 {
2682         if (!chip->initialized)
2683                 return;
2684
2685         /* disable interrupts */
2686         azx_int_disable(chip);
2687         azx_int_clear(chip);
2688
2689         /* disable CORB/RIRB */
2690         azx_free_cmd_io(chip);
2691
2692         /* disable position buffer */
2693         azx_writel(chip, DPLBASE, 0);
2694         azx_writel(chip, DPUBASE, 0);
2695
2696         chip->initialized = 0;
2697 }
2698
2699 #ifdef CONFIG_SND_HDA_DSP_LOADER
2700 /*
2701  * DSP loading code (e.g. for CA0132)
2702  */
2703
2704 /* use the first stream for loading DSP */
2705 static struct azx_dev *
2706 azx_get_dsp_loader_dev(struct azx *chip)
2707 {
2708         return &chip->azx_dev[chip->playback_index_offset];
2709 }
2710
2711 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2712                                 unsigned int byte_size,
2713                                 struct snd_dma_buffer *bufp)
2714 {
2715         u32 *bdl;
2716         struct azx *chip = bus->private_data;
2717         struct azx_dev *azx_dev;
2718         int err;
2719
2720         azx_dev = azx_get_dsp_loader_dev(chip);
2721
2722         dsp_lock(azx_dev);
2723         spin_lock_irq(&chip->reg_lock);
2724         if (azx_dev->running || azx_dev->locked) {
2725                 spin_unlock_irq(&chip->reg_lock);
2726                 err = -EBUSY;
2727                 goto unlock;
2728         }
2729         azx_dev->prepared = 0;
2730         chip->saved_azx_dev = *azx_dev;
2731         azx_dev->locked = 1;
2732         spin_unlock_irq(&chip->reg_lock);
2733
2734         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2735                                   snd_dma_pci_data(chip->pci),
2736                                   byte_size, bufp);
2737         if (err < 0)
2738                 goto err_alloc;
2739
2740         mark_pages_wc(chip, bufp, true);
2741         azx_dev->bufsize = byte_size;
2742         azx_dev->period_bytes = byte_size;
2743         azx_dev->format_val = format;
2744
2745         azx_stream_reset(chip, azx_dev);
2746
2747         /* reset BDL address */
2748         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2749         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2750
2751         azx_dev->frags = 0;
2752         bdl = (u32 *)azx_dev->bdl.area;
2753         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2754         if (err < 0)
2755                 goto error;
2756
2757         azx_setup_controller(chip, azx_dev);
2758         dsp_unlock(azx_dev);
2759         return azx_dev->stream_tag;
2760
2761  error:
2762         mark_pages_wc(chip, bufp, false);
2763         snd_dma_free_pages(bufp);
2764  err_alloc:
2765         spin_lock_irq(&chip->reg_lock);
2766         if (azx_dev->opened)
2767                 *azx_dev = chip->saved_azx_dev;
2768         azx_dev->locked = 0;
2769         spin_unlock_irq(&chip->reg_lock);
2770  unlock:
2771         dsp_unlock(azx_dev);
2772         return err;
2773 }
2774
2775 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2776 {
2777         struct azx *chip = bus->private_data;
2778         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2779
2780         if (start)
2781                 azx_stream_start(chip, azx_dev);
2782         else
2783                 azx_stream_stop(chip, azx_dev);
2784         azx_dev->running = start;
2785 }
2786
2787 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2788                                  struct snd_dma_buffer *dmab)
2789 {
2790         struct azx *chip = bus->private_data;
2791         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2792
2793         if (!dmab->area || !azx_dev->locked)
2794                 return;
2795
2796         dsp_lock(azx_dev);
2797         /* reset BDL address */
2798         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2799         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2800         azx_sd_writel(azx_dev, SD_CTL, 0);
2801         azx_dev->bufsize = 0;
2802         azx_dev->period_bytes = 0;
2803         azx_dev->format_val = 0;
2804
2805         mark_pages_wc(chip, dmab, false);
2806         snd_dma_free_pages(dmab);
2807         dmab->area = NULL;
2808
2809         spin_lock_irq(&chip->reg_lock);
2810         if (azx_dev->opened)
2811                 *azx_dev = chip->saved_azx_dev;
2812         azx_dev->locked = 0;
2813         spin_unlock_irq(&chip->reg_lock);
2814         dsp_unlock(azx_dev);
2815 }
2816 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2817
2818 #ifdef CONFIG_PM
2819 /* power-up/down the controller */
2820 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2821 {
2822         struct azx *chip = bus->private_data;
2823
2824         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2825                 return;
2826
2827         if (power_up)
2828                 pm_runtime_get_sync(&chip->pci->dev);
2829         else
2830                 pm_runtime_put_sync(&chip->pci->dev);
2831 }
2832
2833 static DEFINE_MUTEX(card_list_lock);
2834 static LIST_HEAD(card_list);
2835
2836 static void azx_add_card_list(struct azx *chip)
2837 {
2838         mutex_lock(&card_list_lock);
2839         list_add(&chip->list, &card_list);
2840         mutex_unlock(&card_list_lock);
2841 }
2842
2843 static void azx_del_card_list(struct azx *chip)
2844 {
2845         mutex_lock(&card_list_lock);
2846         list_del_init(&chip->list);
2847         mutex_unlock(&card_list_lock);
2848 }
2849
2850 /* trigger power-save check at writing parameter */
2851 static int param_set_xint(const char *val, const struct kernel_param *kp)
2852 {
2853         struct azx *chip;
2854         struct hda_codec *c;
2855         int prev = power_save;
2856         int ret = param_set_int(val, kp);
2857
2858         if (ret || prev == power_save)
2859                 return ret;
2860
2861         mutex_lock(&card_list_lock);
2862         list_for_each_entry(chip, &card_list, list) {
2863                 if (!chip->bus || chip->disabled)
2864                         continue;
2865                 list_for_each_entry(c, &chip->bus->codec_list, list)
2866                         snd_hda_power_sync(c);
2867         }
2868         mutex_unlock(&card_list_lock);
2869         return 0;
2870 }
2871 #else
2872 #define azx_add_card_list(chip) /* NOP */
2873 #define azx_del_card_list(chip) /* NOP */
2874 #endif /* CONFIG_PM */
2875
2876 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2877 /*
2878  * power management
2879  */
2880 static int azx_suspend(struct device *dev)
2881 {
2882         struct pci_dev *pci = to_pci_dev(dev);
2883         struct snd_card *card = dev_get_drvdata(dev);
2884         struct azx *chip = card->private_data;
2885         struct azx_pcm *p;
2886
2887         if (chip->disabled)
2888                 return 0;
2889
2890         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2891         azx_clear_irq_pending(chip);
2892         list_for_each_entry(p, &chip->pcm_list, list)
2893                 snd_pcm_suspend_all(p->pcm);
2894         if (chip->initialized)
2895                 snd_hda_suspend(chip->bus);
2896         azx_stop_chip(chip);
2897         if (chip->irq >= 0) {
2898                 free_irq(chip->irq, chip);
2899                 chip->irq = -1;
2900         }
2901         if (chip->msi)
2902                 pci_disable_msi(chip->pci);
2903         pci_disable_device(pci);
2904         pci_save_state(pci);
2905         pci_set_power_state(pci, PCI_D3hot);
2906         return 0;
2907 }
2908
2909 static int azx_resume(struct device *dev)
2910 {
2911         struct pci_dev *pci = to_pci_dev(dev);
2912         struct snd_card *card = dev_get_drvdata(dev);
2913         struct azx *chip = card->private_data;
2914
2915         if (chip->disabled)
2916                 return 0;
2917
2918         pci_set_power_state(pci, PCI_D0);
2919         pci_restore_state(pci);
2920         if (pci_enable_device(pci) < 0) {
2921                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2922                        "disabling device\n");
2923                 snd_card_disconnect(card);
2924                 return -EIO;
2925         }
2926         pci_set_master(pci);
2927         if (chip->msi)
2928                 if (pci_enable_msi(pci) < 0)
2929                         chip->msi = 0;
2930         if (azx_acquire_irq(chip, 1) < 0)
2931                 return -EIO;
2932         azx_init_pci(chip);
2933
2934         azx_init_chip(chip, 1);
2935
2936         snd_hda_resume(chip->bus);
2937         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2938         return 0;
2939 }
2940 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2941
2942 #ifdef CONFIG_PM_RUNTIME
2943 static int azx_runtime_suspend(struct device *dev)
2944 {
2945         struct snd_card *card = dev_get_drvdata(dev);
2946         struct azx *chip = card->private_data;
2947
2948         azx_stop_chip(chip);
2949         azx_clear_irq_pending(chip);
2950         return 0;
2951 }
2952
2953 static int azx_runtime_resume(struct device *dev)
2954 {
2955         struct snd_card *card = dev_get_drvdata(dev);
2956         struct azx *chip = card->private_data;
2957
2958         azx_init_pci(chip);
2959         azx_init_chip(chip, 1);
2960         return 0;
2961 }
2962
2963 static int azx_runtime_idle(struct device *dev)
2964 {
2965         struct snd_card *card = dev_get_drvdata(dev);
2966         struct azx *chip = card->private_data;
2967
2968         if (!power_save_controller ||
2969             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2970                 return -EBUSY;
2971
2972         return 0;
2973 }
2974
2975 #endif /* CONFIG_PM_RUNTIME */
2976
2977 #ifdef CONFIG_PM
2978 static const struct dev_pm_ops azx_pm = {
2979         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2980         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2981 };
2982
2983 #define AZX_PM_OPS      &azx_pm
2984 #else
2985 #define AZX_PM_OPS      NULL
2986 #endif /* CONFIG_PM */
2987
2988
2989 /*
2990  * reboot notifier for hang-up problem at power-down
2991  */
2992 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2993 {
2994         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2995         snd_hda_bus_reboot_notify(chip->bus);
2996         azx_stop_chip(chip);
2997         return NOTIFY_OK;
2998 }
2999
3000 static void azx_notifier_register(struct azx *chip)
3001 {
3002         chip->reboot_notifier.notifier_call = azx_halt;
3003         register_reboot_notifier(&chip->reboot_notifier);
3004 }
3005
3006 static void azx_notifier_unregister(struct azx *chip)
3007 {
3008         if (chip->reboot_notifier.notifier_call)
3009                 unregister_reboot_notifier(&chip->reboot_notifier);
3010 }
3011
3012 static int azx_first_init(struct azx *chip);
3013 static int azx_probe_continue(struct azx *chip);
3014
3015 #ifdef SUPPORT_VGA_SWITCHEROO
3016 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3017
3018 static void azx_vs_set_state(struct pci_dev *pci,
3019                              enum vga_switcheroo_state state)
3020 {
3021         struct snd_card *card = pci_get_drvdata(pci);
3022         struct azx *chip = card->private_data;
3023         bool disabled;
3024
3025         wait_for_completion(&chip->probe_wait);
3026         if (chip->init_failed)
3027                 return;
3028
3029         disabled = (state == VGA_SWITCHEROO_OFF);
3030         if (chip->disabled == disabled)
3031                 return;
3032
3033         if (!chip->bus) {
3034                 chip->disabled = disabled;
3035                 if (!disabled) {
3036                         snd_printk(KERN_INFO SFX
3037                                    "%s: Start delayed initialization\n",
3038                                    pci_name(chip->pci));
3039                         if (azx_first_init(chip) < 0 ||
3040                             azx_probe_continue(chip) < 0) {
3041                                 snd_printk(KERN_ERR SFX
3042                                            "%s: initialization error\n",
3043                                            pci_name(chip->pci));
3044                                 chip->init_failed = true;
3045                         }
3046                 }
3047         } else {
3048                 snd_printk(KERN_INFO SFX
3049                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3050                            disabled ? "Disabling" : "Enabling");
3051                 if (disabled) {
3052                         azx_suspend(&pci->dev);
3053                         chip->disabled = true;
3054                         if (snd_hda_lock_devices(chip->bus))
3055                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3056                                            pci_name(chip->pci));
3057                 } else {
3058                         snd_hda_unlock_devices(chip->bus);
3059                         chip->disabled = false;
3060                         azx_resume(&pci->dev);
3061                 }
3062         }
3063 }
3064
3065 static bool azx_vs_can_switch(struct pci_dev *pci)
3066 {
3067         struct snd_card *card = pci_get_drvdata(pci);
3068         struct azx *chip = card->private_data;
3069
3070         wait_for_completion(&chip->probe_wait);
3071         if (chip->init_failed)
3072                 return false;
3073         if (chip->disabled || !chip->bus)
3074                 return true;
3075         if (snd_hda_lock_devices(chip->bus))
3076                 return false;
3077         snd_hda_unlock_devices(chip->bus);
3078         return true;
3079 }
3080
3081 static void init_vga_switcheroo(struct azx *chip)
3082 {
3083         struct pci_dev *p = get_bound_vga(chip->pci);
3084         if (p) {
3085                 snd_printk(KERN_INFO SFX
3086                            "%s: Handle VGA-switcheroo audio client\n",
3087                            pci_name(chip->pci));
3088                 chip->use_vga_switcheroo = 1;
3089                 pci_dev_put(p);
3090         }
3091 }
3092
3093 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3094         .set_gpu_state = azx_vs_set_state,
3095         .can_switch = azx_vs_can_switch,
3096 };
3097
3098 static int register_vga_switcheroo(struct azx *chip)
3099 {
3100         int err;
3101
3102         if (!chip->use_vga_switcheroo)
3103                 return 0;
3104         /* FIXME: currently only handling DIS controller
3105          * is there any machine with two switchable HDMI audio controllers?
3106          */
3107         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3108                                                     VGA_SWITCHEROO_DIS,
3109                                                     chip->bus != NULL);
3110         if (err < 0)
3111                 return err;
3112         chip->vga_switcheroo_registered = 1;
3113         return 0;
3114 }
3115 #else
3116 #define init_vga_switcheroo(chip)               /* NOP */
3117 #define register_vga_switcheroo(chip)           0
3118 #define check_hdmi_disabled(pci)        false
3119 #endif /* SUPPORT_VGA_SWITCHER */
3120
3121 /*
3122  * destructor
3123  */
3124 static int azx_free(struct azx *chip)
3125 {
3126         int i;
3127
3128         azx_del_card_list(chip);
3129
3130         azx_notifier_unregister(chip);
3131
3132         chip->init_failed = 1; /* to be sure */
3133         complete_all(&chip->probe_wait);
3134
3135         if (use_vga_switcheroo(chip)) {
3136                 if (chip->disabled && chip->bus)
3137                         snd_hda_unlock_devices(chip->bus);
3138                 if (chip->vga_switcheroo_registered)
3139                         vga_switcheroo_unregister_client(chip->pci);
3140         }
3141
3142         if (chip->initialized) {
3143                 azx_clear_irq_pending(chip);
3144                 for (i = 0; i < chip->num_streams; i++)
3145                         azx_stream_stop(chip, &chip->azx_dev[i]);
3146                 azx_stop_chip(chip);
3147         }
3148
3149         if (chip->irq >= 0)
3150                 free_irq(chip->irq, (void*)chip);
3151         if (chip->msi)
3152                 pci_disable_msi(chip->pci);
3153         if (chip->remap_addr)
3154                 iounmap(chip->remap_addr);
3155
3156         if (chip->azx_dev) {
3157                 for (i = 0; i < chip->num_streams; i++)
3158                         if (chip->azx_dev[i].bdl.area) {
3159                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3160                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3161                         }
3162         }
3163         if (chip->rb.area) {
3164                 mark_pages_wc(chip, &chip->rb, false);
3165                 snd_dma_free_pages(&chip->rb);
3166         }
3167         if (chip->posbuf.area) {
3168                 mark_pages_wc(chip, &chip->posbuf, false);
3169                 snd_dma_free_pages(&chip->posbuf);
3170         }
3171         if (chip->region_requested)
3172                 pci_release_regions(chip->pci);
3173         pci_disable_device(chip->pci);
3174         kfree(chip->azx_dev);
3175 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3176         if (chip->fw)
3177                 release_firmware(chip->fw);
3178 #endif
3179         kfree(chip);
3180
3181         return 0;
3182 }
3183
3184 static int azx_dev_free(struct snd_device *device)
3185 {
3186         return azx_free(device->device_data);
3187 }
3188
3189 #ifdef SUPPORT_VGA_SWITCHEROO
3190 /*
3191  * Check of disabled HDMI controller by vga-switcheroo
3192  */
3193 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3194 {
3195         struct pci_dev *p;
3196
3197         /* check only discrete GPU */
3198         switch (pci->vendor) {
3199         case PCI_VENDOR_ID_ATI:
3200         case PCI_VENDOR_ID_AMD:
3201         case PCI_VENDOR_ID_NVIDIA:
3202                 if (pci->devfn == 1) {
3203                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3204                                                         pci->bus->number, 0);
3205                         if (p) {
3206                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3207                                         return p;
3208                                 pci_dev_put(p);
3209                         }
3210                 }
3211                 break;
3212         }
3213         return NULL;
3214 }
3215
3216 static bool check_hdmi_disabled(struct pci_dev *pci)
3217 {
3218         bool vga_inactive = false;
3219         struct pci_dev *p = get_bound_vga(pci);
3220
3221         if (p) {
3222                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3223                         vga_inactive = true;
3224                 pci_dev_put(p);
3225         }
3226         return vga_inactive;
3227 }
3228 #endif /* SUPPORT_VGA_SWITCHEROO */
3229
3230 /*
3231  * white/black-listing for position_fix
3232  */
3233 static struct snd_pci_quirk position_fix_list[] = {
3234         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3235         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3236         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3237         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3238         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3239         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3240         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3241         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3242         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3243         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3244         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3245         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3246         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3247         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3248         {}
3249 };
3250
3251 static int check_position_fix(struct azx *chip, int fix)
3252 {
3253         const struct snd_pci_quirk *q;
3254
3255         switch (fix) {
3256         case POS_FIX_AUTO:
3257         case POS_FIX_LPIB:
3258         case POS_FIX_POSBUF:
3259         case POS_FIX_VIACOMBO:
3260         case POS_FIX_COMBO:
3261                 return fix;
3262         }
3263
3264         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3265         if (q) {
3266                 printk(KERN_INFO
3267                        "hda_intel: position_fix set to %d "
3268                        "for device %04x:%04x\n",
3269                        q->value, q->subvendor, q->subdevice);
3270                 return q->value;
3271         }
3272
3273         /* Check VIA/ATI HD Audio Controller exist */
3274         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3275                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3276                 return POS_FIX_VIACOMBO;
3277         }
3278         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3279                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3280                 return POS_FIX_LPIB;
3281         }
3282         return POS_FIX_AUTO;
3283 }
3284
3285 /*
3286  * black-lists for probe_mask
3287  */
3288 static struct snd_pci_quirk probe_mask_list[] = {
3289         /* Thinkpad often breaks the controller communication when accessing
3290          * to the non-working (or non-existing) modem codec slot.
3291          */
3292         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3293         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3294         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3295         /* broken BIOS */
3296         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3297         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3298         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3299         /* forced codec slots */
3300         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3301         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3302         /* WinFast VP200 H (Teradici) user reported broken communication */
3303         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3304         {}
3305 };
3306
3307 #define AZX_FORCE_CODEC_MASK    0x100
3308
3309 static void check_probe_mask(struct azx *chip, int dev)
3310 {
3311         const struct snd_pci_quirk *q;
3312
3313         chip->codec_probe_mask = probe_mask[dev];
3314         if (chip->codec_probe_mask == -1) {
3315                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3316                 if (q) {
3317                         printk(KERN_INFO
3318                                "hda_intel: probe_mask set to 0x%x "
3319                                "for device %04x:%04x\n",
3320                                q->value, q->subvendor, q->subdevice);
3321                         chip->codec_probe_mask = q->value;
3322                 }
3323         }
3324
3325         /* check forced option */
3326         if (chip->codec_probe_mask != -1 &&
3327             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3328                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3329                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3330                        chip->codec_mask);
3331         }
3332 }
3333
3334 /*
3335  * white/black-list for enable_msi
3336  */
3337 static struct snd_pci_quirk msi_black_list[] = {
3338         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3339         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3340         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3341         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3342         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3343         {}
3344 };
3345
3346 static void check_msi(struct azx *chip)
3347 {
3348         const struct snd_pci_quirk *q;
3349
3350         if (enable_msi >= 0) {
3351                 chip->msi = !!enable_msi;
3352                 return;
3353         }
3354         chip->msi = 1;  /* enable MSI as default */
3355         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3356         if (q) {
3357                 printk(KERN_INFO
3358                        "hda_intel: msi for device %04x:%04x set to %d\n",
3359                        q->subvendor, q->subdevice, q->value);
3360                 chip->msi = q->value;
3361                 return;
3362         }
3363
3364         /* NVidia chipsets seem to cause troubles with MSI */
3365         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3366                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3367                 chip->msi = 0;
3368         }
3369 }
3370
3371 /* check the snoop mode availability */
3372 static void azx_check_snoop_available(struct azx *chip)
3373 {
3374         bool snoop = chip->snoop;
3375
3376         switch (chip->driver_type) {
3377         case AZX_DRIVER_VIA:
3378                 /* force to non-snoop mode for a new VIA controller
3379                  * when BIOS is set
3380                  */
3381                 if (snoop) {
3382                         u8 val;
3383                         pci_read_config_byte(chip->pci, 0x42, &val);
3384                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3385                                 snoop = false;
3386                 }
3387                 break;
3388         case AZX_DRIVER_ATIHDMI_NS:
3389                 /* new ATI HDMI requires non-snoop */
3390                 snoop = false;
3391                 break;
3392         case AZX_DRIVER_CTHDA:
3393                 snoop = false;
3394                 break;
3395         }
3396
3397         if (snoop != chip->snoop) {
3398                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3399                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3400                 chip->snoop = snoop;
3401         }
3402 }
3403
3404 /*
3405  * constructor
3406  */
3407 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3408                       int dev, unsigned int driver_caps,
3409                       struct azx **rchip)
3410 {
3411         static struct snd_device_ops ops = {
3412                 .dev_free = azx_dev_free,
3413         };
3414         struct azx *chip;
3415         int err;
3416
3417         *rchip = NULL;
3418
3419         err = pci_enable_device(pci);
3420         if (err < 0)
3421                 return err;
3422
3423         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3424         if (!chip) {
3425                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3426                 pci_disable_device(pci);
3427                 return -ENOMEM;
3428         }
3429
3430         spin_lock_init(&chip->reg_lock);
3431         mutex_init(&chip->open_mutex);
3432         chip->card = card;
3433         chip->pci = pci;
3434         chip->irq = -1;
3435         chip->driver_caps = driver_caps;
3436         chip->driver_type = driver_caps & 0xff;
3437         check_msi(chip);
3438         chip->dev_index = dev;
3439         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3440         INIT_LIST_HEAD(&chip->pcm_list);
3441         INIT_LIST_HEAD(&chip->list);
3442         init_vga_switcheroo(chip);
3443         init_completion(&chip->probe_wait);
3444
3445         chip->position_fix[0] = chip->position_fix[1] =
3446                 check_position_fix(chip, position_fix[dev]);
3447         /* combo mode uses LPIB for playback */
3448         if (chip->position_fix[0] == POS_FIX_COMBO) {
3449                 chip->position_fix[0] = POS_FIX_LPIB;
3450                 chip->position_fix[1] = POS_FIX_AUTO;
3451         }
3452
3453         check_probe_mask(chip, dev);
3454
3455         chip->single_cmd = single_cmd;
3456         chip->snoop = hda_snoop;
3457         azx_check_snoop_available(chip);
3458
3459         if (bdl_pos_adj[dev] < 0) {
3460                 switch (chip->driver_type) {
3461                 case AZX_DRIVER_ICH:
3462                 case AZX_DRIVER_PCH:
3463                         bdl_pos_adj[dev] = 1;
3464                         break;
3465                 default:
3466                         bdl_pos_adj[dev] = 32;
3467                         break;
3468                 }
3469         }
3470
3471         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3472         if (err < 0) {
3473                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3474                    pci_name(chip->pci));
3475                 azx_free(chip);
3476                 return err;
3477         }
3478
3479         *rchip = chip;
3480         return 0;
3481 }
3482
3483 static int azx_first_init(struct azx *chip)
3484 {
3485         int dev = chip->dev_index;
3486         struct pci_dev *pci = chip->pci;
3487         struct snd_card *card = chip->card;
3488         int i, err;
3489         unsigned short gcap;
3490
3491 #if BITS_PER_LONG != 64
3492         /* Fix up base address on ULI M5461 */
3493         if (chip->driver_type == AZX_DRIVER_ULI) {
3494                 u16 tmp3;
3495                 pci_read_config_word(pci, 0x40, &tmp3);
3496                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3497                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3498         }
3499 #endif
3500
3501         err = pci_request_regions(pci, "ICH HD audio");
3502         if (err < 0)
3503                 return err;
3504         chip->region_requested = 1;
3505
3506         chip->addr = pci_resource_start(pci, 0);
3507         chip->remap_addr = pci_ioremap_bar(pci, 0);
3508         if (chip->remap_addr == NULL) {
3509                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3510                 return -ENXIO;
3511         }
3512
3513         if (chip->msi)
3514                 if (pci_enable_msi(pci) < 0)
3515                         chip->msi = 0;
3516
3517         if (azx_acquire_irq(chip, 0) < 0)
3518                 return -EBUSY;
3519
3520         pci_set_master(pci);
3521         synchronize_irq(chip->irq);
3522
3523         gcap = azx_readw(chip, GCAP);
3524         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3525
3526         /* disable SB600 64bit support for safety */
3527         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3528                 struct pci_dev *p_smbus;
3529                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3530                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3531                                          NULL);
3532                 if (p_smbus) {
3533                         if (p_smbus->revision < 0x30)
3534                                 gcap &= ~ICH6_GCAP_64OK;
3535                         pci_dev_put(p_smbus);
3536                 }
3537         }
3538
3539         /* disable 64bit DMA address on some devices */
3540         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3541                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3542                 gcap &= ~ICH6_GCAP_64OK;
3543         }
3544
3545         /* disable buffer size rounding to 128-byte multiples if supported */
3546         if (align_buffer_size >= 0)
3547                 chip->align_buffer_size = !!align_buffer_size;
3548         else {
3549                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3550                         chip->align_buffer_size = 0;
3551                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3552                         chip->align_buffer_size = 1;
3553                 else
3554                         chip->align_buffer_size = 1;
3555         }
3556
3557         /* allow 64bit DMA address if supported by H/W */
3558         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3559                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3560         else {
3561                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3562                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3563         }
3564
3565         /* read number of streams from GCAP register instead of using
3566          * hardcoded value
3567          */
3568         chip->capture_streams = (gcap >> 8) & 0x0f;
3569         chip->playback_streams = (gcap >> 12) & 0x0f;
3570         if (!chip->playback_streams && !chip->capture_streams) {
3571                 /* gcap didn't give any info, switching to old method */
3572
3573                 switch (chip->driver_type) {
3574                 case AZX_DRIVER_ULI:
3575                         chip->playback_streams = ULI_NUM_PLAYBACK;
3576                         chip->capture_streams = ULI_NUM_CAPTURE;
3577                         break;
3578                 case AZX_DRIVER_ATIHDMI:
3579                 case AZX_DRIVER_ATIHDMI_NS:
3580                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3581                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3582                         break;
3583                 case AZX_DRIVER_GENERIC:
3584                 default:
3585                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3586                         chip->capture_streams = ICH6_NUM_CAPTURE;
3587                         break;
3588                 }
3589         }
3590         chip->capture_index_offset = 0;
3591         chip->playback_index_offset = chip->capture_streams;
3592         chip->num_streams = chip->playback_streams + chip->capture_streams;
3593         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3594                                 GFP_KERNEL);
3595         if (!chip->azx_dev) {
3596                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3597                 return -ENOMEM;
3598         }
3599
3600         for (i = 0; i < chip->num_streams; i++) {
3601                 dsp_lock_init(&chip->azx_dev[i]);
3602                 /* allocate memory for the BDL for each stream */
3603                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3604                                           snd_dma_pci_data(chip->pci),
3605                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3606                 if (err < 0) {
3607                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3608                         return -ENOMEM;
3609                 }
3610                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3611         }
3612         /* allocate memory for the position buffer */
3613         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3614                                   snd_dma_pci_data(chip->pci),
3615                                   chip->num_streams * 8, &chip->posbuf);
3616         if (err < 0) {
3617                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3618                 return -ENOMEM;
3619         }
3620         mark_pages_wc(chip, &chip->posbuf, true);
3621         /* allocate CORB/RIRB */
3622         err = azx_alloc_cmd_io(chip);
3623         if (err < 0)
3624                 return err;
3625
3626         /* initialize streams */
3627         azx_init_stream(chip);
3628
3629         /* initialize chip */
3630         azx_init_pci(chip);
3631         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3632
3633         /* codec detection */
3634         if (!chip->codec_mask) {
3635                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3636                 return -ENODEV;
3637         }
3638
3639         strcpy(card->driver, "HDA-Intel");
3640         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3641                 sizeof(card->shortname));
3642         snprintf(card->longname, sizeof(card->longname),
3643                  "%s at 0x%lx irq %i",
3644                  card->shortname, chip->addr, chip->irq);
3645
3646         return 0;
3647 }
3648
3649 static void power_down_all_codecs(struct azx *chip)
3650 {
3651 #ifdef CONFIG_PM
3652         /* The codecs were powered up in snd_hda_codec_new().
3653          * Now all initialization done, so turn them down if possible
3654          */
3655         struct hda_codec *codec;
3656         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3657                 snd_hda_power_down(codec);
3658         }
3659 #endif
3660 }
3661
3662 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3663 /* callback from request_firmware_nowait() */
3664 static void azx_firmware_cb(const struct firmware *fw, void *context)
3665 {
3666         struct snd_card *card = context;
3667         struct azx *chip = card->private_data;
3668         struct pci_dev *pci = chip->pci;
3669
3670         if (!fw) {
3671                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3672                            pci_name(chip->pci));
3673                 goto error;
3674         }
3675
3676         chip->fw = fw;
3677         if (!chip->disabled) {
3678                 /* continue probing */
3679                 if (azx_probe_continue(chip))
3680                         goto error;
3681         }
3682         return; /* OK */
3683
3684  error:
3685         snd_card_free(card);
3686         pci_set_drvdata(pci, NULL);
3687 }
3688 #endif
3689
3690 static int azx_probe(struct pci_dev *pci,
3691                      const struct pci_device_id *pci_id)
3692 {
3693         static int dev;
3694         struct snd_card *card;
3695         struct azx *chip;
3696         bool probe_now;
3697         int err;
3698
3699         if (dev >= SNDRV_CARDS)
3700                 return -ENODEV;
3701         if (!enable[dev]) {
3702                 dev++;
3703                 return -ENOENT;
3704         }
3705
3706         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3707         if (err < 0) {
3708                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3709                 return err;
3710         }
3711
3712         snd_card_set_dev(card, &pci->dev);
3713
3714         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3715         if (err < 0)
3716                 goto out_free;
3717         card->private_data = chip;
3718
3719         pci_set_drvdata(pci, card);
3720
3721         err = register_vga_switcheroo(chip);
3722         if (err < 0) {
3723                 snd_printk(KERN_ERR SFX
3724                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3725                 goto out_free;
3726         }
3727
3728         if (check_hdmi_disabled(pci)) {
3729                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3730                            pci_name(pci));
3731                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3732                 chip->disabled = true;
3733         }
3734
3735         probe_now = !chip->disabled;
3736         if (probe_now) {
3737                 err = azx_first_init(chip);
3738                 if (err < 0)
3739                         goto out_free;
3740         }
3741
3742 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3743         if (patch[dev] && *patch[dev]) {
3744                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3745                            pci_name(pci), patch[dev]);
3746                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3747                                               &pci->dev, GFP_KERNEL, card,
3748                                               azx_firmware_cb);
3749                 if (err < 0)
3750                         goto out_free;
3751                 probe_now = false; /* continued in azx_firmware_cb() */
3752         }
3753 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3754
3755         if (probe_now) {
3756                 err = azx_probe_continue(chip);
3757                 if (err < 0)
3758                         goto out_free;
3759         }
3760
3761         if (pci_dev_run_wake(pci))
3762                 pm_runtime_put_noidle(&pci->dev);
3763
3764         dev++;
3765         complete_all(&chip->probe_wait);
3766         return 0;
3767
3768 out_free:
3769         snd_card_free(card);
3770         return err;
3771 }
3772
3773 static int azx_probe_continue(struct azx *chip)
3774 {
3775         int dev = chip->dev_index;
3776         int err;
3777
3778 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3779         chip->beep_mode = beep_mode[dev];
3780 #endif
3781
3782         /* create codec instances */
3783         err = azx_codec_create(chip, model[dev]);
3784         if (err < 0)
3785                 goto out_free;
3786 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3787         if (chip->fw) {
3788                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3789                                          chip->fw->data);
3790                 if (err < 0)
3791                         goto out_free;
3792 #ifndef CONFIG_PM
3793                 release_firmware(chip->fw); /* no longer needed */
3794                 chip->fw = NULL;
3795 #endif
3796         }
3797 #endif
3798         if ((probe_only[dev] & 1) == 0) {
3799                 err = azx_codec_configure(chip);
3800                 if (err < 0)
3801                         goto out_free;
3802         }
3803
3804         /* create PCM streams */
3805         err = snd_hda_build_pcms(chip->bus);
3806         if (err < 0)
3807                 goto out_free;
3808
3809         /* create mixer controls */
3810         err = azx_mixer_create(chip);
3811         if (err < 0)
3812                 goto out_free;
3813
3814         err = snd_card_register(chip->card);
3815         if (err < 0)
3816                 goto out_free;
3817
3818         chip->running = 1;
3819         power_down_all_codecs(chip);
3820         azx_notifier_register(chip);
3821         azx_add_card_list(chip);
3822
3823         return 0;
3824
3825 out_free:
3826         chip->init_failed = 1;
3827         return err;
3828 }
3829
3830 static void azx_remove(struct pci_dev *pci)
3831 {
3832         struct snd_card *card = pci_get_drvdata(pci);
3833
3834         if (pci_dev_run_wake(pci))
3835                 pm_runtime_get_noresume(&pci->dev);
3836
3837         if (card)
3838                 snd_card_free(card);
3839 }
3840
3841 /* PCI IDs */
3842 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3843         /* CPT */
3844         { PCI_DEVICE(0x8086, 0x1c20),
3845           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3846         /* PBG */
3847         { PCI_DEVICE(0x8086, 0x1d20),
3848           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3849         /* Panther Point */
3850         { PCI_DEVICE(0x8086, 0x1e20),
3851           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3852         /* Lynx Point */
3853         { PCI_DEVICE(0x8086, 0x8c20),
3854           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3855         /* Wellsburg */
3856         { PCI_DEVICE(0x8086, 0x8d20),
3857           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3858         { PCI_DEVICE(0x8086, 0x8d21),
3859           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3860         /* Lynx Point-LP */
3861         { PCI_DEVICE(0x8086, 0x9c20),
3862           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3863         /* Lynx Point-LP */
3864         { PCI_DEVICE(0x8086, 0x9c21),
3865           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3866         /* Haswell */
3867         { PCI_DEVICE(0x8086, 0x0a0c),
3868           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3869         { PCI_DEVICE(0x8086, 0x0c0c),
3870           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3871         { PCI_DEVICE(0x8086, 0x0d0c),
3872           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3873         /* 5 Series/3400 */
3874         { PCI_DEVICE(0x8086, 0x3b56),
3875           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3876         /* Poulsbo */
3877         { PCI_DEVICE(0x8086, 0x811b),
3878           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3879         /* Oaktrail */
3880         { PCI_DEVICE(0x8086, 0x080a),
3881           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3882         /* BayTrail */
3883         { PCI_DEVICE(0x8086, 0x0f04),
3884           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3885         /* ICH */
3886         { PCI_DEVICE(0x8086, 0x2668),
3887           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3888           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3889         { PCI_DEVICE(0x8086, 0x27d8),
3890           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3891           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3892         { PCI_DEVICE(0x8086, 0x269a),
3893           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3894           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3895         { PCI_DEVICE(0x8086, 0x284b),
3896           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3897           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3898         { PCI_DEVICE(0x8086, 0x293e),
3899           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3900           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3901         { PCI_DEVICE(0x8086, 0x293f),
3902           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3903           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3904         { PCI_DEVICE(0x8086, 0x3a3e),
3905           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3906           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3907         { PCI_DEVICE(0x8086, 0x3a6e),
3908           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3909           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3910         /* Generic Intel */
3911         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3912           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3913           .class_mask = 0xffffff,
3914           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3915         /* ATI SB 450/600/700/800/900 */
3916         { PCI_DEVICE(0x1002, 0x437b),
3917           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3918         { PCI_DEVICE(0x1002, 0x4383),
3919           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3920         /* AMD Hudson */
3921         { PCI_DEVICE(0x1022, 0x780d),
3922           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3923         /* ATI HDMI */
3924         { PCI_DEVICE(0x1002, 0x793b),
3925           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3926         { PCI_DEVICE(0x1002, 0x7919),
3927           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3928         { PCI_DEVICE(0x1002, 0x960f),
3929           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3930         { PCI_DEVICE(0x1002, 0x970f),
3931           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3932         { PCI_DEVICE(0x1002, 0xaa00),
3933           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3934         { PCI_DEVICE(0x1002, 0xaa08),
3935           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3936         { PCI_DEVICE(0x1002, 0xaa10),
3937           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3938         { PCI_DEVICE(0x1002, 0xaa18),
3939           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3940         { PCI_DEVICE(0x1002, 0xaa20),
3941           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3942         { PCI_DEVICE(0x1002, 0xaa28),
3943           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3944         { PCI_DEVICE(0x1002, 0xaa30),
3945           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3946         { PCI_DEVICE(0x1002, 0xaa38),
3947           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3948         { PCI_DEVICE(0x1002, 0xaa40),
3949           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3950         { PCI_DEVICE(0x1002, 0xaa48),
3951           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3952         { PCI_DEVICE(0x1002, 0x9902),
3953           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3954         { PCI_DEVICE(0x1002, 0xaaa0),
3955           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3956         { PCI_DEVICE(0x1002, 0xaaa8),
3957           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3958         { PCI_DEVICE(0x1002, 0xaab0),
3959           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3960         /* VIA VT8251/VT8237A */
3961         { PCI_DEVICE(0x1106, 0x3288),
3962           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3963         /* VIA GFX VT7122/VX900 */
3964         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3965         /* VIA GFX VT6122/VX11 */
3966         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3967         /* SIS966 */
3968         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3969         /* ULI M5461 */
3970         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3971         /* NVIDIA MCP */
3972         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3973           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3974           .class_mask = 0xffffff,
3975           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3976         /* Teradici */
3977         { PCI_DEVICE(0x6549, 0x1200),
3978           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3979         { PCI_DEVICE(0x6549, 0x2200),
3980           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3981         /* Creative X-Fi (CA0110-IBG) */
3982         /* CTHDA chips */
3983         { PCI_DEVICE(0x1102, 0x0010),
3984           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3985         { PCI_DEVICE(0x1102, 0x0012),
3986           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3987 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3988         /* the following entry conflicts with snd-ctxfi driver,
3989          * as ctxfi driver mutates from HD-audio to native mode with
3990          * a special command sequence.
3991          */
3992         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3993           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3994           .class_mask = 0xffffff,
3995           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3996           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3997 #else
3998         /* this entry seems still valid -- i.e. without emu20kx chip */
3999         { PCI_DEVICE(0x1102, 0x0009),
4000           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4001           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4002 #endif
4003         /* Vortex86MX */
4004         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4005         /* VMware HDAudio */
4006         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4007         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4008         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4009           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4010           .class_mask = 0xffffff,
4011           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4012         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4013           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4014           .class_mask = 0xffffff,
4015           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4016         { 0, }
4017 };
4018 MODULE_DEVICE_TABLE(pci, azx_ids);
4019
4020 /* pci_driver definition */
4021 static struct pci_driver azx_driver = {
4022         .name = KBUILD_MODNAME,
4023         .id_table = azx_ids,
4024         .probe = azx_probe,
4025         .remove = azx_remove,
4026         .driver = {
4027                 .pm = AZX_PM_OPS,
4028         },
4029 };
4030
4031 module_pci_driver(azx_driver);