3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
49 #include <linux/pm_runtime.h>
51 /* for snoop control */
52 #include <asm/pgtable.h>
53 #include <asm/cacheflush.h>
55 #include <sound/core.h>
56 #include <sound/initval.h>
57 #include <linux/vgaarb.h>
58 #include <linux/vga_switcheroo.h>
59 #include <linux/firmware.h>
60 #include "hda_codec.h"
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
66 static char *model[SNDRV_CARDS];
67 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
69 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
70 static int probe_only[SNDRV_CARDS];
71 static bool single_cmd;
72 static int enable_msi = -1;
73 #ifdef CONFIG_SND_HDA_PATCH_LOADER
74 static char *patch[SNDRV_CARDS];
76 #ifdef CONFIG_SND_HDA_INPUT_BEEP
77 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
78 CONFIG_SND_HDA_INPUT_BEEP_MODE};
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87 module_param_array(model, charp, NULL, 0444);
88 MODULE_PARM_DESC(model, "Use the given board model.");
89 module_param_array(position_fix, int, NULL, 0444);
90 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
91 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
92 module_param_array(bdl_pos_adj, int, NULL, 0644);
93 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
94 module_param_array(probe_mask, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
96 module_param_array(probe_only, int, NULL, 0444);
97 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
98 module_param(single_cmd, bool, 0444);
99 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100 "(for debugging only).");
101 module_param(enable_msi, bint, 0444);
102 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
103 #ifdef CONFIG_SND_HDA_PATCH_LOADER
104 module_param_array(patch, charp, NULL, 0444);
105 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
107 #ifdef CONFIG_SND_HDA_INPUT_BEEP
108 module_param_array(beep_mode, bool, NULL, 0444);
109 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
110 "(0=off, 1=on) (default=1).");
114 static int param_set_xint(const char *val, const struct kernel_param *kp);
115 static struct kernel_param_ops param_ops_xint = {
116 .set = param_set_xint,
117 .get = param_get_int,
119 #define param_check_xint param_check_int
121 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
122 module_param(power_save, xint, 0644);
123 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124 "(in second, 0 = disable).");
126 /* reset the HD-audio controller in power save mode.
127 * this may give more power-saving, but will take longer time to
130 static bool power_save_controller = 1;
131 module_param(power_save_controller, bool, 0644);
132 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
133 #endif /* CONFIG_PM */
135 static int align_buffer_size = -1;
136 module_param(align_buffer_size, bint, 0644);
137 MODULE_PARM_DESC(align_buffer_size,
138 "Force buffer and period sizes to be multiple of 128 bytes.");
141 static bool hda_snoop = true;
142 module_param_named(snoop, hda_snoop, bool, 0444);
143 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144 #define azx_snoop(chip) (chip)->snoop
146 #define hda_snoop true
147 #define azx_snoop(chip) true
151 MODULE_LICENSE("GPL");
152 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
183 MODULE_DESCRIPTION("Intel HDA driver");
185 #ifdef CONFIG_SND_VERBOSE_PRINTK
186 #define SFX /* nop */
188 #define SFX "hda-intel: "
191 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192 #ifdef CONFIG_SND_HDA_CODEC_HDMI
193 #define SUPPORT_VGA_SWITCHEROO
201 #define ICH6_REG_GCAP 0x00
202 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
203 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
204 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
205 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
206 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
207 #define ICH6_REG_VMIN 0x02
208 #define ICH6_REG_VMAJ 0x03
209 #define ICH6_REG_OUTPAY 0x04
210 #define ICH6_REG_INPAY 0x06
211 #define ICH6_REG_GCTL 0x08
212 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
213 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
214 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
215 #define ICH6_REG_WAKEEN 0x0c
216 #define ICH6_REG_STATESTS 0x0e
217 #define ICH6_REG_GSTS 0x10
218 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
219 #define ICH6_REG_INTCTL 0x20
220 #define ICH6_REG_INTSTS 0x24
221 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
222 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
223 #define ICH6_REG_SSYNC 0x38
224 #define ICH6_REG_CORBLBASE 0x40
225 #define ICH6_REG_CORBUBASE 0x44
226 #define ICH6_REG_CORBWP 0x48
227 #define ICH6_REG_CORBRP 0x4a
228 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
229 #define ICH6_REG_CORBCTL 0x4c
230 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
231 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
232 #define ICH6_REG_CORBSTS 0x4d
233 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
234 #define ICH6_REG_CORBSIZE 0x4e
236 #define ICH6_REG_RIRBLBASE 0x50
237 #define ICH6_REG_RIRBUBASE 0x54
238 #define ICH6_REG_RIRBWP 0x58
239 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
240 #define ICH6_REG_RINTCNT 0x5a
241 #define ICH6_REG_RIRBCTL 0x5c
242 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
243 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
244 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
245 #define ICH6_REG_RIRBSTS 0x5d
246 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
247 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
248 #define ICH6_REG_RIRBSIZE 0x5e
250 #define ICH6_REG_IC 0x60
251 #define ICH6_REG_IR 0x64
252 #define ICH6_REG_IRS 0x68
253 #define ICH6_IRS_VALID (1<<1)
254 #define ICH6_IRS_BUSY (1<<0)
256 #define ICH6_REG_DPLBASE 0x70
257 #define ICH6_REG_DPUBASE 0x74
258 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
260 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
263 /* stream register offsets from stream base */
264 #define ICH6_REG_SD_CTL 0x00
265 #define ICH6_REG_SD_STS 0x03
266 #define ICH6_REG_SD_LPIB 0x04
267 #define ICH6_REG_SD_CBL 0x08
268 #define ICH6_REG_SD_LVI 0x0c
269 #define ICH6_REG_SD_FIFOW 0x0e
270 #define ICH6_REG_SD_FIFOSIZE 0x10
271 #define ICH6_REG_SD_FORMAT 0x12
272 #define ICH6_REG_SD_BDLPL 0x18
273 #define ICH6_REG_SD_BDLPU 0x1c
276 #define ICH6_PCIREG_TCSEL 0x44
282 /* max number of SDs */
283 /* ICH, ATI and VIA have 4 playback and 4 capture */
284 #define ICH6_NUM_CAPTURE 4
285 #define ICH6_NUM_PLAYBACK 4
287 /* ULI has 6 playback and 5 capture */
288 #define ULI_NUM_CAPTURE 5
289 #define ULI_NUM_PLAYBACK 6
291 /* ATI HDMI has 1 playback and 0 capture */
292 #define ATIHDMI_NUM_CAPTURE 0
293 #define ATIHDMI_NUM_PLAYBACK 1
295 /* TERA has 4 playback and 3 capture */
296 #define TERA_NUM_CAPTURE 3
297 #define TERA_NUM_PLAYBACK 4
299 /* this number is statically defined for simplicity */
300 #define MAX_AZX_DEV 16
302 /* max number of fragments - we may use more if allocating more pages for BDL */
303 #define BDL_SIZE 4096
304 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
305 #define AZX_MAX_FRAG 32
306 /* max buffer size - no h/w limit, you can increase as you like */
307 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
309 /* RIRB int mask: overrun[2], response[0] */
310 #define RIRB_INT_RESPONSE 0x01
311 #define RIRB_INT_OVERRUN 0x04
312 #define RIRB_INT_MASK 0x05
314 /* STATESTS int mask: S3,SD2,SD1,SD0 */
315 #define AZX_MAX_CODECS 8
316 #define AZX_DEFAULT_CODECS 4
317 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
320 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
321 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
322 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
323 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
324 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
325 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
326 #define SD_CTL_STREAM_TAG_SHIFT 20
328 /* SD_CTL and SD_STS */
329 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
330 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
331 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
332 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
336 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
338 /* INTCTL and INTSTS */
339 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
340 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
341 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
343 /* below are so far hardcoded - should read registers in future */
344 #define ICH6_MAX_CORB_ENTRIES 256
345 #define ICH6_MAX_RIRB_ENTRIES 256
347 /* position fix mode */
356 /* Defines for ATI HD Audio support in SB450 south bridge */
357 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
358 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
360 /* Defines for Nvidia HDA support */
361 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
362 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
363 #define NVIDIA_HDA_ISTRM_COH 0x4d
364 #define NVIDIA_HDA_OSTRM_COH 0x4c
365 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
367 /* Defines for Intel SCH HDA snoop control */
368 #define INTEL_SCH_HDA_DEVC 0x78
369 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
371 /* Define IN stream 0 FIFO size offset in VIA controller */
372 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373 /* Define VIA HD Audio Device ID*/
374 #define VIA_HDAC_DEVICE_ID 0x3288
376 /* HD Audio class code */
377 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
383 struct snd_dma_buffer bdl; /* BDL buffer */
384 u32 *posbuf; /* position buffer pointer */
386 unsigned int bufsize; /* size of the play buffer in bytes */
387 unsigned int period_bytes; /* size of the period in bytes */
388 unsigned int frags; /* number for period in the play buffer */
389 unsigned int fifo_size; /* FIFO size */
390 unsigned long start_wallclk; /* start + minimum wallclk */
391 unsigned long period_wallclk; /* wallclk for period */
393 void __iomem *sd_addr; /* stream descriptor pointer */
395 u32 sd_int_sta_mask; /* stream int status mask */
398 struct snd_pcm_substream *substream; /* assigned substream,
401 unsigned int format_val; /* format value to be set in the
402 * controller and the codec
404 unsigned char stream_tag; /* assigned stream */
405 unsigned char index; /* stream index */
406 int assigned_key; /* last device# key assigned to */
408 unsigned int opened :1;
409 unsigned int running :1;
410 unsigned int irq_pending :1;
413 * A flag to ensure DMA position is 0
414 * when link position is not greater than FIFO size
416 unsigned int insufficient :1;
417 unsigned int wc_marked:1;
418 unsigned int no_period_wakeup:1;
423 u32 *buf; /* CORB/RIRB buffer
424 * Each CORB entry is 4byte, RIRB is 8byte
426 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
428 unsigned short rp, wp; /* read/write pointers */
429 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
430 u32 res[AZX_MAX_CODECS]; /* last read value */
436 struct hda_codec *codec;
437 struct hda_pcm_stream *hinfo[2];
438 struct list_head list;
442 struct snd_card *card;
446 /* chip type specific */
448 unsigned int driver_caps;
449 int playback_streams;
450 int playback_index_offset;
452 int capture_index_offset;
457 void __iomem *remap_addr;
462 struct mutex open_mutex;
464 /* streams (x num_streams) */
465 struct azx_dev *azx_dev;
468 struct list_head pcm_list; /* azx_pcm list */
471 unsigned short codec_mask;
472 int codec_probe_mask; /* copied from probe_mask option */
474 unsigned int beep_mode;
480 /* CORB/RIRB and position buffers */
481 struct snd_dma_buffer rb;
482 struct snd_dma_buffer posbuf;
484 #ifdef CONFIG_SND_HDA_PATCH_LOADER
485 const struct firmware *fw;
489 int position_fix[2]; /* for both playback/capture streams */
491 unsigned int running :1;
492 unsigned int initialized :1;
493 unsigned int single_cmd :1;
494 unsigned int polling_mode :1;
496 unsigned int irq_pending_warned :1;
497 unsigned int probing :1; /* codec probing phase */
498 unsigned int snoop:1;
499 unsigned int align_buffer_size:1;
500 unsigned int region_requested:1;
502 /* VGA-switcheroo setup */
503 unsigned int use_vga_switcheroo:1;
504 unsigned int init_failed:1; /* delayed init failed */
505 unsigned int disabled:1; /* disabled by VGA-switcher */
508 unsigned int last_cmd[AZX_MAX_CODECS];
510 /* for pending irqs */
511 struct work_struct irq_pending_work;
513 /* reboot notifier (for mysterious hangup problem at power-down) */
514 struct notifier_block reboot_notifier;
516 /* card list (for power_save trigger) */
517 struct list_head list;
527 AZX_DRIVER_ATIHDMI_NS,
536 AZX_NUM_DRIVERS, /* keep this as last entry */
539 /* driver quirks (capabilities) */
540 /* bits 0-7 are used for indicating driver type */
541 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
542 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
543 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
544 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
545 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
546 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
547 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
548 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
549 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
550 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
551 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
552 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
553 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
554 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
555 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
556 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
557 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
559 /* quirks for ATI SB / AMD Hudson */
560 #define AZX_DCAPS_PRESET_ATI_SB \
561 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
562 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
564 /* quirks for ATI/AMD HDMI */
565 #define AZX_DCAPS_PRESET_ATI_HDMI \
566 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
568 /* quirks for Nvidia */
569 #define AZX_DCAPS_PRESET_NVIDIA \
570 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
571 AZX_DCAPS_ALIGN_BUFSIZE)
573 #define AZX_DCAPS_PRESET_CTHDA \
574 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
577 * VGA-switcher support
579 #ifdef SUPPORT_VGA_SWITCHEROO
580 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
582 #define use_vga_switcheroo(chip) 0
585 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
586 #define DELAYED_INIT_MARK
587 #define DELAYED_INITDATA_MARK
589 #define DELAYED_INIT_MARK __devinit
590 #define DELAYED_INITDATA_MARK __devinitdata
593 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
594 [AZX_DRIVER_ICH] = "HDA Intel",
595 [AZX_DRIVER_PCH] = "HDA Intel PCH",
596 [AZX_DRIVER_SCH] = "HDA Intel MID",
597 [AZX_DRIVER_ATI] = "HDA ATI SB",
598 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
599 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
600 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
601 [AZX_DRIVER_SIS] = "HDA SIS966",
602 [AZX_DRIVER_ULI] = "HDA ULI M5461",
603 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
604 [AZX_DRIVER_TERA] = "HDA Teradici",
605 [AZX_DRIVER_CTX] = "HDA Creative",
606 [AZX_DRIVER_CTHDA] = "HDA Creative",
607 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
611 * macros for easy use
613 #define azx_writel(chip,reg,value) \
614 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
615 #define azx_readl(chip,reg) \
616 readl((chip)->remap_addr + ICH6_REG_##reg)
617 #define azx_writew(chip,reg,value) \
618 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
619 #define azx_readw(chip,reg) \
620 readw((chip)->remap_addr + ICH6_REG_##reg)
621 #define azx_writeb(chip,reg,value) \
622 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
623 #define azx_readb(chip,reg) \
624 readb((chip)->remap_addr + ICH6_REG_##reg)
626 #define azx_sd_writel(dev,reg,value) \
627 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
628 #define azx_sd_readl(dev,reg) \
629 readl((dev)->sd_addr + ICH6_REG_##reg)
630 #define azx_sd_writew(dev,reg,value) \
631 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
632 #define azx_sd_readw(dev,reg) \
633 readw((dev)->sd_addr + ICH6_REG_##reg)
634 #define azx_sd_writeb(dev,reg,value) \
635 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
636 #define azx_sd_readb(dev,reg) \
637 readb((dev)->sd_addr + ICH6_REG_##reg)
639 /* for pcm support */
640 #define get_azx_dev(substream) (substream->runtime->private_data)
643 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
648 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
650 set_memory_wc((unsigned long)addr, pages);
652 set_memory_wb((unsigned long)addr, pages);
656 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
659 __mark_pages_wc(chip, buf->area, buf->bytes, on);
661 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
662 struct snd_pcm_runtime *runtime, bool on)
664 if (azx_dev->wc_marked != on) {
665 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
666 azx_dev->wc_marked = on;
670 /* NOP for other archs */
671 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
675 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
676 struct snd_pcm_runtime *runtime, bool on)
681 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
682 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
684 * Interface for HD codec
688 * CORB / RIRB interface
690 static int azx_alloc_cmd_io(struct azx *chip)
694 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
695 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
696 snd_dma_pci_data(chip->pci),
697 PAGE_SIZE, &chip->rb);
699 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
702 mark_pages_wc(chip, &chip->rb, true);
706 static void azx_init_cmd_io(struct azx *chip)
708 spin_lock_irq(&chip->reg_lock);
710 chip->corb.addr = chip->rb.addr;
711 chip->corb.buf = (u32 *)chip->rb.area;
712 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
713 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
715 /* set the corb size to 256 entries (ULI requires explicitly) */
716 azx_writeb(chip, CORBSIZE, 0x02);
717 /* set the corb write pointer to 0 */
718 azx_writew(chip, CORBWP, 0);
719 /* reset the corb hw read pointer */
720 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
721 /* enable corb dma */
722 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
725 chip->rirb.addr = chip->rb.addr + 2048;
726 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
727 chip->rirb.wp = chip->rirb.rp = 0;
728 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
729 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
730 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
732 /* set the rirb size to 256 entries (ULI requires explicitly) */
733 azx_writeb(chip, RIRBSIZE, 0x02);
734 /* reset the rirb hw write pointer */
735 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
736 /* set N=1, get RIRB response interrupt for new entry */
737 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
738 azx_writew(chip, RINTCNT, 0xc0);
740 azx_writew(chip, RINTCNT, 1);
741 /* enable rirb dma and response irq */
742 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
743 spin_unlock_irq(&chip->reg_lock);
746 static void azx_free_cmd_io(struct azx *chip)
748 spin_lock_irq(&chip->reg_lock);
749 /* disable ringbuffer DMAs */
750 azx_writeb(chip, RIRBCTL, 0);
751 azx_writeb(chip, CORBCTL, 0);
752 spin_unlock_irq(&chip->reg_lock);
755 static unsigned int azx_command_addr(u32 cmd)
757 unsigned int addr = cmd >> 28;
759 if (addr >= AZX_MAX_CODECS) {
767 static unsigned int azx_response_addr(u32 res)
769 unsigned int addr = res & 0xf;
771 if (addr >= AZX_MAX_CODECS) {
780 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
782 struct azx *chip = bus->private_data;
783 unsigned int addr = azx_command_addr(val);
786 spin_lock_irq(&chip->reg_lock);
788 /* add command to corb */
789 wp = azx_readb(chip, CORBWP);
791 wp %= ICH6_MAX_CORB_ENTRIES;
793 chip->rirb.cmds[addr]++;
794 chip->corb.buf[wp] = cpu_to_le32(val);
795 azx_writel(chip, CORBWP, wp);
797 spin_unlock_irq(&chip->reg_lock);
802 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
804 /* retrieve RIRB entry - called from interrupt handler */
805 static void azx_update_rirb(struct azx *chip)
811 wp = azx_readb(chip, RIRBWP);
812 if (wp == chip->rirb.wp)
816 while (chip->rirb.rp != wp) {
818 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
820 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
821 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
822 res = le32_to_cpu(chip->rirb.buf[rp]);
823 addr = azx_response_addr(res_ex);
824 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
825 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
826 else if (chip->rirb.cmds[addr]) {
827 chip->rirb.res[addr] = res;
829 chip->rirb.cmds[addr]--;
831 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
834 chip->last_cmd[addr]);
838 /* receive a response */
839 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
842 struct azx *chip = bus->private_data;
843 unsigned long timeout;
844 unsigned long loopcounter;
848 timeout = jiffies + msecs_to_jiffies(1000);
850 for (loopcounter = 0;; loopcounter++) {
851 if (chip->polling_mode || do_poll) {
852 spin_lock_irq(&chip->reg_lock);
853 azx_update_rirb(chip);
854 spin_unlock_irq(&chip->reg_lock);
856 if (!chip->rirb.cmds[addr]) {
861 chip->poll_count = 0;
862 return chip->rirb.res[addr]; /* the last value */
864 if (time_after(jiffies, timeout))
866 if (bus->needs_damn_long_delay || loopcounter > 3000)
867 msleep(2); /* temporary workaround */
874 if (!chip->polling_mode && chip->poll_count < 2) {
875 snd_printdd(SFX "azx_get_response timeout, "
876 "polling the codec once: last cmd=0x%08x\n",
877 chip->last_cmd[addr]);
884 if (!chip->polling_mode) {
885 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
886 "switching to polling mode: last cmd=0x%08x\n",
887 chip->last_cmd[addr]);
888 chip->polling_mode = 1;
893 snd_printk(KERN_WARNING SFX "No response from codec, "
894 "disabling MSI: last cmd=0x%08x\n",
895 chip->last_cmd[addr]);
896 free_irq(chip->irq, chip);
898 pci_disable_msi(chip->pci);
900 if (azx_acquire_irq(chip, 1) < 0) {
908 /* If this critical timeout happens during the codec probing
909 * phase, this is likely an access to a non-existing codec
910 * slot. Better to return an error and reset the system.
915 /* a fatal communication error; need either to reset or to fallback
916 * to the single_cmd mode
919 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
920 bus->response_reset = 1;
921 return -1; /* give a chance to retry */
924 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
925 "switching to single_cmd mode: last cmd=0x%08x\n",
926 chip->last_cmd[addr]);
927 chip->single_cmd = 1;
928 bus->response_reset = 0;
929 /* release CORB/RIRB */
930 azx_free_cmd_io(chip);
931 /* disable unsolicited responses */
932 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
937 * Use the single immediate command instead of CORB/RIRB for simplicity
939 * Note: according to Intel, this is not preferred use. The command was
940 * intended for the BIOS only, and may get confused with unsolicited
941 * responses. So, we shouldn't use it for normal operation from the
943 * I left the codes, however, for debugging/testing purposes.
946 /* receive a response */
947 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
952 /* check IRV busy bit */
953 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
954 /* reuse rirb.res as the response return value */
955 chip->rirb.res[addr] = azx_readl(chip, IR);
960 if (printk_ratelimit())
961 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
962 azx_readw(chip, IRS));
963 chip->rirb.res[addr] = -1;
968 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
970 struct azx *chip = bus->private_data;
971 unsigned int addr = azx_command_addr(val);
976 /* check ICB busy bit */
977 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
978 /* Clear IRV valid bit */
979 azx_writew(chip, IRS, azx_readw(chip, IRS) |
981 azx_writel(chip, IC, val);
982 azx_writew(chip, IRS, azx_readw(chip, IRS) |
984 return azx_single_wait_for_response(chip, addr);
988 if (printk_ratelimit())
989 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
990 azx_readw(chip, IRS), val);
994 /* receive a response */
995 static unsigned int azx_single_get_response(struct hda_bus *bus,
998 struct azx *chip = bus->private_data;
999 return chip->rirb.res[addr];
1003 * The below are the main callbacks from hda_codec.
1005 * They are just the skeleton to call sub-callbacks according to the
1006 * current setting of chip->single_cmd.
1009 /* send a command */
1010 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1012 struct azx *chip = bus->private_data;
1016 chip->last_cmd[azx_command_addr(val)] = val;
1017 if (chip->single_cmd)
1018 return azx_single_send_cmd(bus, val);
1020 return azx_corb_send_cmd(bus, val);
1023 /* get a response */
1024 static unsigned int azx_get_response(struct hda_bus *bus,
1027 struct azx *chip = bus->private_data;
1030 if (chip->single_cmd)
1031 return azx_single_get_response(bus, addr);
1033 return azx_rirb_get_response(bus, addr);
1037 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1040 /* reset codec link */
1041 static int azx_reset(struct azx *chip, int full_reset)
1048 /* clear STATESTS */
1049 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1051 /* reset controller */
1052 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1055 while (azx_readb(chip, GCTL) && --count)
1058 /* delay for >= 100us for codec PLL to settle per spec
1059 * Rev 0.9 section 5.5.1
1063 /* Bring controller out of reset */
1064 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1067 while (!azx_readb(chip, GCTL) && --count)
1070 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1074 /* check to see if controller is ready */
1075 if (!azx_readb(chip, GCTL)) {
1076 snd_printd(SFX "azx_reset: controller not ready!\n");
1080 /* Accept unsolicited responses */
1081 if (!chip->single_cmd)
1082 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1086 if (!chip->codec_mask) {
1087 chip->codec_mask = azx_readw(chip, STATESTS);
1088 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1096 * Lowlevel interface
1099 /* enable interrupts */
1100 static void azx_int_enable(struct azx *chip)
1102 /* enable controller CIE and GIE */
1103 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1104 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1107 /* disable interrupts */
1108 static void azx_int_disable(struct azx *chip)
1112 /* disable interrupts in stream descriptor */
1113 for (i = 0; i < chip->num_streams; i++) {
1114 struct azx_dev *azx_dev = &chip->azx_dev[i];
1115 azx_sd_writeb(azx_dev, SD_CTL,
1116 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1119 /* disable SIE for all streams */
1120 azx_writeb(chip, INTCTL, 0);
1122 /* disable controller CIE and GIE */
1123 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1124 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1127 /* clear interrupts */
1128 static void azx_int_clear(struct azx *chip)
1132 /* clear stream status */
1133 for (i = 0; i < chip->num_streams; i++) {
1134 struct azx_dev *azx_dev = &chip->azx_dev[i];
1135 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1138 /* clear STATESTS */
1139 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1141 /* clear rirb status */
1142 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1144 /* clear int status */
1145 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1148 /* start a stream */
1149 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1152 * Before stream start, initialize parameter
1154 azx_dev->insufficient = 1;
1157 azx_writel(chip, INTCTL,
1158 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1159 /* set DMA start and interrupt mask */
1160 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1161 SD_CTL_DMA_START | SD_INT_MASK);
1165 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1167 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1168 ~(SD_CTL_DMA_START | SD_INT_MASK));
1169 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1173 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1175 azx_stream_clear(chip, azx_dev);
1177 azx_writel(chip, INTCTL,
1178 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1183 * reset and start the controller registers
1185 static void azx_init_chip(struct azx *chip, int full_reset)
1187 if (chip->initialized)
1190 /* reset controller */
1191 azx_reset(chip, full_reset);
1193 /* initialize interrupts */
1194 azx_int_clear(chip);
1195 azx_int_enable(chip);
1197 /* initialize the codec command I/O */
1198 if (!chip->single_cmd)
1199 azx_init_cmd_io(chip);
1201 /* program the position buffer */
1202 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1203 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1205 chip->initialized = 1;
1209 * initialize the PCI registers
1211 /* update bits in a PCI register byte */
1212 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1213 unsigned char mask, unsigned char val)
1217 pci_read_config_byte(pci, reg, &data);
1219 data |= (val & mask);
1220 pci_write_config_byte(pci, reg, data);
1223 static void azx_init_pci(struct azx *chip)
1225 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1226 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1227 * Ensuring these bits are 0 clears playback static on some HD Audio
1229 * The PCI register TCSEL is defined in the Intel manuals.
1231 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1232 snd_printdd(SFX "Clearing TCSEL\n");
1233 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1236 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1237 * we need to enable snoop.
1239 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1240 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1241 update_pci_byte(chip->pci,
1242 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1243 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1246 /* For NVIDIA HDA, enable snoop */
1247 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1248 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1249 update_pci_byte(chip->pci,
1250 NVIDIA_HDA_TRANSREG_ADDR,
1251 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1252 update_pci_byte(chip->pci,
1253 NVIDIA_HDA_ISTRM_COH,
1254 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1255 update_pci_byte(chip->pci,
1256 NVIDIA_HDA_OSTRM_COH,
1257 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1260 /* Enable SCH/PCH snoop if needed */
1261 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1262 unsigned short snoop;
1263 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1264 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1265 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1266 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1267 if (!azx_snoop(chip))
1268 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1269 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1270 pci_read_config_word(chip->pci,
1271 INTEL_SCH_HDA_DEVC, &snoop);
1273 snd_printdd(SFX "SCH snoop: %s\n",
1274 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1275 ? "Disabled" : "Enabled");
1280 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1285 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1287 struct azx *chip = dev_id;
1288 struct azx_dev *azx_dev;
1293 #ifdef CONFIG_PM_RUNTIME
1294 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1298 spin_lock(&chip->reg_lock);
1300 if (chip->disabled) {
1301 spin_unlock(&chip->reg_lock);
1305 status = azx_readl(chip, INTSTS);
1307 spin_unlock(&chip->reg_lock);
1311 for (i = 0; i < chip->num_streams; i++) {
1312 azx_dev = &chip->azx_dev[i];
1313 if (status & azx_dev->sd_int_sta_mask) {
1314 sd_status = azx_sd_readb(azx_dev, SD_STS);
1315 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1316 if (!azx_dev->substream || !azx_dev->running ||
1317 !(sd_status & SD_INT_COMPLETE))
1319 /* check whether this IRQ is really acceptable */
1320 ok = azx_position_ok(chip, azx_dev);
1322 azx_dev->irq_pending = 0;
1323 spin_unlock(&chip->reg_lock);
1324 snd_pcm_period_elapsed(azx_dev->substream);
1325 spin_lock(&chip->reg_lock);
1326 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1327 /* bogus IRQ, process it later */
1328 azx_dev->irq_pending = 1;
1329 queue_work(chip->bus->workq,
1330 &chip->irq_pending_work);
1335 /* clear rirb int */
1336 status = azx_readb(chip, RIRBSTS);
1337 if (status & RIRB_INT_MASK) {
1338 if (status & RIRB_INT_RESPONSE) {
1339 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1341 azx_update_rirb(chip);
1343 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1347 /* clear state status int */
1348 if (azx_readb(chip, STATESTS) & 0x04)
1349 azx_writeb(chip, STATESTS, 0x04);
1351 spin_unlock(&chip->reg_lock);
1358 * set up a BDL entry
1360 static int setup_bdle(struct azx *chip,
1361 struct snd_pcm_substream *substream,
1362 struct azx_dev *azx_dev, u32 **bdlp,
1363 int ofs, int size, int with_ioc)
1371 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1374 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1375 /* program the address field of the BDL entry */
1376 bdl[0] = cpu_to_le32((u32)addr);
1377 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1378 /* program the size field of the BDL entry */
1379 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1380 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1381 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1382 u32 remain = 0x1000 - (ofs & 0xfff);
1386 bdl[2] = cpu_to_le32(chunk);
1387 /* program the IOC to enable interrupt
1388 * only when the whole fragment is processed
1391 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1401 * set up BDL entries
1403 static int azx_setup_periods(struct azx *chip,
1404 struct snd_pcm_substream *substream,
1405 struct azx_dev *azx_dev)
1408 int i, ofs, periods, period_bytes;
1411 /* reset BDL address */
1412 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1413 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1415 period_bytes = azx_dev->period_bytes;
1416 periods = azx_dev->bufsize / period_bytes;
1418 /* program the initial BDL entries */
1419 bdl = (u32 *)azx_dev->bdl.area;
1422 pos_adj = bdl_pos_adj[chip->dev_index];
1423 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1424 struct snd_pcm_runtime *runtime = substream->runtime;
1425 int pos_align = pos_adj;
1426 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1428 pos_adj = pos_align;
1430 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1432 pos_adj = frames_to_bytes(runtime, pos_adj);
1433 if (pos_adj >= period_bytes) {
1434 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1435 bdl_pos_adj[chip->dev_index]);
1438 ofs = setup_bdle(chip, substream, azx_dev,
1439 &bdl, ofs, pos_adj, true);
1445 for (i = 0; i < periods; i++) {
1446 if (i == periods - 1 && pos_adj)
1447 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1448 period_bytes - pos_adj, 0);
1450 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1452 !azx_dev->no_period_wakeup);
1459 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1460 azx_dev->bufsize, period_bytes);
1465 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1470 azx_stream_clear(chip, azx_dev);
1472 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1473 SD_CTL_STREAM_RESET);
1476 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1479 val &= ~SD_CTL_STREAM_RESET;
1480 azx_sd_writeb(azx_dev, SD_CTL, val);
1484 /* waiting for hardware to report that the stream is out of reset */
1485 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1489 /* reset first position - may not be synced with hw at this time */
1490 *azx_dev->posbuf = 0;
1494 * set up the SD for streaming
1496 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1499 /* make sure the run bit is zero for SD */
1500 azx_stream_clear(chip, azx_dev);
1501 /* program the stream_tag */
1502 val = azx_sd_readl(azx_dev, SD_CTL);
1503 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1504 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1505 if (!azx_snoop(chip))
1506 val |= SD_CTL_TRAFFIC_PRIO;
1507 azx_sd_writel(azx_dev, SD_CTL, val);
1509 /* program the length of samples in cyclic buffer */
1510 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1512 /* program the stream format */
1513 /* this value needs to be the same as the one programmed */
1514 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1516 /* program the stream LVI (last valid index) of the BDL */
1517 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1519 /* program the BDL address */
1520 /* lower BDL address */
1521 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1522 /* upper BDL address */
1523 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1525 /* enable the position buffer */
1526 if (chip->position_fix[0] != POS_FIX_LPIB ||
1527 chip->position_fix[1] != POS_FIX_LPIB) {
1528 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1529 azx_writel(chip, DPLBASE,
1530 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1533 /* set the interrupt enable bits in the descriptor control register */
1534 azx_sd_writel(azx_dev, SD_CTL,
1535 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1541 * Probe the given codec address
1543 static int probe_codec(struct azx *chip, int addr)
1545 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1546 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1549 mutex_lock(&chip->bus->cmd_mutex);
1551 azx_send_cmd(chip->bus, cmd);
1552 res = azx_get_response(chip->bus, addr);
1554 mutex_unlock(&chip->bus->cmd_mutex);
1557 snd_printdd(SFX "codec #%d probed OK\n", addr);
1561 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1562 struct hda_pcm *cpcm);
1563 static void azx_stop_chip(struct azx *chip);
1565 static void azx_bus_reset(struct hda_bus *bus)
1567 struct azx *chip = bus->private_data;
1570 azx_stop_chip(chip);
1571 azx_init_chip(chip, 1);
1573 if (chip->initialized) {
1575 list_for_each_entry(p, &chip->pcm_list, list)
1576 snd_pcm_suspend_all(p->pcm);
1577 snd_hda_suspend(chip->bus);
1578 snd_hda_resume(chip->bus);
1585 * Codec initialization
1588 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1589 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1590 [AZX_DRIVER_NVIDIA] = 8,
1591 [AZX_DRIVER_TERA] = 1,
1594 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1596 struct hda_bus_template bus_temp;
1600 memset(&bus_temp, 0, sizeof(bus_temp));
1601 bus_temp.private_data = chip;
1602 bus_temp.modelname = model;
1603 bus_temp.pci = chip->pci;
1604 bus_temp.ops.command = azx_send_cmd;
1605 bus_temp.ops.get_response = azx_get_response;
1606 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1607 bus_temp.ops.bus_reset = azx_bus_reset;
1609 bus_temp.power_save = &power_save;
1610 bus_temp.ops.pm_notify = azx_power_notify;
1613 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1617 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1618 snd_printd(SFX "Enable delay in RIRB handling\n");
1619 chip->bus->needs_damn_long_delay = 1;
1623 max_slots = azx_max_codecs[chip->driver_type];
1625 max_slots = AZX_DEFAULT_CODECS;
1627 /* First try to probe all given codec slots */
1628 for (c = 0; c < max_slots; c++) {
1629 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1630 if (probe_codec(chip, c) < 0) {
1631 /* Some BIOSen give you wrong codec addresses
1634 snd_printk(KERN_WARNING SFX
1635 "Codec #%d probe error; "
1636 "disabling it...\n", c);
1637 chip->codec_mask &= ~(1 << c);
1638 /* More badly, accessing to a non-existing
1639 * codec often screws up the controller chip,
1640 * and disturbs the further communications.
1641 * Thus if an error occurs during probing,
1642 * better to reset the controller chip to
1643 * get back to the sanity state.
1645 azx_stop_chip(chip);
1646 azx_init_chip(chip, 1);
1651 /* AMD chipsets often cause the communication stalls upon certain
1652 * sequence like the pin-detection. It seems that forcing the synced
1653 * access works around the stall. Grrr...
1655 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1656 snd_printd(SFX "Enable sync_write for stable communication\n");
1657 chip->bus->sync_write = 1;
1658 chip->bus->allow_bus_reset = 1;
1661 /* Then create codec instances */
1662 for (c = 0; c < max_slots; c++) {
1663 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1664 struct hda_codec *codec;
1665 err = snd_hda_codec_new(chip->bus, c, &codec);
1668 codec->beep_mode = chip->beep_mode;
1673 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1679 /* configure each codec instance */
1680 static int __devinit azx_codec_configure(struct azx *chip)
1682 struct hda_codec *codec;
1683 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1684 snd_hda_codec_configure(codec);
1694 /* assign a stream for the PCM */
1695 static inline struct azx_dev *
1696 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1699 struct azx_dev *res = NULL;
1700 /* make a non-zero unique key for the substream */
1701 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1702 (substream->stream + 1);
1704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1705 dev = chip->playback_index_offset;
1706 nums = chip->playback_streams;
1708 dev = chip->capture_index_offset;
1709 nums = chip->capture_streams;
1711 for (i = 0; i < nums; i++, dev++)
1712 if (!chip->azx_dev[dev].opened) {
1713 res = &chip->azx_dev[dev];
1714 if (res->assigned_key == key)
1719 res->assigned_key = key;
1724 /* release the assigned stream */
1725 static inline void azx_release_device(struct azx_dev *azx_dev)
1727 azx_dev->opened = 0;
1730 static struct snd_pcm_hardware azx_pcm_hw = {
1731 .info = (SNDRV_PCM_INFO_MMAP |
1732 SNDRV_PCM_INFO_INTERLEAVED |
1733 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1734 SNDRV_PCM_INFO_MMAP_VALID |
1735 /* No full-resume yet implemented */
1736 /* SNDRV_PCM_INFO_RESUME |*/
1737 SNDRV_PCM_INFO_PAUSE |
1738 SNDRV_PCM_INFO_SYNC_START |
1739 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1740 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1741 .rates = SNDRV_PCM_RATE_48000,
1746 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1747 .period_bytes_min = 128,
1748 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1750 .periods_max = AZX_MAX_FRAG,
1754 static int azx_pcm_open(struct snd_pcm_substream *substream)
1756 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1757 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1758 struct azx *chip = apcm->chip;
1759 struct azx_dev *azx_dev;
1760 struct snd_pcm_runtime *runtime = substream->runtime;
1761 unsigned long flags;
1765 mutex_lock(&chip->open_mutex);
1766 azx_dev = azx_assign_device(chip, substream);
1767 if (azx_dev == NULL) {
1768 mutex_unlock(&chip->open_mutex);
1771 runtime->hw = azx_pcm_hw;
1772 runtime->hw.channels_min = hinfo->channels_min;
1773 runtime->hw.channels_max = hinfo->channels_max;
1774 runtime->hw.formats = hinfo->formats;
1775 runtime->hw.rates = hinfo->rates;
1776 snd_pcm_limit_hw_rates(runtime);
1777 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1778 if (chip->align_buffer_size)
1779 /* constrain buffer sizes to be multiple of 128
1780 bytes. This is more efficient in terms of memory
1781 access but isn't required by the HDA spec and
1782 prevents users from specifying exact period/buffer
1783 sizes. For example for 44.1kHz, a period size set
1784 to 20ms will be rounded to 19.59ms. */
1787 /* Don't enforce steps on buffer sizes, still need to
1788 be multiple of 4 bytes (HDA spec). Tested on Intel
1789 HDA controllers, may not work on all devices where
1790 option needs to be disabled */
1793 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1795 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1797 snd_hda_power_up_d3wait(apcm->codec);
1798 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1800 azx_release_device(azx_dev);
1801 snd_hda_power_down(apcm->codec);
1802 mutex_unlock(&chip->open_mutex);
1805 snd_pcm_limit_hw_rates(runtime);
1807 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1808 snd_BUG_ON(!runtime->hw.channels_max) ||
1809 snd_BUG_ON(!runtime->hw.formats) ||
1810 snd_BUG_ON(!runtime->hw.rates)) {
1811 azx_release_device(azx_dev);
1812 hinfo->ops.close(hinfo, apcm->codec, substream);
1813 snd_hda_power_down(apcm->codec);
1814 mutex_unlock(&chip->open_mutex);
1817 spin_lock_irqsave(&chip->reg_lock, flags);
1818 azx_dev->substream = substream;
1819 azx_dev->running = 0;
1820 spin_unlock_irqrestore(&chip->reg_lock, flags);
1822 runtime->private_data = azx_dev;
1823 snd_pcm_set_sync(substream);
1824 mutex_unlock(&chip->open_mutex);
1828 static int azx_pcm_close(struct snd_pcm_substream *substream)
1830 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1831 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1832 struct azx *chip = apcm->chip;
1833 struct azx_dev *azx_dev = get_azx_dev(substream);
1834 unsigned long flags;
1836 mutex_lock(&chip->open_mutex);
1837 spin_lock_irqsave(&chip->reg_lock, flags);
1838 azx_dev->substream = NULL;
1839 azx_dev->running = 0;
1840 spin_unlock_irqrestore(&chip->reg_lock, flags);
1841 azx_release_device(azx_dev);
1842 hinfo->ops.close(hinfo, apcm->codec, substream);
1843 snd_hda_power_down(apcm->codec);
1844 mutex_unlock(&chip->open_mutex);
1848 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1849 struct snd_pcm_hw_params *hw_params)
1851 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1852 struct azx *chip = apcm->chip;
1853 struct snd_pcm_runtime *runtime = substream->runtime;
1854 struct azx_dev *azx_dev = get_azx_dev(substream);
1857 mark_runtime_wc(chip, azx_dev, runtime, false);
1858 azx_dev->bufsize = 0;
1859 azx_dev->period_bytes = 0;
1860 azx_dev->format_val = 0;
1861 ret = snd_pcm_lib_malloc_pages(substream,
1862 params_buffer_bytes(hw_params));
1865 mark_runtime_wc(chip, azx_dev, runtime, true);
1869 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1871 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1872 struct azx_dev *azx_dev = get_azx_dev(substream);
1873 struct azx *chip = apcm->chip;
1874 struct snd_pcm_runtime *runtime = substream->runtime;
1875 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1877 /* reset BDL address */
1878 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1879 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1880 azx_sd_writel(azx_dev, SD_CTL, 0);
1881 azx_dev->bufsize = 0;
1882 azx_dev->period_bytes = 0;
1883 azx_dev->format_val = 0;
1885 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1887 mark_runtime_wc(chip, azx_dev, runtime, false);
1888 return snd_pcm_lib_free_pages(substream);
1891 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1893 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1894 struct azx *chip = apcm->chip;
1895 struct azx_dev *azx_dev = get_azx_dev(substream);
1896 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1897 struct snd_pcm_runtime *runtime = substream->runtime;
1898 unsigned int bufsize, period_bytes, format_val, stream_tag;
1900 struct hda_spdif_out *spdif =
1901 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1902 unsigned short ctls = spdif ? spdif->ctls : 0;
1904 azx_stream_reset(chip, azx_dev);
1905 format_val = snd_hda_calc_stream_format(runtime->rate,
1911 snd_printk(KERN_ERR SFX
1912 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1913 runtime->rate, runtime->channels, runtime->format);
1917 bufsize = snd_pcm_lib_buffer_bytes(substream);
1918 period_bytes = snd_pcm_lib_period_bytes(substream);
1920 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1921 bufsize, format_val);
1923 if (bufsize != azx_dev->bufsize ||
1924 period_bytes != azx_dev->period_bytes ||
1925 format_val != azx_dev->format_val ||
1926 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1927 azx_dev->bufsize = bufsize;
1928 azx_dev->period_bytes = period_bytes;
1929 azx_dev->format_val = format_val;
1930 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1931 err = azx_setup_periods(chip, substream, azx_dev);
1936 /* wallclk has 24Mhz clock source */
1937 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1938 runtime->rate) * 1000);
1939 azx_setup_controller(chip, azx_dev);
1940 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1941 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1943 azx_dev->fifo_size = 0;
1945 stream_tag = azx_dev->stream_tag;
1946 /* CA-IBG chips need the playback stream starting from 1 */
1947 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1948 stream_tag > chip->capture_streams)
1949 stream_tag -= chip->capture_streams;
1950 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1951 azx_dev->format_val, substream);
1954 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1956 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1957 struct azx *chip = apcm->chip;
1958 struct azx_dev *azx_dev;
1959 struct snd_pcm_substream *s;
1960 int rstart = 0, start, nsync = 0, sbits = 0;
1964 case SNDRV_PCM_TRIGGER_START:
1966 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1967 case SNDRV_PCM_TRIGGER_RESUME:
1970 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1971 case SNDRV_PCM_TRIGGER_SUSPEND:
1972 case SNDRV_PCM_TRIGGER_STOP:
1979 snd_pcm_group_for_each_entry(s, substream) {
1980 if (s->pcm->card != substream->pcm->card)
1982 azx_dev = get_azx_dev(s);
1983 sbits |= 1 << azx_dev->index;
1985 snd_pcm_trigger_done(s, substream);
1988 spin_lock(&chip->reg_lock);
1990 /* first, set SYNC bits of corresponding streams */
1991 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1992 azx_writel(chip, OLD_SSYNC,
1993 azx_readl(chip, OLD_SSYNC) | sbits);
1995 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1997 snd_pcm_group_for_each_entry(s, substream) {
1998 if (s->pcm->card != substream->pcm->card)
2000 azx_dev = get_azx_dev(s);
2002 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2004 azx_dev->start_wallclk -=
2005 azx_dev->period_wallclk;
2006 azx_stream_start(chip, azx_dev);
2008 azx_stream_stop(chip, azx_dev);
2010 azx_dev->running = start;
2012 spin_unlock(&chip->reg_lock);
2014 /* wait until all FIFOs get ready */
2015 for (timeout = 5000; timeout; timeout--) {
2017 snd_pcm_group_for_each_entry(s, substream) {
2018 if (s->pcm->card != substream->pcm->card)
2020 azx_dev = get_azx_dev(s);
2021 if (!(azx_sd_readb(azx_dev, SD_STS) &
2030 /* wait until all RUN bits are cleared */
2031 for (timeout = 5000; timeout; timeout--) {
2033 snd_pcm_group_for_each_entry(s, substream) {
2034 if (s->pcm->card != substream->pcm->card)
2036 azx_dev = get_azx_dev(s);
2037 if (azx_sd_readb(azx_dev, SD_CTL) &
2046 spin_lock(&chip->reg_lock);
2047 /* reset SYNC bits */
2048 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2049 azx_writel(chip, OLD_SSYNC,
2050 azx_readl(chip, OLD_SSYNC) & ~sbits);
2052 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2053 spin_unlock(&chip->reg_lock);
2057 /* get the current DMA position with correction on VIA chips */
2058 static unsigned int azx_via_get_position(struct azx *chip,
2059 struct azx_dev *azx_dev)
2061 unsigned int link_pos, mini_pos, bound_pos;
2062 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2063 unsigned int fifo_size;
2065 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2066 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2067 /* Playback, no problem using link position */
2073 * use mod to get the DMA position just like old chipset
2075 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2076 mod_dma_pos %= azx_dev->period_bytes;
2078 /* azx_dev->fifo_size can't get FIFO size of in stream.
2079 * Get from base address + offset.
2081 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2083 if (azx_dev->insufficient) {
2084 /* Link position never gather than FIFO size */
2085 if (link_pos <= fifo_size)
2088 azx_dev->insufficient = 0;
2091 if (link_pos <= fifo_size)
2092 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2094 mini_pos = link_pos - fifo_size;
2096 /* Find nearest previous boudary */
2097 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2098 mod_link_pos = link_pos % azx_dev->period_bytes;
2099 if (mod_link_pos >= fifo_size)
2100 bound_pos = link_pos - mod_link_pos;
2101 else if (mod_dma_pos >= mod_mini_pos)
2102 bound_pos = mini_pos - mod_mini_pos;
2104 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2105 if (bound_pos >= azx_dev->bufsize)
2109 /* Calculate real DMA position we want */
2110 return bound_pos + mod_dma_pos;
2113 static unsigned int azx_get_position(struct azx *chip,
2114 struct azx_dev *azx_dev,
2118 int stream = azx_dev->substream->stream;
2120 switch (chip->position_fix[stream]) {
2123 pos = azx_sd_readl(azx_dev, SD_LPIB);
2125 case POS_FIX_VIACOMBO:
2126 pos = azx_via_get_position(chip, azx_dev);
2129 /* use the position buffer */
2130 pos = le32_to_cpu(*azx_dev->posbuf);
2131 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2132 if (!pos || pos == (u32)-1) {
2134 "hda-intel: Invalid position buffer, "
2135 "using LPIB read method instead.\n");
2136 chip->position_fix[stream] = POS_FIX_LPIB;
2137 pos = azx_sd_readl(azx_dev, SD_LPIB);
2139 chip->position_fix[stream] = POS_FIX_POSBUF;
2144 if (pos >= azx_dev->bufsize)
2147 /* calculate runtime delay from LPIB */
2148 if (azx_dev->substream->runtime &&
2149 chip->position_fix[stream] == POS_FIX_POSBUF &&
2150 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2151 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2153 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2154 delay = pos - lpib_pos;
2156 delay = lpib_pos - pos;
2158 delay += azx_dev->bufsize;
2159 if (delay >= azx_dev->period_bytes) {
2160 snd_printdd("delay %d > period_bytes %d\n",
2161 delay, azx_dev->period_bytes);
2162 delay = 0; /* something is wrong */
2164 azx_dev->substream->runtime->delay =
2165 bytes_to_frames(azx_dev->substream->runtime, delay);
2170 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2172 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2173 struct azx *chip = apcm->chip;
2174 struct azx_dev *azx_dev = get_azx_dev(substream);
2175 return bytes_to_frames(substream->runtime,
2176 azx_get_position(chip, azx_dev, false));
2180 * Check whether the current DMA position is acceptable for updating
2181 * periods. Returns non-zero if it's OK.
2183 * Many HD-audio controllers appear pretty inaccurate about
2184 * the update-IRQ timing. The IRQ is issued before actually the
2185 * data is processed. So, we need to process it afterwords in a
2188 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2194 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2195 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2196 return -1; /* bogus (too early) interrupt */
2198 stream = azx_dev->substream->stream;
2199 pos = azx_get_position(chip, azx_dev, true);
2201 if (WARN_ONCE(!azx_dev->period_bytes,
2202 "hda-intel: zero azx_dev->period_bytes"))
2203 return -1; /* this shouldn't happen! */
2204 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2205 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2206 /* NG - it's below the first next period boundary */
2207 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2208 azx_dev->start_wallclk += wallclk;
2209 return 1; /* OK, it's fine */
2213 * The work for pending PCM period updates.
2215 static void azx_irq_pending_work(struct work_struct *work)
2217 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2220 if (!chip->irq_pending_warned) {
2222 "hda-intel: IRQ timing workaround is activated "
2223 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2224 chip->card->number);
2225 chip->irq_pending_warned = 1;
2230 spin_lock_irq(&chip->reg_lock);
2231 for (i = 0; i < chip->num_streams; i++) {
2232 struct azx_dev *azx_dev = &chip->azx_dev[i];
2233 if (!azx_dev->irq_pending ||
2234 !azx_dev->substream ||
2237 ok = azx_position_ok(chip, azx_dev);
2239 azx_dev->irq_pending = 0;
2240 spin_unlock(&chip->reg_lock);
2241 snd_pcm_period_elapsed(azx_dev->substream);
2242 spin_lock(&chip->reg_lock);
2243 } else if (ok < 0) {
2244 pending = 0; /* too early */
2248 spin_unlock_irq(&chip->reg_lock);
2255 /* clear irq_pending flags and assure no on-going workq */
2256 static void azx_clear_irq_pending(struct azx *chip)
2260 spin_lock_irq(&chip->reg_lock);
2261 for (i = 0; i < chip->num_streams; i++)
2262 chip->azx_dev[i].irq_pending = 0;
2263 spin_unlock_irq(&chip->reg_lock);
2267 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2268 struct vm_area_struct *area)
2270 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2271 struct azx *chip = apcm->chip;
2272 if (!azx_snoop(chip))
2273 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2274 return snd_pcm_lib_default_mmap(substream, area);
2277 #define azx_pcm_mmap NULL
2280 static struct snd_pcm_ops azx_pcm_ops = {
2281 .open = azx_pcm_open,
2282 .close = azx_pcm_close,
2283 .ioctl = snd_pcm_lib_ioctl,
2284 .hw_params = azx_pcm_hw_params,
2285 .hw_free = azx_pcm_hw_free,
2286 .prepare = azx_pcm_prepare,
2287 .trigger = azx_pcm_trigger,
2288 .pointer = azx_pcm_pointer,
2289 .mmap = azx_pcm_mmap,
2290 .page = snd_pcm_sgbuf_ops_page,
2293 static void azx_pcm_free(struct snd_pcm *pcm)
2295 struct azx_pcm *apcm = pcm->private_data;
2297 list_del(&apcm->list);
2302 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2305 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2306 struct hda_pcm *cpcm)
2308 struct azx *chip = bus->private_data;
2309 struct snd_pcm *pcm;
2310 struct azx_pcm *apcm;
2311 int pcm_dev = cpcm->device;
2315 list_for_each_entry(apcm, &chip->pcm_list, list) {
2316 if (apcm->pcm->device == pcm_dev) {
2317 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2321 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2322 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2323 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2327 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2328 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2333 apcm->codec = codec;
2334 pcm->private_data = apcm;
2335 pcm->private_free = azx_pcm_free;
2336 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2337 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2338 list_add_tail(&apcm->list, &chip->pcm_list);
2340 for (s = 0; s < 2; s++) {
2341 apcm->hinfo[s] = &cpcm->stream[s];
2342 if (cpcm->stream[s].substreams)
2343 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2345 /* buffer pre-allocation */
2346 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2347 if (size > MAX_PREALLOC_SIZE)
2348 size = MAX_PREALLOC_SIZE;
2349 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2350 snd_dma_pci_data(chip->pci),
2351 size, MAX_PREALLOC_SIZE);
2356 * mixer creation - all stuff is implemented in hda module
2358 static int __devinit azx_mixer_create(struct azx *chip)
2360 return snd_hda_build_controls(chip->bus);
2365 * initialize SD streams
2367 static int __devinit azx_init_stream(struct azx *chip)
2371 /* initialize each stream (aka device)
2372 * assign the starting bdl address to each stream (device)
2375 for (i = 0; i < chip->num_streams; i++) {
2376 struct azx_dev *azx_dev = &chip->azx_dev[i];
2377 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2378 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2379 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2380 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2381 azx_dev->sd_int_sta_mask = 1 << i;
2382 /* stream tag: must be non-zero and unique */
2384 azx_dev->stream_tag = i + 1;
2390 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2392 if (request_irq(chip->pci->irq, azx_interrupt,
2393 chip->msi ? 0 : IRQF_SHARED,
2394 KBUILD_MODNAME, chip)) {
2395 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2396 "disabling device\n", chip->pci->irq);
2398 snd_card_disconnect(chip->card);
2401 chip->irq = chip->pci->irq;
2402 pci_intx(chip->pci, !chip->msi);
2407 static void azx_stop_chip(struct azx *chip)
2409 if (!chip->initialized)
2412 /* disable interrupts */
2413 azx_int_disable(chip);
2414 azx_int_clear(chip);
2416 /* disable CORB/RIRB */
2417 azx_free_cmd_io(chip);
2419 /* disable position buffer */
2420 azx_writel(chip, DPLBASE, 0);
2421 azx_writel(chip, DPUBASE, 0);
2423 chip->initialized = 0;
2427 /* power-up/down the controller */
2428 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2430 struct azx *chip = bus->private_data;
2433 pm_runtime_get_sync(&chip->pci->dev);
2435 pm_runtime_put_sync(&chip->pci->dev);
2438 static DEFINE_MUTEX(card_list_lock);
2439 static LIST_HEAD(card_list);
2441 static void azx_add_card_list(struct azx *chip)
2443 mutex_lock(&card_list_lock);
2444 list_add(&chip->list, &card_list);
2445 mutex_unlock(&card_list_lock);
2448 static void azx_del_card_list(struct azx *chip)
2450 mutex_lock(&card_list_lock);
2451 list_del_init(&chip->list);
2452 mutex_unlock(&card_list_lock);
2455 /* trigger power-save check at writing parameter */
2456 static int param_set_xint(const char *val, const struct kernel_param *kp)
2459 struct hda_codec *c;
2460 int prev = power_save;
2461 int ret = param_set_int(val, kp);
2463 if (ret || prev == power_save)
2466 mutex_lock(&card_list_lock);
2467 list_for_each_entry(chip, &card_list, list) {
2468 if (!chip->bus || chip->disabled)
2470 list_for_each_entry(c, &chip->bus->codec_list, list)
2471 snd_hda_power_sync(c);
2473 mutex_unlock(&card_list_lock);
2477 #define azx_add_card_list(chip) /* NOP */
2478 #define azx_del_card_list(chip) /* NOP */
2479 #endif /* CONFIG_PM */
2481 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2485 static int azx_suspend(struct device *dev)
2487 struct pci_dev *pci = to_pci_dev(dev);
2488 struct snd_card *card = dev_get_drvdata(dev);
2489 struct azx *chip = card->private_data;
2492 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2493 azx_clear_irq_pending(chip);
2494 list_for_each_entry(p, &chip->pcm_list, list)
2495 snd_pcm_suspend_all(p->pcm);
2496 if (chip->initialized)
2497 snd_hda_suspend(chip->bus);
2498 azx_stop_chip(chip);
2499 if (chip->irq >= 0) {
2500 free_irq(chip->irq, chip);
2504 pci_disable_msi(chip->pci);
2505 pci_disable_device(pci);
2506 pci_save_state(pci);
2507 pci_set_power_state(pci, PCI_D3hot);
2511 static int azx_resume(struct device *dev)
2513 struct pci_dev *pci = to_pci_dev(dev);
2514 struct snd_card *card = dev_get_drvdata(dev);
2515 struct azx *chip = card->private_data;
2517 pci_set_power_state(pci, PCI_D0);
2518 pci_restore_state(pci);
2519 if (pci_enable_device(pci) < 0) {
2520 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2521 "disabling device\n");
2522 snd_card_disconnect(card);
2525 pci_set_master(pci);
2527 if (pci_enable_msi(pci) < 0)
2529 if (azx_acquire_irq(chip, 1) < 0)
2533 azx_init_chip(chip, 1);
2535 snd_hda_resume(chip->bus);
2536 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2539 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2541 #ifdef CONFIG_PM_RUNTIME
2542 static int azx_runtime_suspend(struct device *dev)
2544 struct snd_card *card = dev_get_drvdata(dev);
2545 struct azx *chip = card->private_data;
2547 if (!power_save_controller)
2550 azx_stop_chip(chip);
2551 azx_clear_irq_pending(chip);
2555 static int azx_runtime_resume(struct device *dev)
2557 struct snd_card *card = dev_get_drvdata(dev);
2558 struct azx *chip = card->private_data;
2561 azx_init_chip(chip, 1);
2564 #endif /* CONFIG_PM_RUNTIME */
2567 static const struct dev_pm_ops azx_pm = {
2568 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2569 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2572 #define AZX_PM_OPS &azx_pm
2574 #define AZX_PM_OPS NULL
2575 #endif /* CONFIG_PM */
2579 * reboot notifier for hang-up problem at power-down
2581 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2583 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2584 snd_hda_bus_reboot_notify(chip->bus);
2585 azx_stop_chip(chip);
2589 static void azx_notifier_register(struct azx *chip)
2591 chip->reboot_notifier.notifier_call = azx_halt;
2592 register_reboot_notifier(&chip->reboot_notifier);
2595 static void azx_notifier_unregister(struct azx *chip)
2597 if (chip->reboot_notifier.notifier_call)
2598 unregister_reboot_notifier(&chip->reboot_notifier);
2601 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2602 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2604 #ifdef SUPPORT_VGA_SWITCHEROO
2605 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2607 static void azx_vs_set_state(struct pci_dev *pci,
2608 enum vga_switcheroo_state state)
2610 struct snd_card *card = pci_get_drvdata(pci);
2611 struct azx *chip = card->private_data;
2614 if (chip->init_failed)
2617 disabled = (state == VGA_SWITCHEROO_OFF);
2618 if (chip->disabled == disabled)
2622 chip->disabled = disabled;
2624 snd_printk(KERN_INFO SFX
2625 "%s: Start delayed initialization\n",
2626 pci_name(chip->pci));
2627 if (azx_first_init(chip) < 0 ||
2628 azx_probe_continue(chip) < 0) {
2629 snd_printk(KERN_ERR SFX
2630 "%s: initialization error\n",
2631 pci_name(chip->pci));
2632 chip->init_failed = true;
2636 snd_printk(KERN_INFO SFX
2637 "%s %s via VGA-switcheroo\n",
2638 disabled ? "Disabling" : "Enabling",
2639 pci_name(chip->pci));
2641 azx_suspend(&pci->dev);
2642 chip->disabled = true;
2643 snd_hda_lock_devices(chip->bus);
2645 snd_hda_unlock_devices(chip->bus);
2646 chip->disabled = false;
2647 azx_resume(&pci->dev);
2652 static bool azx_vs_can_switch(struct pci_dev *pci)
2654 struct snd_card *card = pci_get_drvdata(pci);
2655 struct azx *chip = card->private_data;
2657 if (chip->init_failed)
2659 if (chip->disabled || !chip->bus)
2661 if (snd_hda_lock_devices(chip->bus))
2663 snd_hda_unlock_devices(chip->bus);
2667 static void __devinit init_vga_switcheroo(struct azx *chip)
2669 struct pci_dev *p = get_bound_vga(chip->pci);
2671 snd_printk(KERN_INFO SFX
2672 "%s: Handle VGA-switcheroo audio client\n",
2673 pci_name(chip->pci));
2674 chip->use_vga_switcheroo = 1;
2679 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2680 .set_gpu_state = azx_vs_set_state,
2681 .can_switch = azx_vs_can_switch,
2684 static int __devinit register_vga_switcheroo(struct azx *chip)
2686 if (!chip->use_vga_switcheroo)
2688 /* FIXME: currently only handling DIS controller
2689 * is there any machine with two switchable HDMI audio controllers?
2691 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2696 #define init_vga_switcheroo(chip) /* NOP */
2697 #define register_vga_switcheroo(chip) 0
2698 #define check_hdmi_disabled(pci) false
2699 #endif /* SUPPORT_VGA_SWITCHER */
2704 static int azx_free(struct azx *chip)
2708 azx_del_card_list(chip);
2710 azx_notifier_unregister(chip);
2712 if (use_vga_switcheroo(chip)) {
2713 if (chip->disabled && chip->bus)
2714 snd_hda_unlock_devices(chip->bus);
2715 vga_switcheroo_unregister_client(chip->pci);
2718 if (chip->initialized) {
2719 azx_clear_irq_pending(chip);
2720 for (i = 0; i < chip->num_streams; i++)
2721 azx_stream_stop(chip, &chip->azx_dev[i]);
2722 azx_stop_chip(chip);
2726 free_irq(chip->irq, (void*)chip);
2728 pci_disable_msi(chip->pci);
2729 if (chip->remap_addr)
2730 iounmap(chip->remap_addr);
2732 if (chip->azx_dev) {
2733 for (i = 0; i < chip->num_streams; i++)
2734 if (chip->azx_dev[i].bdl.area) {
2735 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2736 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2739 if (chip->rb.area) {
2740 mark_pages_wc(chip, &chip->rb, false);
2741 snd_dma_free_pages(&chip->rb);
2743 if (chip->posbuf.area) {
2744 mark_pages_wc(chip, &chip->posbuf, false);
2745 snd_dma_free_pages(&chip->posbuf);
2747 if (chip->region_requested)
2748 pci_release_regions(chip->pci);
2749 pci_disable_device(chip->pci);
2750 kfree(chip->azx_dev);
2751 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2753 release_firmware(chip->fw);
2760 static int azx_dev_free(struct snd_device *device)
2762 return azx_free(device->device_data);
2765 #ifdef SUPPORT_VGA_SWITCHEROO
2767 * Check of disabled HDMI controller by vga-switcheroo
2769 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2773 /* check only discrete GPU */
2774 switch (pci->vendor) {
2775 case PCI_VENDOR_ID_ATI:
2776 case PCI_VENDOR_ID_AMD:
2777 case PCI_VENDOR_ID_NVIDIA:
2778 if (pci->devfn == 1) {
2779 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2780 pci->bus->number, 0);
2782 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2792 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2794 bool vga_inactive = false;
2795 struct pci_dev *p = get_bound_vga(pci);
2798 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2799 vga_inactive = true;
2802 return vga_inactive;
2804 #endif /* SUPPORT_VGA_SWITCHEROO */
2807 * white/black-listing for position_fix
2809 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2810 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2811 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2812 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2813 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2814 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2815 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2816 SND_PCI_QUIRK(0x1043, 0x1ac3, "ASUS X53S", POS_FIX_POSBUF),
2817 SND_PCI_QUIRK(0x1043, 0x1b43, "ASUS K53E", POS_FIX_POSBUF),
2818 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2819 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2820 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2821 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2822 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2823 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2824 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2825 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2829 static int __devinit check_position_fix(struct azx *chip, int fix)
2831 const struct snd_pci_quirk *q;
2836 case POS_FIX_POSBUF:
2837 case POS_FIX_VIACOMBO:
2842 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2845 "hda_intel: position_fix set to %d "
2846 "for device %04x:%04x\n",
2847 q->value, q->subvendor, q->subdevice);
2851 /* Check VIA/ATI HD Audio Controller exist */
2852 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2853 snd_printd(SFX "Using VIACOMBO position fix\n");
2854 return POS_FIX_VIACOMBO;
2856 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2857 snd_printd(SFX "Using LPIB position fix\n");
2858 return POS_FIX_LPIB;
2860 return POS_FIX_AUTO;
2864 * black-lists for probe_mask
2866 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2867 /* Thinkpad often breaks the controller communication when accessing
2868 * to the non-working (or non-existing) modem codec slot.
2870 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2871 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2872 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2874 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2875 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2876 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2877 /* forced codec slots */
2878 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2879 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2880 /* WinFast VP200 H (Teradici) user reported broken communication */
2881 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2885 #define AZX_FORCE_CODEC_MASK 0x100
2887 static void __devinit check_probe_mask(struct azx *chip, int dev)
2889 const struct snd_pci_quirk *q;
2891 chip->codec_probe_mask = probe_mask[dev];
2892 if (chip->codec_probe_mask == -1) {
2893 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2896 "hda_intel: probe_mask set to 0x%x "
2897 "for device %04x:%04x\n",
2898 q->value, q->subvendor, q->subdevice);
2899 chip->codec_probe_mask = q->value;
2903 /* check forced option */
2904 if (chip->codec_probe_mask != -1 &&
2905 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2906 chip->codec_mask = chip->codec_probe_mask & 0xff;
2907 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2913 * white/black-list for enable_msi
2915 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2916 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2917 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2918 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2919 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2920 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2924 static void __devinit check_msi(struct azx *chip)
2926 const struct snd_pci_quirk *q;
2928 if (enable_msi >= 0) {
2929 chip->msi = !!enable_msi;
2932 chip->msi = 1; /* enable MSI as default */
2933 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2936 "hda_intel: msi for device %04x:%04x set to %d\n",
2937 q->subvendor, q->subdevice, q->value);
2938 chip->msi = q->value;
2942 /* NVidia chipsets seem to cause troubles with MSI */
2943 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2944 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2949 /* check the snoop mode availability */
2950 static void __devinit azx_check_snoop_available(struct azx *chip)
2952 bool snoop = chip->snoop;
2954 switch (chip->driver_type) {
2955 case AZX_DRIVER_VIA:
2956 /* force to non-snoop mode for a new VIA controller
2961 pci_read_config_byte(chip->pci, 0x42, &val);
2962 if (!(val & 0x80) && chip->pci->revision == 0x30)
2966 case AZX_DRIVER_ATIHDMI_NS:
2967 /* new ATI HDMI requires non-snoop */
2972 if (snoop != chip->snoop) {
2973 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2974 snoop ? "snoop" : "non-snoop");
2975 chip->snoop = snoop;
2982 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2983 int dev, unsigned int driver_caps,
2986 static struct snd_device_ops ops = {
2987 .dev_free = azx_dev_free,
2994 err = pci_enable_device(pci);
2998 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3000 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3001 pci_disable_device(pci);
3005 spin_lock_init(&chip->reg_lock);
3006 mutex_init(&chip->open_mutex);
3010 chip->driver_caps = driver_caps;
3011 chip->driver_type = driver_caps & 0xff;
3013 chip->dev_index = dev;
3014 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3015 INIT_LIST_HEAD(&chip->pcm_list);
3016 INIT_LIST_HEAD(&chip->list);
3017 init_vga_switcheroo(chip);
3019 chip->position_fix[0] = chip->position_fix[1] =
3020 check_position_fix(chip, position_fix[dev]);
3021 /* combo mode uses LPIB for playback */
3022 if (chip->position_fix[0] == POS_FIX_COMBO) {
3023 chip->position_fix[0] = POS_FIX_LPIB;
3024 chip->position_fix[1] = POS_FIX_AUTO;
3027 check_probe_mask(chip, dev);
3029 chip->single_cmd = single_cmd;
3030 chip->snoop = hda_snoop;
3031 azx_check_snoop_available(chip);
3033 if (bdl_pos_adj[dev] < 0) {
3034 switch (chip->driver_type) {
3035 case AZX_DRIVER_ICH:
3036 case AZX_DRIVER_PCH:
3037 bdl_pos_adj[dev] = 1;
3040 bdl_pos_adj[dev] = 32;
3045 if (check_hdmi_disabled(pci)) {
3046 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3048 if (use_vga_switcheroo(chip)) {
3049 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3050 chip->disabled = true;
3054 pci_disable_device(pci);
3058 err = azx_first_init(chip);
3065 err = register_vga_switcheroo(chip);
3067 snd_printk(KERN_ERR SFX
3068 "Error registering VGA-switcheroo client\n");
3073 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3075 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3084 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3086 int dev = chip->dev_index;
3087 struct pci_dev *pci = chip->pci;
3088 struct snd_card *card = chip->card;
3090 unsigned short gcap;
3092 #if BITS_PER_LONG != 64
3093 /* Fix up base address on ULI M5461 */
3094 if (chip->driver_type == AZX_DRIVER_ULI) {
3096 pci_read_config_word(pci, 0x40, &tmp3);
3097 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3098 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3102 err = pci_request_regions(pci, "ICH HD audio");
3105 chip->region_requested = 1;
3107 chip->addr = pci_resource_start(pci, 0);
3108 chip->remap_addr = pci_ioremap_bar(pci, 0);
3109 if (chip->remap_addr == NULL) {
3110 snd_printk(KERN_ERR SFX "ioremap error\n");
3115 if (pci_enable_msi(pci) < 0)
3118 if (azx_acquire_irq(chip, 0) < 0)
3121 pci_set_master(pci);
3122 synchronize_irq(chip->irq);
3124 gcap = azx_readw(chip, GCAP);
3125 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3127 /* disable SB600 64bit support for safety */
3128 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3129 struct pci_dev *p_smbus;
3130 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3131 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3134 if (p_smbus->revision < 0x30)
3135 gcap &= ~ICH6_GCAP_64OK;
3136 pci_dev_put(p_smbus);
3140 /* disable 64bit DMA address on some devices */
3141 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3142 snd_printd(SFX "Disabling 64bit DMA\n");
3143 gcap &= ~ICH6_GCAP_64OK;
3146 /* disable buffer size rounding to 128-byte multiples if supported */
3147 if (align_buffer_size >= 0)
3148 chip->align_buffer_size = !!align_buffer_size;
3150 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3151 chip->align_buffer_size = 0;
3152 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3153 chip->align_buffer_size = 1;
3155 chip->align_buffer_size = 1;
3158 /* allow 64bit DMA address if supported by H/W */
3159 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3160 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3162 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3163 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3166 /* read number of streams from GCAP register instead of using
3169 chip->capture_streams = (gcap >> 8) & 0x0f;
3170 chip->playback_streams = (gcap >> 12) & 0x0f;
3171 if (!chip->playback_streams && !chip->capture_streams) {
3172 /* gcap didn't give any info, switching to old method */
3174 switch (chip->driver_type) {
3175 case AZX_DRIVER_ULI:
3176 chip->playback_streams = ULI_NUM_PLAYBACK;
3177 chip->capture_streams = ULI_NUM_CAPTURE;
3179 case AZX_DRIVER_ATIHDMI:
3180 case AZX_DRIVER_ATIHDMI_NS:
3181 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3182 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3184 case AZX_DRIVER_GENERIC:
3186 chip->playback_streams = ICH6_NUM_PLAYBACK;
3187 chip->capture_streams = ICH6_NUM_CAPTURE;
3191 chip->capture_index_offset = 0;
3192 chip->playback_index_offset = chip->capture_streams;
3193 chip->num_streams = chip->playback_streams + chip->capture_streams;
3194 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3196 if (!chip->azx_dev) {
3197 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3201 for (i = 0; i < chip->num_streams; i++) {
3202 /* allocate memory for the BDL for each stream */
3203 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3204 snd_dma_pci_data(chip->pci),
3205 BDL_SIZE, &chip->azx_dev[i].bdl);
3207 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3210 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3212 /* allocate memory for the position buffer */
3213 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3214 snd_dma_pci_data(chip->pci),
3215 chip->num_streams * 8, &chip->posbuf);
3217 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3220 mark_pages_wc(chip, &chip->posbuf, true);
3221 /* allocate CORB/RIRB */
3222 err = azx_alloc_cmd_io(chip);
3226 /* initialize streams */
3227 azx_init_stream(chip);
3229 /* initialize chip */
3231 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3233 /* codec detection */
3234 if (!chip->codec_mask) {
3235 snd_printk(KERN_ERR SFX "no codecs found!\n");
3239 strcpy(card->driver, "HDA-Intel");
3240 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3241 sizeof(card->shortname));
3242 snprintf(card->longname, sizeof(card->longname),
3243 "%s at 0x%lx irq %i",
3244 card->shortname, chip->addr, chip->irq);
3249 static void power_down_all_codecs(struct azx *chip)
3252 /* The codecs were powered up in snd_hda_codec_new().
3253 * Now all initialization done, so turn them down if possible
3255 struct hda_codec *codec;
3256 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3257 snd_hda_power_down(codec);
3262 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3263 /* callback from request_firmware_nowait() */
3264 static void azx_firmware_cb(const struct firmware *fw, void *context)
3266 struct snd_card *card = context;
3267 struct azx *chip = card->private_data;
3268 struct pci_dev *pci = chip->pci;
3271 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3276 if (!chip->disabled) {
3277 /* continue probing */
3278 if (azx_probe_continue(chip))
3284 snd_card_free(card);
3285 pci_set_drvdata(pci, NULL);
3289 static int __devinit azx_probe(struct pci_dev *pci,
3290 const struct pci_device_id *pci_id)
3293 struct snd_card *card;
3298 if (dev >= SNDRV_CARDS)
3305 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3307 snd_printk(KERN_ERR SFX "Error creating card!\n");
3311 snd_card_set_dev(card, &pci->dev);
3313 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3316 card->private_data = chip;
3317 probe_now = !chip->disabled;
3319 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3320 if (patch[dev] && *patch[dev]) {
3321 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3323 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3324 &pci->dev, GFP_KERNEL, card,
3328 probe_now = false; /* continued in azx_firmware_cb() */
3330 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3333 err = azx_probe_continue(chip);
3338 pci_set_drvdata(pci, card);
3340 if (pci_dev_run_wake(pci))
3341 pm_runtime_put_noidle(&pci->dev);
3347 snd_card_free(card);
3351 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3353 int dev = chip->dev_index;
3356 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3357 chip->beep_mode = beep_mode[dev];
3360 /* create codec instances */
3361 err = azx_codec_create(chip, model[dev]);
3364 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3366 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3370 release_firmware(chip->fw); /* no longer needed */
3374 if ((probe_only[dev] & 1) == 0) {
3375 err = azx_codec_configure(chip);
3380 /* create PCM streams */
3381 err = snd_hda_build_pcms(chip->bus);
3385 /* create mixer controls */
3386 err = azx_mixer_create(chip);
3390 err = snd_card_register(chip->card);
3395 power_down_all_codecs(chip);
3396 azx_notifier_register(chip);
3397 azx_add_card_list(chip);
3402 chip->init_failed = 1;
3406 static void __devexit azx_remove(struct pci_dev *pci)
3408 struct snd_card *card = pci_get_drvdata(pci);
3410 if (pci_dev_run_wake(pci))
3411 pm_runtime_get_noresume(&pci->dev);
3414 snd_card_free(card);
3415 pci_set_drvdata(pci, NULL);
3419 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3421 { PCI_DEVICE(0x8086, 0x1c20),
3422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3423 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3425 { PCI_DEVICE(0x8086, 0x1d20),
3426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3429 { PCI_DEVICE(0x8086, 0x1e20),
3430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3431 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3433 { PCI_DEVICE(0x8086, 0x8c20),
3434 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3435 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3437 { PCI_DEVICE(0x8086, 0x9c20),
3438 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3439 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3441 { PCI_DEVICE(0x8086, 0x9c21),
3442 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3443 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3445 { PCI_DEVICE(0x8086, 0x0c0c),
3446 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3447 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3448 { PCI_DEVICE(0x8086, 0x0d0c),
3449 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3450 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3452 { PCI_DEVICE(0x8086, 0x3b56),
3453 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3454 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3456 { PCI_DEVICE(0x8086, 0x811b),
3457 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3458 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3459 { PCI_DEVICE(0x8086, 0x080a),
3460 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3461 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3463 { PCI_DEVICE(0x8086, 0x2668),
3464 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3465 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3466 { PCI_DEVICE(0x8086, 0x27d8),
3467 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3468 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3469 { PCI_DEVICE(0x8086, 0x269a),
3470 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3471 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3472 { PCI_DEVICE(0x8086, 0x284b),
3473 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3474 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3475 { PCI_DEVICE(0x8086, 0x293e),
3476 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3477 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3478 { PCI_DEVICE(0x8086, 0x293f),
3479 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3480 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3481 { PCI_DEVICE(0x8086, 0x3a3e),
3482 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3483 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3484 { PCI_DEVICE(0x8086, 0x3a6e),
3485 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3486 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3488 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3489 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3490 .class_mask = 0xffffff,
3491 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3492 /* ATI SB 450/600/700/800/900 */
3493 { PCI_DEVICE(0x1002, 0x437b),
3494 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3495 { PCI_DEVICE(0x1002, 0x4383),
3496 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3498 { PCI_DEVICE(0x1022, 0x780d),
3499 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3501 { PCI_DEVICE(0x1002, 0x793b),
3502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3503 { PCI_DEVICE(0x1002, 0x7919),
3504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3505 { PCI_DEVICE(0x1002, 0x960f),
3506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3507 { PCI_DEVICE(0x1002, 0x970f),
3508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3509 { PCI_DEVICE(0x1002, 0xaa00),
3510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3511 { PCI_DEVICE(0x1002, 0xaa08),
3512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3513 { PCI_DEVICE(0x1002, 0xaa10),
3514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3515 { PCI_DEVICE(0x1002, 0xaa18),
3516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3517 { PCI_DEVICE(0x1002, 0xaa20),
3518 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3519 { PCI_DEVICE(0x1002, 0xaa28),
3520 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3521 { PCI_DEVICE(0x1002, 0xaa30),
3522 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3523 { PCI_DEVICE(0x1002, 0xaa38),
3524 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3525 { PCI_DEVICE(0x1002, 0xaa40),
3526 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3527 { PCI_DEVICE(0x1002, 0xaa48),
3528 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3529 { PCI_DEVICE(0x1002, 0x9902),
3530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3531 { PCI_DEVICE(0x1002, 0xaaa0),
3532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3533 { PCI_DEVICE(0x1002, 0xaaa8),
3534 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3535 { PCI_DEVICE(0x1002, 0xaab0),
3536 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3537 /* VIA VT8251/VT8237A */
3538 { PCI_DEVICE(0x1106, 0x3288),
3539 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3540 /* VIA GFX VT7122/VX900 */
3541 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3542 /* VIA GFX VT6122/VX11 */
3543 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3545 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3547 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3549 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3550 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3551 .class_mask = 0xffffff,
3552 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3554 { PCI_DEVICE(0x6549, 0x1200),
3555 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3556 /* Creative X-Fi (CA0110-IBG) */
3558 { PCI_DEVICE(0x1102, 0x0010),
3559 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3560 { PCI_DEVICE(0x1102, 0x0012),
3561 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3562 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3563 /* the following entry conflicts with snd-ctxfi driver,
3564 * as ctxfi driver mutates from HD-audio to native mode with
3565 * a special command sequence.
3567 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3568 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3569 .class_mask = 0xffffff,
3570 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3571 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3573 /* this entry seems still valid -- i.e. without emu20kx chip */
3574 { PCI_DEVICE(0x1102, 0x0009),
3575 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3576 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3579 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3580 /* VMware HDAudio */
3581 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3582 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3583 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3584 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3585 .class_mask = 0xffffff,
3586 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3587 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3588 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3589 .class_mask = 0xffffff,
3590 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3593 MODULE_DEVICE_TABLE(pci, azx_ids);
3595 /* pci_driver definition */
3596 static struct pci_driver azx_driver = {
3597 .name = KBUILD_MODNAME,
3598 .id_table = azx_ids,
3600 .remove = __devexit_p(azx_remove),
3606 module_pci_driver(azx_driver);