sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53
  54 #ifdef CONFIG_X86
  55 /* for snoop control */
  56 #include <asm/pgtable.h>
  57 #include <asm/cacheflush.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <linux/vgaarb.h>
  62 #include <linux/vga_switcheroo.h>
  63 #include <linux/firmware.h>
  64 #include "hda_codec.h"
  65
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  70 static char *model[SNDRV_CARDS];
  71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  74 static int probe_only[SNDRV_CARDS];
  75 static int jackpoll_ms[SNDRV_CARDS];
  76 static bool single_cmd;
  77 static int enable_msi = -1;
  78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  79 static char *patch[SNDRV_CARDS];
  80 #endif
  81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  84 #endif
  85
  86 module_param_array(index, int, NULL, 0444);
  87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  88 module_param_array(id, charp, NULL, 0444);
  89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  90 module_param_array(enable, bool, NULL, 0444);
  91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  92 module_param_array(model, charp, NULL, 0444);
  93 MODULE_PARM_DESC(model, "Use the given board model.");
  94 module_param_array(position_fix, int, NULL, 0444);
  95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  97 module_param_array(bdl_pos_adj, int, NULL, 0644);
  98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  99 module_param_array(probe_mask, int, NULL, 0444);
 100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 101 module_param_array(probe_only, int, NULL, 0444);
 102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 103 module_param_array(jackpoll_ms, int, NULL, 0444);
 104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 105 module_param(single_cmd, bool, 0444);
 106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 107                  "(for debugging only).");
 108 module_param(enable_msi, bint, 0444);
 109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 111 module_param_array(patch, charp, NULL, 0444);
 112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 113 #endif
 114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 115 module_param_array(beep_mode, bool, NULL, 0444);
 116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 117                             "(0=off, 1=on) (default=1).");
 118 #endif
 119
 120 #ifdef CONFIG_PM
 121 static int param_set_xint(const char *val, const struct kernel_param *kp);
 122 static struct kernel_param_ops param_ops_xint = {
 123         .set = param_set_xint,
 124         .get = param_get_int,
 125 };
 126 #define param_check_xint param_check_int
 127
 128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 129 module_param(power_save, xint, 0644);
 130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 131                  "(in second, 0 = disable).");
 132
 133 /* reset the HD-audio controller in power save mode.
 134  * this may give more power-saving, but will take longer time to
 135  * wake up.
 136  */
 137 static bool power_save_controller = 1;
 138 module_param(power_save_controller, bool, 0644);
 139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 140 #endif /* CONFIG_PM */
 141
 142 static int align_buffer_size = -1;
 143 module_param(align_buffer_size, bint, 0644);
 144 MODULE_PARM_DESC(align_buffer_size,
 145                 "Force buffer and period sizes to be multiple of 128 bytes.");
 146
 147 #ifdef CONFIG_X86
 148 static bool hda_snoop = true;
 149 module_param_named(snoop, hda_snoop, bool, 0444);
 150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 151 #define azx_snoop(chip)         (chip)->snoop
 152 #else
 153 #define hda_snoop               true
 154 #define azx_snoop(chip)         true
 155 #endif
 156
 157
 158 MODULE_LICENSE("GPL");
 159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 160                          "{Intel, ICH6M},"
 161                          "{Intel, ICH7},"
 162                          "{Intel, ESB2},"
 163                          "{Intel, ICH8},"
 164                          "{Intel, ICH9},"
 165                          "{Intel, ICH10},"
 166                          "{Intel, PCH},"
 167                          "{Intel, CPT},"
 168                          "{Intel, PPT},"
 169                          "{Intel, LPT},"
 170                          "{Intel, LPT_LP},"
 171                          "{Intel, HPT},"
 172                          "{Intel, PBG},"
 173                          "{Intel, SCH},"
 174                          "{ATI, SB450},"
 175                          "{ATI, SB600},"
 176                          "{ATI, RS600},"
 177                          "{ATI, RS690},"
 178                          "{ATI, RS780},"
 179                          "{ATI, R600},"
 180                          "{ATI, RV630},"
 181                          "{ATI, RV610},"
 182                          "{ATI, RV670},"
 183                          "{ATI, RV635},"
 184                          "{ATI, RV620},"
 185                          "{ATI, RV770},"
 186                          "{VIA, VT8251},"
 187                          "{VIA, VT8237A},"
 188                          "{SiS, SIS966},"
 189                          "{ULI, M5461}}");
 190 MODULE_DESCRIPTION("Intel HDA driver");
 191
 192 #ifdef CONFIG_SND_VERBOSE_PRINTK
 193 #define SFX     /* nop */
 194 #else
 195 #define SFX     "hda-intel "
 196 #endif
 197
 198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 200 #define SUPPORT_VGA_SWITCHEROO
 201 #endif
 202 #endif
 203
 204
 205 /*
 206  * registers
 207  */
 208 #define ICH6_REG_GCAP                   0x00
 209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 214 #define ICH6_REG_VMIN                   0x02
 215 #define ICH6_REG_VMAJ                   0x03
 216 #define ICH6_REG_OUTPAY                 0x04
 217 #define ICH6_REG_INPAY                  0x06
 218 #define ICH6_REG_GCTL                   0x08
 219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 222 #define ICH6_REG_WAKEEN                 0x0c
 223 #define ICH6_REG_STATESTS               0x0e
 224 #define ICH6_REG_GSTS                   0x10
 225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 226 #define ICH6_REG_INTCTL                 0x20
 227 #define ICH6_REG_INTSTS                 0x24
 228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 230 #define ICH6_REG_SSYNC                  0x38
 231 #define ICH6_REG_CORBLBASE              0x40
 232 #define ICH6_REG_CORBUBASE              0x44
 233 #define ICH6_REG_CORBWP                 0x48
 234 #define ICH6_REG_CORBRP                 0x4a
 235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 236 #define ICH6_REG_CORBCTL                0x4c
 237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 239 #define ICH6_REG_CORBSTS                0x4d
 240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 241 #define ICH6_REG_CORBSIZE               0x4e
 242
 243 #define ICH6_REG_RIRBLBASE              0x50
 244 #define ICH6_REG_RIRBUBASE              0x54
 245 #define ICH6_REG_RIRBWP                 0x58
 246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 247 #define ICH6_REG_RINTCNT                0x5a
 248 #define ICH6_REG_RIRBCTL                0x5c
 249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 252 #define ICH6_REG_RIRBSTS                0x5d
 253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 255 #define ICH6_REG_RIRBSIZE               0x5e
 256
 257 #define ICH6_REG_IC                     0x60
 258 #define ICH6_REG_IR                     0x64
 259 #define ICH6_REG_IRS                    0x68
 260 #define   ICH6_IRS_VALID        (1<<1)
 261 #define   ICH6_IRS_BUSY         (1<<0)
 262
 263 #define ICH6_REG_DPLBASE                0x70
 264 #define ICH6_REG_DPUBASE                0x74
 265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 266
 267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 269
 270 /* stream register offsets from stream base */
 271 #define ICH6_REG_SD_CTL                 0x00
 272 #define ICH6_REG_SD_STS                 0x03
 273 #define ICH6_REG_SD_LPIB                0x04
 274 #define ICH6_REG_SD_CBL                 0x08
 275 #define ICH6_REG_SD_LVI                 0x0c
 276 #define ICH6_REG_SD_FIFOW               0x0e
 277 #define ICH6_REG_SD_FIFOSIZE            0x10
 278 #define ICH6_REG_SD_FORMAT              0x12
 279 #define ICH6_REG_SD_BDLPL               0x18
 280 #define ICH6_REG_SD_BDLPU               0x1c
 281
 282 /* PCI space */
 283 #define ICH6_PCIREG_TCSEL       0x44
 284
 285 /*
 286  * other constants
 287  */
 288
 289 /* max number of SDs */
 290 /* ICH, ATI and VIA have 4 playback and 4 capture */
 291 #define ICH6_NUM_CAPTURE        4
 292 #define ICH6_NUM_PLAYBACK       4
 293
 294 /* ULI has 6 playback and 5 capture */
 295 #define ULI_NUM_CAPTURE         5
 296 #define ULI_NUM_PLAYBACK        6
 297
 298 /* ATI HDMI has 1 playback and 0 capture */
 299 #define ATIHDMI_NUM_CAPTURE     0
 300 #define ATIHDMI_NUM_PLAYBACK    1
 301
 302 /* TERA has 4 playback and 3 capture */
 303 #define TERA_NUM_CAPTURE        3
 304 #define TERA_NUM_PLAYBACK       4
 305
 306 /* this number is statically defined for simplicity */
 307 #define MAX_AZX_DEV             16
 308
 309 /* max number of fragments - we may use more if allocating more pages for BDL */
 310 #define BDL_SIZE                4096
 311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 312 #define AZX_MAX_FRAG            32
 313 /* max buffer size - no h/w limit, you can increase as you like */
 314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 315
 316 /* RIRB int mask: overrun[2], response[0] */
 317 #define RIRB_INT_RESPONSE       0x01
 318 #define RIRB_INT_OVERRUN        0x04
 319 #define RIRB_INT_MASK           0x05
 320
 321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 322 #define AZX_MAX_CODECS          8
 323 #define AZX_DEFAULT_CODECS      4
 324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 325
 326 /* SD_CTL bits */
 327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 333 #define SD_CTL_STREAM_TAG_SHIFT 20
 334
 335 /* SD_CTL and SD_STS */
 336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 340                                  SD_INT_COMPLETE)
 341
 342 /* SD_STS */
 343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 344
 345 /* INTCTL and INTSTS */
 346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 349
 350 /* below are so far hardcoded - should read registers in future */
 351 #define ICH6_MAX_CORB_ENTRIES   256
 352 #define ICH6_MAX_RIRB_ENTRIES   256
 353
 354 /* position fix mode */
 355 enum {
 356         POS_FIX_AUTO,
 357         POS_FIX_LPIB,
 358         POS_FIX_POSBUF,
 359         POS_FIX_VIACOMBO,
 360         POS_FIX_COMBO,
 361 };
 362
 363 /* Defines for ATI HD Audio support in SB450 south bridge */
 364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 366
 367 /* Defines for Nvidia HDA support */
 368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 370 #define NVIDIA_HDA_ISTRM_COH          0x4d
 371 #define NVIDIA_HDA_OSTRM_COH          0x4c
 372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 373
 374 /* Defines for Intel SCH HDA snoop control */
 375 #define INTEL_SCH_HDA_DEVC      0x78
 376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 377
 378 /* Define IN stream 0 FIFO size offset in VIA controller */
 379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 380 /* Define VIA HD Audio Device ID*/
 381 #define VIA_HDAC_DEVICE_ID              0x3288
 382
 383 /* HD Audio class code */
 384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 385
 386 /*
 387  */
 388
 389 struct azx_dev {
 390         struct snd_dma_buffer bdl; /* BDL buffer */
 391         u32 *posbuf;            /* position buffer pointer */
 392
 393         unsigned int bufsize;   /* size of the play buffer in bytes */
 394         unsigned int period_bytes; /* size of the period in bytes */
 395         unsigned int frags;     /* number for period in the play buffer */
 396         unsigned int fifo_size; /* FIFO size */
 397         unsigned long start_wallclk;    /* start + minimum wallclk */
 398         unsigned long period_wallclk;   /* wallclk for period */
 399
 400         void __iomem *sd_addr;  /* stream descriptor pointer */
 401
 402         u32 sd_int_sta_mask;    /* stream int status mask */
 403
 404         /* pcm support */
 405         struct snd_pcm_substream *substream;    /* assigned substream,
 406                                                  * set in PCM open
 407                                                  */
 408         unsigned int format_val;        /* format value to be set in the
 409                                          * controller and the codec
 410                                          */
 411         unsigned char stream_tag;       /* assigned stream */
 412         unsigned char index;            /* stream index */
 413         int assigned_key;               /* last device# key assigned to */
 414
 415         unsigned int opened :1;
 416         unsigned int running :1;
 417         unsigned int irq_pending :1;
 418         unsigned int prepared:1;
 419         unsigned int locked:1;
 420         /*
 421          * For VIA:
 422          *  A flag to ensure DMA position is 0
 423          *  when link position is not greater than FIFO size
 424          */
 425         unsigned int insufficient :1;
 426         unsigned int wc_marked:1;
 427         unsigned int no_period_wakeup:1;
 428
 429         struct timecounter  azx_tc;
 430         struct cyclecounter azx_cc;
 431
 432 #ifdef CONFIG_SND_HDA_DSP_LOADER
 433         struct mutex dsp_mutex;
 434 #endif
 435 };
 436
 437 /* DSP lock helpers */
 438 #ifdef CONFIG_SND_HDA_DSP_LOADER
 439 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
 440 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
 441 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
 442 #define dsp_is_locked(dev)      ((dev)->locked)
 443 #else
 444 #define dsp_lock_init(dev)      do {} while (0)
 445 #define dsp_lock(dev)           do {} while (0)
 446 #define dsp_unlock(dev)         do {} while (0)
 447 #define dsp_is_locked(dev)      0
 448 #endif
 449
 450 /* CORB/RIRB */
 451 struct azx_rb {
 452         u32 *buf;               /* CORB/RIRB buffer
 453                                  * Each CORB entry is 4byte, RIRB is 8byte
 454                                  */
 455         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 456         /* for RIRB */
 457         unsigned short rp, wp;  /* read/write pointers */
 458         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 459         u32 res[AZX_MAX_CODECS];        /* last read value */
 460 };
 461
 462 struct azx_pcm {
 463         struct azx *chip;
 464         struct snd_pcm *pcm;
 465         struct hda_codec *codec;
 466         struct hda_pcm_stream *hinfo[2];
 467         struct list_head list;
 468 };
 469
 470 struct azx {
 471         struct snd_card *card;
 472         struct pci_dev *pci;
 473         int dev_index;
 474
 475         /* chip type specific */
 476         int driver_type;
 477         unsigned int driver_caps;
 478         int playback_streams;
 479         int playback_index_offset;
 480         int capture_streams;
 481         int capture_index_offset;
 482         int num_streams;
 483
 484         /* pci resources */
 485         unsigned long addr;
 486         void __iomem *remap_addr;
 487         int irq;
 488
 489         /* locks */
 490         spinlock_t reg_lock;
 491         struct mutex open_mutex;
 492         struct completion probe_wait;
 493
 494         /* streams (x num_streams) */
 495         struct azx_dev *azx_dev;
 496
 497         /* PCM */
 498         struct list_head pcm_list; /* azx_pcm list */
 499
 500         /* HD codec */
 501         unsigned short codec_mask;
 502         int  codec_probe_mask; /* copied from probe_mask option */
 503         struct hda_bus *bus;
 504         unsigned int beep_mode;
 505
 506         /* CORB/RIRB */
 507         struct azx_rb corb;
 508         struct azx_rb rirb;
 509
 510         /* CORB/RIRB and position buffers */
 511         struct snd_dma_buffer rb;
 512         struct snd_dma_buffer posbuf;
 513
 514 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 515         const struct firmware *fw;
 516 #endif
 517
 518         /* flags */
 519         int position_fix[2]; /* for both playback/capture streams */
 520         int poll_count;
 521         unsigned int running :1;
 522         unsigned int initialized :1;
 523         unsigned int single_cmd :1;
 524         unsigned int polling_mode :1;
 525         unsigned int msi :1;
 526         unsigned int irq_pending_warned :1;
 527         unsigned int probing :1; /* codec probing phase */
 528         unsigned int snoop:1;
 529         unsigned int align_buffer_size:1;
 530         unsigned int region_requested:1;
 531
 532         /* VGA-switcheroo setup */
 533         unsigned int use_vga_switcheroo:1;
 534         unsigned int vga_switcheroo_registered:1;
 535         unsigned int init_failed:1; /* delayed init failed */
 536         unsigned int disabled:1; /* disabled by VGA-switcher */
 537
 538         /* for debugging */
 539         unsigned int last_cmd[AZX_MAX_CODECS];
 540
 541         /* for pending irqs */
 542         struct work_struct irq_pending_work;
 543
 544         /* reboot notifier (for mysterious hangup problem at power-down) */
 545         struct notifier_block reboot_notifier;
 546
 547         /* card list (for power_save trigger) */
 548         struct list_head list;
 549
 550 #ifdef CONFIG_SND_HDA_DSP_LOADER
 551         struct azx_dev saved_azx_dev;
 552 #endif
 553 };
 554
 555 #define CREATE_TRACE_POINTS
 556 #include "hda_intel_trace.h"
 557
 558 /* driver types */
 559 enum {
 560         AZX_DRIVER_ICH,
 561         AZX_DRIVER_PCH,
 562         AZX_DRIVER_SCH,
 563         AZX_DRIVER_ATI,
 564         AZX_DRIVER_ATIHDMI,
 565         AZX_DRIVER_ATIHDMI_NS,
 566         AZX_DRIVER_VIA,
 567         AZX_DRIVER_SIS,
 568         AZX_DRIVER_ULI,
 569         AZX_DRIVER_NVIDIA,
 570         AZX_DRIVER_TERA,
 571         AZX_DRIVER_CTX,
 572         AZX_DRIVER_CTHDA,
 573         AZX_DRIVER_GENERIC,
 574         AZX_NUM_DRIVERS, /* keep this as last entry */
 575 };
 576
 577 /* driver quirks (capabilities) */
 578 /* bits 0-7 are used for indicating driver type */
 579 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 580 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 581 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 582 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 583 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 584 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 585 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 586 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 587 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 588 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 589 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 590 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 591 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 592 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 593 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 594 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 595 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 596 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 597
 598 /* quirks for Intel PCH */
 599 #define AZX_DCAPS_INTEL_PCH_NOPM \
 600         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 601          AZX_DCAPS_COUNT_LPIB_DELAY)
 602
 603 #define AZX_DCAPS_INTEL_PCH \
 604         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 605
 606 /* quirks for ATI SB / AMD Hudson */
 607 #define AZX_DCAPS_PRESET_ATI_SB \
 608         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 609          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 610
 611 /* quirks for ATI/AMD HDMI */
 612 #define AZX_DCAPS_PRESET_ATI_HDMI \
 613         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 614
 615 /* quirks for Nvidia */
 616 #define AZX_DCAPS_PRESET_NVIDIA \
 617         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 618          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
 619
 620 #define AZX_DCAPS_PRESET_CTHDA \
 621         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 622
 623 /*
 624  * VGA-switcher support
 625  */
 626 #ifdef SUPPORT_VGA_SWITCHEROO
 627 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 628 #else
 629 #define use_vga_switcheroo(chip)        0
 630 #endif
 631
 632 static char *driver_short_names[] = {
 633         [AZX_DRIVER_ICH] = "HDA Intel",
 634         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 635         [AZX_DRIVER_SCH] = "HDA Intel MID",
 636         [AZX_DRIVER_ATI] = "HDA ATI SB",
 637         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 638         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 639         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 640         [AZX_DRIVER_SIS] = "HDA SIS966",
 641         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 642         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 643         [AZX_DRIVER_TERA] = "HDA Teradici",
 644         [AZX_DRIVER_CTX] = "HDA Creative",
 645         [AZX_DRIVER_CTHDA] = "HDA Creative",
 646         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 647 };
 648
 649 /*
 650  * macros for easy use
 651  */
 652 #define azx_writel(chip,reg,value) \
 653         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 654 #define azx_readl(chip,reg) \
 655         readl((chip)->remap_addr + ICH6_REG_##reg)
 656 #define azx_writew(chip,reg,value) \
 657         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 658 #define azx_readw(chip,reg) \
 659         readw((chip)->remap_addr + ICH6_REG_##reg)
 660 #define azx_writeb(chip,reg,value) \
 661         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 662 #define azx_readb(chip,reg) \
 663         readb((chip)->remap_addr + ICH6_REG_##reg)
 664
 665 #define azx_sd_writel(dev,reg,value) \
 666         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 667 #define azx_sd_readl(dev,reg) \
 668         readl((dev)->sd_addr + ICH6_REG_##reg)
 669 #define azx_sd_writew(dev,reg,value) \
 670         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 671 #define azx_sd_readw(dev,reg) \
 672         readw((dev)->sd_addr + ICH6_REG_##reg)
 673 #define azx_sd_writeb(dev,reg,value) \
 674         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 675 #define azx_sd_readb(dev,reg) \
 676         readb((dev)->sd_addr + ICH6_REG_##reg)
 677
 678 /* for pcm support */
 679 #define get_azx_dev(substream) (substream->runtime->private_data)
 680
 681 #ifdef CONFIG_X86
 682 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 683 {
 684         int pages;
 685
 686         if (azx_snoop(chip))
 687                 return;
 688         if (!dmab || !dmab->area || !dmab->bytes)
 689                 return;
 690
 691 #ifdef CONFIG_SND_DMA_SGBUF
 692         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 693                 struct snd_sg_buf *sgbuf = dmab->private_data;
 694                 if (on)
 695                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 696                 else
 697                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 698                 return;
 699         }
 700 #endif
 701
 702         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 703         if (on)
 704                 set_memory_wc((unsigned long)dmab->area, pages);
 705         else
 706                 set_memory_wb((unsigned long)dmab->area, pages);
 707 }
 708
 709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 710                                  bool on)
 711 {
 712         __mark_pages_wc(chip, buf, on);
 713 }
 714 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 715                                    struct snd_pcm_substream *substream, bool on)
 716 {
 717         if (azx_dev->wc_marked != on) {
 718                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 719                 azx_dev->wc_marked = on;
 720         }
 721 }
 722 #else
 723 /* NOP for other archs */
 724 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 725                                  bool on)
 726 {
 727 }
 728 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 729                                    struct snd_pcm_substream *substream, bool on)
 730 {
 731 }
 732 #endif
 733
 734 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 735 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 736 /*
 737  * Interface for HD codec
 738  */
 739
 740 /*
 741  * CORB / RIRB interface
 742  */
 743 static int azx_alloc_cmd_io(struct azx *chip)
 744 {
 745         int err;
 746
 747         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 748         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 749                                   snd_dma_pci_data(chip->pci),
 750                                   PAGE_SIZE, &chip->rb);
 751         if (err < 0) {
 752                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
 753                 return err;
 754         }
 755         mark_pages_wc(chip, &chip->rb, true);
 756         return 0;
 757 }
 758
 759 static void azx_init_cmd_io(struct azx *chip)
 760 {
 761         spin_lock_irq(&chip->reg_lock);
 762         /* CORB set up */
 763         chip->corb.addr = chip->rb.addr;
 764         chip->corb.buf = (u32 *)chip->rb.area;
 765         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 766         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 767
 768         /* set the corb size to 256 entries (ULI requires explicitly) */
 769         azx_writeb(chip, CORBSIZE, 0x02);
 770         /* set the corb write pointer to 0 */
 771         azx_writew(chip, CORBWP, 0);
 772         /* reset the corb hw read pointer */
 773         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 774         /* enable corb dma */
 775         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 776
 777         /* RIRB set up */
 778         chip->rirb.addr = chip->rb.addr + 2048;
 779         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 780         chip->rirb.wp = chip->rirb.rp = 0;
 781         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 782         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 783         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 784
 785         /* set the rirb size to 256 entries (ULI requires explicitly) */
 786         azx_writeb(chip, RIRBSIZE, 0x02);
 787         /* reset the rirb hw write pointer */
 788         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 789         /* set N=1, get RIRB response interrupt for new entry */
 790         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 791                 azx_writew(chip, RINTCNT, 0xc0);
 792         else
 793                 azx_writew(chip, RINTCNT, 1);
 794         /* enable rirb dma and response irq */
 795         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 796         spin_unlock_irq(&chip->reg_lock);
 797 }
 798
 799 static void azx_free_cmd_io(struct azx *chip)
 800 {
 801         spin_lock_irq(&chip->reg_lock);
 802         /* disable ringbuffer DMAs */
 803         azx_writeb(chip, RIRBCTL, 0);
 804         azx_writeb(chip, CORBCTL, 0);
 805         spin_unlock_irq(&chip->reg_lock);
 806 }
 807
 808 static unsigned int azx_command_addr(u32 cmd)
 809 {
 810         unsigned int addr = cmd >> 28;
 811
 812         if (addr >= AZX_MAX_CODECS) {
 813                 snd_BUG();
 814                 addr = 0;
 815         }
 816
 817         return addr;
 818 }
 819
 820 static unsigned int azx_response_addr(u32 res)
 821 {
 822         unsigned int addr = res & 0xf;
 823
 824         if (addr >= AZX_MAX_CODECS) {
 825                 snd_BUG();
 826                 addr = 0;
 827         }
 828
 829         return addr;
 830 }
 831
 832 /* send a command */
 833 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 834 {
 835         struct azx *chip = bus->private_data;
 836         unsigned int addr = azx_command_addr(val);
 837         unsigned int wp, rp;
 838
 839         spin_lock_irq(&chip->reg_lock);
 840
 841         /* add command to corb */
 842         wp = azx_readw(chip, CORBWP);
 843         if (wp == 0xffff) {
 844                 /* something wrong, controller likely turned to D3 */
 845                 spin_unlock_irq(&chip->reg_lock);
 846                 return -EIO;
 847         }
 848         wp++;
 849         wp %= ICH6_MAX_CORB_ENTRIES;
 850
 851         rp = azx_readw(chip, CORBRP);
 852         if (wp == rp) {
 853                 /* oops, it's full */
 854                 spin_unlock_irq(&chip->reg_lock);
 855                 return -EAGAIN;
 856         }
 857
 858         chip->rirb.cmds[addr]++;
 859         chip->corb.buf[wp] = cpu_to_le32(val);
 860         azx_writel(chip, CORBWP, wp);
 861
 862         spin_unlock_irq(&chip->reg_lock);
 863
 864         return 0;
 865 }
 866
 867 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 868
 869 /* retrieve RIRB entry - called from interrupt handler */
 870 static void azx_update_rirb(struct azx *chip)
 871 {
 872         unsigned int rp, wp;
 873         unsigned int addr;
 874         u32 res, res_ex;
 875
 876         wp = azx_readw(chip, RIRBWP);
 877         if (wp == 0xffff) {
 878                 /* something wrong, controller likely turned to D3 */
 879                 return;
 880         }
 881
 882         if (wp == chip->rirb.wp)
 883                 return;
 884         chip->rirb.wp = wp;
 885
 886         while (chip->rirb.rp != wp) {
 887                 chip->rirb.rp++;
 888                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 889
 890                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 891                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 892                 res = le32_to_cpu(chip->rirb.buf[rp]);
 893                 addr = azx_response_addr(res_ex);
 894                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 895                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 896                 else if (chip->rirb.cmds[addr]) {
 897                         chip->rirb.res[addr] = res;
 898                         smp_wmb();
 899                         chip->rirb.cmds[addr]--;
 900                 } else
 901                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
 902                                    "last cmd=%#08x\n",
 903                                    pci_name(chip->pci),
 904                                    res, res_ex,
 905                                    chip->last_cmd[addr]);
 906         }
 907 }
 908
 909 /* receive a response */
 910 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 911                                           unsigned int addr)
 912 {
 913         struct azx *chip = bus->private_data;
 914         unsigned long timeout;
 915         unsigned long loopcounter;
 916         int do_poll = 0;
 917
 918  again:
 919         timeout = jiffies + msecs_to_jiffies(1000);
 920
 921         for (loopcounter = 0;; loopcounter++) {
 922                 if (chip->polling_mode || do_poll) {
 923                         spin_lock_irq(&chip->reg_lock);
 924                         azx_update_rirb(chip);
 925                         spin_unlock_irq(&chip->reg_lock);
 926                 }
 927                 if (!chip->rirb.cmds[addr]) {
 928                         smp_rmb();
 929                         bus->rirb_error = 0;
 930
 931                         if (!do_poll)
 932                                 chip->poll_count = 0;
 933                         return chip->rirb.res[addr]; /* the last value */
 934                 }
 935                 if (time_after(jiffies, timeout))
 936                         break;
 937                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 938                         msleep(2); /* temporary workaround */
 939                 else {
 940                         udelay(10);
 941                         cond_resched();
 942                 }
 943         }
 944
 945         if (!bus->no_response_fallback)
 946                 return -1;
 947
 948         if (!chip->polling_mode && chip->poll_count < 2) {
 949                 snd_printdd(SFX "%s: azx_get_response timeout, "
 950                            "polling the codec once: last cmd=0x%08x\n",
 951                            pci_name(chip->pci), chip->last_cmd[addr]);
 952                 do_poll = 1;
 953                 chip->poll_count++;
 954                 goto again;
 955         }
 956
 957
 958         if (!chip->polling_mode) {
 959                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
 960                            "switching to polling mode: last cmd=0x%08x\n",
 961                            pci_name(chip->pci), chip->last_cmd[addr]);
 962                 chip->polling_mode = 1;
 963                 goto again;
 964         }
 965
 966         if (chip->msi) {
 967                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
 968                            "disabling MSI: last cmd=0x%08x\n",
 969                            pci_name(chip->pci), chip->last_cmd[addr]);
 970                 free_irq(chip->irq, chip);
 971                 chip->irq = -1;
 972                 pci_disable_msi(chip->pci);
 973                 chip->msi = 0;
 974                 if (azx_acquire_irq(chip, 1) < 0) {
 975                         bus->rirb_error = 1;
 976                         return -1;
 977                 }
 978                 goto again;
 979         }
 980
 981         if (chip->probing) {
 982                 /* If this critical timeout happens during the codec probing
 983                  * phase, this is likely an access to a non-existing codec
 984                  * slot.  Better to return an error and reset the system.
 985                  */
 986                 return -1;
 987         }
 988
 989         /* a fatal communication error; need either to reset or to fallback
 990          * to the single_cmd mode
 991          */
 992         bus->rirb_error = 1;
 993         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 994                 bus->response_reset = 1;
 995                 return -1; /* give a chance to retry */
 996         }
 997
 998         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 999                    "switching to single_cmd mode: last cmd=0x%08x\n",
1000                    chip->last_cmd[addr]);
1001         chip->single_cmd = 1;
1002         bus->response_reset = 0;
1003         /* release CORB/RIRB */
1004         azx_free_cmd_io(chip);
1005         /* disable unsolicited responses */
1006         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1007         return -1;
1008 }
1009
1010 /*
1011  * Use the single immediate command instead of CORB/RIRB for simplicity
1012  *
1013  * Note: according to Intel, this is not preferred use.  The command was
1014  *       intended for the BIOS only, and may get confused with unsolicited
1015  *       responses.  So, we shouldn't use it for normal operation from the
1016  *       driver.
1017  *       I left the codes, however, for debugging/testing purposes.
1018  */
1019
1020 /* receive a response */
1021 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1022 {
1023         int timeout = 50;
1024
1025         while (timeout--) {
1026                 /* check IRV busy bit */
1027                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1028                         /* reuse rirb.res as the response return value */
1029                         chip->rirb.res[addr] = azx_readl(chip, IR);
1030                         return 0;
1031                 }
1032                 udelay(1);
1033         }
1034         if (printk_ratelimit())
1035                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1036                            pci_name(chip->pci), azx_readw(chip, IRS));
1037         chip->rirb.res[addr] = -1;
1038         return -EIO;
1039 }
1040
1041 /* send a command */
1042 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1043 {
1044         struct azx *chip = bus->private_data;
1045         unsigned int addr = azx_command_addr(val);
1046         int timeout = 50;
1047
1048         bus->rirb_error = 0;
1049         while (timeout--) {
1050                 /* check ICB busy bit */
1051                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1052                         /* Clear IRV valid bit */
1053                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1054                                    ICH6_IRS_VALID);
1055                         azx_writel(chip, IC, val);
1056                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1057                                    ICH6_IRS_BUSY);
1058                         return azx_single_wait_for_response(chip, addr);
1059                 }
1060                 udelay(1);
1061         }
1062         if (printk_ratelimit())
1063                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1064                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1065         return -EIO;
1066 }
1067
1068 /* receive a response */
1069 static unsigned int azx_single_get_response(struct hda_bus *bus,
1070                                             unsigned int addr)
1071 {
1072         struct azx *chip = bus->private_data;
1073         return chip->rirb.res[addr];
1074 }
1075
1076 /*
1077  * The below are the main callbacks from hda_codec.
1078  *
1079  * They are just the skeleton to call sub-callbacks according to the
1080  * current setting of chip->single_cmd.
1081  */
1082
1083 /* send a command */
1084 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1085 {
1086         struct azx *chip = bus->private_data;
1087
1088         if (chip->disabled)
1089                 return 0;
1090         chip->last_cmd[azx_command_addr(val)] = val;
1091         if (chip->single_cmd)
1092                 return azx_single_send_cmd(bus, val);
1093         else
1094                 return azx_corb_send_cmd(bus, val);
1095 }
1096
1097 /* get a response */
1098 static unsigned int azx_get_response(struct hda_bus *bus,
1099                                      unsigned int addr)
1100 {
1101         struct azx *chip = bus->private_data;
1102         if (chip->disabled)
1103                 return 0;
1104         if (chip->single_cmd)
1105                 return azx_single_get_response(bus, addr);
1106         else
1107                 return azx_rirb_get_response(bus, addr);
1108 }
1109
1110 #ifdef CONFIG_PM
1111 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1112 #endif
1113
1114 #ifdef CONFIG_SND_HDA_DSP_LOADER
1115 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1116                                 unsigned int byte_size,
1117                                 struct snd_dma_buffer *bufp);
1118 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1119 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1120                                  struct snd_dma_buffer *dmab);
1121 #endif
1122
1123 /* enter link reset */
1124 static void azx_enter_link_reset(struct azx *chip)
1125 {
1126         unsigned long timeout;
1127
1128         /* reset controller */
1129         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1130
1131         timeout = jiffies + msecs_to_jiffies(100);
1132         while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1133                         time_before(jiffies, timeout))
1134                 usleep_range(500, 1000);
1135 }
1136
1137 /* exit link reset */
1138 static void azx_exit_link_reset(struct azx *chip)
1139 {
1140         unsigned long timeout;
1141
1142         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1143
1144         timeout = jiffies + msecs_to_jiffies(100);
1145         while (!azx_readb(chip, GCTL) &&
1146                         time_before(jiffies, timeout))
1147                 usleep_range(500, 1000);
1148 }
1149
1150 /* reset codec link */
1151 static int azx_reset(struct azx *chip, int full_reset)
1152 {
1153         if (!full_reset)
1154                 goto __skip;
1155
1156         /* clear STATESTS */
1157         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1158
1159         /* reset controller */
1160         azx_enter_link_reset(chip);
1161
1162         /* delay for >= 100us for codec PLL to settle per spec
1163          * Rev 0.9 section 5.5.1
1164          */
1165         usleep_range(500, 1000);
1166
1167         /* Bring controller out of reset */
1168         azx_exit_link_reset(chip);
1169
1170         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1171         usleep_range(1000, 1200);
1172
1173       __skip:
1174         /* check to see if controller is ready */
1175         if (!azx_readb(chip, GCTL)) {
1176                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1177                 return -EBUSY;
1178         }
1179
1180         /* Accept unsolicited responses */
1181         if (!chip->single_cmd)
1182                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1183                            ICH6_GCTL_UNSOL);
1184
1185         /* detect codecs */
1186         if (!chip->codec_mask) {
1187                 chip->codec_mask = azx_readw(chip, STATESTS);
1188                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1189         }
1190
1191         return 0;
1192 }
1193
1194
1195 /*
1196  * Lowlevel interface
1197  */
1198
1199 /* enable interrupts */
1200 static void azx_int_enable(struct azx *chip)
1201 {
1202         /* enable controller CIE and GIE */
1203         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1204                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1205 }
1206
1207 /* disable interrupts */
1208 static void azx_int_disable(struct azx *chip)
1209 {
1210         int i;
1211
1212         /* disable interrupts in stream descriptor */
1213         for (i = 0; i < chip->num_streams; i++) {
1214                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1215                 azx_sd_writeb(azx_dev, SD_CTL,
1216                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1217         }
1218
1219         /* disable SIE for all streams */
1220         azx_writeb(chip, INTCTL, 0);
1221
1222         /* disable controller CIE and GIE */
1223         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1224                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1225 }
1226
1227 /* clear interrupts */
1228 static void azx_int_clear(struct azx *chip)
1229 {
1230         int i;
1231
1232         /* clear stream status */
1233         for (i = 0; i < chip->num_streams; i++) {
1234                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1235                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1236         }
1237
1238         /* clear STATESTS */
1239         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1240
1241         /* clear rirb status */
1242         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1243
1244         /* clear int status */
1245         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1246 }
1247
1248 /* start a stream */
1249 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1250 {
1251         /*
1252          * Before stream start, initialize parameter
1253          */
1254         azx_dev->insufficient = 1;
1255
1256         /* enable SIE */
1257         azx_writel(chip, INTCTL,
1258                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1259         /* set DMA start and interrupt mask */
1260         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1261                       SD_CTL_DMA_START | SD_INT_MASK);
1262 }
1263
1264 /* stop DMA */
1265 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1266 {
1267         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1268                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1269         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1270 }
1271
1272 /* stop a stream */
1273 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1274 {
1275         azx_stream_clear(chip, azx_dev);
1276         /* disable SIE */
1277         azx_writel(chip, INTCTL,
1278                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1279 }
1280
1281
1282 /*
1283  * reset and start the controller registers
1284  */
1285 static void azx_init_chip(struct azx *chip, int full_reset)
1286 {
1287         if (chip->initialized)
1288                 return;
1289
1290         /* reset controller */
1291         azx_reset(chip, full_reset);
1292
1293         /* initialize interrupts */
1294         azx_int_clear(chip);
1295         azx_int_enable(chip);
1296
1297         /* initialize the codec command I/O */
1298         if (!chip->single_cmd)
1299                 azx_init_cmd_io(chip);
1300
1301         /* program the position buffer */
1302         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1303         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1304
1305         chip->initialized = 1;
1306 }
1307
1308 /*
1309  * initialize the PCI registers
1310  */
1311 /* update bits in a PCI register byte */
1312 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1313                             unsigned char mask, unsigned char val)
1314 {
1315         unsigned char data;
1316
1317         pci_read_config_byte(pci, reg, &data);
1318         data &= ~mask;
1319         data |= (val & mask);
1320         pci_write_config_byte(pci, reg, data);
1321 }
1322
1323 static void azx_init_pci(struct azx *chip)
1324 {
1325         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1326          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1327          * Ensuring these bits are 0 clears playback static on some HD Audio
1328          * codecs.
1329          * The PCI register TCSEL is defined in the Intel manuals.
1330          */
1331         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1332                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1333                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1334         }
1335
1336         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1337          * we need to enable snoop.
1338          */
1339         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1340                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1341                 update_pci_byte(chip->pci,
1342                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1343                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1344         }
1345
1346         /* For NVIDIA HDA, enable snoop */
1347         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1348                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1349                 update_pci_byte(chip->pci,
1350                                 NVIDIA_HDA_TRANSREG_ADDR,
1351                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1352                 update_pci_byte(chip->pci,
1353                                 NVIDIA_HDA_ISTRM_COH,
1354                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1355                 update_pci_byte(chip->pci,
1356                                 NVIDIA_HDA_OSTRM_COH,
1357                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1358         }
1359
1360         /* Enable SCH/PCH snoop if needed */
1361         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1362                 unsigned short snoop;
1363                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1364                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1365                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1366                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1367                         if (!azx_snoop(chip))
1368                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1369                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1370                         pci_read_config_word(chip->pci,
1371                                 INTEL_SCH_HDA_DEVC, &snoop);
1372                 }
1373                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1374                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1375                                 ? "Disabled" : "Enabled");
1376         }
1377 }
1378
1379
1380 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1381
1382 /*
1383  * interrupt handler
1384  */
1385 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1386 {
1387         struct azx *chip = dev_id;
1388         struct azx_dev *azx_dev;
1389         u32 status;
1390         u8 sd_status;
1391         int i, ok;
1392
1393 #ifdef CONFIG_PM_RUNTIME
1394         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1395                 return IRQ_NONE;
1396 #endif
1397
1398         spin_lock(&chip->reg_lock);
1399
1400         if (chip->disabled) {
1401                 spin_unlock(&chip->reg_lock);
1402                 return IRQ_NONE;
1403         }
1404
1405         status = azx_readl(chip, INTSTS);
1406         if (status == 0) {
1407                 spin_unlock(&chip->reg_lock);
1408                 return IRQ_NONE;
1409         }
1410
1411         for (i = 0; i < chip->num_streams; i++) {
1412                 azx_dev = &chip->azx_dev[i];
1413                 if (status & azx_dev->sd_int_sta_mask) {
1414                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1415                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1416                         if (!azx_dev->substream || !azx_dev->running ||
1417                             !(sd_status & SD_INT_COMPLETE))
1418                                 continue;
1419                         /* check whether this IRQ is really acceptable */
1420                         ok = azx_position_ok(chip, azx_dev);
1421                         if (ok == 1) {
1422                                 azx_dev->irq_pending = 0;
1423                                 spin_unlock(&chip->reg_lock);
1424                                 snd_pcm_period_elapsed(azx_dev->substream);
1425                                 spin_lock(&chip->reg_lock);
1426                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1427                                 /* bogus IRQ, process it later */
1428                                 azx_dev->irq_pending = 1;
1429                                 queue_work(chip->bus->workq,
1430                                            &chip->irq_pending_work);
1431                         }
1432                 }
1433         }
1434
1435         /* clear rirb int */
1436         status = azx_readb(chip, RIRBSTS);
1437         if (status & RIRB_INT_MASK) {
1438                 if (status & RIRB_INT_RESPONSE) {
1439                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1440                                 udelay(80);
1441                         azx_update_rirb(chip);
1442                 }
1443                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1444         }
1445
1446 #if 0
1447         /* clear state status int */
1448         if (azx_readb(chip, STATESTS) & 0x04)
1449                 azx_writeb(chip, STATESTS, 0x04);
1450 #endif
1451         spin_unlock(&chip->reg_lock);
1452
1453         return IRQ_HANDLED;
1454 }
1455
1456
1457 /*
1458  * set up a BDL entry
1459  */
1460 static int setup_bdle(struct azx *chip,
1461                       struct snd_dma_buffer *dmab,
1462                       struct azx_dev *azx_dev, u32 **bdlp,
1463                       int ofs, int size, int with_ioc)
1464 {
1465         u32 *bdl = *bdlp;
1466
1467         while (size > 0) {
1468                 dma_addr_t addr;
1469                 int chunk;
1470
1471                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1472                         return -EINVAL;
1473
1474                 addr = snd_sgbuf_get_addr(dmab, ofs);
1475                 /* program the address field of the BDL entry */
1476                 bdl[0] = cpu_to_le32((u32)addr);
1477                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1478                 /* program the size field of the BDL entry */
1479                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1480                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1481                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1482                         u32 remain = 0x1000 - (ofs & 0xfff);
1483                         if (chunk > remain)
1484                                 chunk = remain;
1485                 }
1486                 bdl[2] = cpu_to_le32(chunk);
1487                 /* program the IOC to enable interrupt
1488                  * only when the whole fragment is processed
1489                  */
1490                 size -= chunk;
1491                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1492                 bdl += 4;
1493                 azx_dev->frags++;
1494                 ofs += chunk;
1495         }
1496         *bdlp = bdl;
1497         return ofs;
1498 }
1499
1500 /*
1501  * set up BDL entries
1502  */
1503 static int azx_setup_periods(struct azx *chip,
1504                              struct snd_pcm_substream *substream,
1505                              struct azx_dev *azx_dev)
1506 {
1507         u32 *bdl;
1508         int i, ofs, periods, period_bytes;
1509         int pos_adj;
1510
1511         /* reset BDL address */
1512         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1513         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1514
1515         period_bytes = azx_dev->period_bytes;
1516         periods = azx_dev->bufsize / period_bytes;
1517
1518         /* program the initial BDL entries */
1519         bdl = (u32 *)azx_dev->bdl.area;
1520         ofs = 0;
1521         azx_dev->frags = 0;
1522         pos_adj = bdl_pos_adj[chip->dev_index];
1523         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1524                 struct snd_pcm_runtime *runtime = substream->runtime;
1525                 int pos_align = pos_adj;
1526                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1527                 if (!pos_adj)
1528                         pos_adj = pos_align;
1529                 else
1530                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1531                                 pos_align;
1532                 pos_adj = frames_to_bytes(runtime, pos_adj);
1533                 if (pos_adj >= period_bytes) {
1534                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1535                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1536                         pos_adj = 0;
1537                 } else {
1538                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1539                                          azx_dev,
1540                                          &bdl, ofs, pos_adj, true);
1541                         if (ofs < 0)
1542                                 goto error;
1543                 }
1544         } else
1545                 pos_adj = 0;
1546         for (i = 0; i < periods; i++) {
1547                 if (i == periods - 1 && pos_adj)
1548                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1549                                          azx_dev, &bdl, ofs,
1550                                          period_bytes - pos_adj, 0);
1551                 else
1552                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1553                                          azx_dev, &bdl, ofs,
1554                                          period_bytes,
1555                                          !azx_dev->no_period_wakeup);
1556                 if (ofs < 0)
1557                         goto error;
1558         }
1559         return 0;
1560
1561  error:
1562         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1563                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1564         return -EINVAL;
1565 }
1566
1567 /* reset stream */
1568 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1569 {
1570         unsigned char val;
1571         int timeout;
1572
1573         azx_stream_clear(chip, azx_dev);
1574
1575         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1576                       SD_CTL_STREAM_RESET);
1577         udelay(3);
1578         timeout = 300;
1579         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1580                --timeout)
1581                 ;
1582         val &= ~SD_CTL_STREAM_RESET;
1583         azx_sd_writeb(azx_dev, SD_CTL, val);
1584         udelay(3);
1585
1586         timeout = 300;
1587         /* waiting for hardware to report that the stream is out of reset */
1588         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1589                --timeout)
1590                 ;
1591
1592         /* reset first position - may not be synced with hw at this time */
1593         *azx_dev->posbuf = 0;
1594 }
1595
1596 /*
1597  * set up the SD for streaming
1598  */
1599 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1600 {
1601         unsigned int val;
1602         /* make sure the run bit is zero for SD */
1603         azx_stream_clear(chip, azx_dev);
1604         /* program the stream_tag */
1605         val = azx_sd_readl(azx_dev, SD_CTL);
1606         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1607                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1608         if (!azx_snoop(chip))
1609                 val |= SD_CTL_TRAFFIC_PRIO;
1610         azx_sd_writel(azx_dev, SD_CTL, val);
1611
1612         /* program the length of samples in cyclic buffer */
1613         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1614
1615         /* program the stream format */
1616         /* this value needs to be the same as the one programmed */
1617         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1618
1619         /* program the stream LVI (last valid index) of the BDL */
1620         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1621
1622         /* program the BDL address */
1623         /* lower BDL address */
1624         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1625         /* upper BDL address */
1626         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1627
1628         /* enable the position buffer */
1629         if (chip->position_fix[0] != POS_FIX_LPIB ||
1630             chip->position_fix[1] != POS_FIX_LPIB) {
1631                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1632                         azx_writel(chip, DPLBASE,
1633                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1634         }
1635
1636         /* set the interrupt enable bits in the descriptor control register */
1637         azx_sd_writel(azx_dev, SD_CTL,
1638                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1639
1640         return 0;
1641 }
1642
1643 /*
1644  * Probe the given codec address
1645  */
1646 static int probe_codec(struct azx *chip, int addr)
1647 {
1648         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1649                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1650         unsigned int res;
1651
1652         mutex_lock(&chip->bus->cmd_mutex);
1653         chip->probing = 1;
1654         azx_send_cmd(chip->bus, cmd);
1655         res = azx_get_response(chip->bus, addr);
1656         chip->probing = 0;
1657         mutex_unlock(&chip->bus->cmd_mutex);
1658         if (res == -1)
1659                 return -EIO;
1660         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1661         return 0;
1662 }
1663
1664 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1665                                  struct hda_pcm *cpcm);
1666 static void azx_stop_chip(struct azx *chip);
1667
1668 static void azx_bus_reset(struct hda_bus *bus)
1669 {
1670         struct azx *chip = bus->private_data;
1671
1672         bus->in_reset = 1;
1673         azx_stop_chip(chip);
1674         azx_init_chip(chip, 1);
1675 #ifdef CONFIG_PM
1676         if (chip->initialized) {
1677                 struct azx_pcm *p;
1678                 list_for_each_entry(p, &chip->pcm_list, list)
1679                         snd_pcm_suspend_all(p->pcm);
1680                 snd_hda_suspend(chip->bus);
1681                 snd_hda_resume(chip->bus);
1682         }
1683 #endif
1684         bus->in_reset = 0;
1685 }
1686
1687 static int get_jackpoll_interval(struct azx *chip)
1688 {
1689         int i = jackpoll_ms[chip->dev_index];
1690         unsigned int j;
1691         if (i == 0)
1692                 return 0;
1693         if (i < 50 || i > 60000)
1694                 j = 0;
1695         else
1696                 j = msecs_to_jiffies(i);
1697         if (j == 0)
1698                 snd_printk(KERN_WARNING SFX
1699                            "jackpoll_ms value out of range: %d\n", i);
1700         return j;
1701 }
1702
1703 /*
1704  * Codec initialization
1705  */
1706
1707 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1708 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1709         [AZX_DRIVER_NVIDIA] = 8,
1710         [AZX_DRIVER_TERA] = 1,
1711 };
1712
1713 static int azx_codec_create(struct azx *chip, const char *model)
1714 {
1715         struct hda_bus_template bus_temp;
1716         int c, codecs, err;
1717         int max_slots;
1718
1719         memset(&bus_temp, 0, sizeof(bus_temp));
1720         bus_temp.private_data = chip;
1721         bus_temp.modelname = model;
1722         bus_temp.pci = chip->pci;
1723         bus_temp.ops.command = azx_send_cmd;
1724         bus_temp.ops.get_response = azx_get_response;
1725         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1726         bus_temp.ops.bus_reset = azx_bus_reset;
1727 #ifdef CONFIG_PM
1728         bus_temp.power_save = &power_save;
1729         bus_temp.ops.pm_notify = azx_power_notify;
1730 #endif
1731 #ifdef CONFIG_SND_HDA_DSP_LOADER
1732         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1733         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1734         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1735 #endif
1736
1737         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1738         if (err < 0)
1739                 return err;
1740
1741         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1742                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1743                 chip->bus->needs_damn_long_delay = 1;
1744         }
1745
1746         codecs = 0;
1747         max_slots = azx_max_codecs[chip->driver_type];
1748         if (!max_slots)
1749                 max_slots = AZX_DEFAULT_CODECS;
1750
1751         /* First try to probe all given codec slots */
1752         for (c = 0; c < max_slots; c++) {
1753                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1754                         if (probe_codec(chip, c) < 0) {
1755                                 /* Some BIOSen give you wrong codec addresses
1756                                  * that don't exist
1757                                  */
1758                                 snd_printk(KERN_WARNING SFX
1759                                            "%s: Codec #%d probe error; "
1760                                            "disabling it...\n", pci_name(chip->pci), c);
1761                                 chip->codec_mask &= ~(1 << c);
1762                                 /* More badly, accessing to a non-existing
1763                                  * codec often screws up the controller chip,
1764                                  * and disturbs the further communications.
1765                                  * Thus if an error occurs during probing,
1766                                  * better to reset the controller chip to
1767                                  * get back to the sanity state.
1768                                  */
1769                                 azx_stop_chip(chip);
1770                                 azx_init_chip(chip, 1);
1771                         }
1772                 }
1773         }
1774
1775         /* AMD chipsets often cause the communication stalls upon certain
1776          * sequence like the pin-detection.  It seems that forcing the synced
1777          * access works around the stall.  Grrr...
1778          */
1779         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1780                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1781                         pci_name(chip->pci));
1782                 chip->bus->sync_write = 1;
1783                 chip->bus->allow_bus_reset = 1;
1784         }
1785
1786         /* Then create codec instances */
1787         for (c = 0; c < max_slots; c++) {
1788                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1789                         struct hda_codec *codec;
1790                         err = snd_hda_codec_new(chip->bus, c, &codec);
1791                         if (err < 0)
1792                                 continue;
1793                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1794                         codec->beep_mode = chip->beep_mode;
1795                         codecs++;
1796                 }
1797         }
1798         if (!codecs) {
1799                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1800                 return -ENXIO;
1801         }
1802         return 0;
1803 }
1804
1805 /* configure each codec instance */
1806 static int azx_codec_configure(struct azx *chip)
1807 {
1808         struct hda_codec *codec;
1809         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1810                 snd_hda_codec_configure(codec);
1811         }
1812         return 0;
1813 }
1814
1815
1816 /*
1817  * PCM support
1818  */
1819
1820 /* assign a stream for the PCM */
1821 static inline struct azx_dev *
1822 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1823 {
1824         int dev, i, nums;
1825         struct azx_dev *res = NULL;
1826         /* make a non-zero unique key for the substream */
1827         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1828                 (substream->stream + 1);
1829
1830         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1831                 dev = chip->playback_index_offset;
1832                 nums = chip->playback_streams;
1833         } else {
1834                 dev = chip->capture_index_offset;
1835                 nums = chip->capture_streams;
1836         }
1837         for (i = 0; i < nums; i++, dev++) {
1838                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1839                 dsp_lock(azx_dev);
1840                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1841                         res = azx_dev;
1842                         if (res->assigned_key == key) {
1843                                 res->opened = 1;
1844                                 res->assigned_key = key;
1845                                 dsp_unlock(azx_dev);
1846                                 return azx_dev;
1847                         }
1848                 }
1849                 dsp_unlock(azx_dev);
1850         }
1851         if (res) {
1852                 dsp_lock(res);
1853                 res->opened = 1;
1854                 res->assigned_key = key;
1855                 dsp_unlock(res);
1856         }
1857         return res;
1858 }
1859
1860 /* release the assigned stream */
1861 static inline void azx_release_device(struct azx_dev *azx_dev)
1862 {
1863         azx_dev->opened = 0;
1864 }
1865
1866 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1867 {
1868         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1869         struct snd_pcm_substream *substream = azx_dev->substream;
1870         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1871         struct azx *chip = apcm->chip;
1872
1873         return azx_readl(chip, WALLCLK);
1874 }
1875
1876 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1877                                 bool force, cycle_t last)
1878 {
1879         struct azx_dev *azx_dev = get_azx_dev(substream);
1880         struct timecounter *tc = &azx_dev->azx_tc;
1881         struct cyclecounter *cc = &azx_dev->azx_cc;
1882         u64 nsec;
1883
1884         cc->read = azx_cc_read;
1885         cc->mask = CLOCKSOURCE_MASK(32);
1886
1887         /*
1888          * Converting from 24 MHz to ns means applying a 125/3 factor.
1889          * To avoid any saturation issues in intermediate operations,
1890          * the 125 factor is applied first. The division is applied
1891          * last after reading the timecounter value.
1892          * Applying the 1/3 factor as part of the multiplication
1893          * requires at least 20 bits for a decent precision, however
1894          * overflows occur after about 4 hours or less, not a option.
1895          */
1896
1897         cc->mult = 125; /* saturation after 195 years */
1898         cc->shift = 0;
1899
1900         nsec = 0; /* audio time is elapsed time since trigger */
1901         timecounter_init(tc, cc, nsec);
1902         if (force)
1903                 /*
1904                  * force timecounter to use predefined value,
1905                  * used for synchronized starts
1906                  */
1907                 tc->cycle_last = last;
1908 }
1909
1910 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1911                                 u64 nsec)
1912 {
1913         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1914         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1915         u64 codec_frames, codec_nsecs;
1916
1917         if (!hinfo->ops.get_delay)
1918                 return nsec;
1919
1920         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1921         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1922                               substream->runtime->rate);
1923
1924         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1925                 return nsec + codec_nsecs;
1926
1927         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1928 }
1929
1930 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1931                                 struct timespec *ts)
1932 {
1933         struct azx_dev *azx_dev = get_azx_dev(substream);
1934         u64 nsec;
1935
1936         nsec = timecounter_read(&azx_dev->azx_tc);
1937         nsec = div_u64(nsec, 3); /* can be optimized */
1938         nsec = azx_adjust_codec_delay(substream, nsec);
1939
1940         *ts = ns_to_timespec(nsec);
1941
1942         return 0;
1943 }
1944
1945 static struct snd_pcm_hardware azx_pcm_hw = {
1946         .info =                 (SNDRV_PCM_INFO_MMAP |
1947                                  SNDRV_PCM_INFO_INTERLEAVED |
1948                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1949                                  SNDRV_PCM_INFO_MMAP_VALID |
1950                                  /* No full-resume yet implemented */
1951                                  /* SNDRV_PCM_INFO_RESUME |*/
1952                                  SNDRV_PCM_INFO_PAUSE |
1953                                  SNDRV_PCM_INFO_SYNC_START |
1954                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1955                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1956         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1957         .rates =                SNDRV_PCM_RATE_48000,
1958         .rate_min =             48000,
1959         .rate_max =             48000,
1960         .channels_min =         2,
1961         .channels_max =         2,
1962         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1963         .period_bytes_min =     128,
1964         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1965         .periods_min =          2,
1966         .periods_max =          AZX_MAX_FRAG,
1967         .fifo_size =            0,
1968 };
1969
1970 static int azx_pcm_open(struct snd_pcm_substream *substream)
1971 {
1972         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1973         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1974         struct azx *chip = apcm->chip;
1975         struct azx_dev *azx_dev;
1976         struct snd_pcm_runtime *runtime = substream->runtime;
1977         unsigned long flags;
1978         int err;
1979         int buff_step;
1980
1981         mutex_lock(&chip->open_mutex);
1982         azx_dev = azx_assign_device(chip, substream);
1983         if (azx_dev == NULL) {
1984                 mutex_unlock(&chip->open_mutex);
1985                 return -EBUSY;
1986         }
1987         runtime->hw = azx_pcm_hw;
1988         runtime->hw.channels_min = hinfo->channels_min;
1989         runtime->hw.channels_max = hinfo->channels_max;
1990         runtime->hw.formats = hinfo->formats;
1991         runtime->hw.rates = hinfo->rates;
1992         snd_pcm_limit_hw_rates(runtime);
1993         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1994
1995         /* avoid wrap-around with wall-clock */
1996         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1997                                 20,
1998                                 178000000);
1999
2000         if (chip->align_buffer_size)
2001                 /* constrain buffer sizes to be multiple of 128
2002                    bytes. This is more efficient in terms of memory
2003                    access but isn't required by the HDA spec and
2004                    prevents users from specifying exact period/buffer
2005                    sizes. For example for 44.1kHz, a period size set
2006                    to 20ms will be rounded to 19.59ms. */
2007                 buff_step = 128;
2008         else
2009                 /* Don't enforce steps on buffer sizes, still need to
2010                    be multiple of 4 bytes (HDA spec). Tested on Intel
2011                    HDA controllers, may not work on all devices where
2012                    option needs to be disabled */
2013                 buff_step = 4;
2014
2015         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2016                                    buff_step);
2017         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2018                                    buff_step);
2019         snd_hda_power_up_d3wait(apcm->codec);
2020         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2021         if (err < 0) {
2022                 azx_release_device(azx_dev);
2023                 snd_hda_power_down(apcm->codec);
2024                 mutex_unlock(&chip->open_mutex);
2025                 return err;
2026         }
2027         snd_pcm_limit_hw_rates(runtime);
2028         /* sanity check */
2029         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2030             snd_BUG_ON(!runtime->hw.channels_max) ||
2031             snd_BUG_ON(!runtime->hw.formats) ||
2032             snd_BUG_ON(!runtime->hw.rates)) {
2033                 azx_release_device(azx_dev);
2034                 hinfo->ops.close(hinfo, apcm->codec, substream);
2035                 snd_hda_power_down(apcm->codec);
2036                 mutex_unlock(&chip->open_mutex);
2037                 return -EINVAL;
2038         }
2039
2040         /* disable WALLCLOCK timestamps for capture streams
2041            until we figure out how to handle digital inputs */
2042         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2043                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2044
2045         spin_lock_irqsave(&chip->reg_lock, flags);
2046         azx_dev->substream = substream;
2047         azx_dev->running = 0;
2048         spin_unlock_irqrestore(&chip->reg_lock, flags);
2049
2050         runtime->private_data = azx_dev;
2051         snd_pcm_set_sync(substream);
2052         mutex_unlock(&chip->open_mutex);
2053         return 0;
2054 }
2055
2056 static int azx_pcm_close(struct snd_pcm_substream *substream)
2057 {
2058         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2059         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2060         struct azx *chip = apcm->chip;
2061         struct azx_dev *azx_dev = get_azx_dev(substream);
2062         unsigned long flags;
2063
2064         mutex_lock(&chip->open_mutex);
2065         spin_lock_irqsave(&chip->reg_lock, flags);
2066         azx_dev->substream = NULL;
2067         azx_dev->running = 0;
2068         spin_unlock_irqrestore(&chip->reg_lock, flags);
2069         azx_release_device(azx_dev);
2070         hinfo->ops.close(hinfo, apcm->codec, substream);
2071         snd_hda_power_down(apcm->codec);
2072         mutex_unlock(&chip->open_mutex);
2073         return 0;
2074 }
2075
2076 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2077                              struct snd_pcm_hw_params *hw_params)
2078 {
2079         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2080         struct azx *chip = apcm->chip;
2081         struct azx_dev *azx_dev = get_azx_dev(substream);
2082         int ret;
2083
2084         dsp_lock(azx_dev);
2085         if (dsp_is_locked(azx_dev)) {
2086                 ret = -EBUSY;
2087                 goto unlock;
2088         }
2089
2090         mark_runtime_wc(chip, azx_dev, substream, false);
2091         azx_dev->bufsize = 0;
2092         azx_dev->period_bytes = 0;
2093         azx_dev->format_val = 0;
2094         ret = snd_pcm_lib_malloc_pages(substream,
2095                                         params_buffer_bytes(hw_params));
2096         if (ret < 0)
2097                 goto unlock;
2098         mark_runtime_wc(chip, azx_dev, substream, true);
2099  unlock:
2100         dsp_unlock(azx_dev);
2101         return ret;
2102 }
2103
2104 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2105 {
2106         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2107         struct azx_dev *azx_dev = get_azx_dev(substream);
2108         struct azx *chip = apcm->chip;
2109         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2110
2111         /* reset BDL address */
2112         dsp_lock(azx_dev);
2113         if (!dsp_is_locked(azx_dev)) {
2114                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2115                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2116                 azx_sd_writel(azx_dev, SD_CTL, 0);
2117                 azx_dev->bufsize = 0;
2118                 azx_dev->period_bytes = 0;
2119                 azx_dev->format_val = 0;
2120         }
2121
2122         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2123
2124         mark_runtime_wc(chip, azx_dev, substream, false);
2125         azx_dev->prepared = 0;
2126         dsp_unlock(azx_dev);
2127         return snd_pcm_lib_free_pages(substream);
2128 }
2129
2130 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2131 {
2132         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2133         struct azx *chip = apcm->chip;
2134         struct azx_dev *azx_dev = get_azx_dev(substream);
2135         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2136         struct snd_pcm_runtime *runtime = substream->runtime;
2137         unsigned int bufsize, period_bytes, format_val, stream_tag;
2138         int err;
2139         struct hda_spdif_out *spdif =
2140                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2141         unsigned short ctls = spdif ? spdif->ctls : 0;
2142
2143         dsp_lock(azx_dev);
2144         if (dsp_is_locked(azx_dev)) {
2145                 err = -EBUSY;
2146                 goto unlock;
2147         }
2148
2149         azx_stream_reset(chip, azx_dev);
2150         format_val = snd_hda_calc_stream_format(runtime->rate,
2151                                                 runtime->channels,
2152                                                 runtime->format,
2153                                                 hinfo->maxbps,
2154                                                 ctls);
2155         if (!format_val) {
2156                 snd_printk(KERN_ERR SFX
2157                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2158                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2159                 err = -EINVAL;
2160                 goto unlock;
2161         }
2162
2163         bufsize = snd_pcm_lib_buffer_bytes(substream);
2164         period_bytes = snd_pcm_lib_period_bytes(substream);
2165
2166         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2167                     pci_name(chip->pci), bufsize, format_val);
2168
2169         if (bufsize != azx_dev->bufsize ||
2170             period_bytes != azx_dev->period_bytes ||
2171             format_val != azx_dev->format_val ||
2172             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2173                 azx_dev->bufsize = bufsize;
2174                 azx_dev->period_bytes = period_bytes;
2175                 azx_dev->format_val = format_val;
2176                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2177                 err = azx_setup_periods(chip, substream, azx_dev);
2178                 if (err < 0)
2179                         goto unlock;
2180         }
2181
2182         /* wallclk has 24Mhz clock source */
2183         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2184                                                 runtime->rate) * 1000);
2185         azx_setup_controller(chip, azx_dev);
2186         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2187                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2188         else
2189                 azx_dev->fifo_size = 0;
2190
2191         stream_tag = azx_dev->stream_tag;
2192         /* CA-IBG chips need the playback stream starting from 1 */
2193         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2194             stream_tag > chip->capture_streams)
2195                 stream_tag -= chip->capture_streams;
2196         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2197                                      azx_dev->format_val, substream);
2198
2199  unlock:
2200         if (!err)
2201                 azx_dev->prepared = 1;
2202         dsp_unlock(azx_dev);
2203         return err;
2204 }
2205
2206 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2207 {
2208         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2209         struct azx *chip = apcm->chip;
2210         struct azx_dev *azx_dev;
2211         struct snd_pcm_substream *s;
2212         int rstart = 0, start, nsync = 0, sbits = 0;
2213         int nwait, timeout;
2214
2215         azx_dev = get_azx_dev(substream);
2216         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2217
2218         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2219                 return -EPIPE;
2220
2221         switch (cmd) {
2222         case SNDRV_PCM_TRIGGER_START:
2223                 rstart = 1;
2224         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2225         case SNDRV_PCM_TRIGGER_RESUME:
2226                 start = 1;
2227                 break;
2228         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2229         case SNDRV_PCM_TRIGGER_SUSPEND:
2230         case SNDRV_PCM_TRIGGER_STOP:
2231                 start = 0;
2232                 break;
2233         default:
2234                 return -EINVAL;
2235         }
2236
2237         snd_pcm_group_for_each_entry(s, substream) {
2238                 if (s->pcm->card != substream->pcm->card)
2239                         continue;
2240                 azx_dev = get_azx_dev(s);
2241                 sbits |= 1 << azx_dev->index;
2242                 nsync++;
2243                 snd_pcm_trigger_done(s, substream);
2244         }
2245
2246         spin_lock(&chip->reg_lock);
2247
2248         /* first, set SYNC bits of corresponding streams */
2249         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2250                 azx_writel(chip, OLD_SSYNC,
2251                         azx_readl(chip, OLD_SSYNC) | sbits);
2252         else
2253                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2254
2255         snd_pcm_group_for_each_entry(s, substream) {
2256                 if (s->pcm->card != substream->pcm->card)
2257                         continue;
2258                 azx_dev = get_azx_dev(s);
2259                 if (start) {
2260                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2261                         if (!rstart)
2262                                 azx_dev->start_wallclk -=
2263                                                 azx_dev->period_wallclk;
2264                         azx_stream_start(chip, azx_dev);
2265                 } else {
2266                         azx_stream_stop(chip, azx_dev);
2267                 }
2268                 azx_dev->running = start;
2269         }
2270         spin_unlock(&chip->reg_lock);
2271         if (start) {
2272                 /* wait until all FIFOs get ready */
2273                 for (timeout = 5000; timeout; timeout--) {
2274                         nwait = 0;
2275                         snd_pcm_group_for_each_entry(s, substream) {
2276                                 if (s->pcm->card != substream->pcm->card)
2277                                         continue;
2278                                 azx_dev = get_azx_dev(s);
2279                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2280                                       SD_STS_FIFO_READY))
2281                                         nwait++;
2282                         }
2283                         if (!nwait)
2284                                 break;
2285                         cpu_relax();
2286                 }
2287         } else {
2288                 /* wait until all RUN bits are cleared */
2289                 for (timeout = 5000; timeout; timeout--) {
2290                         nwait = 0;
2291                         snd_pcm_group_for_each_entry(s, substream) {
2292                                 if (s->pcm->card != substream->pcm->card)
2293                                         continue;
2294                                 azx_dev = get_azx_dev(s);
2295                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2296                                     SD_CTL_DMA_START)
2297                                         nwait++;
2298                         }
2299                         if (!nwait)
2300                                 break;
2301                         cpu_relax();
2302                 }
2303         }
2304         spin_lock(&chip->reg_lock);
2305         /* reset SYNC bits */
2306         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2307                 azx_writel(chip, OLD_SSYNC,
2308                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2309         else
2310                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2311         if (start) {
2312                 azx_timecounter_init(substream, 0, 0);
2313                 if (nsync > 1) {
2314                         cycle_t cycle_last;
2315
2316                         /* same start cycle for master and group */
2317                         azx_dev = get_azx_dev(substream);
2318                         cycle_last = azx_dev->azx_tc.cycle_last;
2319
2320                         snd_pcm_group_for_each_entry(s, substream) {
2321                                 if (s->pcm->card != substream->pcm->card)
2322                                         continue;
2323                                 azx_timecounter_init(s, 1, cycle_last);
2324                         }
2325                 }
2326         }
2327         spin_unlock(&chip->reg_lock);
2328         return 0;
2329 }
2330
2331 /* get the current DMA position with correction on VIA chips */
2332 static unsigned int azx_via_get_position(struct azx *chip,
2333                                          struct azx_dev *azx_dev)
2334 {
2335         unsigned int link_pos, mini_pos, bound_pos;
2336         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2337         unsigned int fifo_size;
2338
2339         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2340         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2341                 /* Playback, no problem using link position */
2342                 return link_pos;
2343         }
2344
2345         /* Capture */
2346         /* For new chipset,
2347          * use mod to get the DMA position just like old chipset
2348          */
2349         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2350         mod_dma_pos %= azx_dev->period_bytes;
2351
2352         /* azx_dev->fifo_size can't get FIFO size of in stream.
2353          * Get from base address + offset.
2354          */
2355         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2356
2357         if (azx_dev->insufficient) {
2358                 /* Link position never gather than FIFO size */
2359                 if (link_pos <= fifo_size)
2360                         return 0;
2361
2362                 azx_dev->insufficient = 0;
2363         }
2364
2365         if (link_pos <= fifo_size)
2366                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2367         else
2368                 mini_pos = link_pos - fifo_size;
2369
2370         /* Find nearest previous boudary */
2371         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2372         mod_link_pos = link_pos % azx_dev->period_bytes;
2373         if (mod_link_pos >= fifo_size)
2374                 bound_pos = link_pos - mod_link_pos;
2375         else if (mod_dma_pos >= mod_mini_pos)
2376                 bound_pos = mini_pos - mod_mini_pos;
2377         else {
2378                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2379                 if (bound_pos >= azx_dev->bufsize)
2380                         bound_pos = 0;
2381         }
2382
2383         /* Calculate real DMA position we want */
2384         return bound_pos + mod_dma_pos;
2385 }
2386
2387 static unsigned int azx_get_position(struct azx *chip,
2388                                      struct azx_dev *azx_dev,
2389                                      bool with_check)
2390 {
2391         struct snd_pcm_substream *substream = azx_dev->substream;
2392         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2393         unsigned int pos;
2394         int stream = substream->stream;
2395         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2396         int delay = 0;
2397
2398         switch (chip->position_fix[stream]) {
2399         case POS_FIX_LPIB:
2400                 /* read LPIB */
2401                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2402                 break;
2403         case POS_FIX_VIACOMBO:
2404                 pos = azx_via_get_position(chip, azx_dev);
2405                 break;
2406         default:
2407                 /* use the position buffer */
2408                 pos = le32_to_cpu(*azx_dev->posbuf);
2409                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2410                         if (!pos || pos == (u32)-1) {
2411                                 printk(KERN_WARNING
2412                                        "hda-intel: Invalid position buffer, "
2413                                        "using LPIB read method instead.\n");
2414                                 chip->position_fix[stream] = POS_FIX_LPIB;
2415                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2416                         } else
2417                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2418                 }
2419                 break;
2420         }
2421
2422         if (pos >= azx_dev->bufsize)
2423                 pos = 0;
2424
2425         /* calculate runtime delay from LPIB */
2426         if (substream->runtime &&
2427             chip->position_fix[stream] == POS_FIX_POSBUF &&
2428             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2429                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2430                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2431                         delay = pos - lpib_pos;
2432                 else
2433                         delay = lpib_pos - pos;
2434                 if (delay < 0)
2435                         delay += azx_dev->bufsize;
2436                 if (delay >= azx_dev->period_bytes) {
2437                         snd_printk(KERN_WARNING SFX
2438                                    "%s: Unstable LPIB (%d >= %d); "
2439                                    "disabling LPIB delay counting\n",
2440                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2441                         delay = 0;
2442                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2443                 }
2444                 delay = bytes_to_frames(substream->runtime, delay);
2445         }
2446
2447         if (substream->runtime) {
2448                 if (hinfo->ops.get_delay)
2449                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2450                                                       substream);
2451                 substream->runtime->delay = delay;
2452         }
2453
2454         trace_azx_get_position(chip, azx_dev, pos, delay);
2455         return pos;
2456 }
2457
2458 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2459 {
2460         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2461         struct azx *chip = apcm->chip;
2462         struct azx_dev *azx_dev = get_azx_dev(substream);
2463         return bytes_to_frames(substream->runtime,
2464                                azx_get_position(chip, azx_dev, false));
2465 }
2466
2467 /*
2468  * Check whether the current DMA position is acceptable for updating
2469  * periods.  Returns non-zero if it's OK.
2470  *
2471  * Many HD-audio controllers appear pretty inaccurate about
2472  * the update-IRQ timing.  The IRQ is issued before actually the
2473  * data is processed.  So, we need to process it afterwords in a
2474  * workqueue.
2475  */
2476 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2477 {
2478         u32 wallclk;
2479         unsigned int pos;
2480
2481         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2482         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2483                 return -1;      /* bogus (too early) interrupt */
2484
2485         pos = azx_get_position(chip, azx_dev, true);
2486
2487         if (WARN_ONCE(!azx_dev->period_bytes,
2488                       "hda-intel: zero azx_dev->period_bytes"))
2489                 return -1; /* this shouldn't happen! */
2490         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2491             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2492                 /* NG - it's below the first next period boundary */
2493                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2494         azx_dev->start_wallclk += wallclk;
2495         return 1; /* OK, it's fine */
2496 }
2497
2498 /*
2499  * The work for pending PCM period updates.
2500  */
2501 static void azx_irq_pending_work(struct work_struct *work)
2502 {
2503         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2504         int i, pending, ok;
2505
2506         if (!chip->irq_pending_warned) {
2507                 printk(KERN_WARNING
2508                        "hda-intel: IRQ timing workaround is activated "
2509                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2510                        chip->card->number);
2511                 chip->irq_pending_warned = 1;
2512         }
2513
2514         for (;;) {
2515                 pending = 0;
2516                 spin_lock_irq(&chip->reg_lock);
2517                 for (i = 0; i < chip->num_streams; i++) {
2518                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2519                         if (!azx_dev->irq_pending ||
2520                             !azx_dev->substream ||
2521                             !azx_dev->running)
2522                                 continue;
2523                         ok = azx_position_ok(chip, azx_dev);
2524                         if (ok > 0) {
2525                                 azx_dev->irq_pending = 0;
2526                                 spin_unlock(&chip->reg_lock);
2527                                 snd_pcm_period_elapsed(azx_dev->substream);
2528                                 spin_lock(&chip->reg_lock);
2529                         } else if (ok < 0) {
2530                                 pending = 0;    /* too early */
2531                         } else
2532                                 pending++;
2533                 }
2534                 spin_unlock_irq(&chip->reg_lock);
2535                 if (!pending)
2536                         return;
2537                 msleep(1);
2538         }
2539 }
2540
2541 /* clear irq_pending flags and assure no on-going workq */
2542 static void azx_clear_irq_pending(struct azx *chip)
2543 {
2544         int i;
2545
2546         spin_lock_irq(&chip->reg_lock);
2547         for (i = 0; i < chip->num_streams; i++)
2548                 chip->azx_dev[i].irq_pending = 0;
2549         spin_unlock_irq(&chip->reg_lock);
2550 }
2551
2552 #ifdef CONFIG_X86
2553 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2554                         struct vm_area_struct *area)
2555 {
2556         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2557         struct azx *chip = apcm->chip;
2558         if (!azx_snoop(chip))
2559                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2560         return snd_pcm_lib_default_mmap(substream, area);
2561 }
2562 #else
2563 #define azx_pcm_mmap    NULL
2564 #endif
2565
2566 static struct snd_pcm_ops azx_pcm_ops = {
2567         .open = azx_pcm_open,
2568         .close = azx_pcm_close,
2569         .ioctl = snd_pcm_lib_ioctl,
2570         .hw_params = azx_pcm_hw_params,
2571         .hw_free = azx_pcm_hw_free,
2572         .prepare = azx_pcm_prepare,
2573         .trigger = azx_pcm_trigger,
2574         .pointer = azx_pcm_pointer,
2575         .wall_clock =  azx_get_wallclock_tstamp,
2576         .mmap = azx_pcm_mmap,
2577         .page = snd_pcm_sgbuf_ops_page,
2578 };
2579
2580 static void azx_pcm_free(struct snd_pcm *pcm)
2581 {
2582         struct azx_pcm *apcm = pcm->private_data;
2583         if (apcm) {
2584                 list_del(&apcm->list);
2585                 kfree(apcm);
2586         }
2587 }
2588
2589 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2590
2591 static int
2592 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2593                       struct hda_pcm *cpcm)
2594 {
2595         struct azx *chip = bus->private_data;
2596         struct snd_pcm *pcm;
2597         struct azx_pcm *apcm;
2598         int pcm_dev = cpcm->device;
2599         unsigned int size;
2600         int s, err;
2601
2602         list_for_each_entry(apcm, &chip->pcm_list, list) {
2603                 if (apcm->pcm->device == pcm_dev) {
2604                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2605                                    pci_name(chip->pci), pcm_dev);
2606                         return -EBUSY;
2607                 }
2608         }
2609         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2610                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2611                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2612                           &pcm);
2613         if (err < 0)
2614                 return err;
2615         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2616         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2617         if (apcm == NULL)
2618                 return -ENOMEM;
2619         apcm->chip = chip;
2620         apcm->pcm = pcm;
2621         apcm->codec = codec;
2622         pcm->private_data = apcm;
2623         pcm->private_free = azx_pcm_free;
2624         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2625                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2626         list_add_tail(&apcm->list, &chip->pcm_list);
2627         cpcm->pcm = pcm;
2628         for (s = 0; s < 2; s++) {
2629                 apcm->hinfo[s] = &cpcm->stream[s];
2630                 if (cpcm->stream[s].substreams)
2631                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2632         }
2633         /* buffer pre-allocation */
2634         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2635         if (size > MAX_PREALLOC_SIZE)
2636                 size = MAX_PREALLOC_SIZE;
2637         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2638                                               snd_dma_pci_data(chip->pci),
2639                                               size, MAX_PREALLOC_SIZE);
2640         return 0;
2641 }
2642
2643 /*
2644  * mixer creation - all stuff is implemented in hda module
2645  */
2646 static int azx_mixer_create(struct azx *chip)
2647 {
2648         return snd_hda_build_controls(chip->bus);
2649 }
2650
2651
2652 /*
2653  * initialize SD streams
2654  */
2655 static int azx_init_stream(struct azx *chip)
2656 {
2657         int i;
2658
2659         /* initialize each stream (aka device)
2660          * assign the starting bdl address to each stream (device)
2661          * and initialize
2662          */
2663         for (i = 0; i < chip->num_streams; i++) {
2664                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2665                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2666                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2667                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2668                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2669                 azx_dev->sd_int_sta_mask = 1 << i;
2670                 /* stream tag: must be non-zero and unique */
2671                 azx_dev->index = i;
2672                 azx_dev->stream_tag = i + 1;
2673         }
2674
2675         return 0;
2676 }
2677
2678 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2679 {
2680         if (request_irq(chip->pci->irq, azx_interrupt,
2681                         chip->msi ? 0 : IRQF_SHARED,
2682                         KBUILD_MODNAME, chip)) {
2683                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2684                        "disabling device\n", chip->pci->irq);
2685                 if (do_disconnect)
2686                         snd_card_disconnect(chip->card);
2687                 return -1;
2688         }
2689         chip->irq = chip->pci->irq;
2690         pci_intx(chip->pci, !chip->msi);
2691         return 0;
2692 }
2693
2694
2695 static void azx_stop_chip(struct azx *chip)
2696 {
2697         if (!chip->initialized)
2698                 return;
2699
2700         /* disable interrupts */
2701         azx_int_disable(chip);
2702         azx_int_clear(chip);
2703
2704         /* disable CORB/RIRB */
2705         azx_free_cmd_io(chip);
2706
2707         /* disable position buffer */
2708         azx_writel(chip, DPLBASE, 0);
2709         azx_writel(chip, DPUBASE, 0);
2710
2711         chip->initialized = 0;
2712 }
2713
2714 #ifdef CONFIG_SND_HDA_DSP_LOADER
2715 /*
2716  * DSP loading code (e.g. for CA0132)
2717  */
2718
2719 /* use the first stream for loading DSP */
2720 static struct azx_dev *
2721 azx_get_dsp_loader_dev(struct azx *chip)
2722 {
2723         return &chip->azx_dev[chip->playback_index_offset];
2724 }
2725
2726 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2727                                 unsigned int byte_size,
2728                                 struct snd_dma_buffer *bufp)
2729 {
2730         u32 *bdl;
2731         struct azx *chip = bus->private_data;
2732         struct azx_dev *azx_dev;
2733         int err;
2734
2735         azx_dev = azx_get_dsp_loader_dev(chip);
2736
2737         dsp_lock(azx_dev);
2738         spin_lock_irq(&chip->reg_lock);
2739         if (azx_dev->running || azx_dev->locked) {
2740                 spin_unlock_irq(&chip->reg_lock);
2741                 err = -EBUSY;
2742                 goto unlock;
2743         }
2744         azx_dev->prepared = 0;
2745         chip->saved_azx_dev = *azx_dev;
2746         azx_dev->locked = 1;
2747         spin_unlock_irq(&chip->reg_lock);
2748
2749         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2750                                   snd_dma_pci_data(chip->pci),
2751                                   byte_size, bufp);
2752         if (err < 0)
2753                 goto err_alloc;
2754
2755         mark_pages_wc(chip, bufp, true);
2756         azx_dev->bufsize = byte_size;
2757         azx_dev->period_bytes = byte_size;
2758         azx_dev->format_val = format;
2759
2760         azx_stream_reset(chip, azx_dev);
2761
2762         /* reset BDL address */
2763         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2764         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2765
2766         azx_dev->frags = 0;
2767         bdl = (u32 *)azx_dev->bdl.area;
2768         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2769         if (err < 0)
2770                 goto error;
2771
2772         azx_setup_controller(chip, azx_dev);
2773         dsp_unlock(azx_dev);
2774         return azx_dev->stream_tag;
2775
2776  error:
2777         mark_pages_wc(chip, bufp, false);
2778         snd_dma_free_pages(bufp);
2779  err_alloc:
2780         spin_lock_irq(&chip->reg_lock);
2781         if (azx_dev->opened)
2782                 *azx_dev = chip->saved_azx_dev;
2783         azx_dev->locked = 0;
2784         spin_unlock_irq(&chip->reg_lock);
2785  unlock:
2786         dsp_unlock(azx_dev);
2787         return err;
2788 }
2789
2790 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2791 {
2792         struct azx *chip = bus->private_data;
2793         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2794
2795         if (start)
2796                 azx_stream_start(chip, azx_dev);
2797         else
2798                 azx_stream_stop(chip, azx_dev);
2799         azx_dev->running = start;
2800 }
2801
2802 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2803                                  struct snd_dma_buffer *dmab)
2804 {
2805         struct azx *chip = bus->private_data;
2806         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2807
2808         if (!dmab->area || !azx_dev->locked)
2809                 return;
2810
2811         dsp_lock(azx_dev);
2812         /* reset BDL address */
2813         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2814         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2815         azx_sd_writel(azx_dev, SD_CTL, 0);
2816         azx_dev->bufsize = 0;
2817         azx_dev->period_bytes = 0;
2818         azx_dev->format_val = 0;
2819
2820         mark_pages_wc(chip, dmab, false);
2821         snd_dma_free_pages(dmab);
2822         dmab->area = NULL;
2823
2824         spin_lock_irq(&chip->reg_lock);
2825         if (azx_dev->opened)
2826                 *azx_dev = chip->saved_azx_dev;
2827         azx_dev->locked = 0;
2828         spin_unlock_irq(&chip->reg_lock);
2829         dsp_unlock(azx_dev);
2830 }
2831 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2832
2833 #ifdef CONFIG_PM
2834 /* power-up/down the controller */
2835 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2836 {
2837         struct azx *chip = bus->private_data;
2838
2839         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2840                 return;
2841
2842         if (power_up)
2843                 pm_runtime_get_sync(&chip->pci->dev);
2844         else
2845                 pm_runtime_put_sync(&chip->pci->dev);
2846 }
2847
2848 static DEFINE_MUTEX(card_list_lock);
2849 static LIST_HEAD(card_list);
2850
2851 static void azx_add_card_list(struct azx *chip)
2852 {
2853         mutex_lock(&card_list_lock);
2854         list_add(&chip->list, &card_list);
2855         mutex_unlock(&card_list_lock);
2856 }
2857
2858 static void azx_del_card_list(struct azx *chip)
2859 {
2860         mutex_lock(&card_list_lock);
2861         list_del_init(&chip->list);
2862         mutex_unlock(&card_list_lock);
2863 }
2864
2865 /* trigger power-save check at writing parameter */
2866 static int param_set_xint(const char *val, const struct kernel_param *kp)
2867 {
2868         struct azx *chip;
2869         struct hda_codec *c;
2870         int prev = power_save;
2871         int ret = param_set_int(val, kp);
2872
2873         if (ret || prev == power_save)
2874                 return ret;
2875
2876         mutex_lock(&card_list_lock);
2877         list_for_each_entry(chip, &card_list, list) {
2878                 if (!chip->bus || chip->disabled)
2879                         continue;
2880                 list_for_each_entry(c, &chip->bus->codec_list, list)
2881                         snd_hda_power_sync(c);
2882         }
2883         mutex_unlock(&card_list_lock);
2884         return 0;
2885 }
2886 #else
2887 #define azx_add_card_list(chip) /* NOP */
2888 #define azx_del_card_list(chip) /* NOP */
2889 #endif /* CONFIG_PM */
2890
2891 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2892 /*
2893  * power management
2894  */
2895 static int azx_suspend(struct device *dev)
2896 {
2897         struct pci_dev *pci = to_pci_dev(dev);
2898         struct snd_card *card = dev_get_drvdata(dev);
2899         struct azx *chip = card->private_data;
2900         struct azx_pcm *p;
2901
2902         if (chip->disabled)
2903                 return 0;
2904
2905         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2906         azx_clear_irq_pending(chip);
2907         list_for_each_entry(p, &chip->pcm_list, list)
2908                 snd_pcm_suspend_all(p->pcm);
2909         if (chip->initialized)
2910                 snd_hda_suspend(chip->bus);
2911         azx_stop_chip(chip);
2912         azx_enter_link_reset(chip);
2913         if (chip->irq >= 0) {
2914                 free_irq(chip->irq, chip);
2915                 chip->irq = -1;
2916         }
2917         if (chip->msi)
2918                 pci_disable_msi(chip->pci);
2919         pci_disable_device(pci);
2920         pci_save_state(pci);
2921         pci_set_power_state(pci, PCI_D3hot);
2922         return 0;
2923 }
2924
2925 static int azx_resume(struct device *dev)
2926 {
2927         struct pci_dev *pci = to_pci_dev(dev);
2928         struct snd_card *card = dev_get_drvdata(dev);
2929         struct azx *chip = card->private_data;
2930
2931         if (chip->disabled)
2932                 return 0;
2933
2934         pci_set_power_state(pci, PCI_D0);
2935         pci_restore_state(pci);
2936         if (pci_enable_device(pci) < 0) {
2937                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2938                        "disabling device\n");
2939                 snd_card_disconnect(card);
2940                 return -EIO;
2941         }
2942         pci_set_master(pci);
2943         if (chip->msi)
2944                 if (pci_enable_msi(pci) < 0)
2945                         chip->msi = 0;
2946         if (azx_acquire_irq(chip, 1) < 0)
2947                 return -EIO;
2948         azx_init_pci(chip);
2949
2950         azx_init_chip(chip, 1);
2951
2952         snd_hda_resume(chip->bus);
2953         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2954         return 0;
2955 }
2956 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2957
2958 #ifdef CONFIG_PM_RUNTIME
2959 static int azx_runtime_suspend(struct device *dev)
2960 {
2961         struct snd_card *card = dev_get_drvdata(dev);
2962         struct azx *chip = card->private_data;
2963
2964         azx_stop_chip(chip);
2965         azx_enter_link_reset(chip);
2966         azx_clear_irq_pending(chip);
2967         return 0;
2968 }
2969
2970 static int azx_runtime_resume(struct device *dev)
2971 {
2972         struct snd_card *card = dev_get_drvdata(dev);
2973         struct azx *chip = card->private_data;
2974
2975         azx_init_pci(chip);
2976         azx_init_chip(chip, 1);
2977         return 0;
2978 }
2979
2980 static int azx_runtime_idle(struct device *dev)
2981 {
2982         struct snd_card *card = dev_get_drvdata(dev);
2983         struct azx *chip = card->private_data;
2984
2985         if (!power_save_controller ||
2986             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2987                 return -EBUSY;
2988
2989         return 0;
2990 }
2991
2992 #endif /* CONFIG_PM_RUNTIME */
2993
2994 #ifdef CONFIG_PM
2995 static const struct dev_pm_ops azx_pm = {
2996         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2997         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2998 };
2999
3000 #define AZX_PM_OPS      &azx_pm
3001 #else
3002 #define AZX_PM_OPS      NULL
3003 #endif /* CONFIG_PM */
3004
3005
3006 /*
3007  * reboot notifier for hang-up problem at power-down
3008  */
3009 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3010 {
3011         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3012         snd_hda_bus_reboot_notify(chip->bus);
3013         azx_stop_chip(chip);
3014         return NOTIFY_OK;
3015 }
3016
3017 static void azx_notifier_register(struct azx *chip)
3018 {
3019         chip->reboot_notifier.notifier_call = azx_halt;
3020         register_reboot_notifier(&chip->reboot_notifier);
3021 }
3022
3023 static void azx_notifier_unregister(struct azx *chip)
3024 {
3025         if (chip->reboot_notifier.notifier_call)
3026                 unregister_reboot_notifier(&chip->reboot_notifier);
3027 }
3028
3029 static int azx_first_init(struct azx *chip);
3030 static int azx_probe_continue(struct azx *chip);
3031
3032 #ifdef SUPPORT_VGA_SWITCHEROO
3033 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3034
3035 static void azx_vs_set_state(struct pci_dev *pci,
3036                              enum vga_switcheroo_state state)
3037 {
3038         struct snd_card *card = pci_get_drvdata(pci);
3039         struct azx *chip = card->private_data;
3040         bool disabled;
3041
3042         wait_for_completion(&chip->probe_wait);
3043         if (chip->init_failed)
3044                 return;
3045
3046         disabled = (state == VGA_SWITCHEROO_OFF);
3047         if (chip->disabled == disabled)
3048                 return;
3049
3050         if (!chip->bus) {
3051                 chip->disabled = disabled;
3052                 if (!disabled) {
3053                         snd_printk(KERN_INFO SFX
3054                                    "%s: Start delayed initialization\n",
3055                                    pci_name(chip->pci));
3056                         if (azx_first_init(chip) < 0 ||
3057                             azx_probe_continue(chip) < 0) {
3058                                 snd_printk(KERN_ERR SFX
3059                                            "%s: initialization error\n",
3060                                            pci_name(chip->pci));
3061                                 chip->init_failed = true;
3062                         }
3063                 }
3064         } else {
3065                 snd_printk(KERN_INFO SFX
3066                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3067                            disabled ? "Disabling" : "Enabling");
3068                 if (disabled) {
3069                         azx_suspend(&pci->dev);
3070                         chip->disabled = true;
3071                         if (snd_hda_lock_devices(chip->bus))
3072                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3073                                            pci_name(chip->pci));
3074                 } else {
3075                         snd_hda_unlock_devices(chip->bus);
3076                         chip->disabled = false;
3077                         azx_resume(&pci->dev);
3078                 }
3079         }
3080 }
3081
3082 static bool azx_vs_can_switch(struct pci_dev *pci)
3083 {
3084         struct snd_card *card = pci_get_drvdata(pci);
3085         struct azx *chip = card->private_data;
3086
3087         wait_for_completion(&chip->probe_wait);
3088         if (chip->init_failed)
3089                 return false;
3090         if (chip->disabled || !chip->bus)
3091                 return true;
3092         if (snd_hda_lock_devices(chip->bus))
3093                 return false;
3094         snd_hda_unlock_devices(chip->bus);
3095         return true;
3096 }
3097
3098 static void init_vga_switcheroo(struct azx *chip)
3099 {
3100         struct pci_dev *p = get_bound_vga(chip->pci);
3101         if (p) {
3102                 snd_printk(KERN_INFO SFX
3103                            "%s: Handle VGA-switcheroo audio client\n",
3104                            pci_name(chip->pci));
3105                 chip->use_vga_switcheroo = 1;
3106                 pci_dev_put(p);
3107         }
3108 }
3109
3110 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3111         .set_gpu_state = azx_vs_set_state,
3112         .can_switch = azx_vs_can_switch,
3113 };
3114
3115 static int register_vga_switcheroo(struct azx *chip)
3116 {
3117         int err;
3118
3119         if (!chip->use_vga_switcheroo)
3120                 return 0;
3121         /* FIXME: currently only handling DIS controller
3122          * is there any machine with two switchable HDMI audio controllers?
3123          */
3124         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3125                                                     VGA_SWITCHEROO_DIS,
3126                                                     chip->bus != NULL);
3127         if (err < 0)
3128                 return err;
3129         chip->vga_switcheroo_registered = 1;
3130         return 0;
3131 }
3132 #else
3133 #define init_vga_switcheroo(chip)               /* NOP */
3134 #define register_vga_switcheroo(chip)           0
3135 #define check_hdmi_disabled(pci)        false
3136 #endif /* SUPPORT_VGA_SWITCHER */
3137
3138 /*
3139  * destructor
3140  */
3141 static int azx_free(struct azx *chip)
3142 {
3143         int i;
3144
3145         azx_del_card_list(chip);
3146
3147         azx_notifier_unregister(chip);
3148
3149         chip->init_failed = 1; /* to be sure */
3150         complete_all(&chip->probe_wait);
3151
3152         if (use_vga_switcheroo(chip)) {
3153                 if (chip->disabled && chip->bus)
3154                         snd_hda_unlock_devices(chip->bus);
3155                 if (chip->vga_switcheroo_registered)
3156                         vga_switcheroo_unregister_client(chip->pci);
3157         }
3158
3159         if (chip->initialized) {
3160                 azx_clear_irq_pending(chip);
3161                 for (i = 0; i < chip->num_streams; i++)
3162                         azx_stream_stop(chip, &chip->azx_dev[i]);
3163                 azx_stop_chip(chip);
3164         }
3165
3166         if (chip->irq >= 0)
3167                 free_irq(chip->irq, (void*)chip);
3168         if (chip->msi)
3169                 pci_disable_msi(chip->pci);
3170         if (chip->remap_addr)
3171                 iounmap(chip->remap_addr);
3172
3173         if (chip->azx_dev) {
3174                 for (i = 0; i < chip->num_streams; i++)
3175                         if (chip->azx_dev[i].bdl.area) {
3176                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3177                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3178                         }
3179         }
3180         if (chip->rb.area) {
3181                 mark_pages_wc(chip, &chip->rb, false);
3182                 snd_dma_free_pages(&chip->rb);
3183         }
3184         if (chip->posbuf.area) {
3185                 mark_pages_wc(chip, &chip->posbuf, false);
3186                 snd_dma_free_pages(&chip->posbuf);
3187         }
3188         if (chip->region_requested)
3189                 pci_release_regions(chip->pci);
3190         pci_disable_device(chip->pci);
3191         kfree(chip->azx_dev);
3192 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3193         if (chip->fw)
3194                 release_firmware(chip->fw);
3195 #endif
3196         kfree(chip);
3197
3198         return 0;
3199 }
3200
3201 static int azx_dev_free(struct snd_device *device)
3202 {
3203         return azx_free(device->device_data);
3204 }
3205
3206 #ifdef SUPPORT_VGA_SWITCHEROO
3207 /*
3208  * Check of disabled HDMI controller by vga-switcheroo
3209  */
3210 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3211 {
3212         struct pci_dev *p;
3213
3214         /* check only discrete GPU */
3215         switch (pci->vendor) {
3216         case PCI_VENDOR_ID_ATI:
3217         case PCI_VENDOR_ID_AMD:
3218         case PCI_VENDOR_ID_NVIDIA:
3219                 if (pci->devfn == 1) {
3220                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3221                                                         pci->bus->number, 0);
3222                         if (p) {
3223                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3224                                         return p;
3225                                 pci_dev_put(p);
3226                         }
3227                 }
3228                 break;
3229         }
3230         return NULL;
3231 }
3232
3233 static bool check_hdmi_disabled(struct pci_dev *pci)
3234 {
3235         bool vga_inactive = false;
3236         struct pci_dev *p = get_bound_vga(pci);
3237
3238         if (p) {
3239                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3240                         vga_inactive = true;
3241                 pci_dev_put(p);
3242         }
3243         return vga_inactive;
3244 }
3245 #endif /* SUPPORT_VGA_SWITCHEROO */
3246
3247 /*
3248  * white/black-listing for position_fix
3249  */
3250 static struct snd_pci_quirk position_fix_list[] = {
3251         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3252         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3253         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3254         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3255         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3256         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3257         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3258         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3259         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3260         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3261         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3262         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3263         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3264         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3265         {}
3266 };
3267
3268 static int check_position_fix(struct azx *chip, int fix)
3269 {
3270         const struct snd_pci_quirk *q;
3271
3272         switch (fix) {
3273         case POS_FIX_AUTO:
3274         case POS_FIX_LPIB:
3275         case POS_FIX_POSBUF:
3276         case POS_FIX_VIACOMBO:
3277         case POS_FIX_COMBO:
3278                 return fix;
3279         }
3280
3281         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3282         if (q) {
3283                 printk(KERN_INFO
3284                        "hda_intel: position_fix set to %d "
3285                        "for device %04x:%04x\n",
3286                        q->value, q->subvendor, q->subdevice);
3287                 return q->value;
3288         }
3289
3290         /* Check VIA/ATI HD Audio Controller exist */
3291         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3292                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3293                 return POS_FIX_VIACOMBO;
3294         }
3295         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3296                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3297                 return POS_FIX_LPIB;
3298         }
3299         return POS_FIX_AUTO;
3300 }
3301
3302 /*
3303  * black-lists for probe_mask
3304  */
3305 static struct snd_pci_quirk probe_mask_list[] = {
3306         /* Thinkpad often breaks the controller communication when accessing
3307          * to the non-working (or non-existing) modem codec slot.
3308          */
3309         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3310         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3311         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3312         /* broken BIOS */
3313         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3314         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3315         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3316         /* forced codec slots */
3317         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3318         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3319         /* WinFast VP200 H (Teradici) user reported broken communication */
3320         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3321         {}
3322 };
3323
3324 #define AZX_FORCE_CODEC_MASK    0x100
3325
3326 static void check_probe_mask(struct azx *chip, int dev)
3327 {
3328         const struct snd_pci_quirk *q;
3329
3330         chip->codec_probe_mask = probe_mask[dev];
3331         if (chip->codec_probe_mask == -1) {
3332                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3333                 if (q) {
3334                         printk(KERN_INFO
3335                                "hda_intel: probe_mask set to 0x%x "
3336                                "for device %04x:%04x\n",
3337                                q->value, q->subvendor, q->subdevice);
3338                         chip->codec_probe_mask = q->value;
3339                 }
3340         }
3341
3342         /* check forced option */
3343         if (chip->codec_probe_mask != -1 &&
3344             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3345                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3346                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3347                        chip->codec_mask);
3348         }
3349 }
3350
3351 /*
3352  * white/black-list for enable_msi
3353  */
3354 static struct snd_pci_quirk msi_black_list[] = {
3355         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3356         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3357         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3358         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3359         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3360         {}
3361 };
3362
3363 static void check_msi(struct azx *chip)
3364 {
3365         const struct snd_pci_quirk *q;
3366
3367         if (enable_msi >= 0) {
3368                 chip->msi = !!enable_msi;
3369                 return;
3370         }
3371         chip->msi = 1;  /* enable MSI as default */
3372         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3373         if (q) {
3374                 printk(KERN_INFO
3375                        "hda_intel: msi for device %04x:%04x set to %d\n",
3376                        q->subvendor, q->subdevice, q->value);
3377                 chip->msi = q->value;
3378                 return;
3379         }
3380
3381         /* NVidia chipsets seem to cause troubles with MSI */
3382         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3383                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3384                 chip->msi = 0;
3385         }
3386 }
3387
3388 /* check the snoop mode availability */
3389 static void azx_check_snoop_available(struct azx *chip)
3390 {
3391         bool snoop = chip->snoop;
3392
3393         switch (chip->driver_type) {
3394         case AZX_DRIVER_VIA:
3395                 /* force to non-snoop mode for a new VIA controller
3396                  * when BIOS is set
3397                  */
3398                 if (snoop) {
3399                         u8 val;
3400                         pci_read_config_byte(chip->pci, 0x42, &val);
3401                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3402                                 snoop = false;
3403                 }
3404                 break;
3405         case AZX_DRIVER_ATIHDMI_NS:
3406                 /* new ATI HDMI requires non-snoop */
3407                 snoop = false;
3408                 break;
3409         case AZX_DRIVER_CTHDA:
3410                 snoop = false;
3411                 break;
3412         }
3413
3414         if (snoop != chip->snoop) {
3415                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3416                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3417                 chip->snoop = snoop;
3418         }
3419 }
3420
3421 /*
3422  * constructor
3423  */
3424 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3425                       int dev, unsigned int driver_caps,
3426                       struct azx **rchip)
3427 {
3428         static struct snd_device_ops ops = {
3429                 .dev_free = azx_dev_free,
3430         };
3431         struct azx *chip;
3432         int err;
3433
3434         *rchip = NULL;
3435
3436         err = pci_enable_device(pci);
3437         if (err < 0)
3438                 return err;
3439
3440         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3441         if (!chip) {
3442                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3443                 pci_disable_device(pci);
3444                 return -ENOMEM;
3445         }
3446
3447         spin_lock_init(&chip->reg_lock);
3448         mutex_init(&chip->open_mutex);
3449         chip->card = card;
3450         chip->pci = pci;
3451         chip->irq = -1;
3452         chip->driver_caps = driver_caps;
3453         chip->driver_type = driver_caps & 0xff;
3454         check_msi(chip);
3455         chip->dev_index = dev;
3456         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3457         INIT_LIST_HEAD(&chip->pcm_list);
3458         INIT_LIST_HEAD(&chip->list);
3459         init_vga_switcheroo(chip);
3460         init_completion(&chip->probe_wait);
3461
3462         chip->position_fix[0] = chip->position_fix[1] =
3463                 check_position_fix(chip, position_fix[dev]);
3464         /* combo mode uses LPIB for playback */
3465         if (chip->position_fix[0] == POS_FIX_COMBO) {
3466                 chip->position_fix[0] = POS_FIX_LPIB;
3467                 chip->position_fix[1] = POS_FIX_AUTO;
3468         }
3469
3470         check_probe_mask(chip, dev);
3471
3472         chip->single_cmd = single_cmd;
3473         chip->snoop = hda_snoop;
3474         azx_check_snoop_available(chip);
3475
3476         if (bdl_pos_adj[dev] < 0) {
3477                 switch (chip->driver_type) {
3478                 case AZX_DRIVER_ICH:
3479                 case AZX_DRIVER_PCH:
3480                         bdl_pos_adj[dev] = 1;
3481                         break;
3482                 default:
3483                         bdl_pos_adj[dev] = 32;
3484                         break;
3485                 }
3486         }
3487
3488         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3489         if (err < 0) {
3490                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3491                    pci_name(chip->pci));
3492                 azx_free(chip);
3493                 return err;
3494         }
3495
3496         *rchip = chip;
3497         return 0;
3498 }
3499
3500 static int azx_first_init(struct azx *chip)
3501 {
3502         int dev = chip->dev_index;
3503         struct pci_dev *pci = chip->pci;
3504         struct snd_card *card = chip->card;
3505         int i, err;
3506         unsigned short gcap;
3507
3508 #if BITS_PER_LONG != 64
3509         /* Fix up base address on ULI M5461 */
3510         if (chip->driver_type == AZX_DRIVER_ULI) {
3511                 u16 tmp3;
3512                 pci_read_config_word(pci, 0x40, &tmp3);
3513                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3514                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3515         }
3516 #endif
3517
3518         err = pci_request_regions(pci, "ICH HD audio");
3519         if (err < 0)
3520                 return err;
3521         chip->region_requested = 1;
3522
3523         chip->addr = pci_resource_start(pci, 0);
3524         chip->remap_addr = pci_ioremap_bar(pci, 0);
3525         if (chip->remap_addr == NULL) {
3526                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3527                 return -ENXIO;
3528         }
3529
3530         if (chip->msi)
3531                 if (pci_enable_msi(pci) < 0)
3532                         chip->msi = 0;
3533
3534         if (azx_acquire_irq(chip, 0) < 0)
3535                 return -EBUSY;
3536
3537         pci_set_master(pci);
3538         synchronize_irq(chip->irq);
3539
3540         gcap = azx_readw(chip, GCAP);
3541         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3542
3543         /* disable SB600 64bit support for safety */
3544         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3545                 struct pci_dev *p_smbus;
3546                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3547                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3548                                          NULL);
3549                 if (p_smbus) {
3550                         if (p_smbus->revision < 0x30)
3551                                 gcap &= ~ICH6_GCAP_64OK;
3552                         pci_dev_put(p_smbus);
3553                 }
3554         }
3555
3556         /* disable 64bit DMA address on some devices */
3557         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3558                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3559                 gcap &= ~ICH6_GCAP_64OK;
3560         }
3561
3562         /* disable buffer size rounding to 128-byte multiples if supported */
3563         if (align_buffer_size >= 0)
3564                 chip->align_buffer_size = !!align_buffer_size;
3565         else {
3566                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3567                         chip->align_buffer_size = 0;
3568                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3569                         chip->align_buffer_size = 1;
3570                 else
3571                         chip->align_buffer_size = 1;
3572         }
3573
3574         /* allow 64bit DMA address if supported by H/W */
3575         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3576                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3577         else {
3578                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3579                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3580         }
3581
3582         /* read number of streams from GCAP register instead of using
3583          * hardcoded value
3584          */
3585         chip->capture_streams = (gcap >> 8) & 0x0f;
3586         chip->playback_streams = (gcap >> 12) & 0x0f;
3587         if (!chip->playback_streams && !chip->capture_streams) {
3588                 /* gcap didn't give any info, switching to old method */
3589
3590                 switch (chip->driver_type) {
3591                 case AZX_DRIVER_ULI:
3592                         chip->playback_streams = ULI_NUM_PLAYBACK;
3593                         chip->capture_streams = ULI_NUM_CAPTURE;
3594                         break;
3595                 case AZX_DRIVER_ATIHDMI:
3596                 case AZX_DRIVER_ATIHDMI_NS:
3597                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3598                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3599                         break;
3600                 case AZX_DRIVER_GENERIC:
3601                 default:
3602                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3603                         chip->capture_streams = ICH6_NUM_CAPTURE;
3604                         break;
3605                 }
3606         }
3607         chip->capture_index_offset = 0;
3608         chip->playback_index_offset = chip->capture_streams;
3609         chip->num_streams = chip->playback_streams + chip->capture_streams;
3610         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3611                                 GFP_KERNEL);
3612         if (!chip->azx_dev) {
3613                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3614                 return -ENOMEM;
3615         }
3616
3617         for (i = 0; i < chip->num_streams; i++) {
3618                 dsp_lock_init(&chip->azx_dev[i]);
3619                 /* allocate memory for the BDL for each stream */
3620                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3621                                           snd_dma_pci_data(chip->pci),
3622                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3623                 if (err < 0) {
3624                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3625                         return -ENOMEM;
3626                 }
3627                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3628         }
3629         /* allocate memory for the position buffer */
3630         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3631                                   snd_dma_pci_data(chip->pci),
3632                                   chip->num_streams * 8, &chip->posbuf);
3633         if (err < 0) {
3634                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3635                 return -ENOMEM;
3636         }
3637         mark_pages_wc(chip, &chip->posbuf, true);
3638         /* allocate CORB/RIRB */
3639         err = azx_alloc_cmd_io(chip);
3640         if (err < 0)
3641                 return err;
3642
3643         /* initialize streams */
3644         azx_init_stream(chip);
3645
3646         /* initialize chip */
3647         azx_init_pci(chip);
3648         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3649
3650         /* codec detection */
3651         if (!chip->codec_mask) {
3652                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3653                 return -ENODEV;
3654         }
3655
3656         strcpy(card->driver, "HDA-Intel");
3657         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3658                 sizeof(card->shortname));
3659         snprintf(card->longname, sizeof(card->longname),
3660                  "%s at 0x%lx irq %i",
3661                  card->shortname, chip->addr, chip->irq);
3662
3663         return 0;
3664 }
3665
3666 static void power_down_all_codecs(struct azx *chip)
3667 {
3668 #ifdef CONFIG_PM
3669         /* The codecs were powered up in snd_hda_codec_new().
3670          * Now all initialization done, so turn them down if possible
3671          */
3672         struct hda_codec *codec;
3673         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3674                 snd_hda_power_down(codec);
3675         }
3676 #endif
3677 }
3678
3679 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3680 /* callback from request_firmware_nowait() */
3681 static void azx_firmware_cb(const struct firmware *fw, void *context)
3682 {
3683         struct snd_card *card = context;
3684         struct azx *chip = card->private_data;
3685         struct pci_dev *pci = chip->pci;
3686
3687         if (!fw) {
3688                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3689                            pci_name(chip->pci));
3690                 goto error;
3691         }
3692
3693         chip->fw = fw;
3694         if (!chip->disabled) {
3695                 /* continue probing */
3696                 if (azx_probe_continue(chip))
3697                         goto error;
3698         }
3699         return; /* OK */
3700
3701  error:
3702         snd_card_free(card);
3703         pci_set_drvdata(pci, NULL);
3704 }
3705 #endif
3706
3707 static int azx_probe(struct pci_dev *pci,
3708                      const struct pci_device_id *pci_id)
3709 {
3710         static int dev;
3711         struct snd_card *card;
3712         struct azx *chip;
3713         bool probe_now;
3714         int err;
3715
3716         if (dev >= SNDRV_CARDS)
3717                 return -ENODEV;
3718         if (!enable[dev]) {
3719                 dev++;
3720                 return -ENOENT;
3721         }
3722
3723         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3724         if (err < 0) {
3725                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3726                 return err;
3727         }
3728
3729         snd_card_set_dev(card, &pci->dev);
3730
3731         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3732         if (err < 0)
3733                 goto out_free;
3734         card->private_data = chip;
3735
3736         pci_set_drvdata(pci, card);
3737
3738         err = register_vga_switcheroo(chip);
3739         if (err < 0) {
3740                 snd_printk(KERN_ERR SFX
3741                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3742                 goto out_free;
3743         }
3744
3745         if (check_hdmi_disabled(pci)) {
3746                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3747                            pci_name(pci));
3748                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3749                 chip->disabled = true;
3750         }
3751
3752         probe_now = !chip->disabled;
3753         if (probe_now) {
3754                 err = azx_first_init(chip);
3755                 if (err < 0)
3756                         goto out_free;
3757         }
3758
3759 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3760         if (patch[dev] && *patch[dev]) {
3761                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3762                            pci_name(pci), patch[dev]);
3763                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3764                                               &pci->dev, GFP_KERNEL, card,
3765                                               azx_firmware_cb);
3766                 if (err < 0)
3767                         goto out_free;
3768                 probe_now = false; /* continued in azx_firmware_cb() */
3769         }
3770 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3771
3772         if (probe_now) {
3773                 err = azx_probe_continue(chip);
3774                 if (err < 0)
3775                         goto out_free;
3776         }
3777
3778         if (pci_dev_run_wake(pci))
3779                 pm_runtime_put_noidle(&pci->dev);
3780
3781         dev++;
3782         complete_all(&chip->probe_wait);
3783         return 0;
3784
3785 out_free:
3786         snd_card_free(card);
3787         return err;
3788 }
3789
3790 static int azx_probe_continue(struct azx *chip)
3791 {
3792         int dev = chip->dev_index;
3793         int err;
3794
3795 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3796         chip->beep_mode = beep_mode[dev];
3797 #endif
3798
3799         /* create codec instances */
3800         err = azx_codec_create(chip, model[dev]);
3801         if (err < 0)
3802                 goto out_free;
3803 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3804         if (chip->fw) {
3805                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3806                                          chip->fw->data);
3807                 if (err < 0)
3808                         goto out_free;
3809 #ifndef CONFIG_PM
3810                 release_firmware(chip->fw); /* no longer needed */
3811                 chip->fw = NULL;
3812 #endif
3813         }
3814 #endif
3815         if ((probe_only[dev] & 1) == 0) {
3816                 err = azx_codec_configure(chip);
3817                 if (err < 0)
3818                         goto out_free;
3819         }
3820
3821         /* create PCM streams */
3822         err = snd_hda_build_pcms(chip->bus);
3823         if (err < 0)
3824                 goto out_free;
3825
3826         /* create mixer controls */
3827         err = azx_mixer_create(chip);
3828         if (err < 0)
3829                 goto out_free;
3830
3831         err = snd_card_register(chip->card);
3832         if (err < 0)
3833                 goto out_free;
3834
3835         chip->running = 1;
3836         power_down_all_codecs(chip);
3837         azx_notifier_register(chip);
3838         azx_add_card_list(chip);
3839
3840         return 0;
3841
3842 out_free:
3843         chip->init_failed = 1;
3844         return err;
3845 }
3846
3847 static void azx_remove(struct pci_dev *pci)
3848 {
3849         struct snd_card *card = pci_get_drvdata(pci);
3850
3851         if (pci_dev_run_wake(pci))
3852                 pm_runtime_get_noresume(&pci->dev);
3853
3854         if (card)
3855                 snd_card_free(card);
3856 }
3857
3858 /* PCI IDs */
3859 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3860         /* CPT */
3861         { PCI_DEVICE(0x8086, 0x1c20),
3862           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3863         /* PBG */
3864         { PCI_DEVICE(0x8086, 0x1d20),
3865           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3866         /* Panther Point */
3867         { PCI_DEVICE(0x8086, 0x1e20),
3868           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3869         /* Lynx Point */
3870         { PCI_DEVICE(0x8086, 0x8c20),
3871           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3872         /* Wellsburg */
3873         { PCI_DEVICE(0x8086, 0x8d20),
3874           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3875         { PCI_DEVICE(0x8086, 0x8d21),
3876           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3877         /* Lynx Point-LP */
3878         { PCI_DEVICE(0x8086, 0x9c20),
3879           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3880         /* Lynx Point-LP */
3881         { PCI_DEVICE(0x8086, 0x9c21),
3882           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3883         /* Haswell */
3884         { PCI_DEVICE(0x8086, 0x0a0c),
3885           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3886         { PCI_DEVICE(0x8086, 0x0c0c),
3887           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3888         { PCI_DEVICE(0x8086, 0x0d0c),
3889           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3890         /* 5 Series/3400 */
3891         { PCI_DEVICE(0x8086, 0x3b56),
3892           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3893         /* Poulsbo */
3894         { PCI_DEVICE(0x8086, 0x811b),
3895           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3896         /* Oaktrail */
3897         { PCI_DEVICE(0x8086, 0x080a),
3898           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3899         /* BayTrail */
3900         { PCI_DEVICE(0x8086, 0x0f04),
3901           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3902         /* ICH */
3903         { PCI_DEVICE(0x8086, 0x2668),
3904           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3905           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3906         { PCI_DEVICE(0x8086, 0x27d8),
3907           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3908           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3909         { PCI_DEVICE(0x8086, 0x269a),
3910           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3911           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3912         { PCI_DEVICE(0x8086, 0x284b),
3913           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3914           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3915         { PCI_DEVICE(0x8086, 0x293e),
3916           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3917           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3918         { PCI_DEVICE(0x8086, 0x293f),
3919           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3920           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3921         { PCI_DEVICE(0x8086, 0x3a3e),
3922           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3923           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3924         { PCI_DEVICE(0x8086, 0x3a6e),
3925           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3926           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3927         /* Generic Intel */
3928         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3929           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3930           .class_mask = 0xffffff,
3931           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3932         /* ATI SB 450/600/700/800/900 */
3933         { PCI_DEVICE(0x1002, 0x437b),
3934           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3935         { PCI_DEVICE(0x1002, 0x4383),
3936           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3937         /* AMD Hudson */
3938         { PCI_DEVICE(0x1022, 0x780d),
3939           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3940         /* ATI HDMI */
3941         { PCI_DEVICE(0x1002, 0x793b),
3942           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3943         { PCI_DEVICE(0x1002, 0x7919),
3944           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3945         { PCI_DEVICE(0x1002, 0x960f),
3946           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3947         { PCI_DEVICE(0x1002, 0x970f),
3948           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3949         { PCI_DEVICE(0x1002, 0xaa00),
3950           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3951         { PCI_DEVICE(0x1002, 0xaa08),
3952           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3953         { PCI_DEVICE(0x1002, 0xaa10),
3954           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3955         { PCI_DEVICE(0x1002, 0xaa18),
3956           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3957         { PCI_DEVICE(0x1002, 0xaa20),
3958           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3959         { PCI_DEVICE(0x1002, 0xaa28),
3960           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3961         { PCI_DEVICE(0x1002, 0xaa30),
3962           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3963         { PCI_DEVICE(0x1002, 0xaa38),
3964           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3965         { PCI_DEVICE(0x1002, 0xaa40),
3966           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3967         { PCI_DEVICE(0x1002, 0xaa48),
3968           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3969         { PCI_DEVICE(0x1002, 0x9902),
3970           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3971         { PCI_DEVICE(0x1002, 0xaaa0),
3972           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3973         { PCI_DEVICE(0x1002, 0xaaa8),
3974           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3975         { PCI_DEVICE(0x1002, 0xaab0),
3976           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3977         /* VIA VT8251/VT8237A */
3978         { PCI_DEVICE(0x1106, 0x3288),
3979           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3980         /* VIA GFX VT7122/VX900 */
3981         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3982         /* VIA GFX VT6122/VX11 */
3983         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3984         /* SIS966 */
3985         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3986         /* ULI M5461 */
3987         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3988         /* NVIDIA MCP */
3989         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3990           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3991           .class_mask = 0xffffff,
3992           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3993         /* Teradici */
3994         { PCI_DEVICE(0x6549, 0x1200),
3995           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3996         { PCI_DEVICE(0x6549, 0x2200),
3997           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3998         /* Creative X-Fi (CA0110-IBG) */
3999         /* CTHDA chips */
4000         { PCI_DEVICE(0x1102, 0x0010),
4001           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4002         { PCI_DEVICE(0x1102, 0x0012),
4003           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4004 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4005         /* the following entry conflicts with snd-ctxfi driver,
4006          * as ctxfi driver mutates from HD-audio to native mode with
4007          * a special command sequence.
4008          */
4009         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4010           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4011           .class_mask = 0xffffff,
4012           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4013           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4014 #else
4015         /* this entry seems still valid -- i.e. without emu20kx chip */
4016         { PCI_DEVICE(0x1102, 0x0009),
4017           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4018           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4019 #endif
4020         /* Vortex86MX */
4021         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4022         /* VMware HDAudio */
4023         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4024         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4025         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4026           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4027           .class_mask = 0xffffff,
4028           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4029         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4030           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4031           .class_mask = 0xffffff,
4032           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4033         { 0, }
4034 };
4035 MODULE_DEVICE_TABLE(pci, azx_ids);
4036
4037 /* pci_driver definition */
4038 static struct pci_driver azx_driver = {
4039         .name = KBUILD_MODNAME,
4040         .id_table = azx_ids,
4041         .probe = azx_probe,
4042         .remove = azx_remove,
4043         .driver = {
4044                 .pm = AZX_PM_OPS,
4045         },
4046 };
4047
4048 module_pci_driver(azx_driver);