sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include "hda_codec.h"
  57
  58
  59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  61 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  62 static char *model[SNDRV_CARDS];
  63 static int position_fix[SNDRV_CARDS];
  64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  66 static int probe_only[SNDRV_CARDS];
  67 static int single_cmd;
  68 static int enable_msi = -1;
  69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  70 static char *patch[SNDRV_CARDS];
  71 #endif
  72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  74                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  75 #endif
  76
  77 module_param_array(index, int, NULL, 0444);
  78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  79 module_param_array(id, charp, NULL, 0444);
  80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  81 module_param_array(enable, bool, NULL, 0444);
  82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  83 module_param_array(model, charp, NULL, 0444);
  84 MODULE_PARM_DESC(model, "Use the given board model.");
  85 module_param_array(position_fix, int, NULL, 0444);
  86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  87                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  88 module_param_array(bdl_pos_adj, int, NULL, 0644);
  89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  90 module_param_array(probe_mask, int, NULL, 0444);
  91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  92 module_param_array(probe_only, int, NULL, 0444);
  93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  94 module_param(single_cmd, bool, 0444);
  95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  96                  "(for debugging only).");
  97 module_param(enable_msi, int, 0444);
  98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 100 module_param_array(patch, charp, NULL, 0444);
 101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 102 #endif
 103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 104 module_param_array(beep_mode, int, NULL, 0444);
 105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 106                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 107 #endif
 108
 109 #ifdef CONFIG_SND_HDA_POWER_SAVE
 110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 111 module_param(power_save, int, 0644);
 112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 113                  "(in second, 0 = disable).");
 114
 115 /* reset the HD-audio controller in power save mode.
 116  * this may give more power-saving, but will take longer time to
 117  * wake up.
 118  */
 119 static int power_save_controller = 1;
 120 module_param(power_save_controller, bool, 0644);
 121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 122 #endif
 123
 124 static int align_buffer_size = 1;
 125 module_param(align_buffer_size, bool, 0644);
 126 MODULE_PARM_DESC(align_buffer_size,
 127                 "Force buffer and period sizes to be multiple of 128 bytes.");
 128
 129 #ifdef CONFIG_X86
 130 static bool hda_snoop = true;
 131 module_param_named(snoop, hda_snoop, bool, 0444);
 132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 133 #define azx_snoop(chip)         (chip)->snoop
 134 #else
 135 #define hda_snoop               true
 136 #define azx_snoop(chip)         true
 137 #endif
 138
 139
 140 MODULE_LICENSE("GPL");
 141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 142                          "{Intel, ICH6M},"
 143                          "{Intel, ICH7},"
 144                          "{Intel, ESB2},"
 145                          "{Intel, ICH8},"
 146                          "{Intel, ICH9},"
 147                          "{Intel, ICH10},"
 148                          "{Intel, PCH},"
 149                          "{Intel, CPT},"
 150                          "{Intel, PPT},"
 151                          "{Intel, PBG},"
 152                          "{Intel, SCH},"
 153                          "{ATI, SB450},"
 154                          "{ATI, SB600},"
 155                          "{ATI, RS600},"
 156                          "{ATI, RS690},"
 157                          "{ATI, RS780},"
 158                          "{ATI, R600},"
 159                          "{ATI, RV630},"
 160                          "{ATI, RV610},"
 161                          "{ATI, RV670},"
 162                          "{ATI, RV635},"
 163                          "{ATI, RV620},"
 164                          "{ATI, RV770},"
 165                          "{VIA, VT8251},"
 166                          "{VIA, VT8237A},"
 167                          "{SiS, SIS966},"
 168                          "{ULI, M5461}}");
 169 MODULE_DESCRIPTION("Intel HDA driver");
 170
 171 #ifdef CONFIG_SND_VERBOSE_PRINTK
 172 #define SFX     /* nop */
 173 #else
 174 #define SFX     "hda-intel: "
 175 #endif
 176
 177 /*
 178  * registers
 179  */
 180 #define ICH6_REG_GCAP                   0x00
 181 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 182 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 183 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 184 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 185 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 186 #define ICH6_REG_VMIN                   0x02
 187 #define ICH6_REG_VMAJ                   0x03
 188 #define ICH6_REG_OUTPAY                 0x04
 189 #define ICH6_REG_INPAY                  0x06
 190 #define ICH6_REG_GCTL                   0x08
 191 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 192 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 193 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 194 #define ICH6_REG_WAKEEN                 0x0c
 195 #define ICH6_REG_STATESTS               0x0e
 196 #define ICH6_REG_GSTS                   0x10
 197 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 198 #define ICH6_REG_INTCTL                 0x20
 199 #define ICH6_REG_INTSTS                 0x24
 200 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 201 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 202 #define ICH6_REG_SSYNC                  0x38
 203 #define ICH6_REG_CORBLBASE              0x40
 204 #define ICH6_REG_CORBUBASE              0x44
 205 #define ICH6_REG_CORBWP                 0x48
 206 #define ICH6_REG_CORBRP                 0x4a
 207 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 208 #define ICH6_REG_CORBCTL                0x4c
 209 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 210 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 211 #define ICH6_REG_CORBSTS                0x4d
 212 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 213 #define ICH6_REG_CORBSIZE               0x4e
 214
 215 #define ICH6_REG_RIRBLBASE              0x50
 216 #define ICH6_REG_RIRBUBASE              0x54
 217 #define ICH6_REG_RIRBWP                 0x58
 218 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 219 #define ICH6_REG_RINTCNT                0x5a
 220 #define ICH6_REG_RIRBCTL                0x5c
 221 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 222 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 223 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 224 #define ICH6_REG_RIRBSTS                0x5d
 225 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 226 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 227 #define ICH6_REG_RIRBSIZE               0x5e
 228
 229 #define ICH6_REG_IC                     0x60
 230 #define ICH6_REG_IR                     0x64
 231 #define ICH6_REG_IRS                    0x68
 232 #define   ICH6_IRS_VALID        (1<<1)
 233 #define   ICH6_IRS_BUSY         (1<<0)
 234
 235 #define ICH6_REG_DPLBASE                0x70
 236 #define ICH6_REG_DPUBASE                0x74
 237 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 238
 239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 240 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 241
 242 /* stream register offsets from stream base */
 243 #define ICH6_REG_SD_CTL                 0x00
 244 #define ICH6_REG_SD_STS                 0x03
 245 #define ICH6_REG_SD_LPIB                0x04
 246 #define ICH6_REG_SD_CBL                 0x08
 247 #define ICH6_REG_SD_LVI                 0x0c
 248 #define ICH6_REG_SD_FIFOW               0x0e
 249 #define ICH6_REG_SD_FIFOSIZE            0x10
 250 #define ICH6_REG_SD_FORMAT              0x12
 251 #define ICH6_REG_SD_BDLPL               0x18
 252 #define ICH6_REG_SD_BDLPU               0x1c
 253
 254 /* PCI space */
 255 #define ICH6_PCIREG_TCSEL       0x44
 256
 257 /*
 258  * other constants
 259  */
 260
 261 /* max number of SDs */
 262 /* ICH, ATI and VIA have 4 playback and 4 capture */
 263 #define ICH6_NUM_CAPTURE        4
 264 #define ICH6_NUM_PLAYBACK       4
 265
 266 /* ULI has 6 playback and 5 capture */
 267 #define ULI_NUM_CAPTURE         5
 268 #define ULI_NUM_PLAYBACK        6
 269
 270 /* ATI HDMI has 1 playback and 0 capture */
 271 #define ATIHDMI_NUM_CAPTURE     0
 272 #define ATIHDMI_NUM_PLAYBACK    1
 273
 274 /* TERA has 4 playback and 3 capture */
 275 #define TERA_NUM_CAPTURE        3
 276 #define TERA_NUM_PLAYBACK       4
 277
 278 /* this number is statically defined for simplicity */
 279 #define MAX_AZX_DEV             16
 280
 281 /* max number of fragments - we may use more if allocating more pages for BDL */
 282 #define BDL_SIZE                4096
 283 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 284 #define AZX_MAX_FRAG            32
 285 /* max buffer size - no h/w limit, you can increase as you like */
 286 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 287
 288 /* RIRB int mask: overrun[2], response[0] */
 289 #define RIRB_INT_RESPONSE       0x01
 290 #define RIRB_INT_OVERRUN        0x04
 291 #define RIRB_INT_MASK           0x05
 292
 293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 294 #define AZX_MAX_CODECS          8
 295 #define AZX_DEFAULT_CODECS      4
 296 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 297
 298 /* SD_CTL bits */
 299 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 300 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 301 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 302 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 303 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 304 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 305 #define SD_CTL_STREAM_TAG_SHIFT 20
 306
 307 /* SD_CTL and SD_STS */
 308 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 309 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 310 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 311 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 312                                  SD_INT_COMPLETE)
 313
 314 /* SD_STS */
 315 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 316
 317 /* INTCTL and INTSTS */
 318 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 319 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 320 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 321
 322 /* below are so far hardcoded - should read registers in future */
 323 #define ICH6_MAX_CORB_ENTRIES   256
 324 #define ICH6_MAX_RIRB_ENTRIES   256
 325
 326 /* position fix mode */
 327 enum {
 328         POS_FIX_AUTO,
 329         POS_FIX_LPIB,
 330         POS_FIX_POSBUF,
 331         POS_FIX_VIACOMBO,
 332 };
 333
 334 /* Defines for ATI HD Audio support in SB450 south bridge */
 335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 337
 338 /* Defines for Nvidia HDA support */
 339 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 340 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 341 #define NVIDIA_HDA_ISTRM_COH          0x4d
 342 #define NVIDIA_HDA_OSTRM_COH          0x4c
 343 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 344
 345 /* Defines for Intel SCH HDA snoop control */
 346 #define INTEL_SCH_HDA_DEVC      0x78
 347 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 348
 349 /* Define IN stream 0 FIFO size offset in VIA controller */
 350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 351 /* Define VIA HD Audio Device ID*/
 352 #define VIA_HDAC_DEVICE_ID              0x3288
 353
 354 /* HD Audio class code */
 355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 356
 357 /*
 358  */
 359
 360 struct azx_dev {
 361         struct snd_dma_buffer bdl; /* BDL buffer */
 362         u32 *posbuf;            /* position buffer pointer */
 363
 364         unsigned int bufsize;   /* size of the play buffer in bytes */
 365         unsigned int period_bytes; /* size of the period in bytes */
 366         unsigned int frags;     /* number for period in the play buffer */
 367         unsigned int fifo_size; /* FIFO size */
 368         unsigned long start_wallclk;    /* start + minimum wallclk */
 369         unsigned long period_wallclk;   /* wallclk for period */
 370
 371         void __iomem *sd_addr;  /* stream descriptor pointer */
 372
 373         u32 sd_int_sta_mask;    /* stream int status mask */
 374
 375         /* pcm support */
 376         struct snd_pcm_substream *substream;    /* assigned substream,
 377                                                  * set in PCM open
 378                                                  */
 379         unsigned int format_val;        /* format value to be set in the
 380                                          * controller and the codec
 381                                          */
 382         unsigned char stream_tag;       /* assigned stream */
 383         unsigned char index;            /* stream index */
 384         int device;                     /* last device number assigned to */
 385
 386         unsigned int opened :1;
 387         unsigned int running :1;
 388         unsigned int irq_pending :1;
 389         /*
 390          * For VIA:
 391          *  A flag to ensure DMA position is 0
 392          *  when link position is not greater than FIFO size
 393          */
 394         unsigned int insufficient :1;
 395         unsigned int wc_marked:1;
 396 };
 397
 398 /* CORB/RIRB */
 399 struct azx_rb {
 400         u32 *buf;               /* CORB/RIRB buffer
 401                                  * Each CORB entry is 4byte, RIRB is 8byte
 402                                  */
 403         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 404         /* for RIRB */
 405         unsigned short rp, wp;  /* read/write pointers */
 406         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 407         u32 res[AZX_MAX_CODECS];        /* last read value */
 408 };
 409
 410 struct azx {
 411         struct snd_card *card;
 412         struct pci_dev *pci;
 413         int dev_index;
 414
 415         /* chip type specific */
 416         int driver_type;
 417         unsigned int driver_caps;
 418         int playback_streams;
 419         int playback_index_offset;
 420         int capture_streams;
 421         int capture_index_offset;
 422         int num_streams;
 423
 424         /* pci resources */
 425         unsigned long addr;
 426         void __iomem *remap_addr;
 427         int irq;
 428
 429         /* locks */
 430         spinlock_t reg_lock;
 431         struct mutex open_mutex;
 432
 433         /* streams (x num_streams) */
 434         struct azx_dev *azx_dev;
 435
 436         /* PCM */
 437         struct snd_pcm *pcm[HDA_MAX_PCMS];
 438
 439         /* HD codec */
 440         unsigned short codec_mask;
 441         int  codec_probe_mask; /* copied from probe_mask option */
 442         struct hda_bus *bus;
 443         unsigned int beep_mode;
 444
 445         /* CORB/RIRB */
 446         struct azx_rb corb;
 447         struct azx_rb rirb;
 448
 449         /* CORB/RIRB and position buffers */
 450         struct snd_dma_buffer rb;
 451         struct snd_dma_buffer posbuf;
 452
 453         /* flags */
 454         int position_fix[2]; /* for both playback/capture streams */
 455         int poll_count;
 456         unsigned int running :1;
 457         unsigned int initialized :1;
 458         unsigned int single_cmd :1;
 459         unsigned int polling_mode :1;
 460         unsigned int msi :1;
 461         unsigned int irq_pending_warned :1;
 462         unsigned int probing :1; /* codec probing phase */
 463         unsigned int snoop:1;
 464
 465         /* for debugging */
 466         unsigned int last_cmd[AZX_MAX_CODECS];
 467
 468         /* for pending irqs */
 469         struct work_struct irq_pending_work;
 470
 471         /* reboot notifier (for mysterious hangup problem at power-down) */
 472         struct notifier_block reboot_notifier;
 473 };
 474
 475 /* driver types */
 476 enum {
 477         AZX_DRIVER_ICH,
 478         AZX_DRIVER_PCH,
 479         AZX_DRIVER_SCH,
 480         AZX_DRIVER_ATI,
 481         AZX_DRIVER_ATIHDMI,
 482         AZX_DRIVER_VIA,
 483         AZX_DRIVER_SIS,
 484         AZX_DRIVER_ULI,
 485         AZX_DRIVER_NVIDIA,
 486         AZX_DRIVER_TERA,
 487         AZX_DRIVER_CTX,
 488         AZX_DRIVER_GENERIC,
 489         AZX_NUM_DRIVERS, /* keep this as last entry */
 490 };
 491
 492 /* driver quirks (capabilities) */
 493 /* bits 0-7 are used for indicating driver type */
 494 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 495 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 496 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 497 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 498 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 499 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 500 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 501 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 502 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 503 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 504 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 505 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 506 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 507 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 508
 509 /* quirks for ATI SB / AMD Hudson */
 510 #define AZX_DCAPS_PRESET_ATI_SB \
 511         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 512          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 513
 514 /* quirks for ATI/AMD HDMI */
 515 #define AZX_DCAPS_PRESET_ATI_HDMI \
 516         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 517
 518 /* quirks for Nvidia */
 519 #define AZX_DCAPS_PRESET_NVIDIA \
 520         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
 521
 522 static char *driver_short_names[] __devinitdata = {
 523         [AZX_DRIVER_ICH] = "HDA Intel",
 524         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 525         [AZX_DRIVER_SCH] = "HDA Intel MID",
 526         [AZX_DRIVER_ATI] = "HDA ATI SB",
 527         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 528         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 529         [AZX_DRIVER_SIS] = "HDA SIS966",
 530         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 531         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 532         [AZX_DRIVER_TERA] = "HDA Teradici",
 533         [AZX_DRIVER_CTX] = "HDA Creative",
 534         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 535 };
 536
 537 /*
 538  * macros for easy use
 539  */
 540 #define azx_writel(chip,reg,value) \
 541         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 542 #define azx_readl(chip,reg) \
 543         readl((chip)->remap_addr + ICH6_REG_##reg)
 544 #define azx_writew(chip,reg,value) \
 545         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 546 #define azx_readw(chip,reg) \
 547         readw((chip)->remap_addr + ICH6_REG_##reg)
 548 #define azx_writeb(chip,reg,value) \
 549         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 550 #define azx_readb(chip,reg) \
 551         readb((chip)->remap_addr + ICH6_REG_##reg)
 552
 553 #define azx_sd_writel(dev,reg,value) \
 554         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 555 #define azx_sd_readl(dev,reg) \
 556         readl((dev)->sd_addr + ICH6_REG_##reg)
 557 #define azx_sd_writew(dev,reg,value) \
 558         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 559 #define azx_sd_readw(dev,reg) \
 560         readw((dev)->sd_addr + ICH6_REG_##reg)
 561 #define azx_sd_writeb(dev,reg,value) \
 562         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 563 #define azx_sd_readb(dev,reg) \
 564         readb((dev)->sd_addr + ICH6_REG_##reg)
 565
 566 /* for pcm support */
 567 #define get_azx_dev(substream) (substream->runtime->private_data)
 568
 569 #ifdef CONFIG_X86
 570 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 571 {
 572         if (azx_snoop(chip))
 573                 return;
 574         if (addr && size) {
 575                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 576                 if (on)
 577                         set_memory_wc((unsigned long)addr, pages);
 578                 else
 579                         set_memory_wb((unsigned long)addr, pages);
 580         }
 581 }
 582
 583 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 584                                  bool on)
 585 {
 586         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 587 }
 588 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 589                                    struct snd_pcm_runtime *runtime, bool on)
 590 {
 591         if (azx_dev->wc_marked != on) {
 592                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 593                 azx_dev->wc_marked = on;
 594         }
 595 }
 596 #else
 597 /* NOP for other archs */
 598 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 599                                  bool on)
 600 {
 601 }
 602 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 603                                    struct snd_pcm_runtime *runtime, bool on)
 604 {
 605 }
 606 #endif
 607
 608 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 609 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 610 /*
 611  * Interface for HD codec
 612  */
 613
 614 /*
 615  * CORB / RIRB interface
 616  */
 617 static int azx_alloc_cmd_io(struct azx *chip)
 618 {
 619         int err;
 620
 621         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 622         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 623                                   snd_dma_pci_data(chip->pci),
 624                                   PAGE_SIZE, &chip->rb);
 625         if (err < 0) {
 626                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 627                 return err;
 628         }
 629         mark_pages_wc(chip, &chip->rb, true);
 630         return 0;
 631 }
 632
 633 static void azx_init_cmd_io(struct azx *chip)
 634 {
 635         spin_lock_irq(&chip->reg_lock);
 636         /* CORB set up */
 637         chip->corb.addr = chip->rb.addr;
 638         chip->corb.buf = (u32 *)chip->rb.area;
 639         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 640         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 641
 642         /* set the corb size to 256 entries (ULI requires explicitly) */
 643         azx_writeb(chip, CORBSIZE, 0x02);
 644         /* set the corb write pointer to 0 */
 645         azx_writew(chip, CORBWP, 0);
 646         /* reset the corb hw read pointer */
 647         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 648         /* enable corb dma */
 649         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 650
 651         /* RIRB set up */
 652         chip->rirb.addr = chip->rb.addr + 2048;
 653         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 654         chip->rirb.wp = chip->rirb.rp = 0;
 655         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 656         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 657         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 658
 659         /* set the rirb size to 256 entries (ULI requires explicitly) */
 660         azx_writeb(chip, RIRBSIZE, 0x02);
 661         /* reset the rirb hw write pointer */
 662         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 663         /* set N=1, get RIRB response interrupt for new entry */
 664         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 665                 azx_writew(chip, RINTCNT, 0xc0);
 666         else
 667                 azx_writew(chip, RINTCNT, 1);
 668         /* enable rirb dma and response irq */
 669         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 670         spin_unlock_irq(&chip->reg_lock);
 671 }
 672
 673 static void azx_free_cmd_io(struct azx *chip)
 674 {
 675         spin_lock_irq(&chip->reg_lock);
 676         /* disable ringbuffer DMAs */
 677         azx_writeb(chip, RIRBCTL, 0);
 678         azx_writeb(chip, CORBCTL, 0);
 679         spin_unlock_irq(&chip->reg_lock);
 680 }
 681
 682 static unsigned int azx_command_addr(u32 cmd)
 683 {
 684         unsigned int addr = cmd >> 28;
 685
 686         if (addr >= AZX_MAX_CODECS) {
 687                 snd_BUG();
 688                 addr = 0;
 689         }
 690
 691         return addr;
 692 }
 693
 694 static unsigned int azx_response_addr(u32 res)
 695 {
 696         unsigned int addr = res & 0xf;
 697
 698         if (addr >= AZX_MAX_CODECS) {
 699                 snd_BUG();
 700                 addr = 0;
 701         }
 702
 703         return addr;
 704 }
 705
 706 /* send a command */
 707 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 708 {
 709         struct azx *chip = bus->private_data;
 710         unsigned int addr = azx_command_addr(val);
 711         unsigned int wp;
 712
 713         spin_lock_irq(&chip->reg_lock);
 714
 715         /* add command to corb */
 716         wp = azx_readb(chip, CORBWP);
 717         wp++;
 718         wp %= ICH6_MAX_CORB_ENTRIES;
 719
 720         chip->rirb.cmds[addr]++;
 721         chip->corb.buf[wp] = cpu_to_le32(val);
 722         azx_writel(chip, CORBWP, wp);
 723
 724         spin_unlock_irq(&chip->reg_lock);
 725
 726         return 0;
 727 }
 728
 729 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 730
 731 /* retrieve RIRB entry - called from interrupt handler */
 732 static void azx_update_rirb(struct azx *chip)
 733 {
 734         unsigned int rp, wp;
 735         unsigned int addr;
 736         u32 res, res_ex;
 737
 738         wp = azx_readb(chip, RIRBWP);
 739         if (wp == chip->rirb.wp)
 740                 return;
 741         chip->rirb.wp = wp;
 742
 743         while (chip->rirb.rp != wp) {
 744                 chip->rirb.rp++;
 745                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 746
 747                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 748                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 749                 res = le32_to_cpu(chip->rirb.buf[rp]);
 750                 addr = azx_response_addr(res_ex);
 751                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 752                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 753                 else if (chip->rirb.cmds[addr]) {
 754                         chip->rirb.res[addr] = res;
 755                         smp_wmb();
 756                         chip->rirb.cmds[addr]--;
 757                 } else
 758                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 759                                    "last cmd=%#08x\n",
 760                                    res, res_ex,
 761                                    chip->last_cmd[addr]);
 762         }
 763 }
 764
 765 /* receive a response */
 766 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 767                                           unsigned int addr)
 768 {
 769         struct azx *chip = bus->private_data;
 770         unsigned long timeout;
 771         int do_poll = 0;
 772
 773  again:
 774         timeout = jiffies + msecs_to_jiffies(1000);
 775         for (;;) {
 776                 if (chip->polling_mode || do_poll) {
 777                         spin_lock_irq(&chip->reg_lock);
 778                         azx_update_rirb(chip);
 779                         spin_unlock_irq(&chip->reg_lock);
 780                 }
 781                 if (!chip->rirb.cmds[addr]) {
 782                         smp_rmb();
 783                         bus->rirb_error = 0;
 784
 785                         if (!do_poll)
 786                                 chip->poll_count = 0;
 787                         return chip->rirb.res[addr]; /* the last value */
 788                 }
 789                 if (time_after(jiffies, timeout))
 790                         break;
 791                 if (bus->needs_damn_long_delay)
 792                         msleep(2); /* temporary workaround */
 793                 else {
 794                         udelay(10);
 795                         cond_resched();
 796                 }
 797         }
 798
 799         if (!chip->polling_mode && chip->poll_count < 2) {
 800                 snd_printdd(SFX "azx_get_response timeout, "
 801                            "polling the codec once: last cmd=0x%08x\n",
 802                            chip->last_cmd[addr]);
 803                 do_poll = 1;
 804                 chip->poll_count++;
 805                 goto again;
 806         }
 807
 808
 809         if (!chip->polling_mode) {
 810                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 811                            "switching to polling mode: last cmd=0x%08x\n",
 812                            chip->last_cmd[addr]);
 813                 chip->polling_mode = 1;
 814                 goto again;
 815         }
 816
 817         if (chip->msi) {
 818                 snd_printk(KERN_WARNING SFX "No response from codec, "
 819                            "disabling MSI: last cmd=0x%08x\n",
 820                            chip->last_cmd[addr]);
 821                 free_irq(chip->irq, chip);
 822                 chip->irq = -1;
 823                 pci_disable_msi(chip->pci);
 824                 chip->msi = 0;
 825                 if (azx_acquire_irq(chip, 1) < 0) {
 826                         bus->rirb_error = 1;
 827                         return -1;
 828                 }
 829                 goto again;
 830         }
 831
 832         if (chip->probing) {
 833                 /* If this critical timeout happens during the codec probing
 834                  * phase, this is likely an access to a non-existing codec
 835                  * slot.  Better to return an error and reset the system.
 836                  */
 837                 return -1;
 838         }
 839
 840         /* a fatal communication error; need either to reset or to fallback
 841          * to the single_cmd mode
 842          */
 843         bus->rirb_error = 1;
 844         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 845                 bus->response_reset = 1;
 846                 return -1; /* give a chance to retry */
 847         }
 848
 849         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 850                    "switching to single_cmd mode: last cmd=0x%08x\n",
 851                    chip->last_cmd[addr]);
 852         chip->single_cmd = 1;
 853         bus->response_reset = 0;
 854         /* release CORB/RIRB */
 855         azx_free_cmd_io(chip);
 856         /* disable unsolicited responses */
 857         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 858         return -1;
 859 }
 860
 861 /*
 862  * Use the single immediate command instead of CORB/RIRB for simplicity
 863  *
 864  * Note: according to Intel, this is not preferred use.  The command was
 865  *       intended for the BIOS only, and may get confused with unsolicited
 866  *       responses.  So, we shouldn't use it for normal operation from the
 867  *       driver.
 868  *       I left the codes, however, for debugging/testing purposes.
 869  */
 870
 871 /* receive a response */
 872 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 873 {
 874         int timeout = 50;
 875
 876         while (timeout--) {
 877                 /* check IRV busy bit */
 878                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 879                         /* reuse rirb.res as the response return value */
 880                         chip->rirb.res[addr] = azx_readl(chip, IR);
 881                         return 0;
 882                 }
 883                 udelay(1);
 884         }
 885         if (printk_ratelimit())
 886                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 887                            azx_readw(chip, IRS));
 888         chip->rirb.res[addr] = -1;
 889         return -EIO;
 890 }
 891
 892 /* send a command */
 893 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 894 {
 895         struct azx *chip = bus->private_data;
 896         unsigned int addr = azx_command_addr(val);
 897         int timeout = 50;
 898
 899         bus->rirb_error = 0;
 900         while (timeout--) {
 901                 /* check ICB busy bit */
 902                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 903                         /* Clear IRV valid bit */
 904                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 905                                    ICH6_IRS_VALID);
 906                         azx_writel(chip, IC, val);
 907                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 908                                    ICH6_IRS_BUSY);
 909                         return azx_single_wait_for_response(chip, addr);
 910                 }
 911                 udelay(1);
 912         }
 913         if (printk_ratelimit())
 914                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 915                            azx_readw(chip, IRS), val);
 916         return -EIO;
 917 }
 918
 919 /* receive a response */
 920 static unsigned int azx_single_get_response(struct hda_bus *bus,
 921                                             unsigned int addr)
 922 {
 923         struct azx *chip = bus->private_data;
 924         return chip->rirb.res[addr];
 925 }
 926
 927 /*
 928  * The below are the main callbacks from hda_codec.
 929  *
 930  * They are just the skeleton to call sub-callbacks according to the
 931  * current setting of chip->single_cmd.
 932  */
 933
 934 /* send a command */
 935 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 936 {
 937         struct azx *chip = bus->private_data;
 938
 939         chip->last_cmd[azx_command_addr(val)] = val;
 940         if (chip->single_cmd)
 941                 return azx_single_send_cmd(bus, val);
 942         else
 943                 return azx_corb_send_cmd(bus, val);
 944 }
 945
 946 /* get a response */
 947 static unsigned int azx_get_response(struct hda_bus *bus,
 948                                      unsigned int addr)
 949 {
 950         struct azx *chip = bus->private_data;
 951         if (chip->single_cmd)
 952                 return azx_single_get_response(bus, addr);
 953         else
 954                 return azx_rirb_get_response(bus, addr);
 955 }
 956
 957 #ifdef CONFIG_SND_HDA_POWER_SAVE
 958 static void azx_power_notify(struct hda_bus *bus);
 959 #endif
 960
 961 /* reset codec link */
 962 static int azx_reset(struct azx *chip, int full_reset)
 963 {
 964         int count;
 965
 966         if (!full_reset)
 967                 goto __skip;
 968
 969         /* clear STATESTS */
 970         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 971
 972         /* reset controller */
 973         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 974
 975         count = 50;
 976         while (azx_readb(chip, GCTL) && --count)
 977                 msleep(1);
 978
 979         /* delay for >= 100us for codec PLL to settle per spec
 980          * Rev 0.9 section 5.5.1
 981          */
 982         msleep(1);
 983
 984         /* Bring controller out of reset */
 985         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 986
 987         count = 50;
 988         while (!azx_readb(chip, GCTL) && --count)
 989                 msleep(1);
 990
 991         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 992         msleep(1);
 993
 994       __skip:
 995         /* check to see if controller is ready */
 996         if (!azx_readb(chip, GCTL)) {
 997                 snd_printd(SFX "azx_reset: controller not ready!\n");
 998                 return -EBUSY;
 999         }
1000
1001         /* Accept unsolicited responses */
1002         if (!chip->single_cmd)
1003                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1004                            ICH6_GCTL_UNSOL);
1005
1006         /* detect codecs */
1007         if (!chip->codec_mask) {
1008                 chip->codec_mask = azx_readw(chip, STATESTS);
1009                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1010         }
1011
1012         return 0;
1013 }
1014
1015
1016 /*
1017  * Lowlevel interface
1018  */
1019
1020 /* enable interrupts */
1021 static void azx_int_enable(struct azx *chip)
1022 {
1023         /* enable controller CIE and GIE */
1024         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1025                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1026 }
1027
1028 /* disable interrupts */
1029 static void azx_int_disable(struct azx *chip)
1030 {
1031         int i;
1032
1033         /* disable interrupts in stream descriptor */
1034         for (i = 0; i < chip->num_streams; i++) {
1035                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1036                 azx_sd_writeb(azx_dev, SD_CTL,
1037                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1038         }
1039
1040         /* disable SIE for all streams */
1041         azx_writeb(chip, INTCTL, 0);
1042
1043         /* disable controller CIE and GIE */
1044         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1045                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1046 }
1047
1048 /* clear interrupts */
1049 static void azx_int_clear(struct azx *chip)
1050 {
1051         int i;
1052
1053         /* clear stream status */
1054         for (i = 0; i < chip->num_streams; i++) {
1055                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1056                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1057         }
1058
1059         /* clear STATESTS */
1060         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1061
1062         /* clear rirb status */
1063         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1064
1065         /* clear int status */
1066         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1067 }
1068
1069 /* start a stream */
1070 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1071 {
1072         /*
1073          * Before stream start, initialize parameter
1074          */
1075         azx_dev->insufficient = 1;
1076
1077         /* enable SIE */
1078         azx_writel(chip, INTCTL,
1079                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1080         /* set DMA start and interrupt mask */
1081         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1082                       SD_CTL_DMA_START | SD_INT_MASK);
1083 }
1084
1085 /* stop DMA */
1086 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1087 {
1088         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1089                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1090         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1091 }
1092
1093 /* stop a stream */
1094 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1095 {
1096         azx_stream_clear(chip, azx_dev);
1097         /* disable SIE */
1098         azx_writel(chip, INTCTL,
1099                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1100 }
1101
1102
1103 /*
1104  * reset and start the controller registers
1105  */
1106 static void azx_init_chip(struct azx *chip, int full_reset)
1107 {
1108         if (chip->initialized)
1109                 return;
1110
1111         /* reset controller */
1112         azx_reset(chip, full_reset);
1113
1114         /* initialize interrupts */
1115         azx_int_clear(chip);
1116         azx_int_enable(chip);
1117
1118         /* initialize the codec command I/O */
1119         if (!chip->single_cmd)
1120                 azx_init_cmd_io(chip);
1121
1122         /* program the position buffer */
1123         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1124         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1125
1126         chip->initialized = 1;
1127 }
1128
1129 /*
1130  * initialize the PCI registers
1131  */
1132 /* update bits in a PCI register byte */
1133 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1134                             unsigned char mask, unsigned char val)
1135 {
1136         unsigned char data;
1137
1138         pci_read_config_byte(pci, reg, &data);
1139         data &= ~mask;
1140         data |= (val & mask);
1141         pci_write_config_byte(pci, reg, data);
1142 }
1143
1144 static void azx_init_pci(struct azx *chip)
1145 {
1146         /* force to non-snoop mode for a new VIA controller when BIOS is set */
1147         if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1148                 u8 snoop;
1149                 pci_read_config_byte(chip->pci, 0x42, &snoop);
1150                 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1151                         chip->snoop = 0;
1152                         snd_printdd(SFX "Force to non-snoop mode\n");
1153                 }
1154         }
1155
1156         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1157          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1158          * Ensuring these bits are 0 clears playback static on some HD Audio
1159          * codecs.
1160          * The PCI register TCSEL is defined in the Intel manuals.
1161          */
1162         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1163                 snd_printdd(SFX "Clearing TCSEL\n");
1164                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1165         }
1166
1167         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1168          * we need to enable snoop.
1169          */
1170         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1171                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1172                 update_pci_byte(chip->pci,
1173                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1174                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1175         }
1176
1177         /* For NVIDIA HDA, enable snoop */
1178         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1179                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1180                 update_pci_byte(chip->pci,
1181                                 NVIDIA_HDA_TRANSREG_ADDR,
1182                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1183                 update_pci_byte(chip->pci,
1184                                 NVIDIA_HDA_ISTRM_COH,
1185                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1186                 update_pci_byte(chip->pci,
1187                                 NVIDIA_HDA_OSTRM_COH,
1188                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1189         }
1190
1191         /* Enable SCH/PCH snoop if needed */
1192         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1193                 unsigned short snoop;
1194                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1195                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1196                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1197                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1198                         if (!azx_snoop(chip))
1199                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1200                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1201                         pci_read_config_word(chip->pci,
1202                                 INTEL_SCH_HDA_DEVC, &snoop);
1203                 }
1204                 snd_printdd(SFX "SCH snoop: %s\n",
1205                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1206                                 ? "Disabled" : "Enabled");
1207         }
1208 }
1209
1210
1211 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1212
1213 /*
1214  * interrupt handler
1215  */
1216 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1217 {
1218         struct azx *chip = dev_id;
1219         struct azx_dev *azx_dev;
1220         u32 status;
1221         u8 sd_status;
1222         int i, ok;
1223
1224         spin_lock(&chip->reg_lock);
1225
1226         status = azx_readl(chip, INTSTS);
1227         if (status == 0) {
1228                 spin_unlock(&chip->reg_lock);
1229                 return IRQ_NONE;
1230         }
1231
1232         for (i = 0; i < chip->num_streams; i++) {
1233                 azx_dev = &chip->azx_dev[i];
1234                 if (status & azx_dev->sd_int_sta_mask) {
1235                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1236                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1237                         if (!azx_dev->substream || !azx_dev->running ||
1238                             !(sd_status & SD_INT_COMPLETE))
1239                                 continue;
1240                         /* check whether this IRQ is really acceptable */
1241                         ok = azx_position_ok(chip, azx_dev);
1242                         if (ok == 1) {
1243                                 azx_dev->irq_pending = 0;
1244                                 spin_unlock(&chip->reg_lock);
1245                                 snd_pcm_period_elapsed(azx_dev->substream);
1246                                 spin_lock(&chip->reg_lock);
1247                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1248                                 /* bogus IRQ, process it later */
1249                                 azx_dev->irq_pending = 1;
1250                                 queue_work(chip->bus->workq,
1251                                            &chip->irq_pending_work);
1252                         }
1253                 }
1254         }
1255
1256         /* clear rirb int */
1257         status = azx_readb(chip, RIRBSTS);
1258         if (status & RIRB_INT_MASK) {
1259                 if (status & RIRB_INT_RESPONSE) {
1260                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1261                                 udelay(80);
1262                         azx_update_rirb(chip);
1263                 }
1264                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1265         }
1266
1267 #if 0
1268         /* clear state status int */
1269         if (azx_readb(chip, STATESTS) & 0x04)
1270                 azx_writeb(chip, STATESTS, 0x04);
1271 #endif
1272         spin_unlock(&chip->reg_lock);
1273
1274         return IRQ_HANDLED;
1275 }
1276
1277
1278 /*
1279  * set up a BDL entry
1280  */
1281 static int setup_bdle(struct snd_pcm_substream *substream,
1282                       struct azx_dev *azx_dev, u32 **bdlp,
1283                       int ofs, int size, int with_ioc)
1284 {
1285         u32 *bdl = *bdlp;
1286
1287         while (size > 0) {
1288                 dma_addr_t addr;
1289                 int chunk;
1290
1291                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1292                         return -EINVAL;
1293
1294                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1295                 /* program the address field of the BDL entry */
1296                 bdl[0] = cpu_to_le32((u32)addr);
1297                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1298                 /* program the size field of the BDL entry */
1299                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1300                 bdl[2] = cpu_to_le32(chunk);
1301                 /* program the IOC to enable interrupt
1302                  * only when the whole fragment is processed
1303                  */
1304                 size -= chunk;
1305                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1306                 bdl += 4;
1307                 azx_dev->frags++;
1308                 ofs += chunk;
1309         }
1310         *bdlp = bdl;
1311         return ofs;
1312 }
1313
1314 /*
1315  * set up BDL entries
1316  */
1317 static int azx_setup_periods(struct azx *chip,
1318                              struct snd_pcm_substream *substream,
1319                              struct azx_dev *azx_dev)
1320 {
1321         u32 *bdl;
1322         int i, ofs, periods, period_bytes;
1323         int pos_adj;
1324
1325         /* reset BDL address */
1326         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1327         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1328
1329         period_bytes = azx_dev->period_bytes;
1330         periods = azx_dev->bufsize / period_bytes;
1331
1332         /* program the initial BDL entries */
1333         bdl = (u32 *)azx_dev->bdl.area;
1334         ofs = 0;
1335         azx_dev->frags = 0;
1336         pos_adj = bdl_pos_adj[chip->dev_index];
1337         if (pos_adj > 0) {
1338                 struct snd_pcm_runtime *runtime = substream->runtime;
1339                 int pos_align = pos_adj;
1340                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1341                 if (!pos_adj)
1342                         pos_adj = pos_align;
1343                 else
1344                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1345                                 pos_align;
1346                 pos_adj = frames_to_bytes(runtime, pos_adj);
1347                 if (pos_adj >= period_bytes) {
1348                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1349                                    bdl_pos_adj[chip->dev_index]);
1350                         pos_adj = 0;
1351                 } else {
1352                         ofs = setup_bdle(substream, azx_dev,
1353                                          &bdl, ofs, pos_adj,
1354                                          !substream->runtime->no_period_wakeup);
1355                         if (ofs < 0)
1356                                 goto error;
1357                 }
1358         } else
1359                 pos_adj = 0;
1360         for (i = 0; i < periods; i++) {
1361                 if (i == periods - 1 && pos_adj)
1362                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1363                                          period_bytes - pos_adj, 0);
1364                 else
1365                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1366                                          period_bytes,
1367                                          !substream->runtime->no_period_wakeup);
1368                 if (ofs < 0)
1369                         goto error;
1370         }
1371         return 0;
1372
1373  error:
1374         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1375                    azx_dev->bufsize, period_bytes);
1376         return -EINVAL;
1377 }
1378
1379 /* reset stream */
1380 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1381 {
1382         unsigned char val;
1383         int timeout;
1384
1385         azx_stream_clear(chip, azx_dev);
1386
1387         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1388                       SD_CTL_STREAM_RESET);
1389         udelay(3);
1390         timeout = 300;
1391         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1392                --timeout)
1393                 ;
1394         val &= ~SD_CTL_STREAM_RESET;
1395         azx_sd_writeb(azx_dev, SD_CTL, val);
1396         udelay(3);
1397
1398         timeout = 300;
1399         /* waiting for hardware to report that the stream is out of reset */
1400         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1401                --timeout)
1402                 ;
1403
1404         /* reset first position - may not be synced with hw at this time */
1405         *azx_dev->posbuf = 0;
1406 }
1407
1408 /*
1409  * set up the SD for streaming
1410  */
1411 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1412 {
1413         unsigned int val;
1414         /* make sure the run bit is zero for SD */
1415         azx_stream_clear(chip, azx_dev);
1416         /* program the stream_tag */
1417         val = azx_sd_readl(azx_dev, SD_CTL);
1418         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1419                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1420         if (!azx_snoop(chip))
1421                 val |= SD_CTL_TRAFFIC_PRIO;
1422         azx_sd_writel(azx_dev, SD_CTL, val);
1423
1424         /* program the length of samples in cyclic buffer */
1425         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1426
1427         /* program the stream format */
1428         /* this value needs to be the same as the one programmed */
1429         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1430
1431         /* program the stream LVI (last valid index) of the BDL */
1432         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1433
1434         /* program the BDL address */
1435         /* lower BDL address */
1436         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1437         /* upper BDL address */
1438         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1439
1440         /* enable the position buffer */
1441         if (chip->position_fix[0] != POS_FIX_LPIB ||
1442             chip->position_fix[1] != POS_FIX_LPIB) {
1443                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1444                         azx_writel(chip, DPLBASE,
1445                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1446         }
1447
1448         /* set the interrupt enable bits in the descriptor control register */
1449         azx_sd_writel(azx_dev, SD_CTL,
1450                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1451
1452         return 0;
1453 }
1454
1455 /*
1456  * Probe the given codec address
1457  */
1458 static int probe_codec(struct azx *chip, int addr)
1459 {
1460         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1461                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1462         unsigned int res;
1463
1464         mutex_lock(&chip->bus->cmd_mutex);
1465         chip->probing = 1;
1466         azx_send_cmd(chip->bus, cmd);
1467         res = azx_get_response(chip->bus, addr);
1468         chip->probing = 0;
1469         mutex_unlock(&chip->bus->cmd_mutex);
1470         if (res == -1)
1471                 return -EIO;
1472         snd_printdd(SFX "codec #%d probed OK\n", addr);
1473         return 0;
1474 }
1475
1476 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1477                                  struct hda_pcm *cpcm);
1478 static void azx_stop_chip(struct azx *chip);
1479
1480 static void azx_bus_reset(struct hda_bus *bus)
1481 {
1482         struct azx *chip = bus->private_data;
1483
1484         bus->in_reset = 1;
1485         azx_stop_chip(chip);
1486         azx_init_chip(chip, 1);
1487 #ifdef CONFIG_PM
1488         if (chip->initialized) {
1489                 int i;
1490
1491                 for (i = 0; i < HDA_MAX_PCMS; i++)
1492                         snd_pcm_suspend_all(chip->pcm[i]);
1493                 snd_hda_suspend(chip->bus);
1494                 snd_hda_resume(chip->bus);
1495         }
1496 #endif
1497         bus->in_reset = 0;
1498 }
1499
1500 /*
1501  * Codec initialization
1502  */
1503
1504 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1505 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1506         [AZX_DRIVER_NVIDIA] = 8,
1507         [AZX_DRIVER_TERA] = 1,
1508 };
1509
1510 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1511 {
1512         struct hda_bus_template bus_temp;
1513         int c, codecs, err;
1514         int max_slots;
1515
1516         memset(&bus_temp, 0, sizeof(bus_temp));
1517         bus_temp.private_data = chip;
1518         bus_temp.modelname = model;
1519         bus_temp.pci = chip->pci;
1520         bus_temp.ops.command = azx_send_cmd;
1521         bus_temp.ops.get_response = azx_get_response;
1522         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1523         bus_temp.ops.bus_reset = azx_bus_reset;
1524 #ifdef CONFIG_SND_HDA_POWER_SAVE
1525         bus_temp.power_save = &power_save;
1526         bus_temp.ops.pm_notify = azx_power_notify;
1527 #endif
1528
1529         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1530         if (err < 0)
1531                 return err;
1532
1533         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1534                 snd_printd(SFX "Enable delay in RIRB handling\n");
1535                 chip->bus->needs_damn_long_delay = 1;
1536         }
1537
1538         codecs = 0;
1539         max_slots = azx_max_codecs[chip->driver_type];
1540         if (!max_slots)
1541                 max_slots = AZX_DEFAULT_CODECS;
1542
1543         /* First try to probe all given codec slots */
1544         for (c = 0; c < max_slots; c++) {
1545                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1546                         if (probe_codec(chip, c) < 0) {
1547                                 /* Some BIOSen give you wrong codec addresses
1548                                  * that don't exist
1549                                  */
1550                                 snd_printk(KERN_WARNING SFX
1551                                            "Codec #%d probe error; "
1552                                            "disabling it...\n", c);
1553                                 chip->codec_mask &= ~(1 << c);
1554                                 /* More badly, accessing to a non-existing
1555                                  * codec often screws up the controller chip,
1556                                  * and disturbs the further communications.
1557                                  * Thus if an error occurs during probing,
1558                                  * better to reset the controller chip to
1559                                  * get back to the sanity state.
1560                                  */
1561                                 azx_stop_chip(chip);
1562                                 azx_init_chip(chip, 1);
1563                         }
1564                 }
1565         }
1566
1567         /* AMD chipsets often cause the communication stalls upon certain
1568          * sequence like the pin-detection.  It seems that forcing the synced
1569          * access works around the stall.  Grrr...
1570          */
1571         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1572                 snd_printd(SFX "Enable sync_write for stable communication\n");
1573                 chip->bus->sync_write = 1;
1574                 chip->bus->allow_bus_reset = 1;
1575         }
1576
1577         /* Then create codec instances */
1578         for (c = 0; c < max_slots; c++) {
1579                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1580                         struct hda_codec *codec;
1581                         err = snd_hda_codec_new(chip->bus, c, &codec);
1582                         if (err < 0)
1583                                 continue;
1584                         codec->beep_mode = chip->beep_mode;
1585                         codecs++;
1586                 }
1587         }
1588         if (!codecs) {
1589                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1590                 return -ENXIO;
1591         }
1592         return 0;
1593 }
1594
1595 /* configure each codec instance */
1596 static int __devinit azx_codec_configure(struct azx *chip)
1597 {
1598         struct hda_codec *codec;
1599         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1600                 snd_hda_codec_configure(codec);
1601         }
1602         return 0;
1603 }
1604
1605
1606 /*
1607  * PCM support
1608  */
1609
1610 /* assign a stream for the PCM */
1611 static inline struct azx_dev *
1612 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1613 {
1614         int dev, i, nums;
1615         struct azx_dev *res = NULL;
1616
1617         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1618                 dev = chip->playback_index_offset;
1619                 nums = chip->playback_streams;
1620         } else {
1621                 dev = chip->capture_index_offset;
1622                 nums = chip->capture_streams;
1623         }
1624         for (i = 0; i < nums; i++, dev++)
1625                 if (!chip->azx_dev[dev].opened) {
1626                         res = &chip->azx_dev[dev];
1627                         if (res->device == substream->pcm->device)
1628                                 break;
1629                 }
1630         if (res) {
1631                 res->opened = 1;
1632                 res->device = substream->pcm->device;
1633         }
1634         return res;
1635 }
1636
1637 /* release the assigned stream */
1638 static inline void azx_release_device(struct azx_dev *azx_dev)
1639 {
1640         azx_dev->opened = 0;
1641 }
1642
1643 static struct snd_pcm_hardware azx_pcm_hw = {
1644         .info =                 (SNDRV_PCM_INFO_MMAP |
1645                                  SNDRV_PCM_INFO_INTERLEAVED |
1646                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1647                                  SNDRV_PCM_INFO_MMAP_VALID |
1648                                  /* No full-resume yet implemented */
1649                                  /* SNDRV_PCM_INFO_RESUME |*/
1650                                  SNDRV_PCM_INFO_PAUSE |
1651                                  SNDRV_PCM_INFO_SYNC_START |
1652                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1653         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1654         .rates =                SNDRV_PCM_RATE_48000,
1655         .rate_min =             48000,
1656         .rate_max =             48000,
1657         .channels_min =         2,
1658         .channels_max =         2,
1659         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1660         .period_bytes_min =     128,
1661         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1662         .periods_min =          2,
1663         .periods_max =          AZX_MAX_FRAG,
1664         .fifo_size =            0,
1665 };
1666
1667 struct azx_pcm {
1668         struct azx *chip;
1669         struct hda_codec *codec;
1670         struct hda_pcm_stream *hinfo[2];
1671 };
1672
1673 static int azx_pcm_open(struct snd_pcm_substream *substream)
1674 {
1675         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1676         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1677         struct azx *chip = apcm->chip;
1678         struct azx_dev *azx_dev;
1679         struct snd_pcm_runtime *runtime = substream->runtime;
1680         unsigned long flags;
1681         int err;
1682         int buff_step;
1683
1684         mutex_lock(&chip->open_mutex);
1685         azx_dev = azx_assign_device(chip, substream);
1686         if (azx_dev == NULL) {
1687                 mutex_unlock(&chip->open_mutex);
1688                 return -EBUSY;
1689         }
1690         runtime->hw = azx_pcm_hw;
1691         runtime->hw.channels_min = hinfo->channels_min;
1692         runtime->hw.channels_max = hinfo->channels_max;
1693         runtime->hw.formats = hinfo->formats;
1694         runtime->hw.rates = hinfo->rates;
1695         snd_pcm_limit_hw_rates(runtime);
1696         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1697         if (align_buffer_size)
1698                 /* constrain buffer sizes to be multiple of 128
1699                    bytes. This is more efficient in terms of memory
1700                    access but isn't required by the HDA spec and
1701                    prevents users from specifying exact period/buffer
1702                    sizes. For example for 44.1kHz, a period size set
1703                    to 20ms will be rounded to 19.59ms. */
1704                 buff_step = 128;
1705         else
1706                 /* Don't enforce steps on buffer sizes, still need to
1707                    be multiple of 4 bytes (HDA spec). Tested on Intel
1708                    HDA controllers, may not work on all devices where
1709                    option needs to be disabled */
1710                 buff_step = 4;
1711
1712         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1713                                    buff_step);
1714         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1715                                    buff_step);
1716         snd_hda_power_up(apcm->codec);
1717         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1718         if (err < 0) {
1719                 azx_release_device(azx_dev);
1720                 snd_hda_power_down(apcm->codec);
1721                 mutex_unlock(&chip->open_mutex);
1722                 return err;
1723         }
1724         snd_pcm_limit_hw_rates(runtime);
1725         /* sanity check */
1726         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1727             snd_BUG_ON(!runtime->hw.channels_max) ||
1728             snd_BUG_ON(!runtime->hw.formats) ||
1729             snd_BUG_ON(!runtime->hw.rates)) {
1730                 azx_release_device(azx_dev);
1731                 hinfo->ops.close(hinfo, apcm->codec, substream);
1732                 snd_hda_power_down(apcm->codec);
1733                 mutex_unlock(&chip->open_mutex);
1734                 return -EINVAL;
1735         }
1736         spin_lock_irqsave(&chip->reg_lock, flags);
1737         azx_dev->substream = substream;
1738         azx_dev->running = 0;
1739         spin_unlock_irqrestore(&chip->reg_lock, flags);
1740
1741         runtime->private_data = azx_dev;
1742         snd_pcm_set_sync(substream);
1743         mutex_unlock(&chip->open_mutex);
1744         return 0;
1745 }
1746
1747 static int azx_pcm_close(struct snd_pcm_substream *substream)
1748 {
1749         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1750         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1751         struct azx *chip = apcm->chip;
1752         struct azx_dev *azx_dev = get_azx_dev(substream);
1753         unsigned long flags;
1754
1755         mutex_lock(&chip->open_mutex);
1756         spin_lock_irqsave(&chip->reg_lock, flags);
1757         azx_dev->substream = NULL;
1758         azx_dev->running = 0;
1759         spin_unlock_irqrestore(&chip->reg_lock, flags);
1760         azx_release_device(azx_dev);
1761         hinfo->ops.close(hinfo, apcm->codec, substream);
1762         snd_hda_power_down(apcm->codec);
1763         mutex_unlock(&chip->open_mutex);
1764         return 0;
1765 }
1766
1767 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1768                              struct snd_pcm_hw_params *hw_params)
1769 {
1770         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1771         struct azx *chip = apcm->chip;
1772         struct snd_pcm_runtime *runtime = substream->runtime;
1773         struct azx_dev *azx_dev = get_azx_dev(substream);
1774         int ret;
1775
1776         mark_runtime_wc(chip, azx_dev, runtime, false);
1777         azx_dev->bufsize = 0;
1778         azx_dev->period_bytes = 0;
1779         azx_dev->format_val = 0;
1780         ret = snd_pcm_lib_malloc_pages(substream,
1781                                         params_buffer_bytes(hw_params));
1782         if (ret < 0)
1783                 return ret;
1784         mark_runtime_wc(chip, azx_dev, runtime, true);
1785         return ret;
1786 }
1787
1788 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1789 {
1790         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1791         struct azx_dev *azx_dev = get_azx_dev(substream);
1792         struct azx *chip = apcm->chip;
1793         struct snd_pcm_runtime *runtime = substream->runtime;
1794         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1795
1796         /* reset BDL address */
1797         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1798         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1799         azx_sd_writel(azx_dev, SD_CTL, 0);
1800         azx_dev->bufsize = 0;
1801         azx_dev->period_bytes = 0;
1802         azx_dev->format_val = 0;
1803
1804         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1805
1806         mark_runtime_wc(chip, azx_dev, runtime, false);
1807         return snd_pcm_lib_free_pages(substream);
1808 }
1809
1810 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1811 {
1812         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1813         struct azx *chip = apcm->chip;
1814         struct azx_dev *azx_dev = get_azx_dev(substream);
1815         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1816         struct snd_pcm_runtime *runtime = substream->runtime;
1817         unsigned int bufsize, period_bytes, format_val, stream_tag;
1818         int err;
1819         struct hda_spdif_out *spdif =
1820                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1821         unsigned short ctls = spdif ? spdif->ctls : 0;
1822
1823         azx_stream_reset(chip, azx_dev);
1824         format_val = snd_hda_calc_stream_format(runtime->rate,
1825                                                 runtime->channels,
1826                                                 runtime->format,
1827                                                 hinfo->maxbps,
1828                                                 ctls);
1829         if (!format_val) {
1830                 snd_printk(KERN_ERR SFX
1831                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1832                            runtime->rate, runtime->channels, runtime->format);
1833                 return -EINVAL;
1834         }
1835
1836         bufsize = snd_pcm_lib_buffer_bytes(substream);
1837         period_bytes = snd_pcm_lib_period_bytes(substream);
1838
1839         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1840                     bufsize, format_val);
1841
1842         if (bufsize != azx_dev->bufsize ||
1843             period_bytes != azx_dev->period_bytes ||
1844             format_val != azx_dev->format_val) {
1845                 azx_dev->bufsize = bufsize;
1846                 azx_dev->period_bytes = period_bytes;
1847                 azx_dev->format_val = format_val;
1848                 err = azx_setup_periods(chip, substream, azx_dev);
1849                 if (err < 0)
1850                         return err;
1851         }
1852
1853         /* wallclk has 24Mhz clock source */
1854         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1855                                                 runtime->rate) * 1000);
1856         azx_setup_controller(chip, azx_dev);
1857         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1858                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1859         else
1860                 azx_dev->fifo_size = 0;
1861
1862         stream_tag = azx_dev->stream_tag;
1863         /* CA-IBG chips need the playback stream starting from 1 */
1864         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1865             stream_tag > chip->capture_streams)
1866                 stream_tag -= chip->capture_streams;
1867         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1868                                      azx_dev->format_val, substream);
1869 }
1870
1871 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1872 {
1873         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1874         struct azx *chip = apcm->chip;
1875         struct azx_dev *azx_dev;
1876         struct snd_pcm_substream *s;
1877         int rstart = 0, start, nsync = 0, sbits = 0;
1878         int nwait, timeout;
1879
1880         switch (cmd) {
1881         case SNDRV_PCM_TRIGGER_START:
1882                 rstart = 1;
1883         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1884         case SNDRV_PCM_TRIGGER_RESUME:
1885                 start = 1;
1886                 break;
1887         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1888         case SNDRV_PCM_TRIGGER_SUSPEND:
1889         case SNDRV_PCM_TRIGGER_STOP:
1890                 start = 0;
1891                 break;
1892         default:
1893                 return -EINVAL;
1894         }
1895
1896         snd_pcm_group_for_each_entry(s, substream) {
1897                 if (s->pcm->card != substream->pcm->card)
1898                         continue;
1899                 azx_dev = get_azx_dev(s);
1900                 sbits |= 1 << azx_dev->index;
1901                 nsync++;
1902                 snd_pcm_trigger_done(s, substream);
1903         }
1904
1905         spin_lock(&chip->reg_lock);
1906         if (nsync > 1) {
1907                 /* first, set SYNC bits of corresponding streams */
1908                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1909                         azx_writel(chip, OLD_SSYNC,
1910                                    azx_readl(chip, OLD_SSYNC) | sbits);
1911                 else
1912                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1913         }
1914         snd_pcm_group_for_each_entry(s, substream) {
1915                 if (s->pcm->card != substream->pcm->card)
1916                         continue;
1917                 azx_dev = get_azx_dev(s);
1918                 if (start) {
1919                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1920                         if (!rstart)
1921                                 azx_dev->start_wallclk -=
1922                                                 azx_dev->period_wallclk;
1923                         azx_stream_start(chip, azx_dev);
1924                 } else {
1925                         azx_stream_stop(chip, azx_dev);
1926                 }
1927                 azx_dev->running = start;
1928         }
1929         spin_unlock(&chip->reg_lock);
1930         if (start) {
1931                 if (nsync == 1)
1932                         return 0;
1933                 /* wait until all FIFOs get ready */
1934                 for (timeout = 5000; timeout; timeout--) {
1935                         nwait = 0;
1936                         snd_pcm_group_for_each_entry(s, substream) {
1937                                 if (s->pcm->card != substream->pcm->card)
1938                                         continue;
1939                                 azx_dev = get_azx_dev(s);
1940                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1941                                       SD_STS_FIFO_READY))
1942                                         nwait++;
1943                         }
1944                         if (!nwait)
1945                                 break;
1946                         cpu_relax();
1947                 }
1948         } else {
1949                 /* wait until all RUN bits are cleared */
1950                 for (timeout = 5000; timeout; timeout--) {
1951                         nwait = 0;
1952                         snd_pcm_group_for_each_entry(s, substream) {
1953                                 if (s->pcm->card != substream->pcm->card)
1954                                         continue;
1955                                 azx_dev = get_azx_dev(s);
1956                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1957                                     SD_CTL_DMA_START)
1958                                         nwait++;
1959                         }
1960                         if (!nwait)
1961                                 break;
1962                         cpu_relax();
1963                 }
1964         }
1965         if (nsync > 1) {
1966                 spin_lock(&chip->reg_lock);
1967                 /* reset SYNC bits */
1968                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1969                         azx_writel(chip, OLD_SSYNC,
1970                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1971                 else
1972                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1973                 spin_unlock(&chip->reg_lock);
1974         }
1975         return 0;
1976 }
1977
1978 /* get the current DMA position with correction on VIA chips */
1979 static unsigned int azx_via_get_position(struct azx *chip,
1980                                          struct azx_dev *azx_dev)
1981 {
1982         unsigned int link_pos, mini_pos, bound_pos;
1983         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1984         unsigned int fifo_size;
1985
1986         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1987         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1988                 /* Playback, no problem using link position */
1989                 return link_pos;
1990         }
1991
1992         /* Capture */
1993         /* For new chipset,
1994          * use mod to get the DMA position just like old chipset
1995          */
1996         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1997         mod_dma_pos %= azx_dev->period_bytes;
1998
1999         /* azx_dev->fifo_size can't get FIFO size of in stream.
2000          * Get from base address + offset.
2001          */
2002         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2003
2004         if (azx_dev->insufficient) {
2005                 /* Link position never gather than FIFO size */
2006                 if (link_pos <= fifo_size)
2007                         return 0;
2008
2009                 azx_dev->insufficient = 0;
2010         }
2011
2012         if (link_pos <= fifo_size)
2013                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2014         else
2015                 mini_pos = link_pos - fifo_size;
2016
2017         /* Find nearest previous boudary */
2018         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2019         mod_link_pos = link_pos % azx_dev->period_bytes;
2020         if (mod_link_pos >= fifo_size)
2021                 bound_pos = link_pos - mod_link_pos;
2022         else if (mod_dma_pos >= mod_mini_pos)
2023                 bound_pos = mini_pos - mod_mini_pos;
2024         else {
2025                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2026                 if (bound_pos >= azx_dev->bufsize)
2027                         bound_pos = 0;
2028         }
2029
2030         /* Calculate real DMA position we want */
2031         return bound_pos + mod_dma_pos;
2032 }
2033
2034 static unsigned int azx_get_position(struct azx *chip,
2035                                      struct azx_dev *azx_dev)
2036 {
2037         unsigned int pos;
2038         int stream = azx_dev->substream->stream;
2039
2040         switch (chip->position_fix[stream]) {
2041         case POS_FIX_LPIB:
2042                 /* read LPIB */
2043                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2044                 break;
2045         case POS_FIX_VIACOMBO:
2046                 pos = azx_via_get_position(chip, azx_dev);
2047                 break;
2048         default:
2049                 /* use the position buffer */
2050                 pos = le32_to_cpu(*azx_dev->posbuf);
2051                 if (chip->position_fix[stream] == POS_FIX_AUTO) {
2052                         if (!pos || pos == (u32)-1) {
2053                                 printk(KERN_WARNING
2054                                        "hda-intel: Invalid position buffer, "
2055                                        "using LPIB read method instead.\n");
2056                                 chip->position_fix[stream] = POS_FIX_LPIB;
2057                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2058                         } else
2059                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2060                 }
2061                 break;
2062         }
2063
2064         if (pos >= azx_dev->bufsize)
2065                 pos = 0;
2066         return pos;
2067 }
2068
2069 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2070 {
2071         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2072         struct azx *chip = apcm->chip;
2073         struct azx_dev *azx_dev = get_azx_dev(substream);
2074         return bytes_to_frames(substream->runtime,
2075                                azx_get_position(chip, azx_dev));
2076 }
2077
2078 /*
2079  * Check whether the current DMA position is acceptable for updating
2080  * periods.  Returns non-zero if it's OK.
2081  *
2082  * Many HD-audio controllers appear pretty inaccurate about
2083  * the update-IRQ timing.  The IRQ is issued before actually the
2084  * data is processed.  So, we need to process it afterwords in a
2085  * workqueue.
2086  */
2087 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2088 {
2089         u32 wallclk;
2090         unsigned int pos;
2091         int stream;
2092
2093         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2094         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2095                 return -1;      /* bogus (too early) interrupt */
2096
2097         stream = azx_dev->substream->stream;
2098         pos = azx_get_position(chip, azx_dev);
2099
2100         if (WARN_ONCE(!azx_dev->period_bytes,
2101                       "hda-intel: zero azx_dev->period_bytes"))
2102                 return -1; /* this shouldn't happen! */
2103         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2104             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2105                 /* NG - it's below the first next period boundary */
2106                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2107         azx_dev->start_wallclk += wallclk;
2108         return 1; /* OK, it's fine */
2109 }
2110
2111 /*
2112  * The work for pending PCM period updates.
2113  */
2114 static void azx_irq_pending_work(struct work_struct *work)
2115 {
2116         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2117         int i, pending, ok;
2118
2119         if (!chip->irq_pending_warned) {
2120                 printk(KERN_WARNING
2121                        "hda-intel: IRQ timing workaround is activated "
2122                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2123                        chip->card->number);
2124                 chip->irq_pending_warned = 1;
2125         }
2126
2127         for (;;) {
2128                 pending = 0;
2129                 spin_lock_irq(&chip->reg_lock);
2130                 for (i = 0; i < chip->num_streams; i++) {
2131                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2132                         if (!azx_dev->irq_pending ||
2133                             !azx_dev->substream ||
2134                             !azx_dev->running)
2135                                 continue;
2136                         ok = azx_position_ok(chip, azx_dev);
2137                         if (ok > 0) {
2138                                 azx_dev->irq_pending = 0;
2139                                 spin_unlock(&chip->reg_lock);
2140                                 snd_pcm_period_elapsed(azx_dev->substream);
2141                                 spin_lock(&chip->reg_lock);
2142                         } else if (ok < 0) {
2143                                 pending = 0;    /* too early */
2144                         } else
2145                                 pending++;
2146                 }
2147                 spin_unlock_irq(&chip->reg_lock);
2148                 if (!pending)
2149                         return;
2150                 msleep(1);
2151         }
2152 }
2153
2154 /* clear irq_pending flags and assure no on-going workq */
2155 static void azx_clear_irq_pending(struct azx *chip)
2156 {
2157         int i;
2158
2159         spin_lock_irq(&chip->reg_lock);
2160         for (i = 0; i < chip->num_streams; i++)
2161                 chip->azx_dev[i].irq_pending = 0;
2162         spin_unlock_irq(&chip->reg_lock);
2163 }
2164
2165 #ifdef CONFIG_X86
2166 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2167                         struct vm_area_struct *area)
2168 {
2169         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2170         struct azx *chip = apcm->chip;
2171         if (!azx_snoop(chip))
2172                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2173         return snd_pcm_lib_default_mmap(substream, area);
2174 }
2175 #else
2176 #define azx_pcm_mmap    NULL
2177 #endif
2178
2179 static struct snd_pcm_ops azx_pcm_ops = {
2180         .open = azx_pcm_open,
2181         .close = azx_pcm_close,
2182         .ioctl = snd_pcm_lib_ioctl,
2183         .hw_params = azx_pcm_hw_params,
2184         .hw_free = azx_pcm_hw_free,
2185         .prepare = azx_pcm_prepare,
2186         .trigger = azx_pcm_trigger,
2187         .pointer = azx_pcm_pointer,
2188         .mmap = azx_pcm_mmap,
2189         .page = snd_pcm_sgbuf_ops_page,
2190 };
2191
2192 static void azx_pcm_free(struct snd_pcm *pcm)
2193 {
2194         struct azx_pcm *apcm = pcm->private_data;
2195         if (apcm) {
2196                 apcm->chip->pcm[pcm->device] = NULL;
2197                 kfree(apcm);
2198         }
2199 }
2200
2201 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2202
2203 static int
2204 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2205                       struct hda_pcm *cpcm)
2206 {
2207         struct azx *chip = bus->private_data;
2208         struct snd_pcm *pcm;
2209         struct azx_pcm *apcm;
2210         int pcm_dev = cpcm->device;
2211         unsigned int size;
2212         int s, err;
2213
2214         if (pcm_dev >= HDA_MAX_PCMS) {
2215                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2216                            pcm_dev);
2217                 return -EINVAL;
2218         }
2219         if (chip->pcm[pcm_dev]) {
2220                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2221                 return -EBUSY;
2222         }
2223         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2224                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2225                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2226                           &pcm);
2227         if (err < 0)
2228                 return err;
2229         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2230         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2231         if (apcm == NULL)
2232                 return -ENOMEM;
2233         apcm->chip = chip;
2234         apcm->codec = codec;
2235         pcm->private_data = apcm;
2236         pcm->private_free = azx_pcm_free;
2237         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2238                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2239         chip->pcm[pcm_dev] = pcm;
2240         cpcm->pcm = pcm;
2241         for (s = 0; s < 2; s++) {
2242                 apcm->hinfo[s] = &cpcm->stream[s];
2243                 if (cpcm->stream[s].substreams)
2244                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2245         }
2246         /* buffer pre-allocation */
2247         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2248         if (size > MAX_PREALLOC_SIZE)
2249                 size = MAX_PREALLOC_SIZE;
2250         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2251                                               snd_dma_pci_data(chip->pci),
2252                                               size, MAX_PREALLOC_SIZE);
2253         return 0;
2254 }
2255
2256 /*
2257  * mixer creation - all stuff is implemented in hda module
2258  */
2259 static int __devinit azx_mixer_create(struct azx *chip)
2260 {
2261         return snd_hda_build_controls(chip->bus);
2262 }
2263
2264
2265 /*
2266  * initialize SD streams
2267  */
2268 static int __devinit azx_init_stream(struct azx *chip)
2269 {
2270         int i;
2271
2272         /* initialize each stream (aka device)
2273          * assign the starting bdl address to each stream (device)
2274          * and initialize
2275          */
2276         for (i = 0; i < chip->num_streams; i++) {
2277                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2278                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2279                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2280                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2281                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2282                 azx_dev->sd_int_sta_mask = 1 << i;
2283                 /* stream tag: must be non-zero and unique */
2284                 azx_dev->index = i;
2285                 azx_dev->stream_tag = i + 1;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2292 {
2293         if (request_irq(chip->pci->irq, azx_interrupt,
2294                         chip->msi ? 0 : IRQF_SHARED,
2295                         KBUILD_MODNAME, chip)) {
2296                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2297                        "disabling device\n", chip->pci->irq);
2298                 if (do_disconnect)
2299                         snd_card_disconnect(chip->card);
2300                 return -1;
2301         }
2302         chip->irq = chip->pci->irq;
2303         pci_intx(chip->pci, !chip->msi);
2304         return 0;
2305 }
2306
2307
2308 static void azx_stop_chip(struct azx *chip)
2309 {
2310         if (!chip->initialized)
2311                 return;
2312
2313         /* disable interrupts */
2314         azx_int_disable(chip);
2315         azx_int_clear(chip);
2316
2317         /* disable CORB/RIRB */
2318         azx_free_cmd_io(chip);
2319
2320         /* disable position buffer */
2321         azx_writel(chip, DPLBASE, 0);
2322         azx_writel(chip, DPUBASE, 0);
2323
2324         chip->initialized = 0;
2325 }
2326
2327 #ifdef CONFIG_SND_HDA_POWER_SAVE
2328 /* power-up/down the controller */
2329 static void azx_power_notify(struct hda_bus *bus)
2330 {
2331         struct azx *chip = bus->private_data;
2332         struct hda_codec *c;
2333         int power_on = 0;
2334
2335         list_for_each_entry(c, &bus->codec_list, list) {
2336                 if (c->power_on) {
2337                         power_on = 1;
2338                         break;
2339                 }
2340         }
2341         if (power_on)
2342                 azx_init_chip(chip, 1);
2343         else if (chip->running && power_save_controller &&
2344                  !bus->power_keep_link_on)
2345                 azx_stop_chip(chip);
2346 }
2347 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2348
2349 #ifdef CONFIG_PM
2350 /*
2351  * power management
2352  */
2353
2354 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2355 {
2356         struct hda_codec *codec;
2357
2358         list_for_each_entry(codec, &bus->codec_list, list) {
2359                 if (snd_hda_codec_needs_resume(codec))
2360                         return 1;
2361         }
2362         return 0;
2363 }
2364
2365 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2366 {
2367         struct snd_card *card = pci_get_drvdata(pci);
2368         struct azx *chip = card->private_data;
2369         int i;
2370
2371         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2372         azx_clear_irq_pending(chip);
2373         for (i = 0; i < HDA_MAX_PCMS; i++)
2374                 snd_pcm_suspend_all(chip->pcm[i]);
2375         if (chip->initialized)
2376                 snd_hda_suspend(chip->bus);
2377         azx_stop_chip(chip);
2378         if (chip->irq >= 0) {
2379                 free_irq(chip->irq, chip);
2380                 chip->irq = -1;
2381         }
2382         if (chip->msi)
2383                 pci_disable_msi(chip->pci);
2384         pci_disable_device(pci);
2385         pci_save_state(pci);
2386         pci_set_power_state(pci, pci_choose_state(pci, state));
2387         return 0;
2388 }
2389
2390 static int azx_resume(struct pci_dev *pci)
2391 {
2392         struct snd_card *card = pci_get_drvdata(pci);
2393         struct azx *chip = card->private_data;
2394
2395         pci_set_power_state(pci, PCI_D0);
2396         pci_restore_state(pci);
2397         if (pci_enable_device(pci) < 0) {
2398                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2399                        "disabling device\n");
2400                 snd_card_disconnect(card);
2401                 return -EIO;
2402         }
2403         pci_set_master(pci);
2404         if (chip->msi)
2405                 if (pci_enable_msi(pci) < 0)
2406                         chip->msi = 0;
2407         if (azx_acquire_irq(chip, 1) < 0)
2408                 return -EIO;
2409         azx_init_pci(chip);
2410
2411         if (snd_hda_codecs_inuse(chip->bus))
2412                 azx_init_chip(chip, 1);
2413
2414         snd_hda_resume(chip->bus);
2415         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2416         return 0;
2417 }
2418 #endif /* CONFIG_PM */
2419
2420
2421 /*
2422  * reboot notifier for hang-up problem at power-down
2423  */
2424 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2425 {
2426         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2427         snd_hda_bus_reboot_notify(chip->bus);
2428         azx_stop_chip(chip);
2429         return NOTIFY_OK;
2430 }
2431
2432 static void azx_notifier_register(struct azx *chip)
2433 {
2434         chip->reboot_notifier.notifier_call = azx_halt;
2435         register_reboot_notifier(&chip->reboot_notifier);
2436 }
2437
2438 static void azx_notifier_unregister(struct azx *chip)
2439 {
2440         if (chip->reboot_notifier.notifier_call)
2441                 unregister_reboot_notifier(&chip->reboot_notifier);
2442 }
2443
2444 /*
2445  * destructor
2446  */
2447 static int azx_free(struct azx *chip)
2448 {
2449         int i;
2450
2451         azx_notifier_unregister(chip);
2452
2453         if (chip->initialized) {
2454                 azx_clear_irq_pending(chip);
2455                 for (i = 0; i < chip->num_streams; i++)
2456                         azx_stream_stop(chip, &chip->azx_dev[i]);
2457                 azx_stop_chip(chip);
2458         }
2459
2460         if (chip->irq >= 0)
2461                 free_irq(chip->irq, (void*)chip);
2462         if (chip->msi)
2463                 pci_disable_msi(chip->pci);
2464         if (chip->remap_addr)
2465                 iounmap(chip->remap_addr);
2466
2467         if (chip->azx_dev) {
2468                 for (i = 0; i < chip->num_streams; i++)
2469                         if (chip->azx_dev[i].bdl.area) {
2470                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2471                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2472                         }
2473         }
2474         if (chip->rb.area) {
2475                 mark_pages_wc(chip, &chip->rb, false);
2476                 snd_dma_free_pages(&chip->rb);
2477         }
2478         if (chip->posbuf.area) {
2479                 mark_pages_wc(chip, &chip->posbuf, false);
2480                 snd_dma_free_pages(&chip->posbuf);
2481         }
2482         pci_release_regions(chip->pci);
2483         pci_disable_device(chip->pci);
2484         kfree(chip->azx_dev);
2485         kfree(chip);
2486
2487         return 0;
2488 }
2489
2490 static int azx_dev_free(struct snd_device *device)
2491 {
2492         return azx_free(device->device_data);
2493 }
2494
2495 /*
2496  * white/black-listing for position_fix
2497  */
2498 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2499         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2500         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2501         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2502         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2503         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2504         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2505         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2506         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2507         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2508         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2509         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2510         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2511         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2512         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2513         {}
2514 };
2515
2516 static int __devinit check_position_fix(struct azx *chip, int fix)
2517 {
2518         const struct snd_pci_quirk *q;
2519
2520         switch (fix) {
2521         case POS_FIX_LPIB:
2522         case POS_FIX_POSBUF:
2523         case POS_FIX_VIACOMBO:
2524                 return fix;
2525         }
2526
2527         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2528         if (q) {
2529                 printk(KERN_INFO
2530                        "hda_intel: position_fix set to %d "
2531                        "for device %04x:%04x\n",
2532                        q->value, q->subvendor, q->subdevice);
2533                 return q->value;
2534         }
2535
2536         /* Check VIA/ATI HD Audio Controller exist */
2537         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2538                 snd_printd(SFX "Using VIACOMBO position fix\n");
2539                 return POS_FIX_VIACOMBO;
2540         }
2541         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2542                 snd_printd(SFX "Using LPIB position fix\n");
2543                 return POS_FIX_LPIB;
2544         }
2545         return POS_FIX_AUTO;
2546 }
2547
2548 /*
2549  * black-lists for probe_mask
2550  */
2551 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2552         /* Thinkpad often breaks the controller communication when accessing
2553          * to the non-working (or non-existing) modem codec slot.
2554          */
2555         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2556         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2557         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2558         /* broken BIOS */
2559         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2560         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2561         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2562         /* forced codec slots */
2563         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2564         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2565         {}
2566 };
2567
2568 #define AZX_FORCE_CODEC_MASK    0x100
2569
2570 static void __devinit check_probe_mask(struct azx *chip, int dev)
2571 {
2572         const struct snd_pci_quirk *q;
2573
2574         chip->codec_probe_mask = probe_mask[dev];
2575         if (chip->codec_probe_mask == -1) {
2576                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2577                 if (q) {
2578                         printk(KERN_INFO
2579                                "hda_intel: probe_mask set to 0x%x "
2580                                "for device %04x:%04x\n",
2581                                q->value, q->subvendor, q->subdevice);
2582                         chip->codec_probe_mask = q->value;
2583                 }
2584         }
2585
2586         /* check forced option */
2587         if (chip->codec_probe_mask != -1 &&
2588             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2589                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2590                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2591                        chip->codec_mask);
2592         }
2593 }
2594
2595 /*
2596  * white/black-list for enable_msi
2597  */
2598 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2599         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2600         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2601         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2602         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2603         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2604         {}
2605 };
2606
2607 static void __devinit check_msi(struct azx *chip)
2608 {
2609         const struct snd_pci_quirk *q;
2610
2611         if (enable_msi >= 0) {
2612                 chip->msi = !!enable_msi;
2613                 return;
2614         }
2615         chip->msi = 1;  /* enable MSI as default */
2616         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2617         if (q) {
2618                 printk(KERN_INFO
2619                        "hda_intel: msi for device %04x:%04x set to %d\n",
2620                        q->subvendor, q->subdevice, q->value);
2621                 chip->msi = q->value;
2622                 return;
2623         }
2624
2625         /* NVidia chipsets seem to cause troubles with MSI */
2626         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2627                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2628                 chip->msi = 0;
2629         }
2630 }
2631
2632
2633 /*
2634  * constructor
2635  */
2636 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2637                                 int dev, unsigned int driver_caps,
2638                                 struct azx **rchip)
2639 {
2640         struct azx *chip;
2641         int i, err;
2642         unsigned short gcap;
2643         static struct snd_device_ops ops = {
2644                 .dev_free = azx_dev_free,
2645         };
2646
2647         *rchip = NULL;
2648
2649         err = pci_enable_device(pci);
2650         if (err < 0)
2651                 return err;
2652
2653         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2654         if (!chip) {
2655                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2656                 pci_disable_device(pci);
2657                 return -ENOMEM;
2658         }
2659
2660         spin_lock_init(&chip->reg_lock);
2661         mutex_init(&chip->open_mutex);
2662         chip->card = card;
2663         chip->pci = pci;
2664         chip->irq = -1;
2665         chip->driver_caps = driver_caps;
2666         chip->driver_type = driver_caps & 0xff;
2667         check_msi(chip);
2668         chip->dev_index = dev;
2669         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2670
2671         chip->position_fix[0] = chip->position_fix[1] =
2672                 check_position_fix(chip, position_fix[dev]);
2673         check_probe_mask(chip, dev);
2674
2675         chip->single_cmd = single_cmd;
2676         chip->snoop = hda_snoop;
2677
2678         if (bdl_pos_adj[dev] < 0) {
2679                 switch (chip->driver_type) {
2680                 case AZX_DRIVER_ICH:
2681                 case AZX_DRIVER_PCH:
2682                         bdl_pos_adj[dev] = 1;
2683                         break;
2684                 default:
2685                         bdl_pos_adj[dev] = 32;
2686                         break;
2687                 }
2688         }
2689
2690 #if BITS_PER_LONG != 64
2691         /* Fix up base address on ULI M5461 */
2692         if (chip->driver_type == AZX_DRIVER_ULI) {
2693                 u16 tmp3;
2694                 pci_read_config_word(pci, 0x40, &tmp3);
2695                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2696                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2697         }
2698 #endif
2699
2700         err = pci_request_regions(pci, "ICH HD audio");
2701         if (err < 0) {
2702                 kfree(chip);
2703                 pci_disable_device(pci);
2704                 return err;
2705         }
2706
2707         chip->addr = pci_resource_start(pci, 0);
2708         chip->remap_addr = pci_ioremap_bar(pci, 0);
2709         if (chip->remap_addr == NULL) {
2710                 snd_printk(KERN_ERR SFX "ioremap error\n");
2711                 err = -ENXIO;
2712                 goto errout;
2713         }
2714
2715         if (chip->msi)
2716                 if (pci_enable_msi(pci) < 0)
2717                         chip->msi = 0;
2718
2719         if (azx_acquire_irq(chip, 0) < 0) {
2720                 err = -EBUSY;
2721                 goto errout;
2722         }
2723
2724         pci_set_master(pci);
2725         synchronize_irq(chip->irq);
2726
2727         gcap = azx_readw(chip, GCAP);
2728         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2729
2730         /* disable SB600 64bit support for safety */
2731         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2732                 struct pci_dev *p_smbus;
2733                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2734                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2735                                          NULL);
2736                 if (p_smbus) {
2737                         if (p_smbus->revision < 0x30)
2738                                 gcap &= ~ICH6_GCAP_64OK;
2739                         pci_dev_put(p_smbus);
2740                 }
2741         }
2742
2743         /* disable 64bit DMA address on some devices */
2744         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2745                 snd_printd(SFX "Disabling 64bit DMA\n");
2746                 gcap &= ~ICH6_GCAP_64OK;
2747         }
2748
2749         /* disable buffer size rounding to 128-byte multiples if supported */
2750         if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2751                 align_buffer_size = 0;
2752
2753         /* allow 64bit DMA address if supported by H/W */
2754         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2755                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2756         else {
2757                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2758                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2759         }
2760
2761         /* read number of streams from GCAP register instead of using
2762          * hardcoded value
2763          */
2764         chip->capture_streams = (gcap >> 8) & 0x0f;
2765         chip->playback_streams = (gcap >> 12) & 0x0f;
2766         if (!chip->playback_streams && !chip->capture_streams) {
2767                 /* gcap didn't give any info, switching to old method */
2768
2769                 switch (chip->driver_type) {
2770                 case AZX_DRIVER_ULI:
2771                         chip->playback_streams = ULI_NUM_PLAYBACK;
2772                         chip->capture_streams = ULI_NUM_CAPTURE;
2773                         break;
2774                 case AZX_DRIVER_ATIHDMI:
2775                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2776                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2777                         break;
2778                 case AZX_DRIVER_GENERIC:
2779                 default:
2780                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2781                         chip->capture_streams = ICH6_NUM_CAPTURE;
2782                         break;
2783                 }
2784         }
2785         chip->capture_index_offset = 0;
2786         chip->playback_index_offset = chip->capture_streams;
2787         chip->num_streams = chip->playback_streams + chip->capture_streams;
2788         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2789                                 GFP_KERNEL);
2790         if (!chip->azx_dev) {
2791                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2792                 goto errout;
2793         }
2794
2795         for (i = 0; i < chip->num_streams; i++) {
2796                 /* allocate memory for the BDL for each stream */
2797                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2798                                           snd_dma_pci_data(chip->pci),
2799                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2800                 if (err < 0) {
2801                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2802                         goto errout;
2803                 }
2804                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2805         }
2806         /* allocate memory for the position buffer */
2807         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2808                                   snd_dma_pci_data(chip->pci),
2809                                   chip->num_streams * 8, &chip->posbuf);
2810         if (err < 0) {
2811                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2812                 goto errout;
2813         }
2814         mark_pages_wc(chip, &chip->posbuf, true);
2815         /* allocate CORB/RIRB */
2816         err = azx_alloc_cmd_io(chip);
2817         if (err < 0)
2818                 goto errout;
2819
2820         /* initialize streams */
2821         azx_init_stream(chip);
2822
2823         /* initialize chip */
2824         azx_init_pci(chip);
2825         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2826
2827         /* codec detection */
2828         if (!chip->codec_mask) {
2829                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2830                 err = -ENODEV;
2831                 goto errout;
2832         }
2833
2834         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2835         if (err <0) {
2836                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2837                 goto errout;
2838         }
2839
2840         strcpy(card->driver, "HDA-Intel");
2841         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2842                 sizeof(card->shortname));
2843         snprintf(card->longname, sizeof(card->longname),
2844                  "%s at 0x%lx irq %i",
2845                  card->shortname, chip->addr, chip->irq);
2846
2847         *rchip = chip;
2848         return 0;
2849
2850  errout:
2851         azx_free(chip);
2852         return err;
2853 }
2854
2855 static void power_down_all_codecs(struct azx *chip)
2856 {
2857 #ifdef CONFIG_SND_HDA_POWER_SAVE
2858         /* The codecs were powered up in snd_hda_codec_new().
2859          * Now all initialization done, so turn them down if possible
2860          */
2861         struct hda_codec *codec;
2862         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2863                 snd_hda_power_down(codec);
2864         }
2865 #endif
2866 }
2867
2868 static int __devinit azx_probe(struct pci_dev *pci,
2869                                const struct pci_device_id *pci_id)
2870 {
2871         static int dev;
2872         struct snd_card *card;
2873         struct azx *chip;
2874         int err;
2875
2876         if (dev >= SNDRV_CARDS)
2877                 return -ENODEV;
2878         if (!enable[dev]) {
2879                 dev++;
2880                 return -ENOENT;
2881         }
2882
2883         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2884         if (err < 0) {
2885                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2886                 return err;
2887         }
2888
2889         /* set this here since it's referred in snd_hda_load_patch() */
2890         snd_card_set_dev(card, &pci->dev);
2891
2892         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2893         if (err < 0)
2894                 goto out_free;
2895         card->private_data = chip;
2896
2897 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2898         chip->beep_mode = beep_mode[dev];
2899 #endif
2900
2901         /* create codec instances */
2902         err = azx_codec_create(chip, model[dev]);
2903         if (err < 0)
2904                 goto out_free;
2905 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2906         if (patch[dev] && *patch[dev]) {
2907                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2908                            patch[dev]);
2909                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2910                 if (err < 0)
2911                         goto out_free;
2912         }
2913 #endif
2914         if ((probe_only[dev] & 1) == 0) {
2915                 err = azx_codec_configure(chip);
2916                 if (err < 0)
2917                         goto out_free;
2918         }
2919
2920         /* create PCM streams */
2921         err = snd_hda_build_pcms(chip->bus);
2922         if (err < 0)
2923                 goto out_free;
2924
2925         /* create mixer controls */
2926         err = azx_mixer_create(chip);
2927         if (err < 0)
2928                 goto out_free;
2929
2930         err = snd_card_register(card);
2931         if (err < 0)
2932                 goto out_free;
2933
2934         pci_set_drvdata(pci, card);
2935         chip->running = 1;
2936         power_down_all_codecs(chip);
2937         azx_notifier_register(chip);
2938
2939         dev++;
2940         return err;
2941 out_free:
2942         snd_card_free(card);
2943         return err;
2944 }
2945
2946 static void __devexit azx_remove(struct pci_dev *pci)
2947 {
2948         snd_card_free(pci_get_drvdata(pci));
2949         pci_set_drvdata(pci, NULL);
2950 }
2951
2952 /* PCI IDs */
2953 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2954         /* CPT */
2955         { PCI_DEVICE(0x8086, 0x1c20),
2956           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2957           AZX_DCAPS_BUFSIZE },
2958         /* PBG */
2959         { PCI_DEVICE(0x8086, 0x1d20),
2960           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2961           AZX_DCAPS_BUFSIZE},
2962         /* Panther Point */
2963         { PCI_DEVICE(0x8086, 0x1e20),
2964           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2965           AZX_DCAPS_BUFSIZE},
2966         /* SCH */
2967         { PCI_DEVICE(0x8086, 0x811b),
2968           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2969           AZX_DCAPS_BUFSIZE},
2970         { PCI_DEVICE(0x8086, 0x2668),
2971           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2972           AZX_DCAPS_BUFSIZE },  /* ICH6 */
2973         { PCI_DEVICE(0x8086, 0x27d8),
2974           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2975           AZX_DCAPS_BUFSIZE },  /* ICH7 */
2976         { PCI_DEVICE(0x8086, 0x269a),
2977           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2978           AZX_DCAPS_BUFSIZE },  /* ESB2 */
2979         { PCI_DEVICE(0x8086, 0x284b),
2980           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2981           AZX_DCAPS_BUFSIZE },  /* ICH8 */
2982         { PCI_DEVICE(0x8086, 0x293e),
2983           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2984           AZX_DCAPS_BUFSIZE },  /* ICH9 */
2985         { PCI_DEVICE(0x8086, 0x293f),
2986           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2987           AZX_DCAPS_BUFSIZE },  /* ICH9 */
2988         { PCI_DEVICE(0x8086, 0x3a3e),
2989           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2990           AZX_DCAPS_BUFSIZE },  /* ICH10 */
2991         { PCI_DEVICE(0x8086, 0x3a6e),
2992           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2993           AZX_DCAPS_BUFSIZE },  /* ICH10 */
2994         /* Generic Intel */
2995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2996           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2997           .class_mask = 0xffffff,
2998           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2999         /* ATI SB 450/600/700/800/900 */
3000         { PCI_DEVICE(0x1002, 0x437b),
3001           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3002         { PCI_DEVICE(0x1002, 0x4383),
3003           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3004         /* AMD Hudson */
3005         { PCI_DEVICE(0x1022, 0x780d),
3006           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3007         /* ATI HDMI */
3008         { PCI_DEVICE(0x1002, 0x793b),
3009           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3010         { PCI_DEVICE(0x1002, 0x7919),
3011           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3012         { PCI_DEVICE(0x1002, 0x960f),
3013           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3014         { PCI_DEVICE(0x1002, 0x970f),
3015           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3016         { PCI_DEVICE(0x1002, 0xaa00),
3017           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3018         { PCI_DEVICE(0x1002, 0xaa08),
3019           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3020         { PCI_DEVICE(0x1002, 0xaa10),
3021           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3022         { PCI_DEVICE(0x1002, 0xaa18),
3023           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3024         { PCI_DEVICE(0x1002, 0xaa20),
3025           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3026         { PCI_DEVICE(0x1002, 0xaa28),
3027           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3028         { PCI_DEVICE(0x1002, 0xaa30),
3029           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3030         { PCI_DEVICE(0x1002, 0xaa38),
3031           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3032         { PCI_DEVICE(0x1002, 0xaa40),
3033           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3034         { PCI_DEVICE(0x1002, 0xaa48),
3035           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3036         /* VIA VT8251/VT8237A */
3037         { PCI_DEVICE(0x1106, 0x3288),
3038           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3039         /* SIS966 */
3040         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3041         /* ULI M5461 */
3042         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3043         /* NVIDIA MCP */
3044         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3045           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3046           .class_mask = 0xffffff,
3047           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3048         /* Teradici */
3049         { PCI_DEVICE(0x6549, 0x1200),
3050           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3051         /* Creative X-Fi (CA0110-IBG) */
3052 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3053         /* the following entry conflicts with snd-ctxfi driver,
3054          * as ctxfi driver mutates from HD-audio to native mode with
3055          * a special command sequence.
3056          */
3057         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3058           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3059           .class_mask = 0xffffff,
3060           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3061           AZX_DCAPS_RIRB_PRE_DELAY },
3062 #else
3063         /* this entry seems still valid -- i.e. without emu20kx chip */
3064         { PCI_DEVICE(0x1102, 0x0009),
3065           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3066           AZX_DCAPS_RIRB_PRE_DELAY },
3067 #endif
3068         /* Vortex86MX */
3069         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3070         /* VMware HDAudio */
3071         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3072         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3073         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3074           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3075           .class_mask = 0xffffff,
3076           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3077         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3078           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3079           .class_mask = 0xffffff,
3080           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3081         { 0, }
3082 };
3083 MODULE_DEVICE_TABLE(pci, azx_ids);
3084
3085 /* pci_driver definition */
3086 static struct pci_driver driver = {
3087         .name = KBUILD_MODNAME,
3088         .id_table = azx_ids,
3089         .probe = azx_probe,
3090         .remove = __devexit_p(azx_remove),
3091 #ifdef CONFIG_PM
3092         .suspend = azx_suspend,
3093         .resume = azx_resume,
3094 #endif
3095 };
3096
3097 static int __init alsa_card_azx_init(void)
3098 {
3099         return pci_register_driver(&driver);
3100 }
3101
3102 static void __exit alsa_card_azx_exit(void)
3103 {
3104         pci_unregister_driver(&driver);
3105 }
3106
3107 module_init(alsa_card_azx_init)
3108 module_exit(alsa_card_azx_exit)