sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include <linux/vgaarb.h>
  57 #include <linux/vga_switcheroo.h>
  58 #include <linux/firmware.h>
  59 #include "hda_codec.h"
  60
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  65 static char *model[SNDRV_CARDS];
  66 static int position_fix[SNDRV_CARDS];
  67 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  68 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  69 static int probe_only[SNDRV_CARDS];
  70 static bool single_cmd;
  71 static int enable_msi = -1;
  72 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  73 static char *patch[SNDRV_CARDS];
  74 #endif
  75 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  76 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  77                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  78 #endif
  79
  80 module_param_array(index, int, NULL, 0444);
  81 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  82 module_param_array(id, charp, NULL, 0444);
  83 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  84 module_param_array(enable, bool, NULL, 0444);
  85 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  86 module_param_array(model, charp, NULL, 0444);
  87 MODULE_PARM_DESC(model, "Use the given board model.");
  88 module_param_array(position_fix, int, NULL, 0444);
  89 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  90                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  91 module_param_array(bdl_pos_adj, int, NULL, 0644);
  92 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  93 module_param_array(probe_mask, int, NULL, 0444);
  94 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  95 module_param_array(probe_only, int, NULL, 0444);
  96 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  97 module_param(single_cmd, bool, 0444);
  98 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  99                  "(for debugging only).");
 100 module_param(enable_msi, bint, 0444);
 101 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 102 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 103 module_param_array(patch, charp, NULL, 0444);
 104 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 105 #endif
 106 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 107 module_param_array(beep_mode, bool, NULL, 0444);
 108 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 109                             "(0=off, 1=on) (default=1).");
 110 #endif
 111
 112 #ifdef CONFIG_SND_HDA_POWER_SAVE
 113 static int param_set_xint(const char *val, const struct kernel_param *kp);
 114 static struct kernel_param_ops param_ops_xint = {
 115         .set = param_set_xint,
 116         .get = param_get_int,
 117 };
 118 #define param_check_xint param_check_int
 119
 120 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 121 module_param(power_save, xint, 0644);
 122 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 123                  "(in second, 0 = disable).");
 124
 125 /* reset the HD-audio controller in power save mode.
 126  * this may give more power-saving, but will take longer time to
 127  * wake up.
 128  */
 129 static bool power_save_controller = 1;
 130 module_param(power_save_controller, bool, 0644);
 131 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 132 #endif
 133
 134 static int align_buffer_size = -1;
 135 module_param(align_buffer_size, bint, 0644);
 136 MODULE_PARM_DESC(align_buffer_size,
 137                 "Force buffer and period sizes to be multiple of 128 bytes.");
 138
 139 #ifdef CONFIG_X86
 140 static bool hda_snoop = true;
 141 module_param_named(snoop, hda_snoop, bool, 0444);
 142 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 143 #define azx_snoop(chip)         (chip)->snoop
 144 #else
 145 #define hda_snoop               true
 146 #define azx_snoop(chip)         true
 147 #endif
 148
 149
 150 MODULE_LICENSE("GPL");
 151 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 152                          "{Intel, ICH6M},"
 153                          "{Intel, ICH7},"
 154                          "{Intel, ESB2},"
 155                          "{Intel, ICH8},"
 156                          "{Intel, ICH9},"
 157                          "{Intel, ICH10},"
 158                          "{Intel, PCH},"
 159                          "{Intel, CPT},"
 160                          "{Intel, PPT},"
 161                          "{Intel, LPT},"
 162                          "{Intel, HPT},"
 163                          "{Intel, PBG},"
 164                          "{Intel, SCH},"
 165                          "{ATI, SB450},"
 166                          "{ATI, SB600},"
 167                          "{ATI, RS600},"
 168                          "{ATI, RS690},"
 169                          "{ATI, RS780},"
 170                          "{ATI, R600},"
 171                          "{ATI, RV630},"
 172                          "{ATI, RV610},"
 173                          "{ATI, RV670},"
 174                          "{ATI, RV635},"
 175                          "{ATI, RV620},"
 176                          "{ATI, RV770},"
 177                          "{VIA, VT8251},"
 178                          "{VIA, VT8237A},"
 179                          "{SiS, SIS966},"
 180                          "{ULI, M5461}}");
 181 MODULE_DESCRIPTION("Intel HDA driver");
 182
 183 #ifdef CONFIG_SND_VERBOSE_PRINTK
 184 #define SFX     /* nop */
 185 #else
 186 #define SFX     "hda-intel: "
 187 #endif
 188
 189 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 190 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 191 #define SUPPORT_VGA_SWITCHEROO
 192 #endif
 193 #endif
 194
 195
 196 /*
 197  * registers
 198  */
 199 #define ICH6_REG_GCAP                   0x00
 200 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 201 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 202 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 203 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 204 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 205 #define ICH6_REG_VMIN                   0x02
 206 #define ICH6_REG_VMAJ                   0x03
 207 #define ICH6_REG_OUTPAY                 0x04
 208 #define ICH6_REG_INPAY                  0x06
 209 #define ICH6_REG_GCTL                   0x08
 210 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 211 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 212 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 213 #define ICH6_REG_WAKEEN                 0x0c
 214 #define ICH6_REG_STATESTS               0x0e
 215 #define ICH6_REG_GSTS                   0x10
 216 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 217 #define ICH6_REG_INTCTL                 0x20
 218 #define ICH6_REG_INTSTS                 0x24
 219 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 220 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 221 #define ICH6_REG_SSYNC                  0x38
 222 #define ICH6_REG_CORBLBASE              0x40
 223 #define ICH6_REG_CORBUBASE              0x44
 224 #define ICH6_REG_CORBWP                 0x48
 225 #define ICH6_REG_CORBRP                 0x4a
 226 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 227 #define ICH6_REG_CORBCTL                0x4c
 228 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 229 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 230 #define ICH6_REG_CORBSTS                0x4d
 231 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 232 #define ICH6_REG_CORBSIZE               0x4e
 233
 234 #define ICH6_REG_RIRBLBASE              0x50
 235 #define ICH6_REG_RIRBUBASE              0x54
 236 #define ICH6_REG_RIRBWP                 0x58
 237 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 238 #define ICH6_REG_RINTCNT                0x5a
 239 #define ICH6_REG_RIRBCTL                0x5c
 240 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 241 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 242 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 243 #define ICH6_REG_RIRBSTS                0x5d
 244 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 245 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 246 #define ICH6_REG_RIRBSIZE               0x5e
 247
 248 #define ICH6_REG_IC                     0x60
 249 #define ICH6_REG_IR                     0x64
 250 #define ICH6_REG_IRS                    0x68
 251 #define   ICH6_IRS_VALID        (1<<1)
 252 #define   ICH6_IRS_BUSY         (1<<0)
 253
 254 #define ICH6_REG_DPLBASE                0x70
 255 #define ICH6_REG_DPUBASE                0x74
 256 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 257
 258 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 259 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 260
 261 /* stream register offsets from stream base */
 262 #define ICH6_REG_SD_CTL                 0x00
 263 #define ICH6_REG_SD_STS                 0x03
 264 #define ICH6_REG_SD_LPIB                0x04
 265 #define ICH6_REG_SD_CBL                 0x08
 266 #define ICH6_REG_SD_LVI                 0x0c
 267 #define ICH6_REG_SD_FIFOW               0x0e
 268 #define ICH6_REG_SD_FIFOSIZE            0x10
 269 #define ICH6_REG_SD_FORMAT              0x12
 270 #define ICH6_REG_SD_BDLPL               0x18
 271 #define ICH6_REG_SD_BDLPU               0x1c
 272
 273 /* PCI space */
 274 #define ICH6_PCIREG_TCSEL       0x44
 275
 276 /*
 277  * other constants
 278  */
 279
 280 /* max number of SDs */
 281 /* ICH, ATI and VIA have 4 playback and 4 capture */
 282 #define ICH6_NUM_CAPTURE        4
 283 #define ICH6_NUM_PLAYBACK       4
 284
 285 /* ULI has 6 playback and 5 capture */
 286 #define ULI_NUM_CAPTURE         5
 287 #define ULI_NUM_PLAYBACK        6
 288
 289 /* ATI HDMI has 1 playback and 0 capture */
 290 #define ATIHDMI_NUM_CAPTURE     0
 291 #define ATIHDMI_NUM_PLAYBACK    1
 292
 293 /* TERA has 4 playback and 3 capture */
 294 #define TERA_NUM_CAPTURE        3
 295 #define TERA_NUM_PLAYBACK       4
 296
 297 /* this number is statically defined for simplicity */
 298 #define MAX_AZX_DEV             16
 299
 300 /* max number of fragments - we may use more if allocating more pages for BDL */
 301 #define BDL_SIZE                4096
 302 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 303 #define AZX_MAX_FRAG            32
 304 /* max buffer size - no h/w limit, you can increase as you like */
 305 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 306
 307 /* RIRB int mask: overrun[2], response[0] */
 308 #define RIRB_INT_RESPONSE       0x01
 309 #define RIRB_INT_OVERRUN        0x04
 310 #define RIRB_INT_MASK           0x05
 311
 312 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 313 #define AZX_MAX_CODECS          8
 314 #define AZX_DEFAULT_CODECS      4
 315 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 316
 317 /* SD_CTL bits */
 318 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 319 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 320 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 321 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 322 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 323 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 324 #define SD_CTL_STREAM_TAG_SHIFT 20
 325
 326 /* SD_CTL and SD_STS */
 327 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 328 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 329 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 330 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 331                                  SD_INT_COMPLETE)
 332
 333 /* SD_STS */
 334 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 335
 336 /* INTCTL and INTSTS */
 337 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 338 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 339 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 340
 341 /* below are so far hardcoded - should read registers in future */
 342 #define ICH6_MAX_CORB_ENTRIES   256
 343 #define ICH6_MAX_RIRB_ENTRIES   256
 344
 345 /* position fix mode */
 346 enum {
 347         POS_FIX_AUTO,
 348         POS_FIX_LPIB,
 349         POS_FIX_POSBUF,
 350         POS_FIX_VIACOMBO,
 351         POS_FIX_COMBO,
 352 };
 353
 354 /* Defines for ATI HD Audio support in SB450 south bridge */
 355 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 356 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 357
 358 /* Defines for Nvidia HDA support */
 359 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 360 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 361 #define NVIDIA_HDA_ISTRM_COH          0x4d
 362 #define NVIDIA_HDA_OSTRM_COH          0x4c
 363 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 364
 365 /* Defines for Intel SCH HDA snoop control */
 366 #define INTEL_SCH_HDA_DEVC      0x78
 367 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 368
 369 /* Define IN stream 0 FIFO size offset in VIA controller */
 370 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 371 /* Define VIA HD Audio Device ID*/
 372 #define VIA_HDAC_DEVICE_ID              0x3288
 373
 374 /* HD Audio class code */
 375 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 376
 377 /*
 378  */
 379
 380 struct azx_dev {
 381         struct snd_dma_buffer bdl; /* BDL buffer */
 382         u32 *posbuf;            /* position buffer pointer */
 383
 384         unsigned int bufsize;   /* size of the play buffer in bytes */
 385         unsigned int period_bytes; /* size of the period in bytes */
 386         unsigned int frags;     /* number for period in the play buffer */
 387         unsigned int fifo_size; /* FIFO size */
 388         unsigned long start_wallclk;    /* start + minimum wallclk */
 389         unsigned long period_wallclk;   /* wallclk for period */
 390
 391         void __iomem *sd_addr;  /* stream descriptor pointer */
 392
 393         u32 sd_int_sta_mask;    /* stream int status mask */
 394
 395         /* pcm support */
 396         struct snd_pcm_substream *substream;    /* assigned substream,
 397                                                  * set in PCM open
 398                                                  */
 399         unsigned int format_val;        /* format value to be set in the
 400                                          * controller and the codec
 401                                          */
 402         unsigned char stream_tag;       /* assigned stream */
 403         unsigned char index;            /* stream index */
 404         int assigned_key;               /* last device# key assigned to */
 405
 406         unsigned int opened :1;
 407         unsigned int running :1;
 408         unsigned int irq_pending :1;
 409         /*
 410          * For VIA:
 411          *  A flag to ensure DMA position is 0
 412          *  when link position is not greater than FIFO size
 413          */
 414         unsigned int insufficient :1;
 415         unsigned int wc_marked:1;
 416 };
 417
 418 /* CORB/RIRB */
 419 struct azx_rb {
 420         u32 *buf;               /* CORB/RIRB buffer
 421                                  * Each CORB entry is 4byte, RIRB is 8byte
 422                                  */
 423         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 424         /* for RIRB */
 425         unsigned short rp, wp;  /* read/write pointers */
 426         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 427         u32 res[AZX_MAX_CODECS];        /* last read value */
 428 };
 429
 430 struct azx_pcm {
 431         struct azx *chip;
 432         struct snd_pcm *pcm;
 433         struct hda_codec *codec;
 434         struct hda_pcm_stream *hinfo[2];
 435         struct list_head list;
 436 };
 437
 438 struct azx {
 439         struct snd_card *card;
 440         struct pci_dev *pci;
 441         int dev_index;
 442
 443         /* chip type specific */
 444         int driver_type;
 445         unsigned int driver_caps;
 446         int playback_streams;
 447         int playback_index_offset;
 448         int capture_streams;
 449         int capture_index_offset;
 450         int num_streams;
 451
 452         /* pci resources */
 453         unsigned long addr;
 454         void __iomem *remap_addr;
 455         int irq;
 456
 457         /* locks */
 458         spinlock_t reg_lock;
 459         struct mutex open_mutex;
 460
 461         /* streams (x num_streams) */
 462         struct azx_dev *azx_dev;
 463
 464         /* PCM */
 465         struct list_head pcm_list; /* azx_pcm list */
 466
 467         /* HD codec */
 468         unsigned short codec_mask;
 469         int  codec_probe_mask; /* copied from probe_mask option */
 470         struct hda_bus *bus;
 471         unsigned int beep_mode;
 472
 473         /* CORB/RIRB */
 474         struct azx_rb corb;
 475         struct azx_rb rirb;
 476
 477         /* CORB/RIRB and position buffers */
 478         struct snd_dma_buffer rb;
 479         struct snd_dma_buffer posbuf;
 480
 481 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 482         const struct firmware *fw;
 483 #endif
 484
 485         /* flags */
 486         int position_fix[2]; /* for both playback/capture streams */
 487         int poll_count;
 488         unsigned int running :1;
 489         unsigned int initialized :1;
 490         unsigned int single_cmd :1;
 491         unsigned int polling_mode :1;
 492         unsigned int msi :1;
 493         unsigned int irq_pending_warned :1;
 494         unsigned int probing :1; /* codec probing phase */
 495         unsigned int snoop:1;
 496         unsigned int align_buffer_size:1;
 497         unsigned int region_requested:1;
 498
 499         /* VGA-switcheroo setup */
 500         unsigned int use_vga_switcheroo:1;
 501         unsigned int init_failed:1; /* delayed init failed */
 502         unsigned int disabled:1; /* disabled by VGA-switcher */
 503
 504         /* for debugging */
 505         unsigned int last_cmd[AZX_MAX_CODECS];
 506
 507         /* for pending irqs */
 508         struct work_struct irq_pending_work;
 509
 510         /* reboot notifier (for mysterious hangup problem at power-down) */
 511         struct notifier_block reboot_notifier;
 512
 513         /* card list (for power_save trigger) */
 514         struct list_head list;
 515 };
 516
 517 /* driver types */
 518 enum {
 519         AZX_DRIVER_ICH,
 520         AZX_DRIVER_PCH,
 521         AZX_DRIVER_SCH,
 522         AZX_DRIVER_ATI,
 523         AZX_DRIVER_ATIHDMI,
 524         AZX_DRIVER_ATIHDMI_NS,
 525         AZX_DRIVER_VIA,
 526         AZX_DRIVER_SIS,
 527         AZX_DRIVER_ULI,
 528         AZX_DRIVER_NVIDIA,
 529         AZX_DRIVER_TERA,
 530         AZX_DRIVER_CTX,
 531         AZX_DRIVER_CTHDA,
 532         AZX_DRIVER_GENERIC,
 533         AZX_NUM_DRIVERS, /* keep this as last entry */
 534 };
 535
 536 /* driver quirks (capabilities) */
 537 /* bits 0-7 are used for indicating driver type */
 538 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 539 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 540 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 541 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 542 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 543 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 544 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 545 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 546 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 547 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 548 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 549 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 550 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 551 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 552 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 553 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 554 #define AZX_DCAPS_POSFIX_COMBO  (1 << 24)       /* Use COMBO as default */
 555
 556 /* quirks for ATI SB / AMD Hudson */
 557 #define AZX_DCAPS_PRESET_ATI_SB \
 558         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 559          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 560
 561 /* quirks for ATI/AMD HDMI */
 562 #define AZX_DCAPS_PRESET_ATI_HDMI \
 563         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 564
 565 /* quirks for Nvidia */
 566 #define AZX_DCAPS_PRESET_NVIDIA \
 567         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 568          AZX_DCAPS_ALIGN_BUFSIZE)
 569
 570 #define AZX_DCAPS_PRESET_CTHDA \
 571         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 572
 573 /*
 574  * VGA-switcher support
 575  */
 576 #ifdef SUPPORT_VGA_SWITCHEROO
 577 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 578 #else
 579 #define use_vga_switcheroo(chip)        0
 580 #endif
 581
 582 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
 583 #define DELAYED_INIT_MARK
 584 #define DELAYED_INITDATA_MARK
 585 #else
 586 #define DELAYED_INIT_MARK       __devinit
 587 #define DELAYED_INITDATA_MARK   __devinitdata
 588 #endif
 589
 590 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
 591         [AZX_DRIVER_ICH] = "HDA Intel",
 592         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 593         [AZX_DRIVER_SCH] = "HDA Intel MID",
 594         [AZX_DRIVER_ATI] = "HDA ATI SB",
 595         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 596         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 597         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 598         [AZX_DRIVER_SIS] = "HDA SIS966",
 599         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 600         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 601         [AZX_DRIVER_TERA] = "HDA Teradici",
 602         [AZX_DRIVER_CTX] = "HDA Creative",
 603         [AZX_DRIVER_CTHDA] = "HDA Creative",
 604         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 605 };
 606
 607 /*
 608  * macros for easy use
 609  */
 610 #define azx_writel(chip,reg,value) \
 611         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 612 #define azx_readl(chip,reg) \
 613         readl((chip)->remap_addr + ICH6_REG_##reg)
 614 #define azx_writew(chip,reg,value) \
 615         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 616 #define azx_readw(chip,reg) \
 617         readw((chip)->remap_addr + ICH6_REG_##reg)
 618 #define azx_writeb(chip,reg,value) \
 619         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 620 #define azx_readb(chip,reg) \
 621         readb((chip)->remap_addr + ICH6_REG_##reg)
 622
 623 #define azx_sd_writel(dev,reg,value) \
 624         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 625 #define azx_sd_readl(dev,reg) \
 626         readl((dev)->sd_addr + ICH6_REG_##reg)
 627 #define azx_sd_writew(dev,reg,value) \
 628         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 629 #define azx_sd_readw(dev,reg) \
 630         readw((dev)->sd_addr + ICH6_REG_##reg)
 631 #define azx_sd_writeb(dev,reg,value) \
 632         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 633 #define azx_sd_readb(dev,reg) \
 634         readb((dev)->sd_addr + ICH6_REG_##reg)
 635
 636 /* for pcm support */
 637 #define get_azx_dev(substream) (substream->runtime->private_data)
 638
 639 #ifdef CONFIG_X86
 640 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 641 {
 642         if (azx_snoop(chip))
 643                 return;
 644         if (addr && size) {
 645                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 646                 if (on)
 647                         set_memory_wc((unsigned long)addr, pages);
 648                 else
 649                         set_memory_wb((unsigned long)addr, pages);
 650         }
 651 }
 652
 653 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 654                                  bool on)
 655 {
 656         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 657 }
 658 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 659                                    struct snd_pcm_runtime *runtime, bool on)
 660 {
 661         if (azx_dev->wc_marked != on) {
 662                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 663                 azx_dev->wc_marked = on;
 664         }
 665 }
 666 #else
 667 /* NOP for other archs */
 668 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 669                                  bool on)
 670 {
 671 }
 672 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 673                                    struct snd_pcm_runtime *runtime, bool on)
 674 {
 675 }
 676 #endif
 677
 678 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 679 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 680 /*
 681  * Interface for HD codec
 682  */
 683
 684 /*
 685  * CORB / RIRB interface
 686  */
 687 static int azx_alloc_cmd_io(struct azx *chip)
 688 {
 689         int err;
 690
 691         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 692         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 693                                   snd_dma_pci_data(chip->pci),
 694                                   PAGE_SIZE, &chip->rb);
 695         if (err < 0) {
 696                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 697                 return err;
 698         }
 699         mark_pages_wc(chip, &chip->rb, true);
 700         return 0;
 701 }
 702
 703 static void azx_init_cmd_io(struct azx *chip)
 704 {
 705         spin_lock_irq(&chip->reg_lock);
 706         /* CORB set up */
 707         chip->corb.addr = chip->rb.addr;
 708         chip->corb.buf = (u32 *)chip->rb.area;
 709         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 710         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 711
 712         /* set the corb size to 256 entries (ULI requires explicitly) */
 713         azx_writeb(chip, CORBSIZE, 0x02);
 714         /* set the corb write pointer to 0 */
 715         azx_writew(chip, CORBWP, 0);
 716         /* reset the corb hw read pointer */
 717         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 718         /* enable corb dma */
 719         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 720
 721         /* RIRB set up */
 722         chip->rirb.addr = chip->rb.addr + 2048;
 723         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 724         chip->rirb.wp = chip->rirb.rp = 0;
 725         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 726         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 727         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 728
 729         /* set the rirb size to 256 entries (ULI requires explicitly) */
 730         azx_writeb(chip, RIRBSIZE, 0x02);
 731         /* reset the rirb hw write pointer */
 732         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 733         /* set N=1, get RIRB response interrupt for new entry */
 734         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 735                 azx_writew(chip, RINTCNT, 0xc0);
 736         else
 737                 azx_writew(chip, RINTCNT, 1);
 738         /* enable rirb dma and response irq */
 739         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 740         spin_unlock_irq(&chip->reg_lock);
 741 }
 742
 743 static void azx_free_cmd_io(struct azx *chip)
 744 {
 745         spin_lock_irq(&chip->reg_lock);
 746         /* disable ringbuffer DMAs */
 747         azx_writeb(chip, RIRBCTL, 0);
 748         azx_writeb(chip, CORBCTL, 0);
 749         spin_unlock_irq(&chip->reg_lock);
 750 }
 751
 752 static unsigned int azx_command_addr(u32 cmd)
 753 {
 754         unsigned int addr = cmd >> 28;
 755
 756         if (addr >= AZX_MAX_CODECS) {
 757                 snd_BUG();
 758                 addr = 0;
 759         }
 760
 761         return addr;
 762 }
 763
 764 static unsigned int azx_response_addr(u32 res)
 765 {
 766         unsigned int addr = res & 0xf;
 767
 768         if (addr >= AZX_MAX_CODECS) {
 769                 snd_BUG();
 770                 addr = 0;
 771         }
 772
 773         return addr;
 774 }
 775
 776 /* send a command */
 777 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 778 {
 779         struct azx *chip = bus->private_data;
 780         unsigned int addr = azx_command_addr(val);
 781         unsigned int wp;
 782
 783         spin_lock_irq(&chip->reg_lock);
 784
 785         /* add command to corb */
 786         wp = azx_readb(chip, CORBWP);
 787         wp++;
 788         wp %= ICH6_MAX_CORB_ENTRIES;
 789
 790         chip->rirb.cmds[addr]++;
 791         chip->corb.buf[wp] = cpu_to_le32(val);
 792         azx_writel(chip, CORBWP, wp);
 793
 794         spin_unlock_irq(&chip->reg_lock);
 795
 796         return 0;
 797 }
 798
 799 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 800
 801 /* retrieve RIRB entry - called from interrupt handler */
 802 static void azx_update_rirb(struct azx *chip)
 803 {
 804         unsigned int rp, wp;
 805         unsigned int addr;
 806         u32 res, res_ex;
 807
 808         wp = azx_readb(chip, RIRBWP);
 809         if (wp == chip->rirb.wp)
 810                 return;
 811         chip->rirb.wp = wp;
 812
 813         while (chip->rirb.rp != wp) {
 814                 chip->rirb.rp++;
 815                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 816
 817                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 818                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 819                 res = le32_to_cpu(chip->rirb.buf[rp]);
 820                 addr = azx_response_addr(res_ex);
 821                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 822                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 823                 else if (chip->rirb.cmds[addr]) {
 824                         chip->rirb.res[addr] = res;
 825                         smp_wmb();
 826                         chip->rirb.cmds[addr]--;
 827                 } else
 828                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 829                                    "last cmd=%#08x\n",
 830                                    res, res_ex,
 831                                    chip->last_cmd[addr]);
 832         }
 833 }
 834
 835 /* receive a response */
 836 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 837                                           unsigned int addr)
 838 {
 839         struct azx *chip = bus->private_data;
 840         unsigned long timeout;
 841         unsigned long loopcounter;
 842         int do_poll = 0;
 843
 844  again:
 845         timeout = jiffies + msecs_to_jiffies(1000);
 846
 847         for (loopcounter = 0;; loopcounter++) {
 848                 if (chip->polling_mode || do_poll) {
 849                         spin_lock_irq(&chip->reg_lock);
 850                         azx_update_rirb(chip);
 851                         spin_unlock_irq(&chip->reg_lock);
 852                 }
 853                 if (!chip->rirb.cmds[addr]) {
 854                         smp_rmb();
 855                         bus->rirb_error = 0;
 856
 857                         if (!do_poll)
 858                                 chip->poll_count = 0;
 859                         return chip->rirb.res[addr]; /* the last value */
 860                 }
 861                 if (time_after(jiffies, timeout))
 862                         break;
 863                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 864                         msleep(2); /* temporary workaround */
 865                 else {
 866                         udelay(10);
 867                         cond_resched();
 868                 }
 869         }
 870
 871         if (!chip->polling_mode && chip->poll_count < 2) {
 872                 snd_printdd(SFX "azx_get_response timeout, "
 873                            "polling the codec once: last cmd=0x%08x\n",
 874                            chip->last_cmd[addr]);
 875                 do_poll = 1;
 876                 chip->poll_count++;
 877                 goto again;
 878         }
 879
 880
 881         if (!chip->polling_mode) {
 882                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 883                            "switching to polling mode: last cmd=0x%08x\n",
 884                            chip->last_cmd[addr]);
 885                 chip->polling_mode = 1;
 886                 goto again;
 887         }
 888
 889         if (chip->msi) {
 890                 snd_printk(KERN_WARNING SFX "No response from codec, "
 891                            "disabling MSI: last cmd=0x%08x\n",
 892                            chip->last_cmd[addr]);
 893                 free_irq(chip->irq, chip);
 894                 chip->irq = -1;
 895                 pci_disable_msi(chip->pci);
 896                 chip->msi = 0;
 897                 if (azx_acquire_irq(chip, 1) < 0) {
 898                         bus->rirb_error = 1;
 899                         return -1;
 900                 }
 901                 goto again;
 902         }
 903
 904         if (chip->probing) {
 905                 /* If this critical timeout happens during the codec probing
 906                  * phase, this is likely an access to a non-existing codec
 907                  * slot.  Better to return an error and reset the system.
 908                  */
 909                 return -1;
 910         }
 911
 912         /* a fatal communication error; need either to reset or to fallback
 913          * to the single_cmd mode
 914          */
 915         bus->rirb_error = 1;
 916         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 917                 bus->response_reset = 1;
 918                 return -1; /* give a chance to retry */
 919         }
 920
 921         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 922                    "switching to single_cmd mode: last cmd=0x%08x\n",
 923                    chip->last_cmd[addr]);
 924         chip->single_cmd = 1;
 925         bus->response_reset = 0;
 926         /* release CORB/RIRB */
 927         azx_free_cmd_io(chip);
 928         /* disable unsolicited responses */
 929         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 930         return -1;
 931 }
 932
 933 /*
 934  * Use the single immediate command instead of CORB/RIRB for simplicity
 935  *
 936  * Note: according to Intel, this is not preferred use.  The command was
 937  *       intended for the BIOS only, and may get confused with unsolicited
 938  *       responses.  So, we shouldn't use it for normal operation from the
 939  *       driver.
 940  *       I left the codes, however, for debugging/testing purposes.
 941  */
 942
 943 /* receive a response */
 944 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 945 {
 946         int timeout = 50;
 947
 948         while (timeout--) {
 949                 /* check IRV busy bit */
 950                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 951                         /* reuse rirb.res as the response return value */
 952                         chip->rirb.res[addr] = azx_readl(chip, IR);
 953                         return 0;
 954                 }
 955                 udelay(1);
 956         }
 957         if (printk_ratelimit())
 958                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 959                            azx_readw(chip, IRS));
 960         chip->rirb.res[addr] = -1;
 961         return -EIO;
 962 }
 963
 964 /* send a command */
 965 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 966 {
 967         struct azx *chip = bus->private_data;
 968         unsigned int addr = azx_command_addr(val);
 969         int timeout = 50;
 970
 971         bus->rirb_error = 0;
 972         while (timeout--) {
 973                 /* check ICB busy bit */
 974                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 975                         /* Clear IRV valid bit */
 976                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 977                                    ICH6_IRS_VALID);
 978                         azx_writel(chip, IC, val);
 979                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 980                                    ICH6_IRS_BUSY);
 981                         return azx_single_wait_for_response(chip, addr);
 982                 }
 983                 udelay(1);
 984         }
 985         if (printk_ratelimit())
 986                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 987                            azx_readw(chip, IRS), val);
 988         return -EIO;
 989 }
 990
 991 /* receive a response */
 992 static unsigned int azx_single_get_response(struct hda_bus *bus,
 993                                             unsigned int addr)
 994 {
 995         struct azx *chip = bus->private_data;
 996         return chip->rirb.res[addr];
 997 }
 998
 999 /*
1000  * The below are the main callbacks from hda_codec.
1001  *
1002  * They are just the skeleton to call sub-callbacks according to the
1003  * current setting of chip->single_cmd.
1004  */
1005
1006 /* send a command */
1007 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1008 {
1009         struct azx *chip = bus->private_data;
1010
1011         if (chip->disabled)
1012                 return 0;
1013         chip->last_cmd[azx_command_addr(val)] = val;
1014         if (chip->single_cmd)
1015                 return azx_single_send_cmd(bus, val);
1016         else
1017                 return azx_corb_send_cmd(bus, val);
1018 }
1019
1020 /* get a response */
1021 static unsigned int azx_get_response(struct hda_bus *bus,
1022                                      unsigned int addr)
1023 {
1024         struct azx *chip = bus->private_data;
1025         if (chip->disabled)
1026                 return 0;
1027         if (chip->single_cmd)
1028                 return azx_single_get_response(bus, addr);
1029         else
1030                 return azx_rirb_get_response(bus, addr);
1031 }
1032
1033 #ifdef CONFIG_SND_HDA_POWER_SAVE
1034 static void azx_power_notify(struct hda_bus *bus);
1035 #endif
1036
1037 /* reset codec link */
1038 static int azx_reset(struct azx *chip, int full_reset)
1039 {
1040         int count;
1041
1042         if (!full_reset)
1043                 goto __skip;
1044
1045         /* clear STATESTS */
1046         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1047
1048         /* reset controller */
1049         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1050
1051         count = 50;
1052         while (azx_readb(chip, GCTL) && --count)
1053                 msleep(1);
1054
1055         /* delay for >= 100us for codec PLL to settle per spec
1056          * Rev 0.9 section 5.5.1
1057          */
1058         msleep(1);
1059
1060         /* Bring controller out of reset */
1061         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1062
1063         count = 50;
1064         while (!azx_readb(chip, GCTL) && --count)
1065                 msleep(1);
1066
1067         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1068         msleep(1);
1069
1070       __skip:
1071         /* check to see if controller is ready */
1072         if (!azx_readb(chip, GCTL)) {
1073                 snd_printd(SFX "azx_reset: controller not ready!\n");
1074                 return -EBUSY;
1075         }
1076
1077         /* Accept unsolicited responses */
1078         if (!chip->single_cmd)
1079                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1080                            ICH6_GCTL_UNSOL);
1081
1082         /* detect codecs */
1083         if (!chip->codec_mask) {
1084                 chip->codec_mask = azx_readw(chip, STATESTS);
1085                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1086         }
1087
1088         return 0;
1089 }
1090
1091
1092 /*
1093  * Lowlevel interface
1094  */
1095
1096 /* enable interrupts */
1097 static void azx_int_enable(struct azx *chip)
1098 {
1099         /* enable controller CIE and GIE */
1100         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1101                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1102 }
1103
1104 /* disable interrupts */
1105 static void azx_int_disable(struct azx *chip)
1106 {
1107         int i;
1108
1109         /* disable interrupts in stream descriptor */
1110         for (i = 0; i < chip->num_streams; i++) {
1111                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1112                 azx_sd_writeb(azx_dev, SD_CTL,
1113                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1114         }
1115
1116         /* disable SIE for all streams */
1117         azx_writeb(chip, INTCTL, 0);
1118
1119         /* disable controller CIE and GIE */
1120         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1121                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1122 }
1123
1124 /* clear interrupts */
1125 static void azx_int_clear(struct azx *chip)
1126 {
1127         int i;
1128
1129         /* clear stream status */
1130         for (i = 0; i < chip->num_streams; i++) {
1131                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1132                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1133         }
1134
1135         /* clear STATESTS */
1136         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1137
1138         /* clear rirb status */
1139         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1140
1141         /* clear int status */
1142         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1143 }
1144
1145 /* start a stream */
1146 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1147 {
1148         /*
1149          * Before stream start, initialize parameter
1150          */
1151         azx_dev->insufficient = 1;
1152
1153         /* enable SIE */
1154         azx_writel(chip, INTCTL,
1155                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1156         /* set DMA start and interrupt mask */
1157         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1158                       SD_CTL_DMA_START | SD_INT_MASK);
1159 }
1160
1161 /* stop DMA */
1162 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1163 {
1164         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1165                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1166         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1167 }
1168
1169 /* stop a stream */
1170 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1171 {
1172         azx_stream_clear(chip, azx_dev);
1173         /* disable SIE */
1174         azx_writel(chip, INTCTL,
1175                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1176 }
1177
1178
1179 /*
1180  * reset and start the controller registers
1181  */
1182 static void azx_init_chip(struct azx *chip, int full_reset)
1183 {
1184         if (chip->initialized)
1185                 return;
1186
1187         /* reset controller */
1188         azx_reset(chip, full_reset);
1189
1190         /* initialize interrupts */
1191         azx_int_clear(chip);
1192         azx_int_enable(chip);
1193
1194         /* initialize the codec command I/O */
1195         if (!chip->single_cmd)
1196                 azx_init_cmd_io(chip);
1197
1198         /* program the position buffer */
1199         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1200         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1201
1202         chip->initialized = 1;
1203 }
1204
1205 /*
1206  * initialize the PCI registers
1207  */
1208 /* update bits in a PCI register byte */
1209 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1210                             unsigned char mask, unsigned char val)
1211 {
1212         unsigned char data;
1213
1214         pci_read_config_byte(pci, reg, &data);
1215         data &= ~mask;
1216         data |= (val & mask);
1217         pci_write_config_byte(pci, reg, data);
1218 }
1219
1220 static void azx_init_pci(struct azx *chip)
1221 {
1222         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1223          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1224          * Ensuring these bits are 0 clears playback static on some HD Audio
1225          * codecs.
1226          * The PCI register TCSEL is defined in the Intel manuals.
1227          */
1228         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1229                 snd_printdd(SFX "Clearing TCSEL\n");
1230                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1231         }
1232
1233         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1234          * we need to enable snoop.
1235          */
1236         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1237                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1238                 update_pci_byte(chip->pci,
1239                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1240                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1241         }
1242
1243         /* For NVIDIA HDA, enable snoop */
1244         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1245                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1246                 update_pci_byte(chip->pci,
1247                                 NVIDIA_HDA_TRANSREG_ADDR,
1248                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1249                 update_pci_byte(chip->pci,
1250                                 NVIDIA_HDA_ISTRM_COH,
1251                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1252                 update_pci_byte(chip->pci,
1253                                 NVIDIA_HDA_OSTRM_COH,
1254                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1255         }
1256
1257         /* Enable SCH/PCH snoop if needed */
1258         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1259                 unsigned short snoop;
1260                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1261                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1262                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1263                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1264                         if (!azx_snoop(chip))
1265                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1266                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1267                         pci_read_config_word(chip->pci,
1268                                 INTEL_SCH_HDA_DEVC, &snoop);
1269                 }
1270                 snd_printdd(SFX "SCH snoop: %s\n",
1271                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1272                                 ? "Disabled" : "Enabled");
1273         }
1274 }
1275
1276
1277 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1278
1279 /*
1280  * interrupt handler
1281  */
1282 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1283 {
1284         struct azx *chip = dev_id;
1285         struct azx_dev *azx_dev;
1286         u32 status;
1287         u8 sd_status;
1288         int i, ok;
1289
1290         spin_lock(&chip->reg_lock);
1291
1292         if (chip->disabled) {
1293                 spin_unlock(&chip->reg_lock);
1294                 return IRQ_NONE;
1295         }
1296
1297         status = azx_readl(chip, INTSTS);
1298         if (status == 0) {
1299                 spin_unlock(&chip->reg_lock);
1300                 return IRQ_NONE;
1301         }
1302
1303         for (i = 0; i < chip->num_streams; i++) {
1304                 azx_dev = &chip->azx_dev[i];
1305                 if (status & azx_dev->sd_int_sta_mask) {
1306                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1307                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1308                         if (!azx_dev->substream || !azx_dev->running ||
1309                             !(sd_status & SD_INT_COMPLETE))
1310                                 continue;
1311                         /* check whether this IRQ is really acceptable */
1312                         ok = azx_position_ok(chip, azx_dev);
1313                         if (ok == 1) {
1314                                 azx_dev->irq_pending = 0;
1315                                 spin_unlock(&chip->reg_lock);
1316                                 snd_pcm_period_elapsed(azx_dev->substream);
1317                                 spin_lock(&chip->reg_lock);
1318                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1319                                 /* bogus IRQ, process it later */
1320                                 azx_dev->irq_pending = 1;
1321                                 queue_work(chip->bus->workq,
1322                                            &chip->irq_pending_work);
1323                         }
1324                 }
1325         }
1326
1327         /* clear rirb int */
1328         status = azx_readb(chip, RIRBSTS);
1329         if (status & RIRB_INT_MASK) {
1330                 if (status & RIRB_INT_RESPONSE) {
1331                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1332                                 udelay(80);
1333                         azx_update_rirb(chip);
1334                 }
1335                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1336         }
1337
1338 #if 0
1339         /* clear state status int */
1340         if (azx_readb(chip, STATESTS) & 0x04)
1341                 azx_writeb(chip, STATESTS, 0x04);
1342 #endif
1343         spin_unlock(&chip->reg_lock);
1344
1345         return IRQ_HANDLED;
1346 }
1347
1348
1349 /*
1350  * set up a BDL entry
1351  */
1352 static int setup_bdle(struct azx *chip,
1353                       struct snd_pcm_substream *substream,
1354                       struct azx_dev *azx_dev, u32 **bdlp,
1355                       int ofs, int size, int with_ioc)
1356 {
1357         u32 *bdl = *bdlp;
1358
1359         while (size > 0) {
1360                 dma_addr_t addr;
1361                 int chunk;
1362
1363                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1364                         return -EINVAL;
1365
1366                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1367                 /* program the address field of the BDL entry */
1368                 bdl[0] = cpu_to_le32((u32)addr);
1369                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1370                 /* program the size field of the BDL entry */
1371                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1372                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1373                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1374                         u32 remain = 0x1000 - (ofs & 0xfff);
1375                         if (chunk > remain)
1376                                 chunk = remain;
1377                 }
1378                 bdl[2] = cpu_to_le32(chunk);
1379                 /* program the IOC to enable interrupt
1380                  * only when the whole fragment is processed
1381                  */
1382                 size -= chunk;
1383                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1384                 bdl += 4;
1385                 azx_dev->frags++;
1386                 ofs += chunk;
1387         }
1388         *bdlp = bdl;
1389         return ofs;
1390 }
1391
1392 /*
1393  * set up BDL entries
1394  */
1395 static int azx_setup_periods(struct azx *chip,
1396                              struct snd_pcm_substream *substream,
1397                              struct azx_dev *azx_dev)
1398 {
1399         u32 *bdl;
1400         int i, ofs, periods, period_bytes;
1401         int pos_adj;
1402
1403         /* reset BDL address */
1404         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1405         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1406
1407         period_bytes = azx_dev->period_bytes;
1408         periods = azx_dev->bufsize / period_bytes;
1409
1410         /* program the initial BDL entries */
1411         bdl = (u32 *)azx_dev->bdl.area;
1412         ofs = 0;
1413         azx_dev->frags = 0;
1414         pos_adj = bdl_pos_adj[chip->dev_index];
1415         if (pos_adj > 0) {
1416                 struct snd_pcm_runtime *runtime = substream->runtime;
1417                 int pos_align = pos_adj;
1418                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1419                 if (!pos_adj)
1420                         pos_adj = pos_align;
1421                 else
1422                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1423                                 pos_align;
1424                 pos_adj = frames_to_bytes(runtime, pos_adj);
1425                 if (pos_adj >= period_bytes) {
1426                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1427                                    bdl_pos_adj[chip->dev_index]);
1428                         pos_adj = 0;
1429                 } else {
1430                         ofs = setup_bdle(chip, substream, azx_dev,
1431                                          &bdl, ofs, pos_adj,
1432                                          !substream->runtime->no_period_wakeup);
1433                         if (ofs < 0)
1434                                 goto error;
1435                 }
1436         } else
1437                 pos_adj = 0;
1438         for (i = 0; i < periods; i++) {
1439                 if (i == periods - 1 && pos_adj)
1440                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1441                                          period_bytes - pos_adj, 0);
1442                 else
1443                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1444                                          period_bytes,
1445                                          !substream->runtime->no_period_wakeup);
1446                 if (ofs < 0)
1447                         goto error;
1448         }
1449         return 0;
1450
1451  error:
1452         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1453                    azx_dev->bufsize, period_bytes);
1454         return -EINVAL;
1455 }
1456
1457 /* reset stream */
1458 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1459 {
1460         unsigned char val;
1461         int timeout;
1462
1463         azx_stream_clear(chip, azx_dev);
1464
1465         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1466                       SD_CTL_STREAM_RESET);
1467         udelay(3);
1468         timeout = 300;
1469         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1470                --timeout)
1471                 ;
1472         val &= ~SD_CTL_STREAM_RESET;
1473         azx_sd_writeb(azx_dev, SD_CTL, val);
1474         udelay(3);
1475
1476         timeout = 300;
1477         /* waiting for hardware to report that the stream is out of reset */
1478         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1479                --timeout)
1480                 ;
1481
1482         /* reset first position - may not be synced with hw at this time */
1483         *azx_dev->posbuf = 0;
1484 }
1485
1486 /*
1487  * set up the SD for streaming
1488  */
1489 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1490 {
1491         unsigned int val;
1492         /* make sure the run bit is zero for SD */
1493         azx_stream_clear(chip, azx_dev);
1494         /* program the stream_tag */
1495         val = azx_sd_readl(azx_dev, SD_CTL);
1496         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1497                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1498         if (!azx_snoop(chip))
1499                 val |= SD_CTL_TRAFFIC_PRIO;
1500         azx_sd_writel(azx_dev, SD_CTL, val);
1501
1502         /* program the length of samples in cyclic buffer */
1503         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1504
1505         /* program the stream format */
1506         /* this value needs to be the same as the one programmed */
1507         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1508
1509         /* program the stream LVI (last valid index) of the BDL */
1510         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1511
1512         /* program the BDL address */
1513         /* lower BDL address */
1514         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1515         /* upper BDL address */
1516         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1517
1518         /* enable the position buffer */
1519         if (chip->position_fix[0] != POS_FIX_LPIB ||
1520             chip->position_fix[1] != POS_FIX_LPIB) {
1521                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1522                         azx_writel(chip, DPLBASE,
1523                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1524         }
1525
1526         /* set the interrupt enable bits in the descriptor control register */
1527         azx_sd_writel(azx_dev, SD_CTL,
1528                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1529
1530         return 0;
1531 }
1532
1533 /*
1534  * Probe the given codec address
1535  */
1536 static int probe_codec(struct azx *chip, int addr)
1537 {
1538         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1539                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1540         unsigned int res;
1541
1542         mutex_lock(&chip->bus->cmd_mutex);
1543         chip->probing = 1;
1544         azx_send_cmd(chip->bus, cmd);
1545         res = azx_get_response(chip->bus, addr);
1546         chip->probing = 0;
1547         mutex_unlock(&chip->bus->cmd_mutex);
1548         if (res == -1)
1549                 return -EIO;
1550         snd_printdd(SFX "codec #%d probed OK\n", addr);
1551         return 0;
1552 }
1553
1554 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1555                                  struct hda_pcm *cpcm);
1556 static void azx_stop_chip(struct azx *chip);
1557
1558 static void azx_bus_reset(struct hda_bus *bus)
1559 {
1560         struct azx *chip = bus->private_data;
1561
1562         bus->in_reset = 1;
1563         azx_stop_chip(chip);
1564         azx_init_chip(chip, 1);
1565 #ifdef CONFIG_PM
1566         if (chip->initialized) {
1567                 struct azx_pcm *p;
1568                 list_for_each_entry(p, &chip->pcm_list, list)
1569                         snd_pcm_suspend_all(p->pcm);
1570                 snd_hda_suspend(chip->bus);
1571                 snd_hda_resume(chip->bus);
1572         }
1573 #endif
1574         bus->in_reset = 0;
1575 }
1576
1577 /*
1578  * Codec initialization
1579  */
1580
1581 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1582 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1583         [AZX_DRIVER_NVIDIA] = 8,
1584         [AZX_DRIVER_TERA] = 1,
1585 };
1586
1587 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1588 {
1589         struct hda_bus_template bus_temp;
1590         int c, codecs, err;
1591         int max_slots;
1592
1593         memset(&bus_temp, 0, sizeof(bus_temp));
1594         bus_temp.private_data = chip;
1595         bus_temp.modelname = model;
1596         bus_temp.pci = chip->pci;
1597         bus_temp.ops.command = azx_send_cmd;
1598         bus_temp.ops.get_response = azx_get_response;
1599         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1600         bus_temp.ops.bus_reset = azx_bus_reset;
1601 #ifdef CONFIG_SND_HDA_POWER_SAVE
1602         bus_temp.power_save = &power_save;
1603         bus_temp.ops.pm_notify = azx_power_notify;
1604 #endif
1605
1606         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1607         if (err < 0)
1608                 return err;
1609
1610         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1611                 snd_printd(SFX "Enable delay in RIRB handling\n");
1612                 chip->bus->needs_damn_long_delay = 1;
1613         }
1614
1615         codecs = 0;
1616         max_slots = azx_max_codecs[chip->driver_type];
1617         if (!max_slots)
1618                 max_slots = AZX_DEFAULT_CODECS;
1619
1620         /* First try to probe all given codec slots */
1621         for (c = 0; c < max_slots; c++) {
1622                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1623                         if (probe_codec(chip, c) < 0) {
1624                                 /* Some BIOSen give you wrong codec addresses
1625                                  * that don't exist
1626                                  */
1627                                 snd_printk(KERN_WARNING SFX
1628                                            "Codec #%d probe error; "
1629                                            "disabling it...\n", c);
1630                                 chip->codec_mask &= ~(1 << c);
1631                                 /* More badly, accessing to a non-existing
1632                                  * codec often screws up the controller chip,
1633                                  * and disturbs the further communications.
1634                                  * Thus if an error occurs during probing,
1635                                  * better to reset the controller chip to
1636                                  * get back to the sanity state.
1637                                  */
1638                                 azx_stop_chip(chip);
1639                                 azx_init_chip(chip, 1);
1640                         }
1641                 }
1642         }
1643
1644         /* AMD chipsets often cause the communication stalls upon certain
1645          * sequence like the pin-detection.  It seems that forcing the synced
1646          * access works around the stall.  Grrr...
1647          */
1648         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1649                 snd_printd(SFX "Enable sync_write for stable communication\n");
1650                 chip->bus->sync_write = 1;
1651                 chip->bus->allow_bus_reset = 1;
1652         }
1653
1654         /* Then create codec instances */
1655         for (c = 0; c < max_slots; c++) {
1656                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1657                         struct hda_codec *codec;
1658                         err = snd_hda_codec_new(chip->bus, c, &codec);
1659                         if (err < 0)
1660                                 continue;
1661                         codec->beep_mode = chip->beep_mode;
1662                         codecs++;
1663                 }
1664         }
1665         if (!codecs) {
1666                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1667                 return -ENXIO;
1668         }
1669         return 0;
1670 }
1671
1672 /* configure each codec instance */
1673 static int __devinit azx_codec_configure(struct azx *chip)
1674 {
1675         struct hda_codec *codec;
1676         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1677                 snd_hda_codec_configure(codec);
1678         }
1679         return 0;
1680 }
1681
1682
1683 /*
1684  * PCM support
1685  */
1686
1687 /* assign a stream for the PCM */
1688 static inline struct azx_dev *
1689 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1690 {
1691         int dev, i, nums;
1692         struct azx_dev *res = NULL;
1693         /* make a non-zero unique key for the substream */
1694         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1695                 (substream->stream + 1);
1696
1697         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1698                 dev = chip->playback_index_offset;
1699                 nums = chip->playback_streams;
1700         } else {
1701                 dev = chip->capture_index_offset;
1702                 nums = chip->capture_streams;
1703         }
1704         for (i = 0; i < nums; i++, dev++)
1705                 if (!chip->azx_dev[dev].opened) {
1706                         res = &chip->azx_dev[dev];
1707                         if (res->assigned_key == key)
1708                                 break;
1709                 }
1710         if (res) {
1711                 res->opened = 1;
1712                 res->assigned_key = key;
1713         }
1714         return res;
1715 }
1716
1717 /* release the assigned stream */
1718 static inline void azx_release_device(struct azx_dev *azx_dev)
1719 {
1720         azx_dev->opened = 0;
1721 }
1722
1723 static struct snd_pcm_hardware azx_pcm_hw = {
1724         .info =                 (SNDRV_PCM_INFO_MMAP |
1725                                  SNDRV_PCM_INFO_INTERLEAVED |
1726                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1727                                  SNDRV_PCM_INFO_MMAP_VALID |
1728                                  /* No full-resume yet implemented */
1729                                  /* SNDRV_PCM_INFO_RESUME |*/
1730                                  SNDRV_PCM_INFO_PAUSE |
1731                                  SNDRV_PCM_INFO_SYNC_START |
1732                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1733         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1734         .rates =                SNDRV_PCM_RATE_48000,
1735         .rate_min =             48000,
1736         .rate_max =             48000,
1737         .channels_min =         2,
1738         .channels_max =         2,
1739         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1740         .period_bytes_min =     128,
1741         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1742         .periods_min =          2,
1743         .periods_max =          AZX_MAX_FRAG,
1744         .fifo_size =            0,
1745 };
1746
1747 static int azx_pcm_open(struct snd_pcm_substream *substream)
1748 {
1749         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1750         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1751         struct azx *chip = apcm->chip;
1752         struct azx_dev *azx_dev;
1753         struct snd_pcm_runtime *runtime = substream->runtime;
1754         unsigned long flags;
1755         int err;
1756         int buff_step;
1757
1758         mutex_lock(&chip->open_mutex);
1759         azx_dev = azx_assign_device(chip, substream);
1760         if (azx_dev == NULL) {
1761                 mutex_unlock(&chip->open_mutex);
1762                 return -EBUSY;
1763         }
1764         runtime->hw = azx_pcm_hw;
1765         runtime->hw.channels_min = hinfo->channels_min;
1766         runtime->hw.channels_max = hinfo->channels_max;
1767         runtime->hw.formats = hinfo->formats;
1768         runtime->hw.rates = hinfo->rates;
1769         snd_pcm_limit_hw_rates(runtime);
1770         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1771         if (chip->align_buffer_size)
1772                 /* constrain buffer sizes to be multiple of 128
1773                    bytes. This is more efficient in terms of memory
1774                    access but isn't required by the HDA spec and
1775                    prevents users from specifying exact period/buffer
1776                    sizes. For example for 44.1kHz, a period size set
1777                    to 20ms will be rounded to 19.59ms. */
1778                 buff_step = 128;
1779         else
1780                 /* Don't enforce steps on buffer sizes, still need to
1781                    be multiple of 4 bytes (HDA spec). Tested on Intel
1782                    HDA controllers, may not work on all devices where
1783                    option needs to be disabled */
1784                 buff_step = 4;
1785
1786         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1787                                    buff_step);
1788         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1789                                    buff_step);
1790         snd_hda_power_up_d3wait(apcm->codec);
1791         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1792         if (err < 0) {
1793                 azx_release_device(azx_dev);
1794                 snd_hda_power_down(apcm->codec);
1795                 mutex_unlock(&chip->open_mutex);
1796                 return err;
1797         }
1798         snd_pcm_limit_hw_rates(runtime);
1799         /* sanity check */
1800         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1801             snd_BUG_ON(!runtime->hw.channels_max) ||
1802             snd_BUG_ON(!runtime->hw.formats) ||
1803             snd_BUG_ON(!runtime->hw.rates)) {
1804                 azx_release_device(azx_dev);
1805                 hinfo->ops.close(hinfo, apcm->codec, substream);
1806                 snd_hda_power_down(apcm->codec);
1807                 mutex_unlock(&chip->open_mutex);
1808                 return -EINVAL;
1809         }
1810         spin_lock_irqsave(&chip->reg_lock, flags);
1811         azx_dev->substream = substream;
1812         azx_dev->running = 0;
1813         spin_unlock_irqrestore(&chip->reg_lock, flags);
1814
1815         runtime->private_data = azx_dev;
1816         snd_pcm_set_sync(substream);
1817         mutex_unlock(&chip->open_mutex);
1818         return 0;
1819 }
1820
1821 static int azx_pcm_close(struct snd_pcm_substream *substream)
1822 {
1823         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1824         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1825         struct azx *chip = apcm->chip;
1826         struct azx_dev *azx_dev = get_azx_dev(substream);
1827         unsigned long flags;
1828
1829         mutex_lock(&chip->open_mutex);
1830         spin_lock_irqsave(&chip->reg_lock, flags);
1831         azx_dev->substream = NULL;
1832         azx_dev->running = 0;
1833         spin_unlock_irqrestore(&chip->reg_lock, flags);
1834         azx_release_device(azx_dev);
1835         hinfo->ops.close(hinfo, apcm->codec, substream);
1836         snd_hda_power_down(apcm->codec);
1837         mutex_unlock(&chip->open_mutex);
1838         return 0;
1839 }
1840
1841 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1842                              struct snd_pcm_hw_params *hw_params)
1843 {
1844         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1845         struct azx *chip = apcm->chip;
1846         struct snd_pcm_runtime *runtime = substream->runtime;
1847         struct azx_dev *azx_dev = get_azx_dev(substream);
1848         int ret;
1849
1850         mark_runtime_wc(chip, azx_dev, runtime, false);
1851         azx_dev->bufsize = 0;
1852         azx_dev->period_bytes = 0;
1853         azx_dev->format_val = 0;
1854         ret = snd_pcm_lib_malloc_pages(substream,
1855                                         params_buffer_bytes(hw_params));
1856         if (ret < 0)
1857                 return ret;
1858         mark_runtime_wc(chip, azx_dev, runtime, true);
1859         return ret;
1860 }
1861
1862 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1863 {
1864         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1865         struct azx_dev *azx_dev = get_azx_dev(substream);
1866         struct azx *chip = apcm->chip;
1867         struct snd_pcm_runtime *runtime = substream->runtime;
1868         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1869
1870         /* reset BDL address */
1871         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1872         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1873         azx_sd_writel(azx_dev, SD_CTL, 0);
1874         azx_dev->bufsize = 0;
1875         azx_dev->period_bytes = 0;
1876         azx_dev->format_val = 0;
1877
1878         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1879
1880         mark_runtime_wc(chip, azx_dev, runtime, false);
1881         return snd_pcm_lib_free_pages(substream);
1882 }
1883
1884 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1885 {
1886         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1887         struct azx *chip = apcm->chip;
1888         struct azx_dev *azx_dev = get_azx_dev(substream);
1889         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1890         struct snd_pcm_runtime *runtime = substream->runtime;
1891         unsigned int bufsize, period_bytes, format_val, stream_tag;
1892         int err;
1893         struct hda_spdif_out *spdif =
1894                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1895         unsigned short ctls = spdif ? spdif->ctls : 0;
1896
1897         azx_stream_reset(chip, azx_dev);
1898         format_val = snd_hda_calc_stream_format(runtime->rate,
1899                                                 runtime->channels,
1900                                                 runtime->format,
1901                                                 hinfo->maxbps,
1902                                                 ctls);
1903         if (!format_val) {
1904                 snd_printk(KERN_ERR SFX
1905                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1906                            runtime->rate, runtime->channels, runtime->format);
1907                 return -EINVAL;
1908         }
1909
1910         bufsize = snd_pcm_lib_buffer_bytes(substream);
1911         period_bytes = snd_pcm_lib_period_bytes(substream);
1912
1913         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1914                     bufsize, format_val);
1915
1916         if (bufsize != azx_dev->bufsize ||
1917             period_bytes != azx_dev->period_bytes ||
1918             format_val != azx_dev->format_val) {
1919                 azx_dev->bufsize = bufsize;
1920                 azx_dev->period_bytes = period_bytes;
1921                 azx_dev->format_val = format_val;
1922                 err = azx_setup_periods(chip, substream, azx_dev);
1923                 if (err < 0)
1924                         return err;
1925         }
1926
1927         /* wallclk has 24Mhz clock source */
1928         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1929                                                 runtime->rate) * 1000);
1930         azx_setup_controller(chip, azx_dev);
1931         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1932                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1933         else
1934                 azx_dev->fifo_size = 0;
1935
1936         stream_tag = azx_dev->stream_tag;
1937         /* CA-IBG chips need the playback stream starting from 1 */
1938         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1939             stream_tag > chip->capture_streams)
1940                 stream_tag -= chip->capture_streams;
1941         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1942                                      azx_dev->format_val, substream);
1943 }
1944
1945 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1946 {
1947         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1948         struct azx *chip = apcm->chip;
1949         struct azx_dev *azx_dev;
1950         struct snd_pcm_substream *s;
1951         int rstart = 0, start, nsync = 0, sbits = 0;
1952         int nwait, timeout;
1953
1954         switch (cmd) {
1955         case SNDRV_PCM_TRIGGER_START:
1956                 rstart = 1;
1957         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1958         case SNDRV_PCM_TRIGGER_RESUME:
1959                 start = 1;
1960                 break;
1961         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1962         case SNDRV_PCM_TRIGGER_SUSPEND:
1963         case SNDRV_PCM_TRIGGER_STOP:
1964                 start = 0;
1965                 break;
1966         default:
1967                 return -EINVAL;
1968         }
1969
1970         snd_pcm_group_for_each_entry(s, substream) {
1971                 if (s->pcm->card != substream->pcm->card)
1972                         continue;
1973                 azx_dev = get_azx_dev(s);
1974                 sbits |= 1 << azx_dev->index;
1975                 nsync++;
1976                 snd_pcm_trigger_done(s, substream);
1977         }
1978
1979         spin_lock(&chip->reg_lock);
1980         if (nsync > 1) {
1981                 /* first, set SYNC bits of corresponding streams */
1982                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1983                         azx_writel(chip, OLD_SSYNC,
1984                                    azx_readl(chip, OLD_SSYNC) | sbits);
1985                 else
1986                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1987         }
1988         snd_pcm_group_for_each_entry(s, substream) {
1989                 if (s->pcm->card != substream->pcm->card)
1990                         continue;
1991                 azx_dev = get_azx_dev(s);
1992                 if (start) {
1993                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1994                         if (!rstart)
1995                                 azx_dev->start_wallclk -=
1996                                                 azx_dev->period_wallclk;
1997                         azx_stream_start(chip, azx_dev);
1998                 } else {
1999                         azx_stream_stop(chip, azx_dev);
2000                 }
2001                 azx_dev->running = start;
2002         }
2003         spin_unlock(&chip->reg_lock);
2004         if (start) {
2005                 if (nsync == 1)
2006                         return 0;
2007                 /* wait until all FIFOs get ready */
2008                 for (timeout = 5000; timeout; timeout--) {
2009                         nwait = 0;
2010                         snd_pcm_group_for_each_entry(s, substream) {
2011                                 if (s->pcm->card != substream->pcm->card)
2012                                         continue;
2013                                 azx_dev = get_azx_dev(s);
2014                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2015                                       SD_STS_FIFO_READY))
2016                                         nwait++;
2017                         }
2018                         if (!nwait)
2019                                 break;
2020                         cpu_relax();
2021                 }
2022         } else {
2023                 /* wait until all RUN bits are cleared */
2024                 for (timeout = 5000; timeout; timeout--) {
2025                         nwait = 0;
2026                         snd_pcm_group_for_each_entry(s, substream) {
2027                                 if (s->pcm->card != substream->pcm->card)
2028                                         continue;
2029                                 azx_dev = get_azx_dev(s);
2030                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2031                                     SD_CTL_DMA_START)
2032                                         nwait++;
2033                         }
2034                         if (!nwait)
2035                                 break;
2036                         cpu_relax();
2037                 }
2038         }
2039         if (nsync > 1) {
2040                 spin_lock(&chip->reg_lock);
2041                 /* reset SYNC bits */
2042                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2043                         azx_writel(chip, OLD_SSYNC,
2044                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
2045                 else
2046                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2047                 spin_unlock(&chip->reg_lock);
2048         }
2049         return 0;
2050 }
2051
2052 /* get the current DMA position with correction on VIA chips */
2053 static unsigned int azx_via_get_position(struct azx *chip,
2054                                          struct azx_dev *azx_dev)
2055 {
2056         unsigned int link_pos, mini_pos, bound_pos;
2057         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2058         unsigned int fifo_size;
2059
2060         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2061         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2062                 /* Playback, no problem using link position */
2063                 return link_pos;
2064         }
2065
2066         /* Capture */
2067         /* For new chipset,
2068          * use mod to get the DMA position just like old chipset
2069          */
2070         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2071         mod_dma_pos %= azx_dev->period_bytes;
2072
2073         /* azx_dev->fifo_size can't get FIFO size of in stream.
2074          * Get from base address + offset.
2075          */
2076         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2077
2078         if (azx_dev->insufficient) {
2079                 /* Link position never gather than FIFO size */
2080                 if (link_pos <= fifo_size)
2081                         return 0;
2082
2083                 azx_dev->insufficient = 0;
2084         }
2085
2086         if (link_pos <= fifo_size)
2087                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2088         else
2089                 mini_pos = link_pos - fifo_size;
2090
2091         /* Find nearest previous boudary */
2092         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2093         mod_link_pos = link_pos % azx_dev->period_bytes;
2094         if (mod_link_pos >= fifo_size)
2095                 bound_pos = link_pos - mod_link_pos;
2096         else if (mod_dma_pos >= mod_mini_pos)
2097                 bound_pos = mini_pos - mod_mini_pos;
2098         else {
2099                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2100                 if (bound_pos >= azx_dev->bufsize)
2101                         bound_pos = 0;
2102         }
2103
2104         /* Calculate real DMA position we want */
2105         return bound_pos + mod_dma_pos;
2106 }
2107
2108 static unsigned int azx_get_position(struct azx *chip,
2109                                      struct azx_dev *azx_dev,
2110                                      bool with_check)
2111 {
2112         unsigned int pos;
2113         int stream = azx_dev->substream->stream;
2114
2115         switch (chip->position_fix[stream]) {
2116         case POS_FIX_LPIB:
2117                 /* read LPIB */
2118                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2119                 break;
2120         case POS_FIX_VIACOMBO:
2121                 pos = azx_via_get_position(chip, azx_dev);
2122                 break;
2123         default:
2124                 /* use the position buffer */
2125                 pos = le32_to_cpu(*azx_dev->posbuf);
2126                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2127                         if (!pos || pos == (u32)-1) {
2128                                 printk(KERN_WARNING
2129                                        "hda-intel: Invalid position buffer, "
2130                                        "using LPIB read method instead.\n");
2131                                 chip->position_fix[stream] = POS_FIX_LPIB;
2132                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2133                         } else
2134                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2135                 }
2136                 break;
2137         }
2138
2139         if (pos >= azx_dev->bufsize)
2140                 pos = 0;
2141         return pos;
2142 }
2143
2144 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2145 {
2146         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2147         struct azx *chip = apcm->chip;
2148         struct azx_dev *azx_dev = get_azx_dev(substream);
2149         return bytes_to_frames(substream->runtime,
2150                                azx_get_position(chip, azx_dev, false));
2151 }
2152
2153 /*
2154  * Check whether the current DMA position is acceptable for updating
2155  * periods.  Returns non-zero if it's OK.
2156  *
2157  * Many HD-audio controllers appear pretty inaccurate about
2158  * the update-IRQ timing.  The IRQ is issued before actually the
2159  * data is processed.  So, we need to process it afterwords in a
2160  * workqueue.
2161  */
2162 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2163 {
2164         u32 wallclk;
2165         unsigned int pos;
2166         int stream;
2167
2168         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2169         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2170                 return -1;      /* bogus (too early) interrupt */
2171
2172         stream = azx_dev->substream->stream;
2173         pos = azx_get_position(chip, azx_dev, true);
2174
2175         if (WARN_ONCE(!azx_dev->period_bytes,
2176                       "hda-intel: zero azx_dev->period_bytes"))
2177                 return -1; /* this shouldn't happen! */
2178         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2179             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2180                 /* NG - it's below the first next period boundary */
2181                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2182         azx_dev->start_wallclk += wallclk;
2183         return 1; /* OK, it's fine */
2184 }
2185
2186 /*
2187  * The work for pending PCM period updates.
2188  */
2189 static void azx_irq_pending_work(struct work_struct *work)
2190 {
2191         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2192         int i, pending, ok;
2193
2194         if (!chip->irq_pending_warned) {
2195                 printk(KERN_WARNING
2196                        "hda-intel: IRQ timing workaround is activated "
2197                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2198                        chip->card->number);
2199                 chip->irq_pending_warned = 1;
2200         }
2201
2202         for (;;) {
2203                 pending = 0;
2204                 spin_lock_irq(&chip->reg_lock);
2205                 for (i = 0; i < chip->num_streams; i++) {
2206                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2207                         if (!azx_dev->irq_pending ||
2208                             !azx_dev->substream ||
2209                             !azx_dev->running)
2210                                 continue;
2211                         ok = azx_position_ok(chip, azx_dev);
2212                         if (ok > 0) {
2213                                 azx_dev->irq_pending = 0;
2214                                 spin_unlock(&chip->reg_lock);
2215                                 snd_pcm_period_elapsed(azx_dev->substream);
2216                                 spin_lock(&chip->reg_lock);
2217                         } else if (ok < 0) {
2218                                 pending = 0;    /* too early */
2219                         } else
2220                                 pending++;
2221                 }
2222                 spin_unlock_irq(&chip->reg_lock);
2223                 if (!pending)
2224                         return;
2225                 msleep(1);
2226         }
2227 }
2228
2229 /* clear irq_pending flags and assure no on-going workq */
2230 static void azx_clear_irq_pending(struct azx *chip)
2231 {
2232         int i;
2233
2234         spin_lock_irq(&chip->reg_lock);
2235         for (i = 0; i < chip->num_streams; i++)
2236                 chip->azx_dev[i].irq_pending = 0;
2237         spin_unlock_irq(&chip->reg_lock);
2238 }
2239
2240 #ifdef CONFIG_X86
2241 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2242                         struct vm_area_struct *area)
2243 {
2244         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2245         struct azx *chip = apcm->chip;
2246         if (!azx_snoop(chip))
2247                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2248         return snd_pcm_lib_default_mmap(substream, area);
2249 }
2250 #else
2251 #define azx_pcm_mmap    NULL
2252 #endif
2253
2254 static struct snd_pcm_ops azx_pcm_ops = {
2255         .open = azx_pcm_open,
2256         .close = azx_pcm_close,
2257         .ioctl = snd_pcm_lib_ioctl,
2258         .hw_params = azx_pcm_hw_params,
2259         .hw_free = azx_pcm_hw_free,
2260         .prepare = azx_pcm_prepare,
2261         .trigger = azx_pcm_trigger,
2262         .pointer = azx_pcm_pointer,
2263         .mmap = azx_pcm_mmap,
2264         .page = snd_pcm_sgbuf_ops_page,
2265 };
2266
2267 static void azx_pcm_free(struct snd_pcm *pcm)
2268 {
2269         struct azx_pcm *apcm = pcm->private_data;
2270         if (apcm) {
2271                 list_del(&apcm->list);
2272                 kfree(apcm);
2273         }
2274 }
2275
2276 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2277
2278 static int
2279 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2280                       struct hda_pcm *cpcm)
2281 {
2282         struct azx *chip = bus->private_data;
2283         struct snd_pcm *pcm;
2284         struct azx_pcm *apcm;
2285         int pcm_dev = cpcm->device;
2286         unsigned int size;
2287         int s, err;
2288
2289         list_for_each_entry(apcm, &chip->pcm_list, list) {
2290                 if (apcm->pcm->device == pcm_dev) {
2291                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2292                         return -EBUSY;
2293                 }
2294         }
2295         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2296                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2297                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2298                           &pcm);
2299         if (err < 0)
2300                 return err;
2301         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2302         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2303         if (apcm == NULL)
2304                 return -ENOMEM;
2305         apcm->chip = chip;
2306         apcm->pcm = pcm;
2307         apcm->codec = codec;
2308         pcm->private_data = apcm;
2309         pcm->private_free = azx_pcm_free;
2310         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2311                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2312         list_add_tail(&apcm->list, &chip->pcm_list);
2313         cpcm->pcm = pcm;
2314         for (s = 0; s < 2; s++) {
2315                 apcm->hinfo[s] = &cpcm->stream[s];
2316                 if (cpcm->stream[s].substreams)
2317                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2318         }
2319         /* buffer pre-allocation */
2320         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2321         if (size > MAX_PREALLOC_SIZE)
2322                 size = MAX_PREALLOC_SIZE;
2323         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2324                                               snd_dma_pci_data(chip->pci),
2325                                               size, MAX_PREALLOC_SIZE);
2326         return 0;
2327 }
2328
2329 /*
2330  * mixer creation - all stuff is implemented in hda module
2331  */
2332 static int __devinit azx_mixer_create(struct azx *chip)
2333 {
2334         return snd_hda_build_controls(chip->bus);
2335 }
2336
2337
2338 /*
2339  * initialize SD streams
2340  */
2341 static int __devinit azx_init_stream(struct azx *chip)
2342 {
2343         int i;
2344
2345         /* initialize each stream (aka device)
2346          * assign the starting bdl address to each stream (device)
2347          * and initialize
2348          */
2349         for (i = 0; i < chip->num_streams; i++) {
2350                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2351                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2352                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2353                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2354                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2355                 azx_dev->sd_int_sta_mask = 1 << i;
2356                 /* stream tag: must be non-zero and unique */
2357                 azx_dev->index = i;
2358                 azx_dev->stream_tag = i + 1;
2359         }
2360
2361         return 0;
2362 }
2363
2364 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2365 {
2366         if (request_irq(chip->pci->irq, azx_interrupt,
2367                         chip->msi ? 0 : IRQF_SHARED,
2368                         KBUILD_MODNAME, chip)) {
2369                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2370                        "disabling device\n", chip->pci->irq);
2371                 if (do_disconnect)
2372                         snd_card_disconnect(chip->card);
2373                 return -1;
2374         }
2375         chip->irq = chip->pci->irq;
2376         pci_intx(chip->pci, !chip->msi);
2377         return 0;
2378 }
2379
2380
2381 static void azx_stop_chip(struct azx *chip)
2382 {
2383         if (!chip->initialized)
2384                 return;
2385
2386         /* disable interrupts */
2387         azx_int_disable(chip);
2388         azx_int_clear(chip);
2389
2390         /* disable CORB/RIRB */
2391         azx_free_cmd_io(chip);
2392
2393         /* disable position buffer */
2394         azx_writel(chip, DPLBASE, 0);
2395         azx_writel(chip, DPUBASE, 0);
2396
2397         chip->initialized = 0;
2398 }
2399
2400 #ifdef CONFIG_SND_HDA_POWER_SAVE
2401 /* power-up/down the controller */
2402 static void azx_power_notify(struct hda_bus *bus)
2403 {
2404         struct azx *chip = bus->private_data;
2405         struct hda_codec *c;
2406         int power_on = 0;
2407
2408         list_for_each_entry(c, &bus->codec_list, list) {
2409                 if (c->power_on) {
2410                         power_on = 1;
2411                         break;
2412                 }
2413         }
2414         if (power_on)
2415                 azx_init_chip(chip, 1);
2416         else if (chip->running && power_save_controller &&
2417                  !bus->power_keep_link_on)
2418                 azx_stop_chip(chip);
2419 }
2420
2421 static DEFINE_MUTEX(card_list_lock);
2422 static LIST_HEAD(card_list);
2423
2424 static void azx_add_card_list(struct azx *chip)
2425 {
2426         mutex_lock(&card_list_lock);
2427         list_add(&chip->list, &card_list);
2428         mutex_unlock(&card_list_lock);
2429 }
2430
2431 static void azx_del_card_list(struct azx *chip)
2432 {
2433         mutex_lock(&card_list_lock);
2434         list_del_init(&chip->list);
2435         mutex_unlock(&card_list_lock);
2436 }
2437
2438 /* trigger power-save check at writing parameter */
2439 static int param_set_xint(const char *val, const struct kernel_param *kp)
2440 {
2441         struct azx *chip;
2442         struct hda_codec *c;
2443         int prev = power_save;
2444         int ret = param_set_int(val, kp);
2445
2446         if (ret || prev == power_save)
2447                 return ret;
2448
2449         mutex_lock(&card_list_lock);
2450         list_for_each_entry(chip, &card_list, list) {
2451                 if (!chip->bus || chip->disabled)
2452                         continue;
2453                 list_for_each_entry(c, &chip->bus->codec_list, list)
2454                         snd_hda_power_sync(c);
2455         }
2456         mutex_unlock(&card_list_lock);
2457         return 0;
2458 }
2459 #else
2460 #define azx_add_card_list(chip) /* NOP */
2461 #define azx_del_card_list(chip) /* NOP */
2462 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2463
2464 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2465 /*
2466  * power management
2467  */
2468 static int azx_suspend(struct device *dev)
2469 {
2470         struct pci_dev *pci = to_pci_dev(dev);
2471         struct snd_card *card = dev_get_drvdata(dev);
2472         struct azx *chip = card->private_data;
2473         struct azx_pcm *p;
2474
2475         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2476         azx_clear_irq_pending(chip);
2477         list_for_each_entry(p, &chip->pcm_list, list)
2478                 snd_pcm_suspend_all(p->pcm);
2479         if (chip->initialized)
2480                 snd_hda_suspend(chip->bus);
2481         azx_stop_chip(chip);
2482         if (chip->irq >= 0) {
2483                 free_irq(chip->irq, chip);
2484                 chip->irq = -1;
2485         }
2486         if (chip->msi)
2487                 pci_disable_msi(chip->pci);
2488         pci_disable_device(pci);
2489         pci_save_state(pci);
2490         pci_set_power_state(pci, PCI_D3hot);
2491         return 0;
2492 }
2493
2494 static int azx_resume(struct device *dev)
2495 {
2496         struct pci_dev *pci = to_pci_dev(dev);
2497         struct snd_card *card = dev_get_drvdata(dev);
2498         struct azx *chip = card->private_data;
2499
2500         pci_set_power_state(pci, PCI_D0);
2501         pci_restore_state(pci);
2502         if (pci_enable_device(pci) < 0) {
2503                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2504                        "disabling device\n");
2505                 snd_card_disconnect(card);
2506                 return -EIO;
2507         }
2508         pci_set_master(pci);
2509         if (chip->msi)
2510                 if (pci_enable_msi(pci) < 0)
2511                         chip->msi = 0;
2512         if (azx_acquire_irq(chip, 1) < 0)
2513                 return -EIO;
2514         azx_init_pci(chip);
2515
2516         azx_init_chip(chip, 1);
2517
2518         snd_hda_resume(chip->bus);
2519         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2520         return 0;
2521 }
2522 static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2523 #define AZX_PM_OPS      &azx_pm
2524 #else
2525 #define AZX_PM_OPS      NULL
2526 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2527
2528
2529 /*
2530  * reboot notifier for hang-up problem at power-down
2531  */
2532 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2533 {
2534         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2535         snd_hda_bus_reboot_notify(chip->bus);
2536         azx_stop_chip(chip);
2537         return NOTIFY_OK;
2538 }
2539
2540 static void azx_notifier_register(struct azx *chip)
2541 {
2542         chip->reboot_notifier.notifier_call = azx_halt;
2543         register_reboot_notifier(&chip->reboot_notifier);
2544 }
2545
2546 static void azx_notifier_unregister(struct azx *chip)
2547 {
2548         if (chip->reboot_notifier.notifier_call)
2549                 unregister_reboot_notifier(&chip->reboot_notifier);
2550 }
2551
2552 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2553 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2554
2555 #ifdef SUPPORT_VGA_SWITCHEROO
2556 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2557
2558 static void azx_vs_set_state(struct pci_dev *pci,
2559                              enum vga_switcheroo_state state)
2560 {
2561         struct snd_card *card = pci_get_drvdata(pci);
2562         struct azx *chip = card->private_data;
2563         bool disabled;
2564
2565         if (chip->init_failed)
2566                 return;
2567
2568         disabled = (state == VGA_SWITCHEROO_OFF);
2569         if (chip->disabled == disabled)
2570                 return;
2571
2572         if (!chip->bus) {
2573                 chip->disabled = disabled;
2574                 if (!disabled) {
2575                         snd_printk(KERN_INFO SFX
2576                                    "%s: Start delayed initialization\n",
2577                                    pci_name(chip->pci));
2578                         if (azx_first_init(chip) < 0 ||
2579                             azx_probe_continue(chip) < 0) {
2580                                 snd_printk(KERN_ERR SFX
2581                                            "%s: initialization error\n",
2582                                            pci_name(chip->pci));
2583                                 chip->init_failed = true;
2584                         }
2585                 }
2586         } else {
2587                 snd_printk(KERN_INFO SFX
2588                            "%s %s via VGA-switcheroo\n",
2589                            disabled ? "Disabling" : "Enabling",
2590                            pci_name(chip->pci));
2591                 if (disabled) {
2592                         azx_suspend(&pci->dev);
2593                         chip->disabled = true;
2594                         snd_hda_lock_devices(chip->bus);
2595                 } else {
2596                         snd_hda_unlock_devices(chip->bus);
2597                         chip->disabled = false;
2598                         azx_resume(&pci->dev);
2599                 }
2600         }
2601 }
2602
2603 static bool azx_vs_can_switch(struct pci_dev *pci)
2604 {
2605         struct snd_card *card = pci_get_drvdata(pci);
2606         struct azx *chip = card->private_data;
2607
2608         if (chip->init_failed)
2609                 return false;
2610         if (chip->disabled || !chip->bus)
2611                 return true;
2612         if (snd_hda_lock_devices(chip->bus))
2613                 return false;
2614         snd_hda_unlock_devices(chip->bus);
2615         return true;
2616 }
2617
2618 static void __devinit init_vga_switcheroo(struct azx *chip)
2619 {
2620         struct pci_dev *p = get_bound_vga(chip->pci);
2621         if (p) {
2622                 snd_printk(KERN_INFO SFX
2623                            "%s: Handle VGA-switcheroo audio client\n",
2624                            pci_name(chip->pci));
2625                 chip->use_vga_switcheroo = 1;
2626                 pci_dev_put(p);
2627         }
2628 }
2629
2630 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2631         .set_gpu_state = azx_vs_set_state,
2632         .can_switch = azx_vs_can_switch,
2633 };
2634
2635 static int __devinit register_vga_switcheroo(struct azx *chip)
2636 {
2637         if (!chip->use_vga_switcheroo)
2638                 return 0;
2639         /* FIXME: currently only handling DIS controller
2640          * is there any machine with two switchable HDMI audio controllers?
2641          */
2642         return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2643                                                     VGA_SWITCHEROO_DIS,
2644                                                     chip->bus != NULL);
2645 }
2646 #else
2647 #define init_vga_switcheroo(chip)               /* NOP */
2648 #define register_vga_switcheroo(chip)           0
2649 #define check_hdmi_disabled(pci)        false
2650 #endif /* SUPPORT_VGA_SWITCHER */
2651
2652 /*
2653  * destructor
2654  */
2655 static int azx_free(struct azx *chip)
2656 {
2657         int i;
2658
2659         azx_del_card_list(chip);
2660
2661         azx_notifier_unregister(chip);
2662
2663         if (use_vga_switcheroo(chip)) {
2664                 if (chip->disabled && chip->bus)
2665                         snd_hda_unlock_devices(chip->bus);
2666                 vga_switcheroo_unregister_client(chip->pci);
2667         }
2668
2669         if (chip->initialized) {
2670                 azx_clear_irq_pending(chip);
2671                 for (i = 0; i < chip->num_streams; i++)
2672                         azx_stream_stop(chip, &chip->azx_dev[i]);
2673                 azx_stop_chip(chip);
2674         }
2675
2676         if (chip->irq >= 0)
2677                 free_irq(chip->irq, (void*)chip);
2678         if (chip->msi)
2679                 pci_disable_msi(chip->pci);
2680         if (chip->remap_addr)
2681                 iounmap(chip->remap_addr);
2682
2683         if (chip->azx_dev) {
2684                 for (i = 0; i < chip->num_streams; i++)
2685                         if (chip->azx_dev[i].bdl.area) {
2686                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2687                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2688                         }
2689         }
2690         if (chip->rb.area) {
2691                 mark_pages_wc(chip, &chip->rb, false);
2692                 snd_dma_free_pages(&chip->rb);
2693         }
2694         if (chip->posbuf.area) {
2695                 mark_pages_wc(chip, &chip->posbuf, false);
2696                 snd_dma_free_pages(&chip->posbuf);
2697         }
2698         if (chip->region_requested)
2699                 pci_release_regions(chip->pci);
2700         pci_disable_device(chip->pci);
2701         kfree(chip->azx_dev);
2702 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2703         if (chip->fw)
2704                 release_firmware(chip->fw);
2705 #endif
2706         kfree(chip);
2707
2708         return 0;
2709 }
2710
2711 static int azx_dev_free(struct snd_device *device)
2712 {
2713         return azx_free(device->device_data);
2714 }
2715
2716 #ifdef SUPPORT_VGA_SWITCHEROO
2717 /*
2718  * Check of disabled HDMI controller by vga-switcheroo
2719  */
2720 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2721 {
2722         struct pci_dev *p;
2723
2724         /* check only discrete GPU */
2725         switch (pci->vendor) {
2726         case PCI_VENDOR_ID_ATI:
2727         case PCI_VENDOR_ID_AMD:
2728         case PCI_VENDOR_ID_NVIDIA:
2729                 if (pci->devfn == 1) {
2730                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2731                                                         pci->bus->number, 0);
2732                         if (p) {
2733                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2734                                         return p;
2735                                 pci_dev_put(p);
2736                         }
2737                 }
2738                 break;
2739         }
2740         return NULL;
2741 }
2742
2743 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2744 {
2745         bool vga_inactive = false;
2746         struct pci_dev *p = get_bound_vga(pci);
2747
2748         if (p) {
2749                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2750                         vga_inactive = true;
2751                 pci_dev_put(p);
2752         }
2753         return vga_inactive;
2754 }
2755 #endif /* SUPPORT_VGA_SWITCHEROO */
2756
2757 /*
2758  * white/black-listing for position_fix
2759  */
2760 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2761         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2762         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2763         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2764         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2765         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2766         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2767         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2768         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2769         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2770         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2771         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2772         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2773         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2774         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2775         {}
2776 };
2777
2778 static int __devinit check_position_fix(struct azx *chip, int fix)
2779 {
2780         const struct snd_pci_quirk *q;
2781
2782         switch (fix) {
2783         case POS_FIX_LPIB:
2784         case POS_FIX_POSBUF:
2785         case POS_FIX_VIACOMBO:
2786         case POS_FIX_COMBO:
2787                 return fix;
2788         }
2789
2790         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2791         if (q) {
2792                 printk(KERN_INFO
2793                        "hda_intel: position_fix set to %d "
2794                        "for device %04x:%04x\n",
2795                        q->value, q->subvendor, q->subdevice);
2796                 return q->value;
2797         }
2798
2799         /* Check VIA/ATI HD Audio Controller exist */
2800         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2801                 snd_printd(SFX "Using VIACOMBO position fix\n");
2802                 return POS_FIX_VIACOMBO;
2803         }
2804         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2805                 snd_printd(SFX "Using LPIB position fix\n");
2806                 return POS_FIX_LPIB;
2807         }
2808         if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2809                 snd_printd(SFX "Using COMBO position fix\n");
2810                 return POS_FIX_COMBO;
2811         }
2812         return POS_FIX_AUTO;
2813 }
2814
2815 /*
2816  * black-lists for probe_mask
2817  */
2818 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2819         /* Thinkpad often breaks the controller communication when accessing
2820          * to the non-working (or non-existing) modem codec slot.
2821          */
2822         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2823         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2824         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2825         /* broken BIOS */
2826         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2827         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2828         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2829         /* forced codec slots */
2830         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2831         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2832         /* WinFast VP200 H (Teradici) user reported broken communication */
2833         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2834         {}
2835 };
2836
2837 #define AZX_FORCE_CODEC_MASK    0x100
2838
2839 static void __devinit check_probe_mask(struct azx *chip, int dev)
2840 {
2841         const struct snd_pci_quirk *q;
2842
2843         chip->codec_probe_mask = probe_mask[dev];
2844         if (chip->codec_probe_mask == -1) {
2845                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2846                 if (q) {
2847                         printk(KERN_INFO
2848                                "hda_intel: probe_mask set to 0x%x "
2849                                "for device %04x:%04x\n",
2850                                q->value, q->subvendor, q->subdevice);
2851                         chip->codec_probe_mask = q->value;
2852                 }
2853         }
2854
2855         /* check forced option */
2856         if (chip->codec_probe_mask != -1 &&
2857             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2858                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2859                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2860                        chip->codec_mask);
2861         }
2862 }
2863
2864 /*
2865  * white/black-list for enable_msi
2866  */
2867 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2868         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2869         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2870         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2871         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2872         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2873         {}
2874 };
2875
2876 static void __devinit check_msi(struct azx *chip)
2877 {
2878         const struct snd_pci_quirk *q;
2879
2880         if (enable_msi >= 0) {
2881                 chip->msi = !!enable_msi;
2882                 return;
2883         }
2884         chip->msi = 1;  /* enable MSI as default */
2885         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2886         if (q) {
2887                 printk(KERN_INFO
2888                        "hda_intel: msi for device %04x:%04x set to %d\n",
2889                        q->subvendor, q->subdevice, q->value);
2890                 chip->msi = q->value;
2891                 return;
2892         }
2893
2894         /* NVidia chipsets seem to cause troubles with MSI */
2895         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2896                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2897                 chip->msi = 0;
2898         }
2899 }
2900
2901 /* check the snoop mode availability */
2902 static void __devinit azx_check_snoop_available(struct azx *chip)
2903 {
2904         bool snoop = chip->snoop;
2905
2906         switch (chip->driver_type) {
2907         case AZX_DRIVER_VIA:
2908                 /* force to non-snoop mode for a new VIA controller
2909                  * when BIOS is set
2910                  */
2911                 if (snoop) {
2912                         u8 val;
2913                         pci_read_config_byte(chip->pci, 0x42, &val);
2914                         if (!(val & 0x80) && chip->pci->revision == 0x30)
2915                                 snoop = false;
2916                 }
2917                 break;
2918         case AZX_DRIVER_ATIHDMI_NS:
2919                 /* new ATI HDMI requires non-snoop */
2920                 snoop = false;
2921                 break;
2922         }
2923
2924         if (snoop != chip->snoop) {
2925                 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2926                            snoop ? "snoop" : "non-snoop");
2927                 chip->snoop = snoop;
2928         }
2929 }
2930
2931 /*
2932  * constructor
2933  */
2934 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2935                                 int dev, unsigned int driver_caps,
2936                                 struct azx **rchip)
2937 {
2938         static struct snd_device_ops ops = {
2939                 .dev_free = azx_dev_free,
2940         };
2941         struct azx *chip;
2942         int err;
2943
2944         *rchip = NULL;
2945
2946         err = pci_enable_device(pci);
2947         if (err < 0)
2948                 return err;
2949
2950         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2951         if (!chip) {
2952                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2953                 pci_disable_device(pci);
2954                 return -ENOMEM;
2955         }
2956
2957         spin_lock_init(&chip->reg_lock);
2958         mutex_init(&chip->open_mutex);
2959         chip->card = card;
2960         chip->pci = pci;
2961         chip->irq = -1;
2962         chip->driver_caps = driver_caps;
2963         chip->driver_type = driver_caps & 0xff;
2964         check_msi(chip);
2965         chip->dev_index = dev;
2966         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2967         INIT_LIST_HEAD(&chip->pcm_list);
2968         INIT_LIST_HEAD(&chip->list);
2969         init_vga_switcheroo(chip);
2970
2971         chip->position_fix[0] = chip->position_fix[1] =
2972                 check_position_fix(chip, position_fix[dev]);
2973         /* combo mode uses LPIB for playback */
2974         if (chip->position_fix[0] == POS_FIX_COMBO) {
2975                 chip->position_fix[0] = POS_FIX_LPIB;
2976                 chip->position_fix[1] = POS_FIX_AUTO;
2977         }
2978
2979         check_probe_mask(chip, dev);
2980
2981         chip->single_cmd = single_cmd;
2982         chip->snoop = hda_snoop;
2983         azx_check_snoop_available(chip);
2984
2985         if (bdl_pos_adj[dev] < 0) {
2986                 switch (chip->driver_type) {
2987                 case AZX_DRIVER_ICH:
2988                 case AZX_DRIVER_PCH:
2989                         bdl_pos_adj[dev] = 1;
2990                         break;
2991                 default:
2992                         bdl_pos_adj[dev] = 32;
2993                         break;
2994                 }
2995         }
2996
2997         if (check_hdmi_disabled(pci)) {
2998                 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2999                            pci_name(pci));
3000                 if (use_vga_switcheroo(chip)) {
3001                         snd_printk(KERN_INFO SFX "Delaying initialization\n");
3002                         chip->disabled = true;
3003                         goto ok;
3004                 }
3005                 kfree(chip);
3006                 pci_disable_device(pci);
3007                 return -ENXIO;
3008         }
3009
3010         err = azx_first_init(chip);
3011         if (err < 0) {
3012                 azx_free(chip);
3013                 return err;
3014         }
3015
3016  ok:
3017         err = register_vga_switcheroo(chip);
3018         if (err < 0) {
3019                 snd_printk(KERN_ERR SFX
3020                            "Error registering VGA-switcheroo client\n");
3021                 azx_free(chip);
3022                 return err;
3023         }
3024
3025         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3026         if (err < 0) {
3027                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3028                 azx_free(chip);
3029                 return err;
3030         }
3031
3032         *rchip = chip;
3033         return 0;
3034 }
3035
3036 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3037 {
3038         int dev = chip->dev_index;
3039         struct pci_dev *pci = chip->pci;
3040         struct snd_card *card = chip->card;
3041         int i, err;
3042         unsigned short gcap;
3043
3044 #if BITS_PER_LONG != 64
3045         /* Fix up base address on ULI M5461 */
3046         if (chip->driver_type == AZX_DRIVER_ULI) {
3047                 u16 tmp3;
3048                 pci_read_config_word(pci, 0x40, &tmp3);
3049                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3050                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3051         }
3052 #endif
3053
3054         err = pci_request_regions(pci, "ICH HD audio");
3055         if (err < 0)
3056                 return err;
3057         chip->region_requested = 1;
3058
3059         chip->addr = pci_resource_start(pci, 0);
3060         chip->remap_addr = pci_ioremap_bar(pci, 0);
3061         if (chip->remap_addr == NULL) {
3062                 snd_printk(KERN_ERR SFX "ioremap error\n");
3063                 return -ENXIO;
3064         }
3065
3066         if (chip->msi)
3067                 if (pci_enable_msi(pci) < 0)
3068                         chip->msi = 0;
3069
3070         if (azx_acquire_irq(chip, 0) < 0)
3071                 return -EBUSY;
3072
3073         pci_set_master(pci);
3074         synchronize_irq(chip->irq);
3075
3076         gcap = azx_readw(chip, GCAP);
3077         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3078
3079         /* disable SB600 64bit support for safety */
3080         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3081                 struct pci_dev *p_smbus;
3082                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3083                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3084                                          NULL);
3085                 if (p_smbus) {
3086                         if (p_smbus->revision < 0x30)
3087                                 gcap &= ~ICH6_GCAP_64OK;
3088                         pci_dev_put(p_smbus);
3089                 }
3090         }
3091
3092         /* disable 64bit DMA address on some devices */
3093         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3094                 snd_printd(SFX "Disabling 64bit DMA\n");
3095                 gcap &= ~ICH6_GCAP_64OK;
3096         }
3097
3098         /* disable buffer size rounding to 128-byte multiples if supported */
3099         if (align_buffer_size >= 0)
3100                 chip->align_buffer_size = !!align_buffer_size;
3101         else {
3102                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3103                         chip->align_buffer_size = 0;
3104                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3105                         chip->align_buffer_size = 1;
3106                 else
3107                         chip->align_buffer_size = 1;
3108         }
3109
3110         /* allow 64bit DMA address if supported by H/W */
3111         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3112                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3113         else {
3114                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3115                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3116         }
3117
3118         /* read number of streams from GCAP register instead of using
3119          * hardcoded value
3120          */
3121         chip->capture_streams = (gcap >> 8) & 0x0f;
3122         chip->playback_streams = (gcap >> 12) & 0x0f;
3123         if (!chip->playback_streams && !chip->capture_streams) {
3124                 /* gcap didn't give any info, switching to old method */
3125
3126                 switch (chip->driver_type) {
3127                 case AZX_DRIVER_ULI:
3128                         chip->playback_streams = ULI_NUM_PLAYBACK;
3129                         chip->capture_streams = ULI_NUM_CAPTURE;
3130                         break;
3131                 case AZX_DRIVER_ATIHDMI:
3132                 case AZX_DRIVER_ATIHDMI_NS:
3133                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3134                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3135                         break;
3136                 case AZX_DRIVER_GENERIC:
3137                 default:
3138                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3139                         chip->capture_streams = ICH6_NUM_CAPTURE;
3140                         break;
3141                 }
3142         }
3143         chip->capture_index_offset = 0;
3144         chip->playback_index_offset = chip->capture_streams;
3145         chip->num_streams = chip->playback_streams + chip->capture_streams;
3146         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3147                                 GFP_KERNEL);
3148         if (!chip->azx_dev) {
3149                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3150                 return -ENOMEM;
3151         }
3152
3153         for (i = 0; i < chip->num_streams; i++) {
3154                 /* allocate memory for the BDL for each stream */
3155                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3156                                           snd_dma_pci_data(chip->pci),
3157                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3158                 if (err < 0) {
3159                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3160                         return -ENOMEM;
3161                 }
3162                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3163         }
3164         /* allocate memory for the position buffer */
3165         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3166                                   snd_dma_pci_data(chip->pci),
3167                                   chip->num_streams * 8, &chip->posbuf);
3168         if (err < 0) {
3169                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3170                 return -ENOMEM;
3171         }
3172         mark_pages_wc(chip, &chip->posbuf, true);
3173         /* allocate CORB/RIRB */
3174         err = azx_alloc_cmd_io(chip);
3175         if (err < 0)
3176                 return err;
3177
3178         /* initialize streams */
3179         azx_init_stream(chip);
3180
3181         /* initialize chip */
3182         azx_init_pci(chip);
3183         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3184
3185         /* codec detection */
3186         if (!chip->codec_mask) {
3187                 snd_printk(KERN_ERR SFX "no codecs found!\n");
3188                 return -ENODEV;
3189         }
3190
3191         strcpy(card->driver, "HDA-Intel");
3192         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3193                 sizeof(card->shortname));
3194         snprintf(card->longname, sizeof(card->longname),
3195                  "%s at 0x%lx irq %i",
3196                  card->shortname, chip->addr, chip->irq);
3197
3198         return 0;
3199 }
3200
3201 static void power_down_all_codecs(struct azx *chip)
3202 {
3203 #ifdef CONFIG_SND_HDA_POWER_SAVE
3204         /* The codecs were powered up in snd_hda_codec_new().
3205          * Now all initialization done, so turn them down if possible
3206          */
3207         struct hda_codec *codec;
3208         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3209                 snd_hda_power_down(codec);
3210         }
3211 #endif
3212 }
3213
3214 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3215 /* callback from request_firmware_nowait() */
3216 static void azx_firmware_cb(const struct firmware *fw, void *context)
3217 {
3218         struct snd_card *card = context;
3219         struct azx *chip = card->private_data;
3220         struct pci_dev *pci = chip->pci;
3221
3222         if (!fw) {
3223                 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3224                 goto error;
3225         }
3226
3227         chip->fw = fw;
3228         if (!chip->disabled) {
3229                 /* continue probing */
3230                 if (azx_probe_continue(chip))
3231                         goto error;
3232         }
3233         return; /* OK */
3234
3235  error:
3236         snd_card_free(card);
3237         pci_set_drvdata(pci, NULL);
3238 }
3239 #endif
3240
3241 static int __devinit azx_probe(struct pci_dev *pci,
3242                                const struct pci_device_id *pci_id)
3243 {
3244         static int dev;
3245         struct snd_card *card;
3246         struct azx *chip;
3247         bool probe_now;
3248         int err;
3249
3250         if (dev >= SNDRV_CARDS)
3251                 return -ENODEV;
3252         if (!enable[dev]) {
3253                 dev++;
3254                 return -ENOENT;
3255         }
3256
3257         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3258         if (err < 0) {
3259                 snd_printk(KERN_ERR SFX "Error creating card!\n");
3260                 return err;
3261         }
3262
3263         snd_card_set_dev(card, &pci->dev);
3264
3265         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3266         if (err < 0)
3267                 goto out_free;
3268         card->private_data = chip;
3269         probe_now = !chip->disabled;
3270
3271 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3272         if (patch[dev] && *patch[dev]) {
3273                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3274                            patch[dev]);
3275                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3276                                               &pci->dev, GFP_KERNEL, card,
3277                                               azx_firmware_cb);
3278                 if (err < 0)
3279                         goto out_free;
3280                 probe_now = false; /* continued in azx_firmware_cb() */
3281         }
3282 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3283
3284         if (probe_now) {
3285                 err = azx_probe_continue(chip);
3286                 if (err < 0)
3287                         goto out_free;
3288         }
3289
3290         pci_set_drvdata(pci, card);
3291
3292         dev++;
3293         return 0;
3294
3295 out_free:
3296         snd_card_free(card);
3297         return err;
3298 }
3299
3300 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3301 {
3302         int dev = chip->dev_index;
3303         int err;
3304
3305 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3306         chip->beep_mode = beep_mode[dev];
3307 #endif
3308
3309         /* create codec instances */
3310         err = azx_codec_create(chip, model[dev]);
3311         if (err < 0)
3312                 goto out_free;
3313 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3314         if (chip->fw) {
3315                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3316                                          chip->fw->data);
3317                 if (err < 0)
3318                         goto out_free;
3319                 release_firmware(chip->fw); /* no longer needed */
3320                 chip->fw = NULL;
3321         }
3322 #endif
3323         if ((probe_only[dev] & 1) == 0) {
3324                 err = azx_codec_configure(chip);
3325                 if (err < 0)
3326                         goto out_free;
3327         }
3328
3329         /* create PCM streams */
3330         err = snd_hda_build_pcms(chip->bus);
3331         if (err < 0)
3332                 goto out_free;
3333
3334         /* create mixer controls */
3335         err = azx_mixer_create(chip);
3336         if (err < 0)
3337                 goto out_free;
3338
3339         err = snd_card_register(chip->card);
3340         if (err < 0)
3341                 goto out_free;
3342
3343         chip->running = 1;
3344         power_down_all_codecs(chip);
3345         azx_notifier_register(chip);
3346         azx_add_card_list(chip);
3347
3348         return 0;
3349
3350 out_free:
3351         chip->init_failed = 1;
3352         return err;
3353 }
3354
3355 static void __devexit azx_remove(struct pci_dev *pci)
3356 {
3357         struct snd_card *card = pci_get_drvdata(pci);
3358         if (card)
3359                 snd_card_free(card);
3360         pci_set_drvdata(pci, NULL);
3361 }
3362
3363 /* PCI IDs */
3364 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3365         /* CPT */
3366         { PCI_DEVICE(0x8086, 0x1c20),
3367           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3368           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3369         /* PBG */
3370         { PCI_DEVICE(0x8086, 0x1d20),
3371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3372           AZX_DCAPS_BUFSIZE},
3373         /* Panther Point */
3374         { PCI_DEVICE(0x8086, 0x1e20),
3375           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3376           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3377         /* Lynx Point */
3378         { PCI_DEVICE(0x8086, 0x8c20),
3379           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3380           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3381         /* Haswell */
3382         { PCI_DEVICE(0x8086, 0x0c0c),
3383           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3384           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3385         /* SCH */
3386         { PCI_DEVICE(0x8086, 0x811b),
3387           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3388           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3389         { PCI_DEVICE(0x8086, 0x080a),
3390           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3391           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3392         /* ICH */
3393         { PCI_DEVICE(0x8086, 0x2668),
3394           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3395           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3396         { PCI_DEVICE(0x8086, 0x27d8),
3397           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3398           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3399         { PCI_DEVICE(0x8086, 0x269a),
3400           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3401           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3402         { PCI_DEVICE(0x8086, 0x284b),
3403           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3404           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3405         { PCI_DEVICE(0x8086, 0x293e),
3406           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3407           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3408         { PCI_DEVICE(0x8086, 0x293f),
3409           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3410           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3411         { PCI_DEVICE(0x8086, 0x3a3e),
3412           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3413           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3414         { PCI_DEVICE(0x8086, 0x3a6e),
3415           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3416           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3417         /* Generic Intel */
3418         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3419           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3420           .class_mask = 0xffffff,
3421           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3422         /* ATI SB 450/600/700/800/900 */
3423         { PCI_DEVICE(0x1002, 0x437b),
3424           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3425         { PCI_DEVICE(0x1002, 0x4383),
3426           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3427         /* AMD Hudson */
3428         { PCI_DEVICE(0x1022, 0x780d),
3429           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3430         /* ATI HDMI */
3431         { PCI_DEVICE(0x1002, 0x793b),
3432           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3433         { PCI_DEVICE(0x1002, 0x7919),
3434           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3435         { PCI_DEVICE(0x1002, 0x960f),
3436           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3437         { PCI_DEVICE(0x1002, 0x970f),
3438           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3439         { PCI_DEVICE(0x1002, 0xaa00),
3440           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3441         { PCI_DEVICE(0x1002, 0xaa08),
3442           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3443         { PCI_DEVICE(0x1002, 0xaa10),
3444           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3445         { PCI_DEVICE(0x1002, 0xaa18),
3446           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3447         { PCI_DEVICE(0x1002, 0xaa20),
3448           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3449         { PCI_DEVICE(0x1002, 0xaa28),
3450           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3451         { PCI_DEVICE(0x1002, 0xaa30),
3452           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3453         { PCI_DEVICE(0x1002, 0xaa38),
3454           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3455         { PCI_DEVICE(0x1002, 0xaa40),
3456           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3457         { PCI_DEVICE(0x1002, 0xaa48),
3458           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3459         { PCI_DEVICE(0x1002, 0x9902),
3460           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3461         { PCI_DEVICE(0x1002, 0xaaa0),
3462           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3463         { PCI_DEVICE(0x1002, 0xaaa8),
3464           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3465         { PCI_DEVICE(0x1002, 0xaab0),
3466           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3467         /* VIA VT8251/VT8237A */
3468         { PCI_DEVICE(0x1106, 0x3288),
3469           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3470         /* VIA GFX VT7122/VX900 */
3471         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3472         /* VIA GFX VT6122/VX11 */
3473         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3474         /* SIS966 */
3475         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3476         /* ULI M5461 */
3477         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3478         /* NVIDIA MCP */
3479         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3480           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3481           .class_mask = 0xffffff,
3482           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3483         /* Teradici */
3484         { PCI_DEVICE(0x6549, 0x1200),
3485           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3486         /* Creative X-Fi (CA0110-IBG) */
3487         /* CTHDA chips */
3488         { PCI_DEVICE(0x1102, 0x0010),
3489           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3490         { PCI_DEVICE(0x1102, 0x0012),
3491           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3492 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3493         /* the following entry conflicts with snd-ctxfi driver,
3494          * as ctxfi driver mutates from HD-audio to native mode with
3495          * a special command sequence.
3496          */
3497         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3498           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3499           .class_mask = 0xffffff,
3500           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3501           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3502 #else
3503         /* this entry seems still valid -- i.e. without emu20kx chip */
3504         { PCI_DEVICE(0x1102, 0x0009),
3505           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3506           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3507 #endif
3508         /* Vortex86MX */
3509         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3510         /* VMware HDAudio */
3511         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3512         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3513         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3514           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3515           .class_mask = 0xffffff,
3516           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3517         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3518           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3519           .class_mask = 0xffffff,
3520           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3521         { 0, }
3522 };
3523 MODULE_DEVICE_TABLE(pci, azx_ids);
3524
3525 /* pci_driver definition */
3526 static struct pci_driver azx_driver = {
3527         .name = KBUILD_MODNAME,
3528         .id_table = azx_ids,
3529         .probe = azx_probe,
3530         .remove = __devexit_p(azx_remove),
3531         .driver = {
3532                 .pm = AZX_PM_OPS,
3533         },
3534 };
3535
3536 module_pci_driver(azx_driver);