sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include <linux/vgaarb.h>
  57 #include <linux/vga_switcheroo.h>
  58 #include <linux/firmware.h>
  59 #include "hda_codec.h"
  60
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  65 static char *model[SNDRV_CARDS];
  66 static int position_fix[SNDRV_CARDS];
  67 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  68 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  69 static int probe_only[SNDRV_CARDS];
  70 static bool single_cmd;
  71 static int enable_msi = -1;
  72 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  73 static char *patch[SNDRV_CARDS];
  74 #endif
  75 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  76 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  77                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  78 #endif
  79
  80 module_param_array(index, int, NULL, 0444);
  81 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  82 module_param_array(id, charp, NULL, 0444);
  83 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  84 module_param_array(enable, bool, NULL, 0444);
  85 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  86 module_param_array(model, charp, NULL, 0444);
  87 MODULE_PARM_DESC(model, "Use the given board model.");
  88 module_param_array(position_fix, int, NULL, 0444);
  89 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  90                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  91 module_param_array(bdl_pos_adj, int, NULL, 0644);
  92 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  93 module_param_array(probe_mask, int, NULL, 0444);
  94 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  95 module_param_array(probe_only, int, NULL, 0444);
  96 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  97 module_param(single_cmd, bool, 0444);
  98 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  99                  "(for debugging only).");
 100 module_param(enable_msi, bint, 0444);
 101 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 102 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 103 module_param_array(patch, charp, NULL, 0444);
 104 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 105 #endif
 106 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 107 module_param_array(beep_mode, bool, NULL, 0444);
 108 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 109                             "(0=off, 1=on) (default=1).");
 110 #endif
 111
 112 #ifdef CONFIG_SND_HDA_POWER_SAVE
 113 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 114 module_param(power_save, int, 0644);
 115 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 116                  "(in second, 0 = disable).");
 117
 118 /* reset the HD-audio controller in power save mode.
 119  * this may give more power-saving, but will take longer time to
 120  * wake up.
 121  */
 122 static bool power_save_controller = 1;
 123 module_param(power_save_controller, bool, 0644);
 124 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 125 #endif
 126
 127 static int align_buffer_size = -1;
 128 module_param(align_buffer_size, bint, 0644);
 129 MODULE_PARM_DESC(align_buffer_size,
 130                 "Force buffer and period sizes to be multiple of 128 bytes.");
 131
 132 #ifdef CONFIG_X86
 133 static bool hda_snoop = true;
 134 module_param_named(snoop, hda_snoop, bool, 0444);
 135 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 136 #define azx_snoop(chip)         (chip)->snoop
 137 #else
 138 #define hda_snoop               true
 139 #define azx_snoop(chip)         true
 140 #endif
 141
 142
 143 MODULE_LICENSE("GPL");
 144 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 145                          "{Intel, ICH6M},"
 146                          "{Intel, ICH7},"
 147                          "{Intel, ESB2},"
 148                          "{Intel, ICH8},"
 149                          "{Intel, ICH9},"
 150                          "{Intel, ICH10},"
 151                          "{Intel, PCH},"
 152                          "{Intel, CPT},"
 153                          "{Intel, PPT},"
 154                          "{Intel, LPT},"
 155                          "{Intel, HPT},"
 156                          "{Intel, PBG},"
 157                          "{Intel, SCH},"
 158                          "{ATI, SB450},"
 159                          "{ATI, SB600},"
 160                          "{ATI, RS600},"
 161                          "{ATI, RS690},"
 162                          "{ATI, RS780},"
 163                          "{ATI, R600},"
 164                          "{ATI, RV630},"
 165                          "{ATI, RV610},"
 166                          "{ATI, RV670},"
 167                          "{ATI, RV635},"
 168                          "{ATI, RV620},"
 169                          "{ATI, RV770},"
 170                          "{VIA, VT8251},"
 171                          "{VIA, VT8237A},"
 172                          "{SiS, SIS966},"
 173                          "{ULI, M5461}}");
 174 MODULE_DESCRIPTION("Intel HDA driver");
 175
 176 #ifdef CONFIG_SND_VERBOSE_PRINTK
 177 #define SFX     /* nop */
 178 #else
 179 #define SFX     "hda-intel: "
 180 #endif
 181
 182 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 183 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 184 #define SUPPORT_VGA_SWITCHEROO
 185 #endif
 186 #endif
 187
 188
 189 /*
 190  * registers
 191  */
 192 #define ICH6_REG_GCAP                   0x00
 193 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 194 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 195 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 196 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 197 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 198 #define ICH6_REG_VMIN                   0x02
 199 #define ICH6_REG_VMAJ                   0x03
 200 #define ICH6_REG_OUTPAY                 0x04
 201 #define ICH6_REG_INPAY                  0x06
 202 #define ICH6_REG_GCTL                   0x08
 203 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 204 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 205 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 206 #define ICH6_REG_WAKEEN                 0x0c
 207 #define ICH6_REG_STATESTS               0x0e
 208 #define ICH6_REG_GSTS                   0x10
 209 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 210 #define ICH6_REG_INTCTL                 0x20
 211 #define ICH6_REG_INTSTS                 0x24
 212 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 213 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 214 #define ICH6_REG_SSYNC                  0x38
 215 #define ICH6_REG_CORBLBASE              0x40
 216 #define ICH6_REG_CORBUBASE              0x44
 217 #define ICH6_REG_CORBWP                 0x48
 218 #define ICH6_REG_CORBRP                 0x4a
 219 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 220 #define ICH6_REG_CORBCTL                0x4c
 221 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 222 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 223 #define ICH6_REG_CORBSTS                0x4d
 224 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 225 #define ICH6_REG_CORBSIZE               0x4e
 226
 227 #define ICH6_REG_RIRBLBASE              0x50
 228 #define ICH6_REG_RIRBUBASE              0x54
 229 #define ICH6_REG_RIRBWP                 0x58
 230 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 231 #define ICH6_REG_RINTCNT                0x5a
 232 #define ICH6_REG_RIRBCTL                0x5c
 233 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 234 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 235 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 236 #define ICH6_REG_RIRBSTS                0x5d
 237 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 238 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 239 #define ICH6_REG_RIRBSIZE               0x5e
 240
 241 #define ICH6_REG_IC                     0x60
 242 #define ICH6_REG_IR                     0x64
 243 #define ICH6_REG_IRS                    0x68
 244 #define   ICH6_IRS_VALID        (1<<1)
 245 #define   ICH6_IRS_BUSY         (1<<0)
 246
 247 #define ICH6_REG_DPLBASE                0x70
 248 #define ICH6_REG_DPUBASE                0x74
 249 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 250
 251 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 252 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 253
 254 /* stream register offsets from stream base */
 255 #define ICH6_REG_SD_CTL                 0x00
 256 #define ICH6_REG_SD_STS                 0x03
 257 #define ICH6_REG_SD_LPIB                0x04
 258 #define ICH6_REG_SD_CBL                 0x08
 259 #define ICH6_REG_SD_LVI                 0x0c
 260 #define ICH6_REG_SD_FIFOW               0x0e
 261 #define ICH6_REG_SD_FIFOSIZE            0x10
 262 #define ICH6_REG_SD_FORMAT              0x12
 263 #define ICH6_REG_SD_BDLPL               0x18
 264 #define ICH6_REG_SD_BDLPU               0x1c
 265
 266 /* PCI space */
 267 #define ICH6_PCIREG_TCSEL       0x44
 268
 269 /*
 270  * other constants
 271  */
 272
 273 /* max number of SDs */
 274 /* ICH, ATI and VIA have 4 playback and 4 capture */
 275 #define ICH6_NUM_CAPTURE        4
 276 #define ICH6_NUM_PLAYBACK       4
 277
 278 /* ULI has 6 playback and 5 capture */
 279 #define ULI_NUM_CAPTURE         5
 280 #define ULI_NUM_PLAYBACK        6
 281
 282 /* ATI HDMI has 1 playback and 0 capture */
 283 #define ATIHDMI_NUM_CAPTURE     0
 284 #define ATIHDMI_NUM_PLAYBACK    1
 285
 286 /* TERA has 4 playback and 3 capture */
 287 #define TERA_NUM_CAPTURE        3
 288 #define TERA_NUM_PLAYBACK       4
 289
 290 /* this number is statically defined for simplicity */
 291 #define MAX_AZX_DEV             16
 292
 293 /* max number of fragments - we may use more if allocating more pages for BDL */
 294 #define BDL_SIZE                4096
 295 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 296 #define AZX_MAX_FRAG            32
 297 /* max buffer size - no h/w limit, you can increase as you like */
 298 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 299
 300 /* RIRB int mask: overrun[2], response[0] */
 301 #define RIRB_INT_RESPONSE       0x01
 302 #define RIRB_INT_OVERRUN        0x04
 303 #define RIRB_INT_MASK           0x05
 304
 305 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 306 #define AZX_MAX_CODECS          8
 307 #define AZX_DEFAULT_CODECS      4
 308 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 309
 310 /* SD_CTL bits */
 311 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 312 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 313 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 314 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 315 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 316 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 317 #define SD_CTL_STREAM_TAG_SHIFT 20
 318
 319 /* SD_CTL and SD_STS */
 320 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 321 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 322 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 323 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 324                                  SD_INT_COMPLETE)
 325
 326 /* SD_STS */
 327 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 328
 329 /* INTCTL and INTSTS */
 330 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 331 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 332 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 333
 334 /* below are so far hardcoded - should read registers in future */
 335 #define ICH6_MAX_CORB_ENTRIES   256
 336 #define ICH6_MAX_RIRB_ENTRIES   256
 337
 338 /* position fix mode */
 339 enum {
 340         POS_FIX_AUTO,
 341         POS_FIX_LPIB,
 342         POS_FIX_POSBUF,
 343         POS_FIX_VIACOMBO,
 344         POS_FIX_COMBO,
 345 };
 346
 347 /* Defines for ATI HD Audio support in SB450 south bridge */
 348 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 349 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 350
 351 /* Defines for Nvidia HDA support */
 352 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 353 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 354 #define NVIDIA_HDA_ISTRM_COH          0x4d
 355 #define NVIDIA_HDA_OSTRM_COH          0x4c
 356 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 357
 358 /* Defines for Intel SCH HDA snoop control */
 359 #define INTEL_SCH_HDA_DEVC      0x78
 360 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 361
 362 /* Define IN stream 0 FIFO size offset in VIA controller */
 363 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 364 /* Define VIA HD Audio Device ID*/
 365 #define VIA_HDAC_DEVICE_ID              0x3288
 366
 367 /* HD Audio class code */
 368 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 369
 370 /*
 371  */
 372
 373 struct azx_dev {
 374         struct snd_dma_buffer bdl; /* BDL buffer */
 375         u32 *posbuf;            /* position buffer pointer */
 376
 377         unsigned int bufsize;   /* size of the play buffer in bytes */
 378         unsigned int period_bytes; /* size of the period in bytes */
 379         unsigned int frags;     /* number for period in the play buffer */
 380         unsigned int fifo_size; /* FIFO size */
 381         unsigned long start_wallclk;    /* start + minimum wallclk */
 382         unsigned long period_wallclk;   /* wallclk for period */
 383
 384         void __iomem *sd_addr;  /* stream descriptor pointer */
 385
 386         u32 sd_int_sta_mask;    /* stream int status mask */
 387
 388         /* pcm support */
 389         struct snd_pcm_substream *substream;    /* assigned substream,
 390                                                  * set in PCM open
 391                                                  */
 392         unsigned int format_val;        /* format value to be set in the
 393                                          * controller and the codec
 394                                          */
 395         unsigned char stream_tag;       /* assigned stream */
 396         unsigned char index;            /* stream index */
 397         int assigned_key;               /* last device# key assigned to */
 398
 399         unsigned int opened :1;
 400         unsigned int running :1;
 401         unsigned int irq_pending :1;
 402         /*
 403          * For VIA:
 404          *  A flag to ensure DMA position is 0
 405          *  when link position is not greater than FIFO size
 406          */
 407         unsigned int insufficient :1;
 408         unsigned int wc_marked:1;
 409 };
 410
 411 /* CORB/RIRB */
 412 struct azx_rb {
 413         u32 *buf;               /* CORB/RIRB buffer
 414                                  * Each CORB entry is 4byte, RIRB is 8byte
 415                                  */
 416         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 417         /* for RIRB */
 418         unsigned short rp, wp;  /* read/write pointers */
 419         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 420         u32 res[AZX_MAX_CODECS];        /* last read value */
 421 };
 422
 423 struct azx_pcm {
 424         struct azx *chip;
 425         struct snd_pcm *pcm;
 426         struct hda_codec *codec;
 427         struct hda_pcm_stream *hinfo[2];
 428         struct list_head list;
 429 };
 430
 431 struct azx {
 432         struct snd_card *card;
 433         struct pci_dev *pci;
 434         int dev_index;
 435
 436         /* chip type specific */
 437         int driver_type;
 438         unsigned int driver_caps;
 439         int playback_streams;
 440         int playback_index_offset;
 441         int capture_streams;
 442         int capture_index_offset;
 443         int num_streams;
 444
 445         /* pci resources */
 446         unsigned long addr;
 447         void __iomem *remap_addr;
 448         int irq;
 449
 450         /* locks */
 451         spinlock_t reg_lock;
 452         struct mutex open_mutex;
 453
 454         /* streams (x num_streams) */
 455         struct azx_dev *azx_dev;
 456
 457         /* PCM */
 458         struct list_head pcm_list; /* azx_pcm list */
 459
 460         /* HD codec */
 461         unsigned short codec_mask;
 462         int  codec_probe_mask; /* copied from probe_mask option */
 463         struct hda_bus *bus;
 464         unsigned int beep_mode;
 465
 466         /* CORB/RIRB */
 467         struct azx_rb corb;
 468         struct azx_rb rirb;
 469
 470         /* CORB/RIRB and position buffers */
 471         struct snd_dma_buffer rb;
 472         struct snd_dma_buffer posbuf;
 473
 474 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 475         const struct firmware *fw;
 476 #endif
 477
 478         /* flags */
 479         int position_fix[2]; /* for both playback/capture streams */
 480         int poll_count;
 481         unsigned int running :1;
 482         unsigned int initialized :1;
 483         unsigned int single_cmd :1;
 484         unsigned int polling_mode :1;
 485         unsigned int msi :1;
 486         unsigned int irq_pending_warned :1;
 487         unsigned int probing :1; /* codec probing phase */
 488         unsigned int snoop:1;
 489         unsigned int align_buffer_size:1;
 490         unsigned int region_requested:1;
 491
 492         /* VGA-switcheroo setup */
 493         unsigned int use_vga_switcheroo:1;
 494         unsigned int init_failed:1; /* delayed init failed */
 495         unsigned int disabled:1; /* disabled by VGA-switcher */
 496
 497         /* for debugging */
 498         unsigned int last_cmd[AZX_MAX_CODECS];
 499
 500         /* for pending irqs */
 501         struct work_struct irq_pending_work;
 502
 503         /* reboot notifier (for mysterious hangup problem at power-down) */
 504         struct notifier_block reboot_notifier;
 505 };
 506
 507 /* driver types */
 508 enum {
 509         AZX_DRIVER_ICH,
 510         AZX_DRIVER_PCH,
 511         AZX_DRIVER_SCH,
 512         AZX_DRIVER_ATI,
 513         AZX_DRIVER_ATIHDMI,
 514         AZX_DRIVER_ATIHDMI_NS,
 515         AZX_DRIVER_VIA,
 516         AZX_DRIVER_SIS,
 517         AZX_DRIVER_ULI,
 518         AZX_DRIVER_NVIDIA,
 519         AZX_DRIVER_TERA,
 520         AZX_DRIVER_CTX,
 521         AZX_DRIVER_CTHDA,
 522         AZX_DRIVER_GENERIC,
 523         AZX_NUM_DRIVERS, /* keep this as last entry */
 524 };
 525
 526 /* driver quirks (capabilities) */
 527 /* bits 0-7 are used for indicating driver type */
 528 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 529 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 530 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 531 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 532 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 533 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 534 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 535 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 536 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 537 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 538 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 539 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 540 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 541 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 542 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 543 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 544 #define AZX_DCAPS_POSFIX_COMBO  (1 << 24)       /* Use COMBO as default */
 545
 546 /* quirks for ATI SB / AMD Hudson */
 547 #define AZX_DCAPS_PRESET_ATI_SB \
 548         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 549          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 550
 551 /* quirks for ATI/AMD HDMI */
 552 #define AZX_DCAPS_PRESET_ATI_HDMI \
 553         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 554
 555 /* quirks for Nvidia */
 556 #define AZX_DCAPS_PRESET_NVIDIA \
 557         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 558          AZX_DCAPS_ALIGN_BUFSIZE)
 559
 560 #define AZX_DCAPS_PRESET_CTHDA \
 561         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 562
 563 /*
 564  * VGA-switcher support
 565  */
 566 #ifdef SUPPORT_VGA_SWITCHEROO
 567 #define DELAYED_INIT_MARK
 568 #define DELAYED_INITDATA_MARK
 569 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 570 #else
 571 #define DELAYED_INIT_MARK       __devinit
 572 #define DELAYED_INITDATA_MARK   __devinitdata
 573 #define use_vga_switcheroo(chip)        0
 574 #endif
 575
 576 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
 577         [AZX_DRIVER_ICH] = "HDA Intel",
 578         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 579         [AZX_DRIVER_SCH] = "HDA Intel MID",
 580         [AZX_DRIVER_ATI] = "HDA ATI SB",
 581         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 582         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 583         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 584         [AZX_DRIVER_SIS] = "HDA SIS966",
 585         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 586         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 587         [AZX_DRIVER_TERA] = "HDA Teradici",
 588         [AZX_DRIVER_CTX] = "HDA Creative",
 589         [AZX_DRIVER_CTHDA] = "HDA Creative",
 590         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 591 };
 592
 593 /*
 594  * macros for easy use
 595  */
 596 #define azx_writel(chip,reg,value) \
 597         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 598 #define azx_readl(chip,reg) \
 599         readl((chip)->remap_addr + ICH6_REG_##reg)
 600 #define azx_writew(chip,reg,value) \
 601         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 602 #define azx_readw(chip,reg) \
 603         readw((chip)->remap_addr + ICH6_REG_##reg)
 604 #define azx_writeb(chip,reg,value) \
 605         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 606 #define azx_readb(chip,reg) \
 607         readb((chip)->remap_addr + ICH6_REG_##reg)
 608
 609 #define azx_sd_writel(dev,reg,value) \
 610         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 611 #define azx_sd_readl(dev,reg) \
 612         readl((dev)->sd_addr + ICH6_REG_##reg)
 613 #define azx_sd_writew(dev,reg,value) \
 614         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 615 #define azx_sd_readw(dev,reg) \
 616         readw((dev)->sd_addr + ICH6_REG_##reg)
 617 #define azx_sd_writeb(dev,reg,value) \
 618         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 619 #define azx_sd_readb(dev,reg) \
 620         readb((dev)->sd_addr + ICH6_REG_##reg)
 621
 622 /* for pcm support */
 623 #define get_azx_dev(substream) (substream->runtime->private_data)
 624
 625 #ifdef CONFIG_X86
 626 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 627 {
 628         if (azx_snoop(chip))
 629                 return;
 630         if (addr && size) {
 631                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 632                 if (on)
 633                         set_memory_wc((unsigned long)addr, pages);
 634                 else
 635                         set_memory_wb((unsigned long)addr, pages);
 636         }
 637 }
 638
 639 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 640                                  bool on)
 641 {
 642         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 643 }
 644 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 645                                    struct snd_pcm_runtime *runtime, bool on)
 646 {
 647         if (azx_dev->wc_marked != on) {
 648                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 649                 azx_dev->wc_marked = on;
 650         }
 651 }
 652 #else
 653 /* NOP for other archs */
 654 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 655                                  bool on)
 656 {
 657 }
 658 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 659                                    struct snd_pcm_runtime *runtime, bool on)
 660 {
 661 }
 662 #endif
 663
 664 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 665 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 666 /*
 667  * Interface for HD codec
 668  */
 669
 670 /*
 671  * CORB / RIRB interface
 672  */
 673 static int azx_alloc_cmd_io(struct azx *chip)
 674 {
 675         int err;
 676
 677         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 678         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 679                                   snd_dma_pci_data(chip->pci),
 680                                   PAGE_SIZE, &chip->rb);
 681         if (err < 0) {
 682                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 683                 return err;
 684         }
 685         mark_pages_wc(chip, &chip->rb, true);
 686         return 0;
 687 }
 688
 689 static void azx_init_cmd_io(struct azx *chip)
 690 {
 691         spin_lock_irq(&chip->reg_lock);
 692         /* CORB set up */
 693         chip->corb.addr = chip->rb.addr;
 694         chip->corb.buf = (u32 *)chip->rb.area;
 695         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 696         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 697
 698         /* set the corb size to 256 entries (ULI requires explicitly) */
 699         azx_writeb(chip, CORBSIZE, 0x02);
 700         /* set the corb write pointer to 0 */
 701         azx_writew(chip, CORBWP, 0);
 702         /* reset the corb hw read pointer */
 703         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 704         /* enable corb dma */
 705         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 706
 707         /* RIRB set up */
 708         chip->rirb.addr = chip->rb.addr + 2048;
 709         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 710         chip->rirb.wp = chip->rirb.rp = 0;
 711         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 712         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 713         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 714
 715         /* set the rirb size to 256 entries (ULI requires explicitly) */
 716         azx_writeb(chip, RIRBSIZE, 0x02);
 717         /* reset the rirb hw write pointer */
 718         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 719         /* set N=1, get RIRB response interrupt for new entry */
 720         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 721                 azx_writew(chip, RINTCNT, 0xc0);
 722         else
 723                 azx_writew(chip, RINTCNT, 1);
 724         /* enable rirb dma and response irq */
 725         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 726         spin_unlock_irq(&chip->reg_lock);
 727 }
 728
 729 static void azx_free_cmd_io(struct azx *chip)
 730 {
 731         spin_lock_irq(&chip->reg_lock);
 732         /* disable ringbuffer DMAs */
 733         azx_writeb(chip, RIRBCTL, 0);
 734         azx_writeb(chip, CORBCTL, 0);
 735         spin_unlock_irq(&chip->reg_lock);
 736 }
 737
 738 static unsigned int azx_command_addr(u32 cmd)
 739 {
 740         unsigned int addr = cmd >> 28;
 741
 742         if (addr >= AZX_MAX_CODECS) {
 743                 snd_BUG();
 744                 addr = 0;
 745         }
 746
 747         return addr;
 748 }
 749
 750 static unsigned int azx_response_addr(u32 res)
 751 {
 752         unsigned int addr = res & 0xf;
 753
 754         if (addr >= AZX_MAX_CODECS) {
 755                 snd_BUG();
 756                 addr = 0;
 757         }
 758
 759         return addr;
 760 }
 761
 762 /* send a command */
 763 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 764 {
 765         struct azx *chip = bus->private_data;
 766         unsigned int addr = azx_command_addr(val);
 767         unsigned int wp;
 768
 769         spin_lock_irq(&chip->reg_lock);
 770
 771         /* add command to corb */
 772         wp = azx_readb(chip, CORBWP);
 773         wp++;
 774         wp %= ICH6_MAX_CORB_ENTRIES;
 775
 776         chip->rirb.cmds[addr]++;
 777         chip->corb.buf[wp] = cpu_to_le32(val);
 778         azx_writel(chip, CORBWP, wp);
 779
 780         spin_unlock_irq(&chip->reg_lock);
 781
 782         return 0;
 783 }
 784
 785 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 786
 787 /* retrieve RIRB entry - called from interrupt handler */
 788 static void azx_update_rirb(struct azx *chip)
 789 {
 790         unsigned int rp, wp;
 791         unsigned int addr;
 792         u32 res, res_ex;
 793
 794         wp = azx_readb(chip, RIRBWP);
 795         if (wp == chip->rirb.wp)
 796                 return;
 797         chip->rirb.wp = wp;
 798
 799         while (chip->rirb.rp != wp) {
 800                 chip->rirb.rp++;
 801                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 802
 803                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 804                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 805                 res = le32_to_cpu(chip->rirb.buf[rp]);
 806                 addr = azx_response_addr(res_ex);
 807                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 808                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 809                 else if (chip->rirb.cmds[addr]) {
 810                         chip->rirb.res[addr] = res;
 811                         smp_wmb();
 812                         chip->rirb.cmds[addr]--;
 813                 } else
 814                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 815                                    "last cmd=%#08x\n",
 816                                    res, res_ex,
 817                                    chip->last_cmd[addr]);
 818         }
 819 }
 820
 821 /* receive a response */
 822 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 823                                           unsigned int addr)
 824 {
 825         struct azx *chip = bus->private_data;
 826         unsigned long timeout;
 827         unsigned long loopcounter;
 828         int do_poll = 0;
 829
 830  again:
 831         timeout = jiffies + msecs_to_jiffies(1000);
 832
 833         for (loopcounter = 0;; loopcounter++) {
 834                 if (chip->polling_mode || do_poll) {
 835                         spin_lock_irq(&chip->reg_lock);
 836                         azx_update_rirb(chip);
 837                         spin_unlock_irq(&chip->reg_lock);
 838                 }
 839                 if (!chip->rirb.cmds[addr]) {
 840                         smp_rmb();
 841                         bus->rirb_error = 0;
 842
 843                         if (!do_poll)
 844                                 chip->poll_count = 0;
 845                         return chip->rirb.res[addr]; /* the last value */
 846                 }
 847                 if (time_after(jiffies, timeout))
 848                         break;
 849                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 850                         msleep(2); /* temporary workaround */
 851                 else {
 852                         udelay(10);
 853                         cond_resched();
 854                 }
 855         }
 856
 857         if (!chip->polling_mode && chip->poll_count < 2) {
 858                 snd_printdd(SFX "azx_get_response timeout, "
 859                            "polling the codec once: last cmd=0x%08x\n",
 860                            chip->last_cmd[addr]);
 861                 do_poll = 1;
 862                 chip->poll_count++;
 863                 goto again;
 864         }
 865
 866
 867         if (!chip->polling_mode) {
 868                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 869                            "switching to polling mode: last cmd=0x%08x\n",
 870                            chip->last_cmd[addr]);
 871                 chip->polling_mode = 1;
 872                 goto again;
 873         }
 874
 875         if (chip->msi) {
 876                 snd_printk(KERN_WARNING SFX "No response from codec, "
 877                            "disabling MSI: last cmd=0x%08x\n",
 878                            chip->last_cmd[addr]);
 879                 free_irq(chip->irq, chip);
 880                 chip->irq = -1;
 881                 pci_disable_msi(chip->pci);
 882                 chip->msi = 0;
 883                 if (azx_acquire_irq(chip, 1) < 0) {
 884                         bus->rirb_error = 1;
 885                         return -1;
 886                 }
 887                 goto again;
 888         }
 889
 890         if (chip->probing) {
 891                 /* If this critical timeout happens during the codec probing
 892                  * phase, this is likely an access to a non-existing codec
 893                  * slot.  Better to return an error and reset the system.
 894                  */
 895                 return -1;
 896         }
 897
 898         /* a fatal communication error; need either to reset or to fallback
 899          * to the single_cmd mode
 900          */
 901         bus->rirb_error = 1;
 902         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 903                 bus->response_reset = 1;
 904                 return -1; /* give a chance to retry */
 905         }
 906
 907         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 908                    "switching to single_cmd mode: last cmd=0x%08x\n",
 909                    chip->last_cmd[addr]);
 910         chip->single_cmd = 1;
 911         bus->response_reset = 0;
 912         /* release CORB/RIRB */
 913         azx_free_cmd_io(chip);
 914         /* disable unsolicited responses */
 915         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 916         return -1;
 917 }
 918
 919 /*
 920  * Use the single immediate command instead of CORB/RIRB for simplicity
 921  *
 922  * Note: according to Intel, this is not preferred use.  The command was
 923  *       intended for the BIOS only, and may get confused with unsolicited
 924  *       responses.  So, we shouldn't use it for normal operation from the
 925  *       driver.
 926  *       I left the codes, however, for debugging/testing purposes.
 927  */
 928
 929 /* receive a response */
 930 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 931 {
 932         int timeout = 50;
 933
 934         while (timeout--) {
 935                 /* check IRV busy bit */
 936                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 937                         /* reuse rirb.res as the response return value */
 938                         chip->rirb.res[addr] = azx_readl(chip, IR);
 939                         return 0;
 940                 }
 941                 udelay(1);
 942         }
 943         if (printk_ratelimit())
 944                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 945                            azx_readw(chip, IRS));
 946         chip->rirb.res[addr] = -1;
 947         return -EIO;
 948 }
 949
 950 /* send a command */
 951 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 952 {
 953         struct azx *chip = bus->private_data;
 954         unsigned int addr = azx_command_addr(val);
 955         int timeout = 50;
 956
 957         bus->rirb_error = 0;
 958         while (timeout--) {
 959                 /* check ICB busy bit */
 960                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 961                         /* Clear IRV valid bit */
 962                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 963                                    ICH6_IRS_VALID);
 964                         azx_writel(chip, IC, val);
 965                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 966                                    ICH6_IRS_BUSY);
 967                         return azx_single_wait_for_response(chip, addr);
 968                 }
 969                 udelay(1);
 970         }
 971         if (printk_ratelimit())
 972                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 973                            azx_readw(chip, IRS), val);
 974         return -EIO;
 975 }
 976
 977 /* receive a response */
 978 static unsigned int azx_single_get_response(struct hda_bus *bus,
 979                                             unsigned int addr)
 980 {
 981         struct azx *chip = bus->private_data;
 982         return chip->rirb.res[addr];
 983 }
 984
 985 /*
 986  * The below are the main callbacks from hda_codec.
 987  *
 988  * They are just the skeleton to call sub-callbacks according to the
 989  * current setting of chip->single_cmd.
 990  */
 991
 992 /* send a command */
 993 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 994 {
 995         struct azx *chip = bus->private_data;
 996
 997         if (chip->disabled)
 998                 return 0;
 999         chip->last_cmd[azx_command_addr(val)] = val;
1000         if (chip->single_cmd)
1001                 return azx_single_send_cmd(bus, val);
1002         else
1003                 return azx_corb_send_cmd(bus, val);
1004 }
1005
1006 /* get a response */
1007 static unsigned int azx_get_response(struct hda_bus *bus,
1008                                      unsigned int addr)
1009 {
1010         struct azx *chip = bus->private_data;
1011         if (chip->disabled)
1012                 return 0;
1013         if (chip->single_cmd)
1014                 return azx_single_get_response(bus, addr);
1015         else
1016                 return azx_rirb_get_response(bus, addr);
1017 }
1018
1019 #ifdef CONFIG_SND_HDA_POWER_SAVE
1020 static void azx_power_notify(struct hda_bus *bus);
1021 #endif
1022
1023 /* reset codec link */
1024 static int azx_reset(struct azx *chip, int full_reset)
1025 {
1026         int count;
1027
1028         if (!full_reset)
1029                 goto __skip;
1030
1031         /* clear STATESTS */
1032         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1033
1034         /* reset controller */
1035         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1036
1037         count = 50;
1038         while (azx_readb(chip, GCTL) && --count)
1039                 msleep(1);
1040
1041         /* delay for >= 100us for codec PLL to settle per spec
1042          * Rev 0.9 section 5.5.1
1043          */
1044         msleep(1);
1045
1046         /* Bring controller out of reset */
1047         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1048
1049         count = 50;
1050         while (!azx_readb(chip, GCTL) && --count)
1051                 msleep(1);
1052
1053         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1054         msleep(1);
1055
1056       __skip:
1057         /* check to see if controller is ready */
1058         if (!azx_readb(chip, GCTL)) {
1059                 snd_printd(SFX "azx_reset: controller not ready!\n");
1060                 return -EBUSY;
1061         }
1062
1063         /* Accept unsolicited responses */
1064         if (!chip->single_cmd)
1065                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1066                            ICH6_GCTL_UNSOL);
1067
1068         /* detect codecs */
1069         if (!chip->codec_mask) {
1070                 chip->codec_mask = azx_readw(chip, STATESTS);
1071                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1072         }
1073
1074         return 0;
1075 }
1076
1077
1078 /*
1079  * Lowlevel interface
1080  */
1081
1082 /* enable interrupts */
1083 static void azx_int_enable(struct azx *chip)
1084 {
1085         /* enable controller CIE and GIE */
1086         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1087                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1088 }
1089
1090 /* disable interrupts */
1091 static void azx_int_disable(struct azx *chip)
1092 {
1093         int i;
1094
1095         /* disable interrupts in stream descriptor */
1096         for (i = 0; i < chip->num_streams; i++) {
1097                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1098                 azx_sd_writeb(azx_dev, SD_CTL,
1099                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1100         }
1101
1102         /* disable SIE for all streams */
1103         azx_writeb(chip, INTCTL, 0);
1104
1105         /* disable controller CIE and GIE */
1106         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1107                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1108 }
1109
1110 /* clear interrupts */
1111 static void azx_int_clear(struct azx *chip)
1112 {
1113         int i;
1114
1115         /* clear stream status */
1116         for (i = 0; i < chip->num_streams; i++) {
1117                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1118                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1119         }
1120
1121         /* clear STATESTS */
1122         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1123
1124         /* clear rirb status */
1125         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1126
1127         /* clear int status */
1128         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1129 }
1130
1131 /* start a stream */
1132 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1133 {
1134         /*
1135          * Before stream start, initialize parameter
1136          */
1137         azx_dev->insufficient = 1;
1138
1139         /* enable SIE */
1140         azx_writel(chip, INTCTL,
1141                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1142         /* set DMA start and interrupt mask */
1143         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1144                       SD_CTL_DMA_START | SD_INT_MASK);
1145 }
1146
1147 /* stop DMA */
1148 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1149 {
1150         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1151                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1152         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1153 }
1154
1155 /* stop a stream */
1156 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1157 {
1158         azx_stream_clear(chip, azx_dev);
1159         /* disable SIE */
1160         azx_writel(chip, INTCTL,
1161                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1162 }
1163
1164
1165 /*
1166  * reset and start the controller registers
1167  */
1168 static void azx_init_chip(struct azx *chip, int full_reset)
1169 {
1170         if (chip->initialized)
1171                 return;
1172
1173         /* reset controller */
1174         azx_reset(chip, full_reset);
1175
1176         /* initialize interrupts */
1177         azx_int_clear(chip);
1178         azx_int_enable(chip);
1179
1180         /* initialize the codec command I/O */
1181         if (!chip->single_cmd)
1182                 azx_init_cmd_io(chip);
1183
1184         /* program the position buffer */
1185         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1186         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1187
1188         chip->initialized = 1;
1189 }
1190
1191 /*
1192  * initialize the PCI registers
1193  */
1194 /* update bits in a PCI register byte */
1195 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1196                             unsigned char mask, unsigned char val)
1197 {
1198         unsigned char data;
1199
1200         pci_read_config_byte(pci, reg, &data);
1201         data &= ~mask;
1202         data |= (val & mask);
1203         pci_write_config_byte(pci, reg, data);
1204 }
1205
1206 static void azx_init_pci(struct azx *chip)
1207 {
1208         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1209          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1210          * Ensuring these bits are 0 clears playback static on some HD Audio
1211          * codecs.
1212          * The PCI register TCSEL is defined in the Intel manuals.
1213          */
1214         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1215                 snd_printdd(SFX "Clearing TCSEL\n");
1216                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1217         }
1218
1219         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1220          * we need to enable snoop.
1221          */
1222         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1223                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1224                 update_pci_byte(chip->pci,
1225                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1226                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1227         }
1228
1229         /* For NVIDIA HDA, enable snoop */
1230         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1231                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1232                 update_pci_byte(chip->pci,
1233                                 NVIDIA_HDA_TRANSREG_ADDR,
1234                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1235                 update_pci_byte(chip->pci,
1236                                 NVIDIA_HDA_ISTRM_COH,
1237                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1238                 update_pci_byte(chip->pci,
1239                                 NVIDIA_HDA_OSTRM_COH,
1240                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1241         }
1242
1243         /* Enable SCH/PCH snoop if needed */
1244         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1245                 unsigned short snoop;
1246                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1247                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1248                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1249                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1250                         if (!azx_snoop(chip))
1251                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1252                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1253                         pci_read_config_word(chip->pci,
1254                                 INTEL_SCH_HDA_DEVC, &snoop);
1255                 }
1256                 snd_printdd(SFX "SCH snoop: %s\n",
1257                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1258                                 ? "Disabled" : "Enabled");
1259         }
1260 }
1261
1262
1263 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1264
1265 /*
1266  * interrupt handler
1267  */
1268 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1269 {
1270         struct azx *chip = dev_id;
1271         struct azx_dev *azx_dev;
1272         u32 status;
1273         u8 sd_status;
1274         int i, ok;
1275
1276         spin_lock(&chip->reg_lock);
1277
1278         if (chip->disabled) {
1279                 spin_unlock(&chip->reg_lock);
1280                 return IRQ_NONE;
1281         }
1282
1283         status = azx_readl(chip, INTSTS);
1284         if (status == 0) {
1285                 spin_unlock(&chip->reg_lock);
1286                 return IRQ_NONE;
1287         }
1288
1289         for (i = 0; i < chip->num_streams; i++) {
1290                 azx_dev = &chip->azx_dev[i];
1291                 if (status & azx_dev->sd_int_sta_mask) {
1292                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1293                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1294                         if (!azx_dev->substream || !azx_dev->running ||
1295                             !(sd_status & SD_INT_COMPLETE))
1296                                 continue;
1297                         /* check whether this IRQ is really acceptable */
1298                         ok = azx_position_ok(chip, azx_dev);
1299                         if (ok == 1) {
1300                                 azx_dev->irq_pending = 0;
1301                                 spin_unlock(&chip->reg_lock);
1302                                 snd_pcm_period_elapsed(azx_dev->substream);
1303                                 spin_lock(&chip->reg_lock);
1304                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1305                                 /* bogus IRQ, process it later */
1306                                 azx_dev->irq_pending = 1;
1307                                 queue_work(chip->bus->workq,
1308                                            &chip->irq_pending_work);
1309                         }
1310                 }
1311         }
1312
1313         /* clear rirb int */
1314         status = azx_readb(chip, RIRBSTS);
1315         if (status & RIRB_INT_MASK) {
1316                 if (status & RIRB_INT_RESPONSE) {
1317                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1318                                 udelay(80);
1319                         azx_update_rirb(chip);
1320                 }
1321                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1322         }
1323
1324 #if 0
1325         /* clear state status int */
1326         if (azx_readb(chip, STATESTS) & 0x04)
1327                 azx_writeb(chip, STATESTS, 0x04);
1328 #endif
1329         spin_unlock(&chip->reg_lock);
1330
1331         return IRQ_HANDLED;
1332 }
1333
1334
1335 /*
1336  * set up a BDL entry
1337  */
1338 static int setup_bdle(struct azx *chip,
1339                       struct snd_pcm_substream *substream,
1340                       struct azx_dev *azx_dev, u32 **bdlp,
1341                       int ofs, int size, int with_ioc)
1342 {
1343         u32 *bdl = *bdlp;
1344
1345         while (size > 0) {
1346                 dma_addr_t addr;
1347                 int chunk;
1348
1349                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1350                         return -EINVAL;
1351
1352                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1353                 /* program the address field of the BDL entry */
1354                 bdl[0] = cpu_to_le32((u32)addr);
1355                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1356                 /* program the size field of the BDL entry */
1357                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1358                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1359                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1360                         u32 remain = 0x1000 - (ofs & 0xfff);
1361                         if (chunk > remain)
1362                                 chunk = remain;
1363                 }
1364                 bdl[2] = cpu_to_le32(chunk);
1365                 /* program the IOC to enable interrupt
1366                  * only when the whole fragment is processed
1367                  */
1368                 size -= chunk;
1369                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1370                 bdl += 4;
1371                 azx_dev->frags++;
1372                 ofs += chunk;
1373         }
1374         *bdlp = bdl;
1375         return ofs;
1376 }
1377
1378 /*
1379  * set up BDL entries
1380  */
1381 static int azx_setup_periods(struct azx *chip,
1382                              struct snd_pcm_substream *substream,
1383                              struct azx_dev *azx_dev)
1384 {
1385         u32 *bdl;
1386         int i, ofs, periods, period_bytes;
1387         int pos_adj;
1388
1389         /* reset BDL address */
1390         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1391         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1392
1393         period_bytes = azx_dev->period_bytes;
1394         periods = azx_dev->bufsize / period_bytes;
1395
1396         /* program the initial BDL entries */
1397         bdl = (u32 *)azx_dev->bdl.area;
1398         ofs = 0;
1399         azx_dev->frags = 0;
1400         pos_adj = bdl_pos_adj[chip->dev_index];
1401         if (pos_adj > 0) {
1402                 struct snd_pcm_runtime *runtime = substream->runtime;
1403                 int pos_align = pos_adj;
1404                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1405                 if (!pos_adj)
1406                         pos_adj = pos_align;
1407                 else
1408                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1409                                 pos_align;
1410                 pos_adj = frames_to_bytes(runtime, pos_adj);
1411                 if (pos_adj >= period_bytes) {
1412                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1413                                    bdl_pos_adj[chip->dev_index]);
1414                         pos_adj = 0;
1415                 } else {
1416                         ofs = setup_bdle(chip, substream, azx_dev,
1417                                          &bdl, ofs, pos_adj,
1418                                          !substream->runtime->no_period_wakeup);
1419                         if (ofs < 0)
1420                                 goto error;
1421                 }
1422         } else
1423                 pos_adj = 0;
1424         for (i = 0; i < periods; i++) {
1425                 if (i == periods - 1 && pos_adj)
1426                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1427                                          period_bytes - pos_adj, 0);
1428                 else
1429                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1430                                          period_bytes,
1431                                          !substream->runtime->no_period_wakeup);
1432                 if (ofs < 0)
1433                         goto error;
1434         }
1435         return 0;
1436
1437  error:
1438         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1439                    azx_dev->bufsize, period_bytes);
1440         return -EINVAL;
1441 }
1442
1443 /* reset stream */
1444 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1445 {
1446         unsigned char val;
1447         int timeout;
1448
1449         azx_stream_clear(chip, azx_dev);
1450
1451         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1452                       SD_CTL_STREAM_RESET);
1453         udelay(3);
1454         timeout = 300;
1455         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1456                --timeout)
1457                 ;
1458         val &= ~SD_CTL_STREAM_RESET;
1459         azx_sd_writeb(azx_dev, SD_CTL, val);
1460         udelay(3);
1461
1462         timeout = 300;
1463         /* waiting for hardware to report that the stream is out of reset */
1464         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1465                --timeout)
1466                 ;
1467
1468         /* reset first position - may not be synced with hw at this time */
1469         *azx_dev->posbuf = 0;
1470 }
1471
1472 /*
1473  * set up the SD for streaming
1474  */
1475 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1476 {
1477         unsigned int val;
1478         /* make sure the run bit is zero for SD */
1479         azx_stream_clear(chip, azx_dev);
1480         /* program the stream_tag */
1481         val = azx_sd_readl(azx_dev, SD_CTL);
1482         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1483                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1484         if (!azx_snoop(chip))
1485                 val |= SD_CTL_TRAFFIC_PRIO;
1486         azx_sd_writel(azx_dev, SD_CTL, val);
1487
1488         /* program the length of samples in cyclic buffer */
1489         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1490
1491         /* program the stream format */
1492         /* this value needs to be the same as the one programmed */
1493         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1494
1495         /* program the stream LVI (last valid index) of the BDL */
1496         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1497
1498         /* program the BDL address */
1499         /* lower BDL address */
1500         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1501         /* upper BDL address */
1502         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1503
1504         /* enable the position buffer */
1505         if (chip->position_fix[0] != POS_FIX_LPIB ||
1506             chip->position_fix[1] != POS_FIX_LPIB) {
1507                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1508                         azx_writel(chip, DPLBASE,
1509                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1510         }
1511
1512         /* set the interrupt enable bits in the descriptor control register */
1513         azx_sd_writel(azx_dev, SD_CTL,
1514                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1515
1516         return 0;
1517 }
1518
1519 /*
1520  * Probe the given codec address
1521  */
1522 static int probe_codec(struct azx *chip, int addr)
1523 {
1524         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1525                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1526         unsigned int res;
1527
1528         mutex_lock(&chip->bus->cmd_mutex);
1529         chip->probing = 1;
1530         azx_send_cmd(chip->bus, cmd);
1531         res = azx_get_response(chip->bus, addr);
1532         chip->probing = 0;
1533         mutex_unlock(&chip->bus->cmd_mutex);
1534         if (res == -1)
1535                 return -EIO;
1536         snd_printdd(SFX "codec #%d probed OK\n", addr);
1537         return 0;
1538 }
1539
1540 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1541                                  struct hda_pcm *cpcm);
1542 static void azx_stop_chip(struct azx *chip);
1543
1544 static void azx_bus_reset(struct hda_bus *bus)
1545 {
1546         struct azx *chip = bus->private_data;
1547
1548         bus->in_reset = 1;
1549         azx_stop_chip(chip);
1550         azx_init_chip(chip, 1);
1551 #ifdef CONFIG_PM
1552         if (chip->initialized) {
1553                 struct azx_pcm *p;
1554                 list_for_each_entry(p, &chip->pcm_list, list)
1555                         snd_pcm_suspend_all(p->pcm);
1556                 snd_hda_suspend(chip->bus);
1557                 snd_hda_resume(chip->bus);
1558         }
1559 #endif
1560         bus->in_reset = 0;
1561 }
1562
1563 /*
1564  * Codec initialization
1565  */
1566
1567 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1568 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1569         [AZX_DRIVER_NVIDIA] = 8,
1570         [AZX_DRIVER_TERA] = 1,
1571 };
1572
1573 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1574 {
1575         struct hda_bus_template bus_temp;
1576         int c, codecs, err;
1577         int max_slots;
1578
1579         memset(&bus_temp, 0, sizeof(bus_temp));
1580         bus_temp.private_data = chip;
1581         bus_temp.modelname = model;
1582         bus_temp.pci = chip->pci;
1583         bus_temp.ops.command = azx_send_cmd;
1584         bus_temp.ops.get_response = azx_get_response;
1585         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1586         bus_temp.ops.bus_reset = azx_bus_reset;
1587 #ifdef CONFIG_SND_HDA_POWER_SAVE
1588         bus_temp.power_save = &power_save;
1589         bus_temp.ops.pm_notify = azx_power_notify;
1590 #endif
1591
1592         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1593         if (err < 0)
1594                 return err;
1595
1596         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1597                 snd_printd(SFX "Enable delay in RIRB handling\n");
1598                 chip->bus->needs_damn_long_delay = 1;
1599         }
1600
1601         codecs = 0;
1602         max_slots = azx_max_codecs[chip->driver_type];
1603         if (!max_slots)
1604                 max_slots = AZX_DEFAULT_CODECS;
1605
1606         /* First try to probe all given codec slots */
1607         for (c = 0; c < max_slots; c++) {
1608                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1609                         if (probe_codec(chip, c) < 0) {
1610                                 /* Some BIOSen give you wrong codec addresses
1611                                  * that don't exist
1612                                  */
1613                                 snd_printk(KERN_WARNING SFX
1614                                            "Codec #%d probe error; "
1615                                            "disabling it...\n", c);
1616                                 chip->codec_mask &= ~(1 << c);
1617                                 /* More badly, accessing to a non-existing
1618                                  * codec often screws up the controller chip,
1619                                  * and disturbs the further communications.
1620                                  * Thus if an error occurs during probing,
1621                                  * better to reset the controller chip to
1622                                  * get back to the sanity state.
1623                                  */
1624                                 azx_stop_chip(chip);
1625                                 azx_init_chip(chip, 1);
1626                         }
1627                 }
1628         }
1629
1630         /* AMD chipsets often cause the communication stalls upon certain
1631          * sequence like the pin-detection.  It seems that forcing the synced
1632          * access works around the stall.  Grrr...
1633          */
1634         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1635                 snd_printd(SFX "Enable sync_write for stable communication\n");
1636                 chip->bus->sync_write = 1;
1637                 chip->bus->allow_bus_reset = 1;
1638         }
1639
1640         /* Then create codec instances */
1641         for (c = 0; c < max_slots; c++) {
1642                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1643                         struct hda_codec *codec;
1644                         err = snd_hda_codec_new(chip->bus, c, &codec);
1645                         if (err < 0)
1646                                 continue;
1647                         codec->beep_mode = chip->beep_mode;
1648                         codecs++;
1649                 }
1650         }
1651         if (!codecs) {
1652                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1653                 return -ENXIO;
1654         }
1655         return 0;
1656 }
1657
1658 /* configure each codec instance */
1659 static int __devinit azx_codec_configure(struct azx *chip)
1660 {
1661         struct hda_codec *codec;
1662         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1663                 snd_hda_codec_configure(codec);
1664         }
1665         return 0;
1666 }
1667
1668
1669 /*
1670  * PCM support
1671  */
1672
1673 /* assign a stream for the PCM */
1674 static inline struct azx_dev *
1675 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1676 {
1677         int dev, i, nums;
1678         struct azx_dev *res = NULL;
1679         /* make a non-zero unique key for the substream */
1680         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1681                 (substream->stream + 1);
1682
1683         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1684                 dev = chip->playback_index_offset;
1685                 nums = chip->playback_streams;
1686         } else {
1687                 dev = chip->capture_index_offset;
1688                 nums = chip->capture_streams;
1689         }
1690         for (i = 0; i < nums; i++, dev++)
1691                 if (!chip->azx_dev[dev].opened) {
1692                         res = &chip->azx_dev[dev];
1693                         if (res->assigned_key == key)
1694                                 break;
1695                 }
1696         if (res) {
1697                 res->opened = 1;
1698                 res->assigned_key = key;
1699         }
1700         return res;
1701 }
1702
1703 /* release the assigned stream */
1704 static inline void azx_release_device(struct azx_dev *azx_dev)
1705 {
1706         azx_dev->opened = 0;
1707 }
1708
1709 static struct snd_pcm_hardware azx_pcm_hw = {
1710         .info =                 (SNDRV_PCM_INFO_MMAP |
1711                                  SNDRV_PCM_INFO_INTERLEAVED |
1712                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1713                                  SNDRV_PCM_INFO_MMAP_VALID |
1714                                  /* No full-resume yet implemented */
1715                                  /* SNDRV_PCM_INFO_RESUME |*/
1716                                  SNDRV_PCM_INFO_PAUSE |
1717                                  SNDRV_PCM_INFO_SYNC_START |
1718                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1719         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1720         .rates =                SNDRV_PCM_RATE_48000,
1721         .rate_min =             48000,
1722         .rate_max =             48000,
1723         .channels_min =         2,
1724         .channels_max =         2,
1725         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1726         .period_bytes_min =     128,
1727         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1728         .periods_min =          2,
1729         .periods_max =          AZX_MAX_FRAG,
1730         .fifo_size =            0,
1731 };
1732
1733 static int azx_pcm_open(struct snd_pcm_substream *substream)
1734 {
1735         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1736         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1737         struct azx *chip = apcm->chip;
1738         struct azx_dev *azx_dev;
1739         struct snd_pcm_runtime *runtime = substream->runtime;
1740         unsigned long flags;
1741         int err;
1742         int buff_step;
1743
1744         mutex_lock(&chip->open_mutex);
1745         azx_dev = azx_assign_device(chip, substream);
1746         if (azx_dev == NULL) {
1747                 mutex_unlock(&chip->open_mutex);
1748                 return -EBUSY;
1749         }
1750         runtime->hw = azx_pcm_hw;
1751         runtime->hw.channels_min = hinfo->channels_min;
1752         runtime->hw.channels_max = hinfo->channels_max;
1753         runtime->hw.formats = hinfo->formats;
1754         runtime->hw.rates = hinfo->rates;
1755         snd_pcm_limit_hw_rates(runtime);
1756         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1757         if (chip->align_buffer_size)
1758                 /* constrain buffer sizes to be multiple of 128
1759                    bytes. This is more efficient in terms of memory
1760                    access but isn't required by the HDA spec and
1761                    prevents users from specifying exact period/buffer
1762                    sizes. For example for 44.1kHz, a period size set
1763                    to 20ms will be rounded to 19.59ms. */
1764                 buff_step = 128;
1765         else
1766                 /* Don't enforce steps on buffer sizes, still need to
1767                    be multiple of 4 bytes (HDA spec). Tested on Intel
1768                    HDA controllers, may not work on all devices where
1769                    option needs to be disabled */
1770                 buff_step = 4;
1771
1772         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1773                                    buff_step);
1774         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1775                                    buff_step);
1776         snd_hda_power_up_d3wait(apcm->codec);
1777         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1778         if (err < 0) {
1779                 azx_release_device(azx_dev);
1780                 snd_hda_power_down(apcm->codec);
1781                 mutex_unlock(&chip->open_mutex);
1782                 return err;
1783         }
1784         snd_pcm_limit_hw_rates(runtime);
1785         /* sanity check */
1786         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1787             snd_BUG_ON(!runtime->hw.channels_max) ||
1788             snd_BUG_ON(!runtime->hw.formats) ||
1789             snd_BUG_ON(!runtime->hw.rates)) {
1790                 azx_release_device(azx_dev);
1791                 hinfo->ops.close(hinfo, apcm->codec, substream);
1792                 snd_hda_power_down(apcm->codec);
1793                 mutex_unlock(&chip->open_mutex);
1794                 return -EINVAL;
1795         }
1796         spin_lock_irqsave(&chip->reg_lock, flags);
1797         azx_dev->substream = substream;
1798         azx_dev->running = 0;
1799         spin_unlock_irqrestore(&chip->reg_lock, flags);
1800
1801         runtime->private_data = azx_dev;
1802         snd_pcm_set_sync(substream);
1803         mutex_unlock(&chip->open_mutex);
1804         return 0;
1805 }
1806
1807 static int azx_pcm_close(struct snd_pcm_substream *substream)
1808 {
1809         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1810         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1811         struct azx *chip = apcm->chip;
1812         struct azx_dev *azx_dev = get_azx_dev(substream);
1813         unsigned long flags;
1814
1815         mutex_lock(&chip->open_mutex);
1816         spin_lock_irqsave(&chip->reg_lock, flags);
1817         azx_dev->substream = NULL;
1818         azx_dev->running = 0;
1819         spin_unlock_irqrestore(&chip->reg_lock, flags);
1820         azx_release_device(azx_dev);
1821         hinfo->ops.close(hinfo, apcm->codec, substream);
1822         snd_hda_power_down(apcm->codec);
1823         mutex_unlock(&chip->open_mutex);
1824         return 0;
1825 }
1826
1827 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1828                              struct snd_pcm_hw_params *hw_params)
1829 {
1830         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1831         struct azx *chip = apcm->chip;
1832         struct snd_pcm_runtime *runtime = substream->runtime;
1833         struct azx_dev *azx_dev = get_azx_dev(substream);
1834         int ret;
1835
1836         mark_runtime_wc(chip, azx_dev, runtime, false);
1837         azx_dev->bufsize = 0;
1838         azx_dev->period_bytes = 0;
1839         azx_dev->format_val = 0;
1840         ret = snd_pcm_lib_malloc_pages(substream,
1841                                         params_buffer_bytes(hw_params));
1842         if (ret < 0)
1843                 return ret;
1844         mark_runtime_wc(chip, azx_dev, runtime, true);
1845         return ret;
1846 }
1847
1848 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1849 {
1850         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1851         struct azx_dev *azx_dev = get_azx_dev(substream);
1852         struct azx *chip = apcm->chip;
1853         struct snd_pcm_runtime *runtime = substream->runtime;
1854         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1855
1856         /* reset BDL address */
1857         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1858         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1859         azx_sd_writel(azx_dev, SD_CTL, 0);
1860         azx_dev->bufsize = 0;
1861         azx_dev->period_bytes = 0;
1862         azx_dev->format_val = 0;
1863
1864         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1865
1866         mark_runtime_wc(chip, azx_dev, runtime, false);
1867         return snd_pcm_lib_free_pages(substream);
1868 }
1869
1870 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1871 {
1872         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1873         struct azx *chip = apcm->chip;
1874         struct azx_dev *azx_dev = get_azx_dev(substream);
1875         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1876         struct snd_pcm_runtime *runtime = substream->runtime;
1877         unsigned int bufsize, period_bytes, format_val, stream_tag;
1878         int err;
1879         struct hda_spdif_out *spdif =
1880                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1881         unsigned short ctls = spdif ? spdif->ctls : 0;
1882
1883         azx_stream_reset(chip, azx_dev);
1884         format_val = snd_hda_calc_stream_format(runtime->rate,
1885                                                 runtime->channels,
1886                                                 runtime->format,
1887                                                 hinfo->maxbps,
1888                                                 ctls);
1889         if (!format_val) {
1890                 snd_printk(KERN_ERR SFX
1891                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1892                            runtime->rate, runtime->channels, runtime->format);
1893                 return -EINVAL;
1894         }
1895
1896         bufsize = snd_pcm_lib_buffer_bytes(substream);
1897         period_bytes = snd_pcm_lib_period_bytes(substream);
1898
1899         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1900                     bufsize, format_val);
1901
1902         if (bufsize != azx_dev->bufsize ||
1903             period_bytes != azx_dev->period_bytes ||
1904             format_val != azx_dev->format_val) {
1905                 azx_dev->bufsize = bufsize;
1906                 azx_dev->period_bytes = period_bytes;
1907                 azx_dev->format_val = format_val;
1908                 err = azx_setup_periods(chip, substream, azx_dev);
1909                 if (err < 0)
1910                         return err;
1911         }
1912
1913         /* wallclk has 24Mhz clock source */
1914         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1915                                                 runtime->rate) * 1000);
1916         azx_setup_controller(chip, azx_dev);
1917         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1918                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1919         else
1920                 azx_dev->fifo_size = 0;
1921
1922         stream_tag = azx_dev->stream_tag;
1923         /* CA-IBG chips need the playback stream starting from 1 */
1924         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1925             stream_tag > chip->capture_streams)
1926                 stream_tag -= chip->capture_streams;
1927         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1928                                      azx_dev->format_val, substream);
1929 }
1930
1931 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1932 {
1933         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1934         struct azx *chip = apcm->chip;
1935         struct azx_dev *azx_dev;
1936         struct snd_pcm_substream *s;
1937         int rstart = 0, start, nsync = 0, sbits = 0;
1938         int nwait, timeout;
1939
1940         switch (cmd) {
1941         case SNDRV_PCM_TRIGGER_START:
1942                 rstart = 1;
1943         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1944         case SNDRV_PCM_TRIGGER_RESUME:
1945                 start = 1;
1946                 break;
1947         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1948         case SNDRV_PCM_TRIGGER_SUSPEND:
1949         case SNDRV_PCM_TRIGGER_STOP:
1950                 start = 0;
1951                 break;
1952         default:
1953                 return -EINVAL;
1954         }
1955
1956         snd_pcm_group_for_each_entry(s, substream) {
1957                 if (s->pcm->card != substream->pcm->card)
1958                         continue;
1959                 azx_dev = get_azx_dev(s);
1960                 sbits |= 1 << azx_dev->index;
1961                 nsync++;
1962                 snd_pcm_trigger_done(s, substream);
1963         }
1964
1965         spin_lock(&chip->reg_lock);
1966         if (nsync > 1) {
1967                 /* first, set SYNC bits of corresponding streams */
1968                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1969                         azx_writel(chip, OLD_SSYNC,
1970                                    azx_readl(chip, OLD_SSYNC) | sbits);
1971                 else
1972                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1973         }
1974         snd_pcm_group_for_each_entry(s, substream) {
1975                 if (s->pcm->card != substream->pcm->card)
1976                         continue;
1977                 azx_dev = get_azx_dev(s);
1978                 if (start) {
1979                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1980                         if (!rstart)
1981                                 azx_dev->start_wallclk -=
1982                                                 azx_dev->period_wallclk;
1983                         azx_stream_start(chip, azx_dev);
1984                 } else {
1985                         azx_stream_stop(chip, azx_dev);
1986                 }
1987                 azx_dev->running = start;
1988         }
1989         spin_unlock(&chip->reg_lock);
1990         if (start) {
1991                 if (nsync == 1)
1992                         return 0;
1993                 /* wait until all FIFOs get ready */
1994                 for (timeout = 5000; timeout; timeout--) {
1995                         nwait = 0;
1996                         snd_pcm_group_for_each_entry(s, substream) {
1997                                 if (s->pcm->card != substream->pcm->card)
1998                                         continue;
1999                                 azx_dev = get_azx_dev(s);
2000                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2001                                       SD_STS_FIFO_READY))
2002                                         nwait++;
2003                         }
2004                         if (!nwait)
2005                                 break;
2006                         cpu_relax();
2007                 }
2008         } else {
2009                 /* wait until all RUN bits are cleared */
2010                 for (timeout = 5000; timeout; timeout--) {
2011                         nwait = 0;
2012                         snd_pcm_group_for_each_entry(s, substream) {
2013                                 if (s->pcm->card != substream->pcm->card)
2014                                         continue;
2015                                 azx_dev = get_azx_dev(s);
2016                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2017                                     SD_CTL_DMA_START)
2018                                         nwait++;
2019                         }
2020                         if (!nwait)
2021                                 break;
2022                         cpu_relax();
2023                 }
2024         }
2025         if (nsync > 1) {
2026                 spin_lock(&chip->reg_lock);
2027                 /* reset SYNC bits */
2028                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2029                         azx_writel(chip, OLD_SSYNC,
2030                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
2031                 else
2032                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2033                 spin_unlock(&chip->reg_lock);
2034         }
2035         return 0;
2036 }
2037
2038 /* get the current DMA position with correction on VIA chips */
2039 static unsigned int azx_via_get_position(struct azx *chip,
2040                                          struct azx_dev *azx_dev)
2041 {
2042         unsigned int link_pos, mini_pos, bound_pos;
2043         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2044         unsigned int fifo_size;
2045
2046         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2047         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2048                 /* Playback, no problem using link position */
2049                 return link_pos;
2050         }
2051
2052         /* Capture */
2053         /* For new chipset,
2054          * use mod to get the DMA position just like old chipset
2055          */
2056         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2057         mod_dma_pos %= azx_dev->period_bytes;
2058
2059         /* azx_dev->fifo_size can't get FIFO size of in stream.
2060          * Get from base address + offset.
2061          */
2062         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2063
2064         if (azx_dev->insufficient) {
2065                 /* Link position never gather than FIFO size */
2066                 if (link_pos <= fifo_size)
2067                         return 0;
2068
2069                 azx_dev->insufficient = 0;
2070         }
2071
2072         if (link_pos <= fifo_size)
2073                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2074         else
2075                 mini_pos = link_pos - fifo_size;
2076
2077         /* Find nearest previous boudary */
2078         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2079         mod_link_pos = link_pos % azx_dev->period_bytes;
2080         if (mod_link_pos >= fifo_size)
2081                 bound_pos = link_pos - mod_link_pos;
2082         else if (mod_dma_pos >= mod_mini_pos)
2083                 bound_pos = mini_pos - mod_mini_pos;
2084         else {
2085                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2086                 if (bound_pos >= azx_dev->bufsize)
2087                         bound_pos = 0;
2088         }
2089
2090         /* Calculate real DMA position we want */
2091         return bound_pos + mod_dma_pos;
2092 }
2093
2094 static unsigned int azx_get_position(struct azx *chip,
2095                                      struct azx_dev *azx_dev,
2096                                      bool with_check)
2097 {
2098         unsigned int pos;
2099         int stream = azx_dev->substream->stream;
2100
2101         switch (chip->position_fix[stream]) {
2102         case POS_FIX_LPIB:
2103                 /* read LPIB */
2104                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2105                 break;
2106         case POS_FIX_VIACOMBO:
2107                 pos = azx_via_get_position(chip, azx_dev);
2108                 break;
2109         default:
2110                 /* use the position buffer */
2111                 pos = le32_to_cpu(*azx_dev->posbuf);
2112                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2113                         if (!pos || pos == (u32)-1) {
2114                                 printk(KERN_WARNING
2115                                        "hda-intel: Invalid position buffer, "
2116                                        "using LPIB read method instead.\n");
2117                                 chip->position_fix[stream] = POS_FIX_LPIB;
2118                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2119                         } else
2120                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2121                 }
2122                 break;
2123         }
2124
2125         if (pos >= azx_dev->bufsize)
2126                 pos = 0;
2127         return pos;
2128 }
2129
2130 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2131 {
2132         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2133         struct azx *chip = apcm->chip;
2134         struct azx_dev *azx_dev = get_azx_dev(substream);
2135         return bytes_to_frames(substream->runtime,
2136                                azx_get_position(chip, azx_dev, false));
2137 }
2138
2139 /*
2140  * Check whether the current DMA position is acceptable for updating
2141  * periods.  Returns non-zero if it's OK.
2142  *
2143  * Many HD-audio controllers appear pretty inaccurate about
2144  * the update-IRQ timing.  The IRQ is issued before actually the
2145  * data is processed.  So, we need to process it afterwords in a
2146  * workqueue.
2147  */
2148 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2149 {
2150         u32 wallclk;
2151         unsigned int pos;
2152         int stream;
2153
2154         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2155         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2156                 return -1;      /* bogus (too early) interrupt */
2157
2158         stream = azx_dev->substream->stream;
2159         pos = azx_get_position(chip, azx_dev, true);
2160
2161         if (WARN_ONCE(!azx_dev->period_bytes,
2162                       "hda-intel: zero azx_dev->period_bytes"))
2163                 return -1; /* this shouldn't happen! */
2164         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2165             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2166                 /* NG - it's below the first next period boundary */
2167                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2168         azx_dev->start_wallclk += wallclk;
2169         return 1; /* OK, it's fine */
2170 }
2171
2172 /*
2173  * The work for pending PCM period updates.
2174  */
2175 static void azx_irq_pending_work(struct work_struct *work)
2176 {
2177         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2178         int i, pending, ok;
2179
2180         if (!chip->irq_pending_warned) {
2181                 printk(KERN_WARNING
2182                        "hda-intel: IRQ timing workaround is activated "
2183                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2184                        chip->card->number);
2185                 chip->irq_pending_warned = 1;
2186         }
2187
2188         for (;;) {
2189                 pending = 0;
2190                 spin_lock_irq(&chip->reg_lock);
2191                 for (i = 0; i < chip->num_streams; i++) {
2192                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2193                         if (!azx_dev->irq_pending ||
2194                             !azx_dev->substream ||
2195                             !azx_dev->running)
2196                                 continue;
2197                         ok = azx_position_ok(chip, azx_dev);
2198                         if (ok > 0) {
2199                                 azx_dev->irq_pending = 0;
2200                                 spin_unlock(&chip->reg_lock);
2201                                 snd_pcm_period_elapsed(azx_dev->substream);
2202                                 spin_lock(&chip->reg_lock);
2203                         } else if (ok < 0) {
2204                                 pending = 0;    /* too early */
2205                         } else
2206                                 pending++;
2207                 }
2208                 spin_unlock_irq(&chip->reg_lock);
2209                 if (!pending)
2210                         return;
2211                 msleep(1);
2212         }
2213 }
2214
2215 /* clear irq_pending flags and assure no on-going workq */
2216 static void azx_clear_irq_pending(struct azx *chip)
2217 {
2218         int i;
2219
2220         spin_lock_irq(&chip->reg_lock);
2221         for (i = 0; i < chip->num_streams; i++)
2222                 chip->azx_dev[i].irq_pending = 0;
2223         spin_unlock_irq(&chip->reg_lock);
2224 }
2225
2226 #ifdef CONFIG_X86
2227 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2228                         struct vm_area_struct *area)
2229 {
2230         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2231         struct azx *chip = apcm->chip;
2232         if (!azx_snoop(chip))
2233                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2234         return snd_pcm_lib_default_mmap(substream, area);
2235 }
2236 #else
2237 #define azx_pcm_mmap    NULL
2238 #endif
2239
2240 static struct snd_pcm_ops azx_pcm_ops = {
2241         .open = azx_pcm_open,
2242         .close = azx_pcm_close,
2243         .ioctl = snd_pcm_lib_ioctl,
2244         .hw_params = azx_pcm_hw_params,
2245         .hw_free = azx_pcm_hw_free,
2246         .prepare = azx_pcm_prepare,
2247         .trigger = azx_pcm_trigger,
2248         .pointer = azx_pcm_pointer,
2249         .mmap = azx_pcm_mmap,
2250         .page = snd_pcm_sgbuf_ops_page,
2251 };
2252
2253 static void azx_pcm_free(struct snd_pcm *pcm)
2254 {
2255         struct azx_pcm *apcm = pcm->private_data;
2256         if (apcm) {
2257                 list_del(&apcm->list);
2258                 kfree(apcm);
2259         }
2260 }
2261
2262 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2263
2264 static int
2265 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2266                       struct hda_pcm *cpcm)
2267 {
2268         struct azx *chip = bus->private_data;
2269         struct snd_pcm *pcm;
2270         struct azx_pcm *apcm;
2271         int pcm_dev = cpcm->device;
2272         unsigned int size;
2273         int s, err;
2274
2275         list_for_each_entry(apcm, &chip->pcm_list, list) {
2276                 if (apcm->pcm->device == pcm_dev) {
2277                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2278                         return -EBUSY;
2279                 }
2280         }
2281         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2282                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2283                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2284                           &pcm);
2285         if (err < 0)
2286                 return err;
2287         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2288         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2289         if (apcm == NULL)
2290                 return -ENOMEM;
2291         apcm->chip = chip;
2292         apcm->pcm = pcm;
2293         apcm->codec = codec;
2294         pcm->private_data = apcm;
2295         pcm->private_free = azx_pcm_free;
2296         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2297                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2298         list_add_tail(&apcm->list, &chip->pcm_list);
2299         cpcm->pcm = pcm;
2300         for (s = 0; s < 2; s++) {
2301                 apcm->hinfo[s] = &cpcm->stream[s];
2302                 if (cpcm->stream[s].substreams)
2303                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2304         }
2305         /* buffer pre-allocation */
2306         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2307         if (size > MAX_PREALLOC_SIZE)
2308                 size = MAX_PREALLOC_SIZE;
2309         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2310                                               snd_dma_pci_data(chip->pci),
2311                                               size, MAX_PREALLOC_SIZE);
2312         return 0;
2313 }
2314
2315 /*
2316  * mixer creation - all stuff is implemented in hda module
2317  */
2318 static int __devinit azx_mixer_create(struct azx *chip)
2319 {
2320         return snd_hda_build_controls(chip->bus);
2321 }
2322
2323
2324 /*
2325  * initialize SD streams
2326  */
2327 static int __devinit azx_init_stream(struct azx *chip)
2328 {
2329         int i;
2330
2331         /* initialize each stream (aka device)
2332          * assign the starting bdl address to each stream (device)
2333          * and initialize
2334          */
2335         for (i = 0; i < chip->num_streams; i++) {
2336                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2337                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2338                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2339                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2340                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2341                 azx_dev->sd_int_sta_mask = 1 << i;
2342                 /* stream tag: must be non-zero and unique */
2343                 azx_dev->index = i;
2344                 azx_dev->stream_tag = i + 1;
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2351 {
2352         if (request_irq(chip->pci->irq, azx_interrupt,
2353                         chip->msi ? 0 : IRQF_SHARED,
2354                         KBUILD_MODNAME, chip)) {
2355                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2356                        "disabling device\n", chip->pci->irq);
2357                 if (do_disconnect)
2358                         snd_card_disconnect(chip->card);
2359                 return -1;
2360         }
2361         chip->irq = chip->pci->irq;
2362         pci_intx(chip->pci, !chip->msi);
2363         return 0;
2364 }
2365
2366
2367 static void azx_stop_chip(struct azx *chip)
2368 {
2369         if (!chip->initialized)
2370                 return;
2371
2372         /* disable interrupts */
2373         azx_int_disable(chip);
2374         azx_int_clear(chip);
2375
2376         /* disable CORB/RIRB */
2377         azx_free_cmd_io(chip);
2378
2379         /* disable position buffer */
2380         azx_writel(chip, DPLBASE, 0);
2381         azx_writel(chip, DPUBASE, 0);
2382
2383         chip->initialized = 0;
2384 }
2385
2386 #ifdef CONFIG_SND_HDA_POWER_SAVE
2387 /* power-up/down the controller */
2388 static void azx_power_notify(struct hda_bus *bus)
2389 {
2390         struct azx *chip = bus->private_data;
2391         struct hda_codec *c;
2392         int power_on = 0;
2393
2394         list_for_each_entry(c, &bus->codec_list, list) {
2395                 if (c->power_on) {
2396                         power_on = 1;
2397                         break;
2398                 }
2399         }
2400         if (power_on)
2401                 azx_init_chip(chip, 1);
2402         else if (chip->running && power_save_controller &&
2403                  !bus->power_keep_link_on)
2404                 azx_stop_chip(chip);
2405 }
2406 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2407
2408 #ifdef CONFIG_PM
2409 /*
2410  * power management
2411  */
2412
2413 static int azx_suspend(struct device *dev)
2414 {
2415         struct pci_dev *pci = to_pci_dev(dev);
2416         struct snd_card *card = dev_get_drvdata(dev);
2417         struct azx *chip = card->private_data;
2418         struct azx_pcm *p;
2419
2420         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2421         azx_clear_irq_pending(chip);
2422         list_for_each_entry(p, &chip->pcm_list, list)
2423                 snd_pcm_suspend_all(p->pcm);
2424         if (chip->initialized)
2425                 snd_hda_suspend(chip->bus);
2426         azx_stop_chip(chip);
2427         if (chip->irq >= 0) {
2428                 free_irq(chip->irq, chip);
2429                 chip->irq = -1;
2430         }
2431         if (chip->msi)
2432                 pci_disable_msi(chip->pci);
2433         pci_disable_device(pci);
2434         pci_save_state(pci);
2435         pci_set_power_state(pci, PCI_D3hot);
2436         return 0;
2437 }
2438
2439 static int azx_resume(struct device *dev)
2440 {
2441         struct pci_dev *pci = to_pci_dev(dev);
2442         struct snd_card *card = dev_get_drvdata(dev);
2443         struct azx *chip = card->private_data;
2444
2445         pci_set_power_state(pci, PCI_D0);
2446         pci_restore_state(pci);
2447         if (pci_enable_device(pci) < 0) {
2448                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2449                        "disabling device\n");
2450                 snd_card_disconnect(card);
2451                 return -EIO;
2452         }
2453         pci_set_master(pci);
2454         if (chip->msi)
2455                 if (pci_enable_msi(pci) < 0)
2456                         chip->msi = 0;
2457         if (azx_acquire_irq(chip, 1) < 0)
2458                 return -EIO;
2459         azx_init_pci(chip);
2460
2461         azx_init_chip(chip, 1);
2462
2463         snd_hda_resume(chip->bus);
2464         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2465         return 0;
2466 }
2467 static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2468 #define AZX_PM_OPS      &azx_pm
2469 #else
2470 #define azx_suspend(dev)
2471 #define azx_resume(dev)
2472 #define AZX_PM_OPS      NULL
2473 #endif /* CONFIG_PM */
2474
2475
2476 /*
2477  * reboot notifier for hang-up problem at power-down
2478  */
2479 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2480 {
2481         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2482         snd_hda_bus_reboot_notify(chip->bus);
2483         azx_stop_chip(chip);
2484         return NOTIFY_OK;
2485 }
2486
2487 static void azx_notifier_register(struct azx *chip)
2488 {
2489         chip->reboot_notifier.notifier_call = azx_halt;
2490         register_reboot_notifier(&chip->reboot_notifier);
2491 }
2492
2493 static void azx_notifier_unregister(struct azx *chip)
2494 {
2495         if (chip->reboot_notifier.notifier_call)
2496                 unregister_reboot_notifier(&chip->reboot_notifier);
2497 }
2498
2499 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2500 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2501
2502 #ifdef SUPPORT_VGA_SWITCHEROO
2503 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2504
2505 static void azx_vs_set_state(struct pci_dev *pci,
2506                              enum vga_switcheroo_state state)
2507 {
2508         struct snd_card *card = pci_get_drvdata(pci);
2509         struct azx *chip = card->private_data;
2510         bool disabled;
2511
2512         if (chip->init_failed)
2513                 return;
2514
2515         disabled = (state == VGA_SWITCHEROO_OFF);
2516         if (chip->disabled == disabled)
2517                 return;
2518
2519         if (!chip->bus) {
2520                 chip->disabled = disabled;
2521                 if (!disabled) {
2522                         snd_printk(KERN_INFO SFX
2523                                    "%s: Start delayed initialization\n",
2524                                    pci_name(chip->pci));
2525                         if (azx_first_init(chip) < 0 ||
2526                             azx_probe_continue(chip) < 0) {
2527                                 snd_printk(KERN_ERR SFX
2528                                            "%s: initialization error\n",
2529                                            pci_name(chip->pci));
2530                                 chip->init_failed = true;
2531                         }
2532                 }
2533         } else {
2534                 snd_printk(KERN_INFO SFX
2535                            "%s %s via VGA-switcheroo\n",
2536                            disabled ? "Disabling" : "Enabling",
2537                            pci_name(chip->pci));
2538                 if (disabled) {
2539                         azx_suspend(&pci->dev);
2540                         chip->disabled = true;
2541                         snd_hda_lock_devices(chip->bus);
2542                 } else {
2543                         snd_hda_unlock_devices(chip->bus);
2544                         chip->disabled = false;
2545                         azx_resume(&pci->dev);
2546                 }
2547         }
2548 }
2549
2550 static bool azx_vs_can_switch(struct pci_dev *pci)
2551 {
2552         struct snd_card *card = pci_get_drvdata(pci);
2553         struct azx *chip = card->private_data;
2554
2555         if (chip->init_failed)
2556                 return false;
2557         if (chip->disabled || !chip->bus)
2558                 return true;
2559         if (snd_hda_lock_devices(chip->bus))
2560                 return false;
2561         snd_hda_unlock_devices(chip->bus);
2562         return true;
2563 }
2564
2565 static void __devinit init_vga_switcheroo(struct azx *chip)
2566 {
2567         struct pci_dev *p = get_bound_vga(chip->pci);
2568         if (p) {
2569                 snd_printk(KERN_INFO SFX
2570                            "%s: Handle VGA-switcheroo audio client\n",
2571                            pci_name(chip->pci));
2572                 chip->use_vga_switcheroo = 1;
2573                 pci_dev_put(p);
2574         }
2575 }
2576
2577 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2578         .set_gpu_state = azx_vs_set_state,
2579         .can_switch = azx_vs_can_switch,
2580 };
2581
2582 static int __devinit register_vga_switcheroo(struct azx *chip)
2583 {
2584         if (!chip->use_vga_switcheroo)
2585                 return 0;
2586         /* FIXME: currently only handling DIS controller
2587          * is there any machine with two switchable HDMI audio controllers?
2588          */
2589         return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2590                                                     VGA_SWITCHEROO_DIS,
2591                                                     chip->bus != NULL);
2592 }
2593 #else
2594 #define init_vga_switcheroo(chip)               /* NOP */
2595 #define register_vga_switcheroo(chip)           0
2596 #define check_hdmi_disabled(pci)        false
2597 #endif /* SUPPORT_VGA_SWITCHER */
2598
2599 /*
2600  * destructor
2601  */
2602 static int azx_free(struct azx *chip)
2603 {
2604         int i;
2605
2606         azx_notifier_unregister(chip);
2607
2608         if (use_vga_switcheroo(chip)) {
2609                 if (chip->disabled && chip->bus)
2610                         snd_hda_unlock_devices(chip->bus);
2611                 vga_switcheroo_unregister_client(chip->pci);
2612         }
2613
2614         if (chip->initialized) {
2615                 azx_clear_irq_pending(chip);
2616                 for (i = 0; i < chip->num_streams; i++)
2617                         azx_stream_stop(chip, &chip->azx_dev[i]);
2618                 azx_stop_chip(chip);
2619         }
2620
2621         if (chip->irq >= 0)
2622                 free_irq(chip->irq, (void*)chip);
2623         if (chip->msi)
2624                 pci_disable_msi(chip->pci);
2625         if (chip->remap_addr)
2626                 iounmap(chip->remap_addr);
2627
2628         if (chip->azx_dev) {
2629                 for (i = 0; i < chip->num_streams; i++)
2630                         if (chip->azx_dev[i].bdl.area) {
2631                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2632                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2633                         }
2634         }
2635         if (chip->rb.area) {
2636                 mark_pages_wc(chip, &chip->rb, false);
2637                 snd_dma_free_pages(&chip->rb);
2638         }
2639         if (chip->posbuf.area) {
2640                 mark_pages_wc(chip, &chip->posbuf, false);
2641                 snd_dma_free_pages(&chip->posbuf);
2642         }
2643         if (chip->region_requested)
2644                 pci_release_regions(chip->pci);
2645         pci_disable_device(chip->pci);
2646         kfree(chip->azx_dev);
2647 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2648         if (chip->fw)
2649                 release_firmware(chip->fw);
2650 #endif
2651         kfree(chip);
2652
2653         return 0;
2654 }
2655
2656 static int azx_dev_free(struct snd_device *device)
2657 {
2658         return azx_free(device->device_data);
2659 }
2660
2661 #ifdef SUPPORT_VGA_SWITCHEROO
2662 /*
2663  * Check of disabled HDMI controller by vga-switcheroo
2664  */
2665 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2666 {
2667         struct pci_dev *p;
2668
2669         /* check only discrete GPU */
2670         switch (pci->vendor) {
2671         case PCI_VENDOR_ID_ATI:
2672         case PCI_VENDOR_ID_AMD:
2673         case PCI_VENDOR_ID_NVIDIA:
2674                 if (pci->devfn == 1) {
2675                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2676                                                         pci->bus->number, 0);
2677                         if (p) {
2678                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2679                                         return p;
2680                                 pci_dev_put(p);
2681                         }
2682                 }
2683                 break;
2684         }
2685         return NULL;
2686 }
2687
2688 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2689 {
2690         bool vga_inactive = false;
2691         struct pci_dev *p = get_bound_vga(pci);
2692
2693         if (p) {
2694                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2695                         vga_inactive = true;
2696                 pci_dev_put(p);
2697         }
2698         return vga_inactive;
2699 }
2700 #endif /* SUPPORT_VGA_SWITCHEROO */
2701
2702 /*
2703  * white/black-listing for position_fix
2704  */
2705 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2706         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2707         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2708         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2709         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2710         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2711         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2712         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2713         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2714         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2715         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2716         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2717         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2718         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2719         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2720         {}
2721 };
2722
2723 static int __devinit check_position_fix(struct azx *chip, int fix)
2724 {
2725         const struct snd_pci_quirk *q;
2726
2727         switch (fix) {
2728         case POS_FIX_LPIB:
2729         case POS_FIX_POSBUF:
2730         case POS_FIX_VIACOMBO:
2731         case POS_FIX_COMBO:
2732                 return fix;
2733         }
2734
2735         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2736         if (q) {
2737                 printk(KERN_INFO
2738                        "hda_intel: position_fix set to %d "
2739                        "for device %04x:%04x\n",
2740                        q->value, q->subvendor, q->subdevice);
2741                 return q->value;
2742         }
2743
2744         /* Check VIA/ATI HD Audio Controller exist */
2745         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2746                 snd_printd(SFX "Using VIACOMBO position fix\n");
2747                 return POS_FIX_VIACOMBO;
2748         }
2749         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2750                 snd_printd(SFX "Using LPIB position fix\n");
2751                 return POS_FIX_LPIB;
2752         }
2753         if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2754                 snd_printd(SFX "Using COMBO position fix\n");
2755                 return POS_FIX_COMBO;
2756         }
2757         return POS_FIX_AUTO;
2758 }
2759
2760 /*
2761  * black-lists for probe_mask
2762  */
2763 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2764         /* Thinkpad often breaks the controller communication when accessing
2765          * to the non-working (or non-existing) modem codec slot.
2766          */
2767         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2768         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2769         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2770         /* broken BIOS */
2771         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2772         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2773         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2774         /* forced codec slots */
2775         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2776         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2777         /* WinFast VP200 H (Teradici) user reported broken communication */
2778         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2779         {}
2780 };
2781
2782 #define AZX_FORCE_CODEC_MASK    0x100
2783
2784 static void __devinit check_probe_mask(struct azx *chip, int dev)
2785 {
2786         const struct snd_pci_quirk *q;
2787
2788         chip->codec_probe_mask = probe_mask[dev];
2789         if (chip->codec_probe_mask == -1) {
2790                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2791                 if (q) {
2792                         printk(KERN_INFO
2793                                "hda_intel: probe_mask set to 0x%x "
2794                                "for device %04x:%04x\n",
2795                                q->value, q->subvendor, q->subdevice);
2796                         chip->codec_probe_mask = q->value;
2797                 }
2798         }
2799
2800         /* check forced option */
2801         if (chip->codec_probe_mask != -1 &&
2802             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2803                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2804                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2805                        chip->codec_mask);
2806         }
2807 }
2808
2809 /*
2810  * white/black-list for enable_msi
2811  */
2812 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2813         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2814         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2815         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2816         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2817         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2818         {}
2819 };
2820
2821 static void __devinit check_msi(struct azx *chip)
2822 {
2823         const struct snd_pci_quirk *q;
2824
2825         if (enable_msi >= 0) {
2826                 chip->msi = !!enable_msi;
2827                 return;
2828         }
2829         chip->msi = 1;  /* enable MSI as default */
2830         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2831         if (q) {
2832                 printk(KERN_INFO
2833                        "hda_intel: msi for device %04x:%04x set to %d\n",
2834                        q->subvendor, q->subdevice, q->value);
2835                 chip->msi = q->value;
2836                 return;
2837         }
2838
2839         /* NVidia chipsets seem to cause troubles with MSI */
2840         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2841                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2842                 chip->msi = 0;
2843         }
2844 }
2845
2846 /* check the snoop mode availability */
2847 static void __devinit azx_check_snoop_available(struct azx *chip)
2848 {
2849         bool snoop = chip->snoop;
2850
2851         switch (chip->driver_type) {
2852         case AZX_DRIVER_VIA:
2853                 /* force to non-snoop mode for a new VIA controller
2854                  * when BIOS is set
2855                  */
2856                 if (snoop) {
2857                         u8 val;
2858                         pci_read_config_byte(chip->pci, 0x42, &val);
2859                         if (!(val & 0x80) && chip->pci->revision == 0x30)
2860                                 snoop = false;
2861                 }
2862                 break;
2863         case AZX_DRIVER_ATIHDMI_NS:
2864                 /* new ATI HDMI requires non-snoop */
2865                 snoop = false;
2866                 break;
2867         }
2868
2869         if (snoop != chip->snoop) {
2870                 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2871                            snoop ? "snoop" : "non-snoop");
2872                 chip->snoop = snoop;
2873         }
2874 }
2875
2876 /*
2877  * constructor
2878  */
2879 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2880                                 int dev, unsigned int driver_caps,
2881                                 struct azx **rchip)
2882 {
2883         static struct snd_device_ops ops = {
2884                 .dev_free = azx_dev_free,
2885         };
2886         struct azx *chip;
2887         int err;
2888
2889         *rchip = NULL;
2890
2891         err = pci_enable_device(pci);
2892         if (err < 0)
2893                 return err;
2894
2895         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2896         if (!chip) {
2897                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2898                 pci_disable_device(pci);
2899                 return -ENOMEM;
2900         }
2901
2902         spin_lock_init(&chip->reg_lock);
2903         mutex_init(&chip->open_mutex);
2904         chip->card = card;
2905         chip->pci = pci;
2906         chip->irq = -1;
2907         chip->driver_caps = driver_caps;
2908         chip->driver_type = driver_caps & 0xff;
2909         check_msi(chip);
2910         chip->dev_index = dev;
2911         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2912         INIT_LIST_HEAD(&chip->pcm_list);
2913         init_vga_switcheroo(chip);
2914
2915         chip->position_fix[0] = chip->position_fix[1] =
2916                 check_position_fix(chip, position_fix[dev]);
2917         /* combo mode uses LPIB for playback */
2918         if (chip->position_fix[0] == POS_FIX_COMBO) {
2919                 chip->position_fix[0] = POS_FIX_LPIB;
2920                 chip->position_fix[1] = POS_FIX_AUTO;
2921         }
2922
2923         check_probe_mask(chip, dev);
2924
2925         chip->single_cmd = single_cmd;
2926         chip->snoop = hda_snoop;
2927         azx_check_snoop_available(chip);
2928
2929         if (bdl_pos_adj[dev] < 0) {
2930                 switch (chip->driver_type) {
2931                 case AZX_DRIVER_ICH:
2932                 case AZX_DRIVER_PCH:
2933                         bdl_pos_adj[dev] = 1;
2934                         break;
2935                 default:
2936                         bdl_pos_adj[dev] = 32;
2937                         break;
2938                 }
2939         }
2940
2941         if (check_hdmi_disabled(pci)) {
2942                 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2943                            pci_name(pci));
2944                 if (use_vga_switcheroo(chip)) {
2945                         snd_printk(KERN_INFO SFX "Delaying initialization\n");
2946                         chip->disabled = true;
2947                         goto ok;
2948                 }
2949                 kfree(chip);
2950                 pci_disable_device(pci);
2951                 return -ENXIO;
2952         }
2953
2954         err = azx_first_init(chip);
2955         if (err < 0) {
2956                 azx_free(chip);
2957                 return err;
2958         }
2959
2960  ok:
2961         err = register_vga_switcheroo(chip);
2962         if (err < 0) {
2963                 snd_printk(KERN_ERR SFX
2964                            "Error registering VGA-switcheroo client\n");
2965                 azx_free(chip);
2966                 return err;
2967         }
2968
2969         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2970         if (err < 0) {
2971                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2972                 azx_free(chip);
2973                 return err;
2974         }
2975
2976         *rchip = chip;
2977         return 0;
2978 }
2979
2980 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
2981 {
2982         int dev = chip->dev_index;
2983         struct pci_dev *pci = chip->pci;
2984         struct snd_card *card = chip->card;
2985         int i, err;
2986         unsigned short gcap;
2987
2988 #if BITS_PER_LONG != 64
2989         /* Fix up base address on ULI M5461 */
2990         if (chip->driver_type == AZX_DRIVER_ULI) {
2991                 u16 tmp3;
2992                 pci_read_config_word(pci, 0x40, &tmp3);
2993                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2994                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2995         }
2996 #endif
2997
2998         err = pci_request_regions(pci, "ICH HD audio");
2999         if (err < 0)
3000                 return err;
3001         chip->region_requested = 1;
3002
3003         chip->addr = pci_resource_start(pci, 0);
3004         chip->remap_addr = pci_ioremap_bar(pci, 0);
3005         if (chip->remap_addr == NULL) {
3006                 snd_printk(KERN_ERR SFX "ioremap error\n");
3007                 return -ENXIO;
3008         }
3009
3010         if (chip->msi)
3011                 if (pci_enable_msi(pci) < 0)
3012                         chip->msi = 0;
3013
3014         if (azx_acquire_irq(chip, 0) < 0)
3015                 return -EBUSY;
3016
3017         pci_set_master(pci);
3018         synchronize_irq(chip->irq);
3019
3020         gcap = azx_readw(chip, GCAP);
3021         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3022
3023         /* disable SB600 64bit support for safety */
3024         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3025                 struct pci_dev *p_smbus;
3026                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3027                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3028                                          NULL);
3029                 if (p_smbus) {
3030                         if (p_smbus->revision < 0x30)
3031                                 gcap &= ~ICH6_GCAP_64OK;
3032                         pci_dev_put(p_smbus);
3033                 }
3034         }
3035
3036         /* disable 64bit DMA address on some devices */
3037         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3038                 snd_printd(SFX "Disabling 64bit DMA\n");
3039                 gcap &= ~ICH6_GCAP_64OK;
3040         }
3041
3042         /* disable buffer size rounding to 128-byte multiples if supported */
3043         if (align_buffer_size >= 0)
3044                 chip->align_buffer_size = !!align_buffer_size;
3045         else {
3046                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3047                         chip->align_buffer_size = 0;
3048                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3049                         chip->align_buffer_size = 1;
3050                 else
3051                         chip->align_buffer_size = 1;
3052         }
3053
3054         /* allow 64bit DMA address if supported by H/W */
3055         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3056                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3057         else {
3058                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3059                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3060         }
3061
3062         /* read number of streams from GCAP register instead of using
3063          * hardcoded value
3064          */
3065         chip->capture_streams = (gcap >> 8) & 0x0f;
3066         chip->playback_streams = (gcap >> 12) & 0x0f;
3067         if (!chip->playback_streams && !chip->capture_streams) {
3068                 /* gcap didn't give any info, switching to old method */
3069
3070                 switch (chip->driver_type) {
3071                 case AZX_DRIVER_ULI:
3072                         chip->playback_streams = ULI_NUM_PLAYBACK;
3073                         chip->capture_streams = ULI_NUM_CAPTURE;
3074                         break;
3075                 case AZX_DRIVER_ATIHDMI:
3076                 case AZX_DRIVER_ATIHDMI_NS:
3077                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3078                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3079                         break;
3080                 case AZX_DRIVER_GENERIC:
3081                 default:
3082                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3083                         chip->capture_streams = ICH6_NUM_CAPTURE;
3084                         break;
3085                 }
3086         }
3087         chip->capture_index_offset = 0;
3088         chip->playback_index_offset = chip->capture_streams;
3089         chip->num_streams = chip->playback_streams + chip->capture_streams;
3090         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3091                                 GFP_KERNEL);
3092         if (!chip->azx_dev) {
3093                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3094                 return -ENOMEM;
3095         }
3096
3097         for (i = 0; i < chip->num_streams; i++) {
3098                 /* allocate memory for the BDL for each stream */
3099                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3100                                           snd_dma_pci_data(chip->pci),
3101                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3102                 if (err < 0) {
3103                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3104                         return -ENOMEM;
3105                 }
3106                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3107         }
3108         /* allocate memory for the position buffer */
3109         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3110                                   snd_dma_pci_data(chip->pci),
3111                                   chip->num_streams * 8, &chip->posbuf);
3112         if (err < 0) {
3113                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3114                 return -ENOMEM;
3115         }
3116         mark_pages_wc(chip, &chip->posbuf, true);
3117         /* allocate CORB/RIRB */
3118         err = azx_alloc_cmd_io(chip);
3119         if (err < 0)
3120                 return err;
3121
3122         /* initialize streams */
3123         azx_init_stream(chip);
3124
3125         /* initialize chip */
3126         azx_init_pci(chip);
3127         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3128
3129         /* codec detection */
3130         if (!chip->codec_mask) {
3131                 snd_printk(KERN_ERR SFX "no codecs found!\n");
3132                 return -ENODEV;
3133         }
3134
3135         strcpy(card->driver, "HDA-Intel");
3136         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3137                 sizeof(card->shortname));
3138         snprintf(card->longname, sizeof(card->longname),
3139                  "%s at 0x%lx irq %i",
3140                  card->shortname, chip->addr, chip->irq);
3141
3142         return 0;
3143 }
3144
3145 static void power_down_all_codecs(struct azx *chip)
3146 {
3147 #ifdef CONFIG_SND_HDA_POWER_SAVE
3148         /* The codecs were powered up in snd_hda_codec_new().
3149          * Now all initialization done, so turn them down if possible
3150          */
3151         struct hda_codec *codec;
3152         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3153                 snd_hda_power_down(codec);
3154         }
3155 #endif
3156 }
3157
3158 static int __devinit azx_probe(struct pci_dev *pci,
3159                                const struct pci_device_id *pci_id)
3160 {
3161         static int dev;
3162         struct snd_card *card;
3163         struct azx *chip;
3164         int err;
3165
3166         if (dev >= SNDRV_CARDS)
3167                 return -ENODEV;
3168         if (!enable[dev]) {
3169                 dev++;
3170                 return -ENOENT;
3171         }
3172
3173         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3174         if (err < 0) {
3175                 snd_printk(KERN_ERR SFX "Error creating card!\n");
3176                 return err;
3177         }
3178
3179         snd_card_set_dev(card, &pci->dev);
3180
3181         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3182         if (err < 0)
3183                 goto out_free;
3184         card->private_data = chip;
3185
3186 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3187         if (patch[dev] && *patch[dev]) {
3188                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3189                            patch[dev]);
3190                 err = request_firmware(&chip->fw, patch[dev], &pci->dev);
3191                 if (err < 0)
3192                         goto out_free;
3193         }
3194 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3195
3196         if (!chip->disabled) {
3197                 err = azx_probe_continue(chip);
3198                 if (err < 0)
3199                         goto out_free;
3200         }
3201
3202         pci_set_drvdata(pci, card);
3203
3204         dev++;
3205         return 0;
3206
3207 out_free:
3208         snd_card_free(card);
3209         return err;
3210 }
3211
3212 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3213 {
3214         int dev = chip->dev_index;
3215         int err;
3216
3217 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3218         chip->beep_mode = beep_mode[dev];
3219 #endif
3220
3221         /* create codec instances */
3222         err = azx_codec_create(chip, model[dev]);
3223         if (err < 0)
3224                 goto out_free;
3225 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3226         if (chip->fw) {
3227                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3228                                          chip->fw->data);
3229                 if (err < 0)
3230                         goto out_free;
3231                 release_firmware(chip->fw); /* no longer needed */
3232                 chip->fw = NULL;
3233         }
3234 #endif
3235         if ((probe_only[dev] & 1) == 0) {
3236                 err = azx_codec_configure(chip);
3237                 if (err < 0)
3238                         goto out_free;
3239         }
3240
3241         /* create PCM streams */
3242         err = snd_hda_build_pcms(chip->bus);
3243         if (err < 0)
3244                 goto out_free;
3245
3246         /* create mixer controls */
3247         err = azx_mixer_create(chip);
3248         if (err < 0)
3249                 goto out_free;
3250
3251         err = snd_card_register(chip->card);
3252         if (err < 0)
3253                 goto out_free;
3254
3255         chip->running = 1;
3256         power_down_all_codecs(chip);
3257         azx_notifier_register(chip);
3258
3259         return 0;
3260
3261 out_free:
3262         chip->init_failed = 1;
3263         return err;
3264 }
3265
3266 static void __devexit azx_remove(struct pci_dev *pci)
3267 {
3268         struct snd_card *card = pci_get_drvdata(pci);
3269         if (card)
3270                 snd_card_free(card);
3271         pci_set_drvdata(pci, NULL);
3272 }
3273
3274 /* PCI IDs */
3275 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3276         /* CPT */
3277         { PCI_DEVICE(0x8086, 0x1c20),
3278           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3279           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3280         /* PBG */
3281         { PCI_DEVICE(0x8086, 0x1d20),
3282           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3283           AZX_DCAPS_BUFSIZE},
3284         /* Panther Point */
3285         { PCI_DEVICE(0x8086, 0x1e20),
3286           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3287           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3288         /* Lynx Point */
3289         { PCI_DEVICE(0x8086, 0x8c20),
3290           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3291           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3292         /* Haswell */
3293         { PCI_DEVICE(0x8086, 0x0c0c),
3294           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3295           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3296         /* SCH */
3297         { PCI_DEVICE(0x8086, 0x811b),
3298           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3299           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3300         { PCI_DEVICE(0x8086, 0x080a),
3301           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3302           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3303         /* ICH */
3304         { PCI_DEVICE(0x8086, 0x2668),
3305           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3306           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3307         { PCI_DEVICE(0x8086, 0x27d8),
3308           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3309           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3310         { PCI_DEVICE(0x8086, 0x269a),
3311           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3312           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3313         { PCI_DEVICE(0x8086, 0x284b),
3314           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3315           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3316         { PCI_DEVICE(0x8086, 0x293e),
3317           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3318           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3319         { PCI_DEVICE(0x8086, 0x293f),
3320           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3321           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3322         { PCI_DEVICE(0x8086, 0x3a3e),
3323           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3324           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3325         { PCI_DEVICE(0x8086, 0x3a6e),
3326           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3327           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3328         /* Generic Intel */
3329         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3330           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3331           .class_mask = 0xffffff,
3332           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3333         /* ATI SB 450/600/700/800/900 */
3334         { PCI_DEVICE(0x1002, 0x437b),
3335           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3336         { PCI_DEVICE(0x1002, 0x4383),
3337           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3338         /* AMD Hudson */
3339         { PCI_DEVICE(0x1022, 0x780d),
3340           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3341         /* ATI HDMI */
3342         { PCI_DEVICE(0x1002, 0x793b),
3343           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3344         { PCI_DEVICE(0x1002, 0x7919),
3345           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3346         { PCI_DEVICE(0x1002, 0x960f),
3347           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3348         { PCI_DEVICE(0x1002, 0x970f),
3349           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3350         { PCI_DEVICE(0x1002, 0xaa00),
3351           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3352         { PCI_DEVICE(0x1002, 0xaa08),
3353           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3354         { PCI_DEVICE(0x1002, 0xaa10),
3355           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3356         { PCI_DEVICE(0x1002, 0xaa18),
3357           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3358         { PCI_DEVICE(0x1002, 0xaa20),
3359           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3360         { PCI_DEVICE(0x1002, 0xaa28),
3361           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3362         { PCI_DEVICE(0x1002, 0xaa30),
3363           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3364         { PCI_DEVICE(0x1002, 0xaa38),
3365           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3366         { PCI_DEVICE(0x1002, 0xaa40),
3367           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3368         { PCI_DEVICE(0x1002, 0xaa48),
3369           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3370         { PCI_DEVICE(0x1002, 0x9902),
3371           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3372         { PCI_DEVICE(0x1002, 0xaaa0),
3373           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3374         { PCI_DEVICE(0x1002, 0xaaa8),
3375           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3376         { PCI_DEVICE(0x1002, 0xaab0),
3377           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3378         /* VIA VT8251/VT8237A */
3379         { PCI_DEVICE(0x1106, 0x3288),
3380           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3381         /* VIA GFX VT7122/VX900 */
3382         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3383         /* VIA GFX VT6122/VX11 */
3384         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3385         /* SIS966 */
3386         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3387         /* ULI M5461 */
3388         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3389         /* NVIDIA MCP */
3390         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3391           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3392           .class_mask = 0xffffff,
3393           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3394         /* Teradici */
3395         { PCI_DEVICE(0x6549, 0x1200),
3396           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3397         /* Creative X-Fi (CA0110-IBG) */
3398         /* CTHDA chips */
3399         { PCI_DEVICE(0x1102, 0x0010),
3400           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3401         { PCI_DEVICE(0x1102, 0x0012),
3402           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3403 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3404         /* the following entry conflicts with snd-ctxfi driver,
3405          * as ctxfi driver mutates from HD-audio to native mode with
3406          * a special command sequence.
3407          */
3408         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3409           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3410           .class_mask = 0xffffff,
3411           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3412           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3413 #else
3414         /* this entry seems still valid -- i.e. without emu20kx chip */
3415         { PCI_DEVICE(0x1102, 0x0009),
3416           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3417           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3418 #endif
3419         /* Vortex86MX */
3420         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3421         /* VMware HDAudio */
3422         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3423         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3424         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3425           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3426           .class_mask = 0xffffff,
3427           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3428         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3429           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3430           .class_mask = 0xffffff,
3431           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3432         { 0, }
3433 };
3434 MODULE_DEVICE_TABLE(pci, azx_ids);
3435
3436 /* pci_driver definition */
3437 static struct pci_driver azx_driver = {
3438         .name = KBUILD_MODNAME,
3439         .id_table = azx_ids,
3440         .probe = azx_probe,
3441         .remove = __devexit_p(azx_remove),
3442         .driver = {
3443                 .pm = AZX_PM_OPS,
3444         },
3445 };
3446
3447 module_pci_driver(azx_driver);