3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include <linux/vgaarb.h>
57 #include <linux/vga_switcheroo.h>
58 #include "hda_codec.h"
61 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
63 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
64 static char *model[SNDRV_CARDS];
65 static int position_fix[SNDRV_CARDS];
66 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
67 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int probe_only[SNDRV_CARDS];
69 static bool single_cmd;
70 static int enable_msi = -1;
71 #ifdef CONFIG_SND_HDA_PATCH_LOADER
72 static char *patch[SNDRV_CARDS];
74 #ifdef CONFIG_SND_HDA_INPUT_BEEP
75 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
76 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
85 module_param_array(model, charp, NULL, 0444);
86 MODULE_PARM_DESC(model, "Use the given board model.");
87 module_param_array(position_fix, int, NULL, 0444);
88 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
89 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
90 module_param_array(bdl_pos_adj, int, NULL, 0644);
91 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
92 module_param_array(probe_mask, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
94 module_param_array(probe_only, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
96 module_param(single_cmd, bool, 0444);
97 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
98 "(for debugging only).");
99 module_param(enable_msi, bint, 0444);
100 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
101 #ifdef CONFIG_SND_HDA_PATCH_LOADER
102 module_param_array(patch, charp, NULL, 0444);
103 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
105 #ifdef CONFIG_SND_HDA_INPUT_BEEP
106 module_param_array(beep_mode, int, NULL, 0444);
107 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
108 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
111 #ifdef CONFIG_SND_HDA_POWER_SAVE
112 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
113 module_param(power_save, int, 0644);
114 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
115 "(in second, 0 = disable).");
117 /* reset the HD-audio controller in power save mode.
118 * this may give more power-saving, but will take longer time to
121 static bool power_save_controller = 1;
122 module_param(power_save_controller, bool, 0644);
123 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
126 static int align_buffer_size = -1;
127 module_param(align_buffer_size, bint, 0644);
128 MODULE_PARM_DESC(align_buffer_size,
129 "Force buffer and period sizes to be multiple of 128 bytes.");
132 static bool hda_snoop = true;
133 module_param_named(snoop, hda_snoop, bool, 0444);
134 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
135 #define azx_snoop(chip) (chip)->snoop
137 #define hda_snoop true
138 #define azx_snoop(chip) true
142 MODULE_LICENSE("GPL");
143 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
172 MODULE_DESCRIPTION("Intel HDA driver");
174 #ifdef CONFIG_SND_VERBOSE_PRINTK
175 #define SFX /* nop */
177 #define SFX "hda-intel: "
180 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
181 #ifdef CONFIG_SND_HDA_CODEC_HDMI
182 #define SUPPORT_VGA_SWITCHEROO
190 #define ICH6_REG_GCAP 0x00
191 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
192 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
193 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
194 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
195 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
196 #define ICH6_REG_VMIN 0x02
197 #define ICH6_REG_VMAJ 0x03
198 #define ICH6_REG_OUTPAY 0x04
199 #define ICH6_REG_INPAY 0x06
200 #define ICH6_REG_GCTL 0x08
201 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
202 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
203 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
204 #define ICH6_REG_WAKEEN 0x0c
205 #define ICH6_REG_STATESTS 0x0e
206 #define ICH6_REG_GSTS 0x10
207 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
208 #define ICH6_REG_INTCTL 0x20
209 #define ICH6_REG_INTSTS 0x24
210 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
211 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
212 #define ICH6_REG_SSYNC 0x38
213 #define ICH6_REG_CORBLBASE 0x40
214 #define ICH6_REG_CORBUBASE 0x44
215 #define ICH6_REG_CORBWP 0x48
216 #define ICH6_REG_CORBRP 0x4a
217 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
218 #define ICH6_REG_CORBCTL 0x4c
219 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
220 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
221 #define ICH6_REG_CORBSTS 0x4d
222 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
223 #define ICH6_REG_CORBSIZE 0x4e
225 #define ICH6_REG_RIRBLBASE 0x50
226 #define ICH6_REG_RIRBUBASE 0x54
227 #define ICH6_REG_RIRBWP 0x58
228 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
229 #define ICH6_REG_RINTCNT 0x5a
230 #define ICH6_REG_RIRBCTL 0x5c
231 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
232 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
233 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
234 #define ICH6_REG_RIRBSTS 0x5d
235 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
236 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
237 #define ICH6_REG_RIRBSIZE 0x5e
239 #define ICH6_REG_IC 0x60
240 #define ICH6_REG_IR 0x64
241 #define ICH6_REG_IRS 0x68
242 #define ICH6_IRS_VALID (1<<1)
243 #define ICH6_IRS_BUSY (1<<0)
245 #define ICH6_REG_DPLBASE 0x70
246 #define ICH6_REG_DPUBASE 0x74
247 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
249 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
250 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
252 /* stream register offsets from stream base */
253 #define ICH6_REG_SD_CTL 0x00
254 #define ICH6_REG_SD_STS 0x03
255 #define ICH6_REG_SD_LPIB 0x04
256 #define ICH6_REG_SD_CBL 0x08
257 #define ICH6_REG_SD_LVI 0x0c
258 #define ICH6_REG_SD_FIFOW 0x0e
259 #define ICH6_REG_SD_FIFOSIZE 0x10
260 #define ICH6_REG_SD_FORMAT 0x12
261 #define ICH6_REG_SD_BDLPL 0x18
262 #define ICH6_REG_SD_BDLPU 0x1c
265 #define ICH6_PCIREG_TCSEL 0x44
271 /* max number of SDs */
272 /* ICH, ATI and VIA have 4 playback and 4 capture */
273 #define ICH6_NUM_CAPTURE 4
274 #define ICH6_NUM_PLAYBACK 4
276 /* ULI has 6 playback and 5 capture */
277 #define ULI_NUM_CAPTURE 5
278 #define ULI_NUM_PLAYBACK 6
280 /* ATI HDMI has 1 playback and 0 capture */
281 #define ATIHDMI_NUM_CAPTURE 0
282 #define ATIHDMI_NUM_PLAYBACK 1
284 /* TERA has 4 playback and 3 capture */
285 #define TERA_NUM_CAPTURE 3
286 #define TERA_NUM_PLAYBACK 4
288 /* this number is statically defined for simplicity */
289 #define MAX_AZX_DEV 16
291 /* max number of fragments - we may use more if allocating more pages for BDL */
292 #define BDL_SIZE 4096
293 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
294 #define AZX_MAX_FRAG 32
295 /* max buffer size - no h/w limit, you can increase as you like */
296 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
298 /* RIRB int mask: overrun[2], response[0] */
299 #define RIRB_INT_RESPONSE 0x01
300 #define RIRB_INT_OVERRUN 0x04
301 #define RIRB_INT_MASK 0x05
303 /* STATESTS int mask: S3,SD2,SD1,SD0 */
304 #define AZX_MAX_CODECS 8
305 #define AZX_DEFAULT_CODECS 4
306 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
309 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
310 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
311 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
312 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
313 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
314 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
315 #define SD_CTL_STREAM_TAG_SHIFT 20
317 /* SD_CTL and SD_STS */
318 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
319 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
320 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
321 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
325 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
327 /* INTCTL and INTSTS */
328 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
329 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
330 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
332 /* below are so far hardcoded - should read registers in future */
333 #define ICH6_MAX_CORB_ENTRIES 256
334 #define ICH6_MAX_RIRB_ENTRIES 256
336 /* position fix mode */
345 /* Defines for ATI HD Audio support in SB450 south bridge */
346 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
347 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
349 /* Defines for Nvidia HDA support */
350 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
351 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
352 #define NVIDIA_HDA_ISTRM_COH 0x4d
353 #define NVIDIA_HDA_OSTRM_COH 0x4c
354 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
356 /* Defines for Intel SCH HDA snoop control */
357 #define INTEL_SCH_HDA_DEVC 0x78
358 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
360 /* Define IN stream 0 FIFO size offset in VIA controller */
361 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
362 /* Define VIA HD Audio Device ID*/
363 #define VIA_HDAC_DEVICE_ID 0x3288
365 /* HD Audio class code */
366 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
372 struct snd_dma_buffer bdl; /* BDL buffer */
373 u32 *posbuf; /* position buffer pointer */
375 unsigned int bufsize; /* size of the play buffer in bytes */
376 unsigned int period_bytes; /* size of the period in bytes */
377 unsigned int frags; /* number for period in the play buffer */
378 unsigned int fifo_size; /* FIFO size */
379 unsigned long start_wallclk; /* start + minimum wallclk */
380 unsigned long period_wallclk; /* wallclk for period */
382 void __iomem *sd_addr; /* stream descriptor pointer */
384 u32 sd_int_sta_mask; /* stream int status mask */
387 struct snd_pcm_substream *substream; /* assigned substream,
390 unsigned int format_val; /* format value to be set in the
391 * controller and the codec
393 unsigned char stream_tag; /* assigned stream */
394 unsigned char index; /* stream index */
395 int assigned_key; /* last device# key assigned to */
397 unsigned int opened :1;
398 unsigned int running :1;
399 unsigned int irq_pending :1;
402 * A flag to ensure DMA position is 0
403 * when link position is not greater than FIFO size
405 unsigned int insufficient :1;
406 unsigned int wc_marked:1;
411 u32 *buf; /* CORB/RIRB buffer
412 * Each CORB entry is 4byte, RIRB is 8byte
414 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
416 unsigned short rp, wp; /* read/write pointers */
417 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
418 u32 res[AZX_MAX_CODECS]; /* last read value */
424 struct hda_codec *codec;
425 struct hda_pcm_stream *hinfo[2];
426 struct list_head list;
430 struct snd_card *card;
434 /* chip type specific */
436 unsigned int driver_caps;
437 int playback_streams;
438 int playback_index_offset;
440 int capture_index_offset;
445 void __iomem *remap_addr;
450 struct mutex open_mutex;
452 /* streams (x num_streams) */
453 struct azx_dev *azx_dev;
456 struct list_head pcm_list; /* azx_pcm list */
459 unsigned short codec_mask;
460 int codec_probe_mask; /* copied from probe_mask option */
462 unsigned int beep_mode;
468 /* CORB/RIRB and position buffers */
469 struct snd_dma_buffer rb;
470 struct snd_dma_buffer posbuf;
473 int position_fix[2]; /* for both playback/capture streams */
475 unsigned int running :1;
476 unsigned int initialized :1;
477 unsigned int single_cmd :1;
478 unsigned int polling_mode :1;
480 unsigned int irq_pending_warned :1;
481 unsigned int probing :1; /* codec probing phase */
482 unsigned int snoop:1;
483 unsigned int align_buffer_size:1;
484 unsigned int region_requested:1;
486 /* VGA-switcheroo setup */
487 unsigned int use_vga_switcheroo:1;
488 unsigned int init_failed:1; /* delayed init failed */
489 unsigned int disabled:1; /* disabled by VGA-switcher */
492 unsigned int last_cmd[AZX_MAX_CODECS];
494 /* for pending irqs */
495 struct work_struct irq_pending_work;
497 /* reboot notifier (for mysterious hangup problem at power-down) */
498 struct notifier_block reboot_notifier;
508 AZX_DRIVER_ATIHDMI_NS,
517 AZX_NUM_DRIVERS, /* keep this as last entry */
520 /* driver quirks (capabilities) */
521 /* bits 0-7 are used for indicating driver type */
522 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
523 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
524 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
525 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
526 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
527 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
528 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
529 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
530 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
531 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
532 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
533 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
534 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
535 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
536 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
537 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
539 /* quirks for ATI SB / AMD Hudson */
540 #define AZX_DCAPS_PRESET_ATI_SB \
541 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
542 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
544 /* quirks for ATI/AMD HDMI */
545 #define AZX_DCAPS_PRESET_ATI_HDMI \
546 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
548 /* quirks for Nvidia */
549 #define AZX_DCAPS_PRESET_NVIDIA \
550 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
551 AZX_DCAPS_ALIGN_BUFSIZE)
553 #define AZX_DCAPS_PRESET_CTHDA \
554 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
557 * VGA-switcher support
559 #ifdef SUPPORT_VGA_SWITCHEROO
560 #define DELAYED_INIT_MARK
561 #define DELAYED_INITDATA_MARK
562 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
564 #define DELAYED_INIT_MARK __devinit
565 #define DELAYED_INITDATA_MARK __devinitdata
566 #define use_vga_switcheroo(chip) 0
569 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
570 [AZX_DRIVER_ICH] = "HDA Intel",
571 [AZX_DRIVER_PCH] = "HDA Intel PCH",
572 [AZX_DRIVER_SCH] = "HDA Intel MID",
573 [AZX_DRIVER_ATI] = "HDA ATI SB",
574 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
575 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
576 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
577 [AZX_DRIVER_SIS] = "HDA SIS966",
578 [AZX_DRIVER_ULI] = "HDA ULI M5461",
579 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
580 [AZX_DRIVER_TERA] = "HDA Teradici",
581 [AZX_DRIVER_CTX] = "HDA Creative",
582 [AZX_DRIVER_CTHDA] = "HDA Creative",
583 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
587 * macros for easy use
589 #define azx_writel(chip,reg,value) \
590 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
591 #define azx_readl(chip,reg) \
592 readl((chip)->remap_addr + ICH6_REG_##reg)
593 #define azx_writew(chip,reg,value) \
594 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
595 #define azx_readw(chip,reg) \
596 readw((chip)->remap_addr + ICH6_REG_##reg)
597 #define azx_writeb(chip,reg,value) \
598 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
599 #define azx_readb(chip,reg) \
600 readb((chip)->remap_addr + ICH6_REG_##reg)
602 #define azx_sd_writel(dev,reg,value) \
603 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
604 #define azx_sd_readl(dev,reg) \
605 readl((dev)->sd_addr + ICH6_REG_##reg)
606 #define azx_sd_writew(dev,reg,value) \
607 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
608 #define azx_sd_readw(dev,reg) \
609 readw((dev)->sd_addr + ICH6_REG_##reg)
610 #define azx_sd_writeb(dev,reg,value) \
611 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
612 #define azx_sd_readb(dev,reg) \
613 readb((dev)->sd_addr + ICH6_REG_##reg)
615 /* for pcm support */
616 #define get_azx_dev(substream) (substream->runtime->private_data)
619 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
624 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
626 set_memory_wc((unsigned long)addr, pages);
628 set_memory_wb((unsigned long)addr, pages);
632 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
635 __mark_pages_wc(chip, buf->area, buf->bytes, on);
637 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
638 struct snd_pcm_runtime *runtime, bool on)
640 if (azx_dev->wc_marked != on) {
641 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
642 azx_dev->wc_marked = on;
646 /* NOP for other archs */
647 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
651 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
652 struct snd_pcm_runtime *runtime, bool on)
657 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
658 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
660 * Interface for HD codec
664 * CORB / RIRB interface
666 static int azx_alloc_cmd_io(struct azx *chip)
670 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
671 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
672 snd_dma_pci_data(chip->pci),
673 PAGE_SIZE, &chip->rb);
675 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
678 mark_pages_wc(chip, &chip->rb, true);
682 static void azx_init_cmd_io(struct azx *chip)
684 spin_lock_irq(&chip->reg_lock);
686 chip->corb.addr = chip->rb.addr;
687 chip->corb.buf = (u32 *)chip->rb.area;
688 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
689 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
691 /* set the corb size to 256 entries (ULI requires explicitly) */
692 azx_writeb(chip, CORBSIZE, 0x02);
693 /* set the corb write pointer to 0 */
694 azx_writew(chip, CORBWP, 0);
695 /* reset the corb hw read pointer */
696 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
697 /* enable corb dma */
698 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
701 chip->rirb.addr = chip->rb.addr + 2048;
702 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
703 chip->rirb.wp = chip->rirb.rp = 0;
704 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
705 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
706 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
708 /* set the rirb size to 256 entries (ULI requires explicitly) */
709 azx_writeb(chip, RIRBSIZE, 0x02);
710 /* reset the rirb hw write pointer */
711 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
712 /* set N=1, get RIRB response interrupt for new entry */
713 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
714 azx_writew(chip, RINTCNT, 0xc0);
716 azx_writew(chip, RINTCNT, 1);
717 /* enable rirb dma and response irq */
718 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
719 spin_unlock_irq(&chip->reg_lock);
722 static void azx_free_cmd_io(struct azx *chip)
724 spin_lock_irq(&chip->reg_lock);
725 /* disable ringbuffer DMAs */
726 azx_writeb(chip, RIRBCTL, 0);
727 azx_writeb(chip, CORBCTL, 0);
728 spin_unlock_irq(&chip->reg_lock);
731 static unsigned int azx_command_addr(u32 cmd)
733 unsigned int addr = cmd >> 28;
735 if (addr >= AZX_MAX_CODECS) {
743 static unsigned int azx_response_addr(u32 res)
745 unsigned int addr = res & 0xf;
747 if (addr >= AZX_MAX_CODECS) {
756 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
758 struct azx *chip = bus->private_data;
759 unsigned int addr = azx_command_addr(val);
762 spin_lock_irq(&chip->reg_lock);
764 /* add command to corb */
765 wp = azx_readb(chip, CORBWP);
767 wp %= ICH6_MAX_CORB_ENTRIES;
769 chip->rirb.cmds[addr]++;
770 chip->corb.buf[wp] = cpu_to_le32(val);
771 azx_writel(chip, CORBWP, wp);
773 spin_unlock_irq(&chip->reg_lock);
778 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
780 /* retrieve RIRB entry - called from interrupt handler */
781 static void azx_update_rirb(struct azx *chip)
787 wp = azx_readb(chip, RIRBWP);
788 if (wp == chip->rirb.wp)
792 while (chip->rirb.rp != wp) {
794 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
796 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
797 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
798 res = le32_to_cpu(chip->rirb.buf[rp]);
799 addr = azx_response_addr(res_ex);
800 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
801 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
802 else if (chip->rirb.cmds[addr]) {
803 chip->rirb.res[addr] = res;
805 chip->rirb.cmds[addr]--;
807 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
810 chip->last_cmd[addr]);
814 /* receive a response */
815 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
818 struct azx *chip = bus->private_data;
819 unsigned long timeout;
820 unsigned long loopcounter;
824 timeout = jiffies + msecs_to_jiffies(1000);
826 for (loopcounter = 0;; loopcounter++) {
827 if (chip->polling_mode || do_poll) {
828 spin_lock_irq(&chip->reg_lock);
829 azx_update_rirb(chip);
830 spin_unlock_irq(&chip->reg_lock);
832 if (!chip->rirb.cmds[addr]) {
837 chip->poll_count = 0;
838 return chip->rirb.res[addr]; /* the last value */
840 if (time_after(jiffies, timeout))
842 if (bus->needs_damn_long_delay || loopcounter > 3000)
843 msleep(2); /* temporary workaround */
850 if (!chip->polling_mode && chip->poll_count < 2) {
851 snd_printdd(SFX "azx_get_response timeout, "
852 "polling the codec once: last cmd=0x%08x\n",
853 chip->last_cmd[addr]);
860 if (!chip->polling_mode) {
861 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
862 "switching to polling mode: last cmd=0x%08x\n",
863 chip->last_cmd[addr]);
864 chip->polling_mode = 1;
869 snd_printk(KERN_WARNING SFX "No response from codec, "
870 "disabling MSI: last cmd=0x%08x\n",
871 chip->last_cmd[addr]);
872 free_irq(chip->irq, chip);
874 pci_disable_msi(chip->pci);
876 if (azx_acquire_irq(chip, 1) < 0) {
884 /* If this critical timeout happens during the codec probing
885 * phase, this is likely an access to a non-existing codec
886 * slot. Better to return an error and reset the system.
891 /* a fatal communication error; need either to reset or to fallback
892 * to the single_cmd mode
895 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
896 bus->response_reset = 1;
897 return -1; /* give a chance to retry */
900 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
901 "switching to single_cmd mode: last cmd=0x%08x\n",
902 chip->last_cmd[addr]);
903 chip->single_cmd = 1;
904 bus->response_reset = 0;
905 /* release CORB/RIRB */
906 azx_free_cmd_io(chip);
907 /* disable unsolicited responses */
908 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
913 * Use the single immediate command instead of CORB/RIRB for simplicity
915 * Note: according to Intel, this is not preferred use. The command was
916 * intended for the BIOS only, and may get confused with unsolicited
917 * responses. So, we shouldn't use it for normal operation from the
919 * I left the codes, however, for debugging/testing purposes.
922 /* receive a response */
923 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
928 /* check IRV busy bit */
929 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
930 /* reuse rirb.res as the response return value */
931 chip->rirb.res[addr] = azx_readl(chip, IR);
936 if (printk_ratelimit())
937 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
938 azx_readw(chip, IRS));
939 chip->rirb.res[addr] = -1;
944 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
946 struct azx *chip = bus->private_data;
947 unsigned int addr = azx_command_addr(val);
952 /* check ICB busy bit */
953 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
954 /* Clear IRV valid bit */
955 azx_writew(chip, IRS, azx_readw(chip, IRS) |
957 azx_writel(chip, IC, val);
958 azx_writew(chip, IRS, azx_readw(chip, IRS) |
960 return azx_single_wait_for_response(chip, addr);
964 if (printk_ratelimit())
965 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
966 azx_readw(chip, IRS), val);
970 /* receive a response */
971 static unsigned int azx_single_get_response(struct hda_bus *bus,
974 struct azx *chip = bus->private_data;
975 return chip->rirb.res[addr];
979 * The below are the main callbacks from hda_codec.
981 * They are just the skeleton to call sub-callbacks according to the
982 * current setting of chip->single_cmd.
986 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
988 struct azx *chip = bus->private_data;
992 chip->last_cmd[azx_command_addr(val)] = val;
993 if (chip->single_cmd)
994 return azx_single_send_cmd(bus, val);
996 return azx_corb_send_cmd(bus, val);
1000 static unsigned int azx_get_response(struct hda_bus *bus,
1003 struct azx *chip = bus->private_data;
1006 if (chip->single_cmd)
1007 return azx_single_get_response(bus, addr);
1009 return azx_rirb_get_response(bus, addr);
1012 #ifdef CONFIG_SND_HDA_POWER_SAVE
1013 static void azx_power_notify(struct hda_bus *bus);
1016 /* reset codec link */
1017 static int azx_reset(struct azx *chip, int full_reset)
1024 /* clear STATESTS */
1025 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1027 /* reset controller */
1028 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1031 while (azx_readb(chip, GCTL) && --count)
1034 /* delay for >= 100us for codec PLL to settle per spec
1035 * Rev 0.9 section 5.5.1
1039 /* Bring controller out of reset */
1040 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1043 while (!azx_readb(chip, GCTL) && --count)
1046 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1050 /* check to see if controller is ready */
1051 if (!azx_readb(chip, GCTL)) {
1052 snd_printd(SFX "azx_reset: controller not ready!\n");
1056 /* Accept unsolicited responses */
1057 if (!chip->single_cmd)
1058 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1062 if (!chip->codec_mask) {
1063 chip->codec_mask = azx_readw(chip, STATESTS);
1064 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1072 * Lowlevel interface
1075 /* enable interrupts */
1076 static void azx_int_enable(struct azx *chip)
1078 /* enable controller CIE and GIE */
1079 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1080 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1083 /* disable interrupts */
1084 static void azx_int_disable(struct azx *chip)
1088 /* disable interrupts in stream descriptor */
1089 for (i = 0; i < chip->num_streams; i++) {
1090 struct azx_dev *azx_dev = &chip->azx_dev[i];
1091 azx_sd_writeb(azx_dev, SD_CTL,
1092 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1095 /* disable SIE for all streams */
1096 azx_writeb(chip, INTCTL, 0);
1098 /* disable controller CIE and GIE */
1099 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1100 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1103 /* clear interrupts */
1104 static void azx_int_clear(struct azx *chip)
1108 /* clear stream status */
1109 for (i = 0; i < chip->num_streams; i++) {
1110 struct azx_dev *azx_dev = &chip->azx_dev[i];
1111 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1114 /* clear STATESTS */
1115 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1117 /* clear rirb status */
1118 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1120 /* clear int status */
1121 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1124 /* start a stream */
1125 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1128 * Before stream start, initialize parameter
1130 azx_dev->insufficient = 1;
1133 azx_writel(chip, INTCTL,
1134 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1135 /* set DMA start and interrupt mask */
1136 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1137 SD_CTL_DMA_START | SD_INT_MASK);
1141 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1143 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1144 ~(SD_CTL_DMA_START | SD_INT_MASK));
1145 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1149 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1151 azx_stream_clear(chip, azx_dev);
1153 azx_writel(chip, INTCTL,
1154 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1159 * reset and start the controller registers
1161 static void azx_init_chip(struct azx *chip, int full_reset)
1163 if (chip->initialized)
1166 /* reset controller */
1167 azx_reset(chip, full_reset);
1169 /* initialize interrupts */
1170 azx_int_clear(chip);
1171 azx_int_enable(chip);
1173 /* initialize the codec command I/O */
1174 if (!chip->single_cmd)
1175 azx_init_cmd_io(chip);
1177 /* program the position buffer */
1178 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1179 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1181 chip->initialized = 1;
1185 * initialize the PCI registers
1187 /* update bits in a PCI register byte */
1188 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1189 unsigned char mask, unsigned char val)
1193 pci_read_config_byte(pci, reg, &data);
1195 data |= (val & mask);
1196 pci_write_config_byte(pci, reg, data);
1199 static void azx_init_pci(struct azx *chip)
1201 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1202 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1203 * Ensuring these bits are 0 clears playback static on some HD Audio
1205 * The PCI register TCSEL is defined in the Intel manuals.
1207 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1208 snd_printdd(SFX "Clearing TCSEL\n");
1209 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1212 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1213 * we need to enable snoop.
1215 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1216 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1217 update_pci_byte(chip->pci,
1218 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1219 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1222 /* For NVIDIA HDA, enable snoop */
1223 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1224 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1225 update_pci_byte(chip->pci,
1226 NVIDIA_HDA_TRANSREG_ADDR,
1227 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1228 update_pci_byte(chip->pci,
1229 NVIDIA_HDA_ISTRM_COH,
1230 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1231 update_pci_byte(chip->pci,
1232 NVIDIA_HDA_OSTRM_COH,
1233 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1236 /* Enable SCH/PCH snoop if needed */
1237 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1238 unsigned short snoop;
1239 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1240 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1241 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1242 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1243 if (!azx_snoop(chip))
1244 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1245 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1246 pci_read_config_word(chip->pci,
1247 INTEL_SCH_HDA_DEVC, &snoop);
1249 snd_printdd(SFX "SCH snoop: %s\n",
1250 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1251 ? "Disabled" : "Enabled");
1256 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1261 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1263 struct azx *chip = dev_id;
1264 struct azx_dev *azx_dev;
1269 spin_lock(&chip->reg_lock);
1271 if (chip->disabled) {
1272 spin_unlock(&chip->reg_lock);
1276 status = azx_readl(chip, INTSTS);
1278 spin_unlock(&chip->reg_lock);
1282 for (i = 0; i < chip->num_streams; i++) {
1283 azx_dev = &chip->azx_dev[i];
1284 if (status & azx_dev->sd_int_sta_mask) {
1285 sd_status = azx_sd_readb(azx_dev, SD_STS);
1286 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1287 if (!azx_dev->substream || !azx_dev->running ||
1288 !(sd_status & SD_INT_COMPLETE))
1290 /* check whether this IRQ is really acceptable */
1291 ok = azx_position_ok(chip, azx_dev);
1293 azx_dev->irq_pending = 0;
1294 spin_unlock(&chip->reg_lock);
1295 snd_pcm_period_elapsed(azx_dev->substream);
1296 spin_lock(&chip->reg_lock);
1297 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1298 /* bogus IRQ, process it later */
1299 azx_dev->irq_pending = 1;
1300 queue_work(chip->bus->workq,
1301 &chip->irq_pending_work);
1306 /* clear rirb int */
1307 status = azx_readb(chip, RIRBSTS);
1308 if (status & RIRB_INT_MASK) {
1309 if (status & RIRB_INT_RESPONSE) {
1310 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1312 azx_update_rirb(chip);
1314 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1318 /* clear state status int */
1319 if (azx_readb(chip, STATESTS) & 0x04)
1320 azx_writeb(chip, STATESTS, 0x04);
1322 spin_unlock(&chip->reg_lock);
1329 * set up a BDL entry
1331 static int setup_bdle(struct azx *chip,
1332 struct snd_pcm_substream *substream,
1333 struct azx_dev *azx_dev, u32 **bdlp,
1334 int ofs, int size, int with_ioc)
1342 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1345 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1346 /* program the address field of the BDL entry */
1347 bdl[0] = cpu_to_le32((u32)addr);
1348 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1349 /* program the size field of the BDL entry */
1350 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1351 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1352 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1353 u32 remain = 0x1000 - (ofs & 0xfff);
1357 bdl[2] = cpu_to_le32(chunk);
1358 /* program the IOC to enable interrupt
1359 * only when the whole fragment is processed
1362 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1372 * set up BDL entries
1374 static int azx_setup_periods(struct azx *chip,
1375 struct snd_pcm_substream *substream,
1376 struct azx_dev *azx_dev)
1379 int i, ofs, periods, period_bytes;
1382 /* reset BDL address */
1383 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1384 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1386 period_bytes = azx_dev->period_bytes;
1387 periods = azx_dev->bufsize / period_bytes;
1389 /* program the initial BDL entries */
1390 bdl = (u32 *)azx_dev->bdl.area;
1393 pos_adj = bdl_pos_adj[chip->dev_index];
1395 struct snd_pcm_runtime *runtime = substream->runtime;
1396 int pos_align = pos_adj;
1397 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1399 pos_adj = pos_align;
1401 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1403 pos_adj = frames_to_bytes(runtime, pos_adj);
1404 if (pos_adj >= period_bytes) {
1405 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1406 bdl_pos_adj[chip->dev_index]);
1409 ofs = setup_bdle(chip, substream, azx_dev,
1411 !substream->runtime->no_period_wakeup);
1417 for (i = 0; i < periods; i++) {
1418 if (i == periods - 1 && pos_adj)
1419 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1420 period_bytes - pos_adj, 0);
1422 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1424 !substream->runtime->no_period_wakeup);
1431 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1432 azx_dev->bufsize, period_bytes);
1437 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1442 azx_stream_clear(chip, azx_dev);
1444 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1445 SD_CTL_STREAM_RESET);
1448 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1451 val &= ~SD_CTL_STREAM_RESET;
1452 azx_sd_writeb(azx_dev, SD_CTL, val);
1456 /* waiting for hardware to report that the stream is out of reset */
1457 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1461 /* reset first position - may not be synced with hw at this time */
1462 *azx_dev->posbuf = 0;
1466 * set up the SD for streaming
1468 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1471 /* make sure the run bit is zero for SD */
1472 azx_stream_clear(chip, azx_dev);
1473 /* program the stream_tag */
1474 val = azx_sd_readl(azx_dev, SD_CTL);
1475 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1476 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1477 if (!azx_snoop(chip))
1478 val |= SD_CTL_TRAFFIC_PRIO;
1479 azx_sd_writel(azx_dev, SD_CTL, val);
1481 /* program the length of samples in cyclic buffer */
1482 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1484 /* program the stream format */
1485 /* this value needs to be the same as the one programmed */
1486 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1488 /* program the stream LVI (last valid index) of the BDL */
1489 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1491 /* program the BDL address */
1492 /* lower BDL address */
1493 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1494 /* upper BDL address */
1495 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1497 /* enable the position buffer */
1498 if (chip->position_fix[0] != POS_FIX_LPIB ||
1499 chip->position_fix[1] != POS_FIX_LPIB) {
1500 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1501 azx_writel(chip, DPLBASE,
1502 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1505 /* set the interrupt enable bits in the descriptor control register */
1506 azx_sd_writel(azx_dev, SD_CTL,
1507 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1513 * Probe the given codec address
1515 static int probe_codec(struct azx *chip, int addr)
1517 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1518 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1521 mutex_lock(&chip->bus->cmd_mutex);
1523 azx_send_cmd(chip->bus, cmd);
1524 res = azx_get_response(chip->bus, addr);
1526 mutex_unlock(&chip->bus->cmd_mutex);
1529 snd_printdd(SFX "codec #%d probed OK\n", addr);
1533 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1534 struct hda_pcm *cpcm);
1535 static void azx_stop_chip(struct azx *chip);
1537 static void azx_bus_reset(struct hda_bus *bus)
1539 struct azx *chip = bus->private_data;
1542 azx_stop_chip(chip);
1543 azx_init_chip(chip, 1);
1545 if (chip->initialized) {
1547 list_for_each_entry(p, &chip->pcm_list, list)
1548 snd_pcm_suspend_all(p->pcm);
1549 snd_hda_suspend(chip->bus);
1550 snd_hda_resume(chip->bus);
1557 * Codec initialization
1560 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1561 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1562 [AZX_DRIVER_NVIDIA] = 8,
1563 [AZX_DRIVER_TERA] = 1,
1566 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1568 struct hda_bus_template bus_temp;
1572 memset(&bus_temp, 0, sizeof(bus_temp));
1573 bus_temp.private_data = chip;
1574 bus_temp.modelname = model;
1575 bus_temp.pci = chip->pci;
1576 bus_temp.ops.command = azx_send_cmd;
1577 bus_temp.ops.get_response = azx_get_response;
1578 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1579 bus_temp.ops.bus_reset = azx_bus_reset;
1580 #ifdef CONFIG_SND_HDA_POWER_SAVE
1581 bus_temp.power_save = &power_save;
1582 bus_temp.ops.pm_notify = azx_power_notify;
1585 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1589 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1590 snd_printd(SFX "Enable delay in RIRB handling\n");
1591 chip->bus->needs_damn_long_delay = 1;
1595 max_slots = azx_max_codecs[chip->driver_type];
1597 max_slots = AZX_DEFAULT_CODECS;
1599 /* First try to probe all given codec slots */
1600 for (c = 0; c < max_slots; c++) {
1601 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1602 if (probe_codec(chip, c) < 0) {
1603 /* Some BIOSen give you wrong codec addresses
1606 snd_printk(KERN_WARNING SFX
1607 "Codec #%d probe error; "
1608 "disabling it...\n", c);
1609 chip->codec_mask &= ~(1 << c);
1610 /* More badly, accessing to a non-existing
1611 * codec often screws up the controller chip,
1612 * and disturbs the further communications.
1613 * Thus if an error occurs during probing,
1614 * better to reset the controller chip to
1615 * get back to the sanity state.
1617 azx_stop_chip(chip);
1618 azx_init_chip(chip, 1);
1623 /* AMD chipsets often cause the communication stalls upon certain
1624 * sequence like the pin-detection. It seems that forcing the synced
1625 * access works around the stall. Grrr...
1627 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1628 snd_printd(SFX "Enable sync_write for stable communication\n");
1629 chip->bus->sync_write = 1;
1630 chip->bus->allow_bus_reset = 1;
1633 /* Then create codec instances */
1634 for (c = 0; c < max_slots; c++) {
1635 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1636 struct hda_codec *codec;
1637 err = snd_hda_codec_new(chip->bus, c, &codec);
1640 codec->beep_mode = chip->beep_mode;
1645 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1651 /* configure each codec instance */
1652 static int __devinit azx_codec_configure(struct azx *chip)
1654 struct hda_codec *codec;
1655 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1656 snd_hda_codec_configure(codec);
1666 /* assign a stream for the PCM */
1667 static inline struct azx_dev *
1668 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1671 struct azx_dev *res = NULL;
1672 /* make a non-zero unique key for the substream */
1673 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1674 (substream->stream + 1);
1676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1677 dev = chip->playback_index_offset;
1678 nums = chip->playback_streams;
1680 dev = chip->capture_index_offset;
1681 nums = chip->capture_streams;
1683 for (i = 0; i < nums; i++, dev++)
1684 if (!chip->azx_dev[dev].opened) {
1685 res = &chip->azx_dev[dev];
1686 if (res->assigned_key == key)
1691 res->assigned_key = key;
1696 /* release the assigned stream */
1697 static inline void azx_release_device(struct azx_dev *azx_dev)
1699 azx_dev->opened = 0;
1702 static struct snd_pcm_hardware azx_pcm_hw = {
1703 .info = (SNDRV_PCM_INFO_MMAP |
1704 SNDRV_PCM_INFO_INTERLEAVED |
1705 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1706 SNDRV_PCM_INFO_MMAP_VALID |
1707 /* No full-resume yet implemented */
1708 /* SNDRV_PCM_INFO_RESUME |*/
1709 SNDRV_PCM_INFO_PAUSE |
1710 SNDRV_PCM_INFO_SYNC_START |
1711 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1712 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1713 .rates = SNDRV_PCM_RATE_48000,
1718 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1719 .period_bytes_min = 128,
1720 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1722 .periods_max = AZX_MAX_FRAG,
1726 static int azx_pcm_open(struct snd_pcm_substream *substream)
1728 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1729 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1730 struct azx *chip = apcm->chip;
1731 struct azx_dev *azx_dev;
1732 struct snd_pcm_runtime *runtime = substream->runtime;
1733 unsigned long flags;
1737 mutex_lock(&chip->open_mutex);
1738 azx_dev = azx_assign_device(chip, substream);
1739 if (azx_dev == NULL) {
1740 mutex_unlock(&chip->open_mutex);
1743 runtime->hw = azx_pcm_hw;
1744 runtime->hw.channels_min = hinfo->channels_min;
1745 runtime->hw.channels_max = hinfo->channels_max;
1746 runtime->hw.formats = hinfo->formats;
1747 runtime->hw.rates = hinfo->rates;
1748 snd_pcm_limit_hw_rates(runtime);
1749 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1750 if (chip->align_buffer_size)
1751 /* constrain buffer sizes to be multiple of 128
1752 bytes. This is more efficient in terms of memory
1753 access but isn't required by the HDA spec and
1754 prevents users from specifying exact period/buffer
1755 sizes. For example for 44.1kHz, a period size set
1756 to 20ms will be rounded to 19.59ms. */
1759 /* Don't enforce steps on buffer sizes, still need to
1760 be multiple of 4 bytes (HDA spec). Tested on Intel
1761 HDA controllers, may not work on all devices where
1762 option needs to be disabled */
1765 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1767 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1769 snd_hda_power_up(apcm->codec);
1770 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1772 azx_release_device(azx_dev);
1773 snd_hda_power_down(apcm->codec);
1774 mutex_unlock(&chip->open_mutex);
1777 snd_pcm_limit_hw_rates(runtime);
1779 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1780 snd_BUG_ON(!runtime->hw.channels_max) ||
1781 snd_BUG_ON(!runtime->hw.formats) ||
1782 snd_BUG_ON(!runtime->hw.rates)) {
1783 azx_release_device(azx_dev);
1784 hinfo->ops.close(hinfo, apcm->codec, substream);
1785 snd_hda_power_down(apcm->codec);
1786 mutex_unlock(&chip->open_mutex);
1789 spin_lock_irqsave(&chip->reg_lock, flags);
1790 azx_dev->substream = substream;
1791 azx_dev->running = 0;
1792 spin_unlock_irqrestore(&chip->reg_lock, flags);
1794 runtime->private_data = azx_dev;
1795 snd_pcm_set_sync(substream);
1796 mutex_unlock(&chip->open_mutex);
1800 static int azx_pcm_close(struct snd_pcm_substream *substream)
1802 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1803 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1804 struct azx *chip = apcm->chip;
1805 struct azx_dev *azx_dev = get_azx_dev(substream);
1806 unsigned long flags;
1808 mutex_lock(&chip->open_mutex);
1809 spin_lock_irqsave(&chip->reg_lock, flags);
1810 azx_dev->substream = NULL;
1811 azx_dev->running = 0;
1812 spin_unlock_irqrestore(&chip->reg_lock, flags);
1813 azx_release_device(azx_dev);
1814 hinfo->ops.close(hinfo, apcm->codec, substream);
1815 snd_hda_power_down(apcm->codec);
1816 mutex_unlock(&chip->open_mutex);
1820 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1821 struct snd_pcm_hw_params *hw_params)
1823 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1824 struct azx *chip = apcm->chip;
1825 struct snd_pcm_runtime *runtime = substream->runtime;
1826 struct azx_dev *azx_dev = get_azx_dev(substream);
1829 mark_runtime_wc(chip, azx_dev, runtime, false);
1830 azx_dev->bufsize = 0;
1831 azx_dev->period_bytes = 0;
1832 azx_dev->format_val = 0;
1833 ret = snd_pcm_lib_malloc_pages(substream,
1834 params_buffer_bytes(hw_params));
1837 mark_runtime_wc(chip, azx_dev, runtime, true);
1841 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1843 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1844 struct azx_dev *azx_dev = get_azx_dev(substream);
1845 struct azx *chip = apcm->chip;
1846 struct snd_pcm_runtime *runtime = substream->runtime;
1847 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1849 /* reset BDL address */
1850 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1851 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1852 azx_sd_writel(azx_dev, SD_CTL, 0);
1853 azx_dev->bufsize = 0;
1854 azx_dev->period_bytes = 0;
1855 azx_dev->format_val = 0;
1857 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1859 mark_runtime_wc(chip, azx_dev, runtime, false);
1860 return snd_pcm_lib_free_pages(substream);
1863 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1865 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1866 struct azx *chip = apcm->chip;
1867 struct azx_dev *azx_dev = get_azx_dev(substream);
1868 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1869 struct snd_pcm_runtime *runtime = substream->runtime;
1870 unsigned int bufsize, period_bytes, format_val, stream_tag;
1872 struct hda_spdif_out *spdif =
1873 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1874 unsigned short ctls = spdif ? spdif->ctls : 0;
1876 azx_stream_reset(chip, azx_dev);
1877 format_val = snd_hda_calc_stream_format(runtime->rate,
1883 snd_printk(KERN_ERR SFX
1884 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1885 runtime->rate, runtime->channels, runtime->format);
1889 bufsize = snd_pcm_lib_buffer_bytes(substream);
1890 period_bytes = snd_pcm_lib_period_bytes(substream);
1892 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1893 bufsize, format_val);
1895 if (bufsize != azx_dev->bufsize ||
1896 period_bytes != azx_dev->period_bytes ||
1897 format_val != azx_dev->format_val) {
1898 azx_dev->bufsize = bufsize;
1899 azx_dev->period_bytes = period_bytes;
1900 azx_dev->format_val = format_val;
1901 err = azx_setup_periods(chip, substream, azx_dev);
1906 /* wallclk has 24Mhz clock source */
1907 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1908 runtime->rate) * 1000);
1909 azx_setup_controller(chip, azx_dev);
1910 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1911 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1913 azx_dev->fifo_size = 0;
1915 stream_tag = azx_dev->stream_tag;
1916 /* CA-IBG chips need the playback stream starting from 1 */
1917 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1918 stream_tag > chip->capture_streams)
1919 stream_tag -= chip->capture_streams;
1920 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1921 azx_dev->format_val, substream);
1924 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1926 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1927 struct azx *chip = apcm->chip;
1928 struct azx_dev *azx_dev;
1929 struct snd_pcm_substream *s;
1930 int rstart = 0, start, nsync = 0, sbits = 0;
1934 case SNDRV_PCM_TRIGGER_START:
1936 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1937 case SNDRV_PCM_TRIGGER_RESUME:
1940 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1941 case SNDRV_PCM_TRIGGER_SUSPEND:
1942 case SNDRV_PCM_TRIGGER_STOP:
1949 snd_pcm_group_for_each_entry(s, substream) {
1950 if (s->pcm->card != substream->pcm->card)
1952 azx_dev = get_azx_dev(s);
1953 sbits |= 1 << azx_dev->index;
1955 snd_pcm_trigger_done(s, substream);
1958 spin_lock(&chip->reg_lock);
1960 /* first, set SYNC bits of corresponding streams */
1961 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1962 azx_writel(chip, OLD_SSYNC,
1963 azx_readl(chip, OLD_SSYNC) | sbits);
1965 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1967 snd_pcm_group_for_each_entry(s, substream) {
1968 if (s->pcm->card != substream->pcm->card)
1970 azx_dev = get_azx_dev(s);
1972 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1974 azx_dev->start_wallclk -=
1975 azx_dev->period_wallclk;
1976 azx_stream_start(chip, azx_dev);
1978 azx_stream_stop(chip, azx_dev);
1980 azx_dev->running = start;
1982 spin_unlock(&chip->reg_lock);
1986 /* wait until all FIFOs get ready */
1987 for (timeout = 5000; timeout; timeout--) {
1989 snd_pcm_group_for_each_entry(s, substream) {
1990 if (s->pcm->card != substream->pcm->card)
1992 azx_dev = get_azx_dev(s);
1993 if (!(azx_sd_readb(azx_dev, SD_STS) &
2002 /* wait until all RUN bits are cleared */
2003 for (timeout = 5000; timeout; timeout--) {
2005 snd_pcm_group_for_each_entry(s, substream) {
2006 if (s->pcm->card != substream->pcm->card)
2008 azx_dev = get_azx_dev(s);
2009 if (azx_sd_readb(azx_dev, SD_CTL) &
2019 spin_lock(&chip->reg_lock);
2020 /* reset SYNC bits */
2021 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2022 azx_writel(chip, OLD_SSYNC,
2023 azx_readl(chip, OLD_SSYNC) & ~sbits);
2025 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2026 spin_unlock(&chip->reg_lock);
2031 /* get the current DMA position with correction on VIA chips */
2032 static unsigned int azx_via_get_position(struct azx *chip,
2033 struct azx_dev *azx_dev)
2035 unsigned int link_pos, mini_pos, bound_pos;
2036 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2037 unsigned int fifo_size;
2039 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2040 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2041 /* Playback, no problem using link position */
2047 * use mod to get the DMA position just like old chipset
2049 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2050 mod_dma_pos %= azx_dev->period_bytes;
2052 /* azx_dev->fifo_size can't get FIFO size of in stream.
2053 * Get from base address + offset.
2055 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2057 if (azx_dev->insufficient) {
2058 /* Link position never gather than FIFO size */
2059 if (link_pos <= fifo_size)
2062 azx_dev->insufficient = 0;
2065 if (link_pos <= fifo_size)
2066 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2068 mini_pos = link_pos - fifo_size;
2070 /* Find nearest previous boudary */
2071 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2072 mod_link_pos = link_pos % azx_dev->period_bytes;
2073 if (mod_link_pos >= fifo_size)
2074 bound_pos = link_pos - mod_link_pos;
2075 else if (mod_dma_pos >= mod_mini_pos)
2076 bound_pos = mini_pos - mod_mini_pos;
2078 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2079 if (bound_pos >= azx_dev->bufsize)
2083 /* Calculate real DMA position we want */
2084 return bound_pos + mod_dma_pos;
2087 static unsigned int azx_get_position(struct azx *chip,
2088 struct azx_dev *azx_dev,
2092 int stream = azx_dev->substream->stream;
2094 switch (chip->position_fix[stream]) {
2097 pos = azx_sd_readl(azx_dev, SD_LPIB);
2099 case POS_FIX_VIACOMBO:
2100 pos = azx_via_get_position(chip, azx_dev);
2103 /* use the position buffer */
2104 pos = le32_to_cpu(*azx_dev->posbuf);
2105 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2106 if (!pos || pos == (u32)-1) {
2108 "hda-intel: Invalid position buffer, "
2109 "using LPIB read method instead.\n");
2110 chip->position_fix[stream] = POS_FIX_LPIB;
2111 pos = azx_sd_readl(azx_dev, SD_LPIB);
2113 chip->position_fix[stream] = POS_FIX_POSBUF;
2118 if (pos >= azx_dev->bufsize)
2123 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2125 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2126 struct azx *chip = apcm->chip;
2127 struct azx_dev *azx_dev = get_azx_dev(substream);
2128 return bytes_to_frames(substream->runtime,
2129 azx_get_position(chip, azx_dev, false));
2133 * Check whether the current DMA position is acceptable for updating
2134 * periods. Returns non-zero if it's OK.
2136 * Many HD-audio controllers appear pretty inaccurate about
2137 * the update-IRQ timing. The IRQ is issued before actually the
2138 * data is processed. So, we need to process it afterwords in a
2141 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2147 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2148 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2149 return -1; /* bogus (too early) interrupt */
2151 stream = azx_dev->substream->stream;
2152 pos = azx_get_position(chip, azx_dev, true);
2154 if (WARN_ONCE(!azx_dev->period_bytes,
2155 "hda-intel: zero azx_dev->period_bytes"))
2156 return -1; /* this shouldn't happen! */
2157 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2158 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2159 /* NG - it's below the first next period boundary */
2160 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2161 azx_dev->start_wallclk += wallclk;
2162 return 1; /* OK, it's fine */
2166 * The work for pending PCM period updates.
2168 static void azx_irq_pending_work(struct work_struct *work)
2170 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2173 if (!chip->irq_pending_warned) {
2175 "hda-intel: IRQ timing workaround is activated "
2176 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2177 chip->card->number);
2178 chip->irq_pending_warned = 1;
2183 spin_lock_irq(&chip->reg_lock);
2184 for (i = 0; i < chip->num_streams; i++) {
2185 struct azx_dev *azx_dev = &chip->azx_dev[i];
2186 if (!azx_dev->irq_pending ||
2187 !azx_dev->substream ||
2190 ok = azx_position_ok(chip, azx_dev);
2192 azx_dev->irq_pending = 0;
2193 spin_unlock(&chip->reg_lock);
2194 snd_pcm_period_elapsed(azx_dev->substream);
2195 spin_lock(&chip->reg_lock);
2196 } else if (ok < 0) {
2197 pending = 0; /* too early */
2201 spin_unlock_irq(&chip->reg_lock);
2208 /* clear irq_pending flags and assure no on-going workq */
2209 static void azx_clear_irq_pending(struct azx *chip)
2213 spin_lock_irq(&chip->reg_lock);
2214 for (i = 0; i < chip->num_streams; i++)
2215 chip->azx_dev[i].irq_pending = 0;
2216 spin_unlock_irq(&chip->reg_lock);
2220 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2221 struct vm_area_struct *area)
2223 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2224 struct azx *chip = apcm->chip;
2225 if (!azx_snoop(chip))
2226 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2227 return snd_pcm_lib_default_mmap(substream, area);
2230 #define azx_pcm_mmap NULL
2233 static struct snd_pcm_ops azx_pcm_ops = {
2234 .open = azx_pcm_open,
2235 .close = azx_pcm_close,
2236 .ioctl = snd_pcm_lib_ioctl,
2237 .hw_params = azx_pcm_hw_params,
2238 .hw_free = azx_pcm_hw_free,
2239 .prepare = azx_pcm_prepare,
2240 .trigger = azx_pcm_trigger,
2241 .pointer = azx_pcm_pointer,
2242 .mmap = azx_pcm_mmap,
2243 .page = snd_pcm_sgbuf_ops_page,
2246 static void azx_pcm_free(struct snd_pcm *pcm)
2248 struct azx_pcm *apcm = pcm->private_data;
2250 list_del(&apcm->list);
2255 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2258 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2259 struct hda_pcm *cpcm)
2261 struct azx *chip = bus->private_data;
2262 struct snd_pcm *pcm;
2263 struct azx_pcm *apcm;
2264 int pcm_dev = cpcm->device;
2268 list_for_each_entry(apcm, &chip->pcm_list, list) {
2269 if (apcm->pcm->device == pcm_dev) {
2270 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2274 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2275 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2276 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2280 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2281 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2286 apcm->codec = codec;
2287 pcm->private_data = apcm;
2288 pcm->private_free = azx_pcm_free;
2289 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2290 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2291 list_add_tail(&apcm->list, &chip->pcm_list);
2293 for (s = 0; s < 2; s++) {
2294 apcm->hinfo[s] = &cpcm->stream[s];
2295 if (cpcm->stream[s].substreams)
2296 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2298 /* buffer pre-allocation */
2299 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2300 if (size > MAX_PREALLOC_SIZE)
2301 size = MAX_PREALLOC_SIZE;
2302 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2303 snd_dma_pci_data(chip->pci),
2304 size, MAX_PREALLOC_SIZE);
2309 * mixer creation - all stuff is implemented in hda module
2311 static int __devinit azx_mixer_create(struct azx *chip)
2313 return snd_hda_build_controls(chip->bus);
2318 * initialize SD streams
2320 static int __devinit azx_init_stream(struct azx *chip)
2324 /* initialize each stream (aka device)
2325 * assign the starting bdl address to each stream (device)
2328 for (i = 0; i < chip->num_streams; i++) {
2329 struct azx_dev *azx_dev = &chip->azx_dev[i];
2330 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2331 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2332 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2333 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2334 azx_dev->sd_int_sta_mask = 1 << i;
2335 /* stream tag: must be non-zero and unique */
2337 azx_dev->stream_tag = i + 1;
2343 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2345 if (request_irq(chip->pci->irq, azx_interrupt,
2346 chip->msi ? 0 : IRQF_SHARED,
2347 KBUILD_MODNAME, chip)) {
2348 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2349 "disabling device\n", chip->pci->irq);
2351 snd_card_disconnect(chip->card);
2354 chip->irq = chip->pci->irq;
2355 pci_intx(chip->pci, !chip->msi);
2360 static void azx_stop_chip(struct azx *chip)
2362 if (!chip->initialized)
2365 /* disable interrupts */
2366 azx_int_disable(chip);
2367 azx_int_clear(chip);
2369 /* disable CORB/RIRB */
2370 azx_free_cmd_io(chip);
2372 /* disable position buffer */
2373 azx_writel(chip, DPLBASE, 0);
2374 azx_writel(chip, DPUBASE, 0);
2376 chip->initialized = 0;
2379 #ifdef CONFIG_SND_HDA_POWER_SAVE
2380 /* power-up/down the controller */
2381 static void azx_power_notify(struct hda_bus *bus)
2383 struct azx *chip = bus->private_data;
2384 struct hda_codec *c;
2387 list_for_each_entry(c, &bus->codec_list, list) {
2394 azx_init_chip(chip, 1);
2395 else if (chip->running && power_save_controller &&
2396 !bus->power_keep_link_on)
2397 azx_stop_chip(chip);
2399 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2406 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2408 struct snd_card *card = pci_get_drvdata(pci);
2409 struct azx *chip = card->private_data;
2412 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2413 azx_clear_irq_pending(chip);
2414 list_for_each_entry(p, &chip->pcm_list, list)
2415 snd_pcm_suspend_all(p->pcm);
2416 if (chip->initialized)
2417 snd_hda_suspend(chip->bus);
2418 azx_stop_chip(chip);
2419 if (chip->irq >= 0) {
2420 free_irq(chip->irq, chip);
2424 pci_disable_msi(chip->pci);
2425 pci_disable_device(pci);
2426 pci_save_state(pci);
2427 pci_set_power_state(pci, pci_choose_state(pci, state));
2431 static int azx_resume(struct pci_dev *pci)
2433 struct snd_card *card = pci_get_drvdata(pci);
2434 struct azx *chip = card->private_data;
2436 pci_set_power_state(pci, PCI_D0);
2437 pci_restore_state(pci);
2438 if (pci_enable_device(pci) < 0) {
2439 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2440 "disabling device\n");
2441 snd_card_disconnect(card);
2444 pci_set_master(pci);
2446 if (pci_enable_msi(pci) < 0)
2448 if (azx_acquire_irq(chip, 1) < 0)
2452 azx_init_chip(chip, 1);
2454 snd_hda_resume(chip->bus);
2455 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2458 #endif /* CONFIG_PM */
2462 * reboot notifier for hang-up problem at power-down
2464 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2466 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2467 snd_hda_bus_reboot_notify(chip->bus);
2468 azx_stop_chip(chip);
2472 static void azx_notifier_register(struct azx *chip)
2474 chip->reboot_notifier.notifier_call = azx_halt;
2475 register_reboot_notifier(&chip->reboot_notifier);
2478 static void azx_notifier_unregister(struct azx *chip)
2480 if (chip->reboot_notifier.notifier_call)
2481 unregister_reboot_notifier(&chip->reboot_notifier);
2484 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2485 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2487 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2489 #ifdef SUPPORT_VGA_SWITCHEROO
2490 static void azx_vs_set_state(struct pci_dev *pci,
2491 enum vga_switcheroo_state state)
2493 struct snd_card *card = pci_get_drvdata(pci);
2494 struct azx *chip = card->private_data;
2497 if (chip->init_failed)
2500 disabled = (state == VGA_SWITCHEROO_OFF);
2501 if (chip->disabled == disabled)
2505 chip->disabled = disabled;
2507 snd_printk(KERN_INFO SFX
2508 "%s: Start delayed initialization\n",
2509 pci_name(chip->pci));
2510 if (azx_first_init(chip) < 0 ||
2511 azx_probe_continue(chip) < 0) {
2512 snd_printk(KERN_ERR SFX
2513 "%s: initialization error\n",
2514 pci_name(chip->pci));
2515 chip->init_failed = true;
2519 snd_printk(KERN_INFO SFX
2520 "%s %s via VGA-switcheroo\n",
2521 disabled ? "Disabling" : "Enabling",
2522 pci_name(chip->pci));
2524 azx_suspend(pci, PMSG_FREEZE);
2525 chip->disabled = true;
2526 snd_hda_lock_devices(chip->bus);
2528 snd_hda_unlock_devices(chip->bus);
2529 chip->disabled = false;
2535 static bool azx_vs_can_switch(struct pci_dev *pci)
2537 struct snd_card *card = pci_get_drvdata(pci);
2538 struct azx *chip = card->private_data;
2540 if (chip->init_failed)
2542 if (chip->disabled || !chip->bus)
2544 if (snd_hda_lock_devices(chip->bus))
2546 snd_hda_unlock_devices(chip->bus);
2550 static void __devinit init_vga_switcheroo(struct azx *chip)
2552 struct pci_dev *p = get_bound_vga(chip->pci);
2554 snd_printk(KERN_INFO SFX
2555 "%s: Handle VGA-switcheroo audio client\n",
2556 pci_name(chip->pci));
2557 chip->use_vga_switcheroo = 1;
2562 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2563 .set_gpu_state = azx_vs_set_state,
2564 .can_switch = azx_vs_can_switch,
2567 static int __devinit register_vga_switcheroo(struct azx *chip)
2569 if (!chip->use_vga_switcheroo)
2571 /* FIXME: currently only handling DIS controller
2572 * is there any machine with two switchable HDMI audio controllers?
2574 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2579 #define init_vga_switcheroo(chip) /* NOP */
2580 #define register_vga_switcheroo(chip) 0
2581 #endif /* SUPPORT_VGA_SWITCHER */
2586 static int azx_free(struct azx *chip)
2590 azx_notifier_unregister(chip);
2592 if (use_vga_switcheroo(chip)) {
2593 if (chip->disabled && chip->bus)
2594 snd_hda_unlock_devices(chip->bus);
2595 vga_switcheroo_unregister_client(chip->pci);
2598 if (chip->initialized) {
2599 azx_clear_irq_pending(chip);
2600 for (i = 0; i < chip->num_streams; i++)
2601 azx_stream_stop(chip, &chip->azx_dev[i]);
2602 azx_stop_chip(chip);
2606 free_irq(chip->irq, (void*)chip);
2608 pci_disable_msi(chip->pci);
2609 if (chip->remap_addr)
2610 iounmap(chip->remap_addr);
2612 if (chip->azx_dev) {
2613 for (i = 0; i < chip->num_streams; i++)
2614 if (chip->azx_dev[i].bdl.area) {
2615 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2616 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2619 if (chip->rb.area) {
2620 mark_pages_wc(chip, &chip->rb, false);
2621 snd_dma_free_pages(&chip->rb);
2623 if (chip->posbuf.area) {
2624 mark_pages_wc(chip, &chip->posbuf, false);
2625 snd_dma_free_pages(&chip->posbuf);
2627 if (chip->region_requested)
2628 pci_release_regions(chip->pci);
2629 pci_disable_device(chip->pci);
2630 kfree(chip->azx_dev);
2636 static int azx_dev_free(struct snd_device *device)
2638 return azx_free(device->device_data);
2642 * Check of disabled HDMI controller by vga-switcheroo
2644 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2648 /* check only discrete GPU */
2649 switch (pci->vendor) {
2650 case PCI_VENDOR_ID_ATI:
2651 case PCI_VENDOR_ID_AMD:
2652 case PCI_VENDOR_ID_NVIDIA:
2653 if (pci->devfn == 1) {
2654 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2655 pci->bus->number, 0);
2657 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2667 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2669 bool vga_inactive = false;
2670 struct pci_dev *p = get_bound_vga(pci);
2673 if (vga_default_device() && p != vga_default_device())
2674 vga_inactive = true;
2677 return vga_inactive;
2681 * white/black-listing for position_fix
2683 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2684 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2685 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2686 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2687 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2688 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2689 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2690 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2691 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2692 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2693 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2694 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2695 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2696 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2697 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2701 static int __devinit check_position_fix(struct azx *chip, int fix)
2703 const struct snd_pci_quirk *q;
2707 case POS_FIX_POSBUF:
2708 case POS_FIX_VIACOMBO:
2713 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2716 "hda_intel: position_fix set to %d "
2717 "for device %04x:%04x\n",
2718 q->value, q->subvendor, q->subdevice);
2722 /* Check VIA/ATI HD Audio Controller exist */
2723 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2724 snd_printd(SFX "Using VIACOMBO position fix\n");
2725 return POS_FIX_VIACOMBO;
2727 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2728 snd_printd(SFX "Using LPIB position fix\n");
2729 return POS_FIX_LPIB;
2731 return POS_FIX_AUTO;
2735 * black-lists for probe_mask
2737 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2738 /* Thinkpad often breaks the controller communication when accessing
2739 * to the non-working (or non-existing) modem codec slot.
2741 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2742 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2743 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2745 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2746 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2747 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2748 /* forced codec slots */
2749 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2750 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2751 /* WinFast VP200 H (Teradici) user reported broken communication */
2752 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2756 #define AZX_FORCE_CODEC_MASK 0x100
2758 static void __devinit check_probe_mask(struct azx *chip, int dev)
2760 const struct snd_pci_quirk *q;
2762 chip->codec_probe_mask = probe_mask[dev];
2763 if (chip->codec_probe_mask == -1) {
2764 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2767 "hda_intel: probe_mask set to 0x%x "
2768 "for device %04x:%04x\n",
2769 q->value, q->subvendor, q->subdevice);
2770 chip->codec_probe_mask = q->value;
2774 /* check forced option */
2775 if (chip->codec_probe_mask != -1 &&
2776 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2777 chip->codec_mask = chip->codec_probe_mask & 0xff;
2778 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2784 * white/black-list for enable_msi
2786 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2787 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2788 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2789 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2790 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2791 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2795 static void __devinit check_msi(struct azx *chip)
2797 const struct snd_pci_quirk *q;
2799 if (enable_msi >= 0) {
2800 chip->msi = !!enable_msi;
2803 chip->msi = 1; /* enable MSI as default */
2804 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2807 "hda_intel: msi for device %04x:%04x set to %d\n",
2808 q->subvendor, q->subdevice, q->value);
2809 chip->msi = q->value;
2813 /* NVidia chipsets seem to cause troubles with MSI */
2814 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2815 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2820 /* check the snoop mode availability */
2821 static void __devinit azx_check_snoop_available(struct azx *chip)
2823 bool snoop = chip->snoop;
2825 switch (chip->driver_type) {
2826 case AZX_DRIVER_VIA:
2827 /* force to non-snoop mode for a new VIA controller
2832 pci_read_config_byte(chip->pci, 0x42, &val);
2833 if (!(val & 0x80) && chip->pci->revision == 0x30)
2837 case AZX_DRIVER_ATIHDMI_NS:
2838 /* new ATI HDMI requires non-snoop */
2843 if (snoop != chip->snoop) {
2844 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2845 snoop ? "snoop" : "non-snoop");
2846 chip->snoop = snoop;
2853 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2854 int dev, unsigned int driver_caps,
2857 static struct snd_device_ops ops = {
2858 .dev_free = azx_dev_free,
2865 err = pci_enable_device(pci);
2869 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2871 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2872 pci_disable_device(pci);
2876 spin_lock_init(&chip->reg_lock);
2877 mutex_init(&chip->open_mutex);
2881 chip->driver_caps = driver_caps;
2882 chip->driver_type = driver_caps & 0xff;
2884 chip->dev_index = dev;
2885 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2886 INIT_LIST_HEAD(&chip->pcm_list);
2887 init_vga_switcheroo(chip);
2889 chip->position_fix[0] = chip->position_fix[1] =
2890 check_position_fix(chip, position_fix[dev]);
2891 /* combo mode uses LPIB for playback */
2892 if (chip->position_fix[0] == POS_FIX_COMBO) {
2893 chip->position_fix[0] = POS_FIX_LPIB;
2894 chip->position_fix[1] = POS_FIX_AUTO;
2897 check_probe_mask(chip, dev);
2899 chip->single_cmd = single_cmd;
2900 chip->snoop = hda_snoop;
2901 azx_check_snoop_available(chip);
2903 if (bdl_pos_adj[dev] < 0) {
2904 switch (chip->driver_type) {
2905 case AZX_DRIVER_ICH:
2906 case AZX_DRIVER_PCH:
2907 bdl_pos_adj[dev] = 1;
2910 bdl_pos_adj[dev] = 32;
2915 if (check_hdmi_disabled(pci)) {
2916 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2918 if (use_vga_switcheroo(chip)) {
2919 snd_printk(KERN_INFO SFX "Delaying initialization\n");
2920 chip->disabled = true;
2924 pci_disable_device(pci);
2928 err = azx_first_init(chip);
2935 err = register_vga_switcheroo(chip);
2937 snd_printk(KERN_ERR SFX
2938 "Error registering VGA-switcheroo client\n");
2943 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2945 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2954 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
2956 int dev = chip->dev_index;
2957 struct pci_dev *pci = chip->pci;
2958 struct snd_card *card = chip->card;
2960 unsigned short gcap;
2962 #if BITS_PER_LONG != 64
2963 /* Fix up base address on ULI M5461 */
2964 if (chip->driver_type == AZX_DRIVER_ULI) {
2966 pci_read_config_word(pci, 0x40, &tmp3);
2967 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2968 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2972 err = pci_request_regions(pci, "ICH HD audio");
2975 chip->region_requested = 1;
2977 chip->addr = pci_resource_start(pci, 0);
2978 chip->remap_addr = pci_ioremap_bar(pci, 0);
2979 if (chip->remap_addr == NULL) {
2980 snd_printk(KERN_ERR SFX "ioremap error\n");
2985 if (pci_enable_msi(pci) < 0)
2988 if (azx_acquire_irq(chip, 0) < 0)
2991 pci_set_master(pci);
2992 synchronize_irq(chip->irq);
2994 gcap = azx_readw(chip, GCAP);
2995 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2997 /* disable SB600 64bit support for safety */
2998 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2999 struct pci_dev *p_smbus;
3000 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3001 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3004 if (p_smbus->revision < 0x30)
3005 gcap &= ~ICH6_GCAP_64OK;
3006 pci_dev_put(p_smbus);
3010 /* disable 64bit DMA address on some devices */
3011 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3012 snd_printd(SFX "Disabling 64bit DMA\n");
3013 gcap &= ~ICH6_GCAP_64OK;
3016 /* disable buffer size rounding to 128-byte multiples if supported */
3017 if (align_buffer_size >= 0)
3018 chip->align_buffer_size = !!align_buffer_size;
3020 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3021 chip->align_buffer_size = 0;
3022 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3023 chip->align_buffer_size = 1;
3025 chip->align_buffer_size = 1;
3028 /* allow 64bit DMA address if supported by H/W */
3029 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3030 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3032 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3033 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3036 /* read number of streams from GCAP register instead of using
3039 chip->capture_streams = (gcap >> 8) & 0x0f;
3040 chip->playback_streams = (gcap >> 12) & 0x0f;
3041 if (!chip->playback_streams && !chip->capture_streams) {
3042 /* gcap didn't give any info, switching to old method */
3044 switch (chip->driver_type) {
3045 case AZX_DRIVER_ULI:
3046 chip->playback_streams = ULI_NUM_PLAYBACK;
3047 chip->capture_streams = ULI_NUM_CAPTURE;
3049 case AZX_DRIVER_ATIHDMI:
3050 case AZX_DRIVER_ATIHDMI_NS:
3051 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3052 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3054 case AZX_DRIVER_GENERIC:
3056 chip->playback_streams = ICH6_NUM_PLAYBACK;
3057 chip->capture_streams = ICH6_NUM_CAPTURE;
3061 chip->capture_index_offset = 0;
3062 chip->playback_index_offset = chip->capture_streams;
3063 chip->num_streams = chip->playback_streams + chip->capture_streams;
3064 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3066 if (!chip->azx_dev) {
3067 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3071 for (i = 0; i < chip->num_streams; i++) {
3072 /* allocate memory for the BDL for each stream */
3073 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3074 snd_dma_pci_data(chip->pci),
3075 BDL_SIZE, &chip->azx_dev[i].bdl);
3077 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3080 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3082 /* allocate memory for the position buffer */
3083 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3084 snd_dma_pci_data(chip->pci),
3085 chip->num_streams * 8, &chip->posbuf);
3087 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3090 mark_pages_wc(chip, &chip->posbuf, true);
3091 /* allocate CORB/RIRB */
3092 err = azx_alloc_cmd_io(chip);
3096 /* initialize streams */
3097 azx_init_stream(chip);
3099 /* initialize chip */
3101 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3103 /* codec detection */
3104 if (!chip->codec_mask) {
3105 snd_printk(KERN_ERR SFX "no codecs found!\n");
3109 strcpy(card->driver, "HDA-Intel");
3110 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3111 sizeof(card->shortname));
3112 snprintf(card->longname, sizeof(card->longname),
3113 "%s at 0x%lx irq %i",
3114 card->shortname, chip->addr, chip->irq);
3119 static void power_down_all_codecs(struct azx *chip)
3121 #ifdef CONFIG_SND_HDA_POWER_SAVE
3122 /* The codecs were powered up in snd_hda_codec_new().
3123 * Now all initialization done, so turn them down if possible
3125 struct hda_codec *codec;
3126 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3127 snd_hda_power_down(codec);
3132 static int __devinit azx_probe(struct pci_dev *pci,
3133 const struct pci_device_id *pci_id)
3136 struct snd_card *card;
3140 if (dev >= SNDRV_CARDS)
3147 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3149 snd_printk(KERN_ERR SFX "Error creating card!\n");
3153 /* set this here since it's referred in snd_hda_load_patch() */
3154 snd_card_set_dev(card, &pci->dev);
3156 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3159 card->private_data = chip;
3161 if (!chip->disabled) {
3162 err = azx_probe_continue(chip);
3167 pci_set_drvdata(pci, card);
3173 snd_card_free(card);
3177 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3179 int dev = chip->dev_index;
3182 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3183 chip->beep_mode = beep_mode[dev];
3186 /* create codec instances */
3187 err = azx_codec_create(chip, model[dev]);
3190 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3191 if (patch[dev] && *patch[dev]) {
3192 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3194 err = snd_hda_load_patch(chip->bus, patch[dev]);
3199 if ((probe_only[dev] & 1) == 0) {
3200 err = azx_codec_configure(chip);
3205 /* create PCM streams */
3206 err = snd_hda_build_pcms(chip->bus);
3210 /* create mixer controls */
3211 err = azx_mixer_create(chip);
3215 err = snd_card_register(chip->card);
3220 power_down_all_codecs(chip);
3221 azx_notifier_register(chip);
3226 chip->init_failed = 1;
3230 static void __devexit azx_remove(struct pci_dev *pci)
3232 struct snd_card *card = pci_get_drvdata(pci);
3234 snd_card_free(card);
3235 pci_set_drvdata(pci, NULL);
3239 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3241 { PCI_DEVICE(0x8086, 0x1c20),
3242 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3243 AZX_DCAPS_BUFSIZE },
3245 { PCI_DEVICE(0x8086, 0x1d20),
3246 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3249 { PCI_DEVICE(0x8086, 0x1e20),
3250 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3253 { PCI_DEVICE(0x8086, 0x8c20),
3254 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3257 { PCI_DEVICE(0x8086, 0x811b),
3258 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3259 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3260 { PCI_DEVICE(0x8086, 0x080a),
3261 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3262 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3264 { PCI_DEVICE(0x8086, 0x2668),
3265 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3266 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3267 { PCI_DEVICE(0x8086, 0x27d8),
3268 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3269 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3270 { PCI_DEVICE(0x8086, 0x269a),
3271 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3272 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3273 { PCI_DEVICE(0x8086, 0x284b),
3274 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3275 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3276 { PCI_DEVICE(0x8086, 0x293e),
3277 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3278 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3279 { PCI_DEVICE(0x8086, 0x293f),
3280 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3281 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3282 { PCI_DEVICE(0x8086, 0x3a3e),
3283 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3284 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3285 { PCI_DEVICE(0x8086, 0x3a6e),
3286 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3287 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3289 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3290 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3291 .class_mask = 0xffffff,
3292 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3293 /* ATI SB 450/600/700/800/900 */
3294 { PCI_DEVICE(0x1002, 0x437b),
3295 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3296 { PCI_DEVICE(0x1002, 0x4383),
3297 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3299 { PCI_DEVICE(0x1022, 0x780d),
3300 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3302 { PCI_DEVICE(0x1002, 0x793b),
3303 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3304 { PCI_DEVICE(0x1002, 0x7919),
3305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3306 { PCI_DEVICE(0x1002, 0x960f),
3307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3308 { PCI_DEVICE(0x1002, 0x970f),
3309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3310 { PCI_DEVICE(0x1002, 0xaa00),
3311 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3312 { PCI_DEVICE(0x1002, 0xaa08),
3313 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3314 { PCI_DEVICE(0x1002, 0xaa10),
3315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3316 { PCI_DEVICE(0x1002, 0xaa18),
3317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3318 { PCI_DEVICE(0x1002, 0xaa20),
3319 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3320 { PCI_DEVICE(0x1002, 0xaa28),
3321 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3322 { PCI_DEVICE(0x1002, 0xaa30),
3323 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3324 { PCI_DEVICE(0x1002, 0xaa38),
3325 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3326 { PCI_DEVICE(0x1002, 0xaa40),
3327 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3328 { PCI_DEVICE(0x1002, 0xaa48),
3329 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3330 { PCI_DEVICE(0x1002, 0x9902),
3331 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3332 { PCI_DEVICE(0x1002, 0xaaa0),
3333 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3334 { PCI_DEVICE(0x1002, 0xaaa8),
3335 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3336 { PCI_DEVICE(0x1002, 0xaab0),
3337 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3338 /* VIA VT8251/VT8237A */
3339 { PCI_DEVICE(0x1106, 0x3288),
3340 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3342 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3344 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3346 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3347 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3348 .class_mask = 0xffffff,
3349 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3351 { PCI_DEVICE(0x6549, 0x1200),
3352 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3353 /* Creative X-Fi (CA0110-IBG) */
3354 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3355 /* the following entry conflicts with snd-ctxfi driver,
3356 * as ctxfi driver mutates from HD-audio to native mode with
3357 * a special command sequence.
3359 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3360 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3361 .class_mask = 0xffffff,
3362 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3363 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3365 /* this entry seems still valid -- i.e. without emu20kx chip */
3366 { PCI_DEVICE(0x1102, 0x0009),
3367 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3368 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3371 { PCI_DEVICE(0x1102, 0x0010),
3372 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3373 { PCI_DEVICE(0x1102, 0x0012),
3374 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3376 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3377 /* VMware HDAudio */
3378 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3379 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3380 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3381 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3382 .class_mask = 0xffffff,
3383 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3384 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3385 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3386 .class_mask = 0xffffff,
3387 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3390 MODULE_DEVICE_TABLE(pci, azx_ids);
3392 /* pci_driver definition */
3393 static struct pci_driver azx_driver = {
3394 .name = KBUILD_MODNAME,
3395 .id_table = azx_ids,
3397 .remove = __devexit_p(azx_remove),
3399 .suspend = azx_suspend,
3400 .resume = azx_resume,
3404 module_pci_driver(azx_driver);