3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
68 module_param_array(index, int, NULL, 0444);
69 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
70 module_param_array(id, charp, NULL, 0444);
71 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
74 module_param_array(model, charp, NULL, 0444);
75 MODULE_PARM_DESC(model, "Use the given board model.");
76 module_param_array(position_fix, int, NULL, 0444);
77 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
78 "(0 = auto, 1 = none, 2 = POSBUF).");
79 module_param_array(bdl_pos_adj, int, NULL, 0644);
80 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
81 module_param_array(probe_mask, int, NULL, 0444);
82 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
83 module_param_array(probe_only, bool, NULL, 0444);
84 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
85 module_param(single_cmd, bool, 0444);
86 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
87 "(for debugging only).");
88 module_param(enable_msi, int, 0444);
89 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
90 #ifdef CONFIG_SND_HDA_PATCH_LOADER
91 module_param_array(patch, charp, NULL, 0444);
92 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
95 #ifdef CONFIG_SND_HDA_POWER_SAVE
96 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
97 module_param(power_save, int, 0644);
98 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
99 "(in second, 0 = disable).");
101 /* reset the HD-audio controller in power save mode.
102 * this may give more power-saving, but will take longer time to
105 static int power_save_controller = 1;
106 module_param(power_save_controller, bool, 0644);
107 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
110 MODULE_LICENSE("GPL");
111 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
136 MODULE_DESCRIPTION("Intel HDA driver");
138 #ifdef CONFIG_SND_VERBOSE_PRINTK
139 #define SFX /* nop */
141 #define SFX "hda-intel: "
147 #define ICH6_REG_GCAP 0x00
148 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
149 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
150 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
151 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
152 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
153 #define ICH6_REG_VMIN 0x02
154 #define ICH6_REG_VMAJ 0x03
155 #define ICH6_REG_OUTPAY 0x04
156 #define ICH6_REG_INPAY 0x06
157 #define ICH6_REG_GCTL 0x08
158 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
159 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
160 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
161 #define ICH6_REG_WAKEEN 0x0c
162 #define ICH6_REG_STATESTS 0x0e
163 #define ICH6_REG_GSTS 0x10
164 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
165 #define ICH6_REG_INTCTL 0x20
166 #define ICH6_REG_INTSTS 0x24
167 #define ICH6_REG_WALCLK 0x30
168 #define ICH6_REG_SYNC 0x34
169 #define ICH6_REG_CORBLBASE 0x40
170 #define ICH6_REG_CORBUBASE 0x44
171 #define ICH6_REG_CORBWP 0x48
172 #define ICH6_REG_CORBRP 0x4a
173 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
174 #define ICH6_REG_CORBCTL 0x4c
175 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
176 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
177 #define ICH6_REG_CORBSTS 0x4d
178 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
179 #define ICH6_REG_CORBSIZE 0x4e
181 #define ICH6_REG_RIRBLBASE 0x50
182 #define ICH6_REG_RIRBUBASE 0x54
183 #define ICH6_REG_RIRBWP 0x58
184 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
185 #define ICH6_REG_RINTCNT 0x5a
186 #define ICH6_REG_RIRBCTL 0x5c
187 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
188 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
189 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
190 #define ICH6_REG_RIRBSTS 0x5d
191 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
192 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
193 #define ICH6_REG_RIRBSIZE 0x5e
195 #define ICH6_REG_IC 0x60
196 #define ICH6_REG_IR 0x64
197 #define ICH6_REG_IRS 0x68
198 #define ICH6_IRS_VALID (1<<1)
199 #define ICH6_IRS_BUSY (1<<0)
201 #define ICH6_REG_DPLBASE 0x70
202 #define ICH6_REG_DPUBASE 0x74
203 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
205 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
206 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
208 /* stream register offsets from stream base */
209 #define ICH6_REG_SD_CTL 0x00
210 #define ICH6_REG_SD_STS 0x03
211 #define ICH6_REG_SD_LPIB 0x04
212 #define ICH6_REG_SD_CBL 0x08
213 #define ICH6_REG_SD_LVI 0x0c
214 #define ICH6_REG_SD_FIFOW 0x0e
215 #define ICH6_REG_SD_FIFOSIZE 0x10
216 #define ICH6_REG_SD_FORMAT 0x12
217 #define ICH6_REG_SD_BDLPL 0x18
218 #define ICH6_REG_SD_BDLPU 0x1c
221 #define ICH6_PCIREG_TCSEL 0x44
227 /* max number of SDs */
228 /* ICH, ATI and VIA have 4 playback and 4 capture */
229 #define ICH6_NUM_CAPTURE 4
230 #define ICH6_NUM_PLAYBACK 4
232 /* ULI has 6 playback and 5 capture */
233 #define ULI_NUM_CAPTURE 5
234 #define ULI_NUM_PLAYBACK 6
236 /* ATI HDMI has 1 playback and 0 capture */
237 #define ATIHDMI_NUM_CAPTURE 0
238 #define ATIHDMI_NUM_PLAYBACK 1
240 /* TERA has 4 playback and 3 capture */
241 #define TERA_NUM_CAPTURE 3
242 #define TERA_NUM_PLAYBACK 4
244 /* this number is statically defined for simplicity */
245 #define MAX_AZX_DEV 16
247 /* max number of fragments - we may use more if allocating more pages for BDL */
248 #define BDL_SIZE 4096
249 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
250 #define AZX_MAX_FRAG 32
251 /* max buffer size - no h/w limit, you can increase as you like */
252 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
253 /* max number of PCM devics per card */
254 #define AZX_MAX_PCMS 8
256 /* RIRB int mask: overrun[2], response[0] */
257 #define RIRB_INT_RESPONSE 0x01
258 #define RIRB_INT_OVERRUN 0x04
259 #define RIRB_INT_MASK 0x05
261 /* STATESTS int mask: S3,SD2,SD1,SD0 */
262 #define AZX_MAX_CODECS 4
263 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
266 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
267 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
268 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
269 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
270 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
271 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
272 #define SD_CTL_STREAM_TAG_SHIFT 20
274 /* SD_CTL and SD_STS */
275 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
276 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
277 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
278 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
282 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
284 /* INTCTL and INTSTS */
285 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
286 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
287 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
289 /* below are so far hardcoded - should read registers in future */
290 #define ICH6_MAX_CORB_ENTRIES 256
291 #define ICH6_MAX_RIRB_ENTRIES 256
293 /* position fix mode */
300 /* Defines for ATI HD Audio support in SB450 south bridge */
301 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
302 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
304 /* Defines for Nvidia HDA support */
305 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
306 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
307 #define NVIDIA_HDA_ISTRM_COH 0x4d
308 #define NVIDIA_HDA_OSTRM_COH 0x4c
309 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
311 /* Defines for Intel SCH HDA snoop control */
312 #define INTEL_SCH_HDA_DEVC 0x78
313 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
315 /* Define IN stream 0 FIFO size offset in VIA controller */
316 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
317 /* Define VIA HD Audio Device ID*/
318 #define VIA_HDAC_DEVICE_ID 0x3288
320 /* HD Audio class code */
321 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
327 struct snd_dma_buffer bdl; /* BDL buffer */
328 u32 *posbuf; /* position buffer pointer */
330 unsigned int bufsize; /* size of the play buffer in bytes */
331 unsigned int period_bytes; /* size of the period in bytes */
332 unsigned int frags; /* number for period in the play buffer */
333 unsigned int fifo_size; /* FIFO size */
334 unsigned long start_jiffies; /* start + minimum jiffies */
335 unsigned long min_jiffies; /* minimum jiffies before position is valid */
337 void __iomem *sd_addr; /* stream descriptor pointer */
339 u32 sd_int_sta_mask; /* stream int status mask */
342 struct snd_pcm_substream *substream; /* assigned substream,
345 unsigned int format_val; /* format value to be set in the
346 * controller and the codec
348 unsigned char stream_tag; /* assigned stream */
349 unsigned char index; /* stream index */
351 unsigned int opened :1;
352 unsigned int running :1;
353 unsigned int irq_pending :1;
354 unsigned int start_flag: 1; /* stream full start flag */
357 * A flag to ensure DMA position is 0
358 * when link position is not greater than FIFO size
360 unsigned int insufficient :1;
365 u32 *buf; /* CORB/RIRB buffer
366 * Each CORB entry is 4byte, RIRB is 8byte
368 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
370 unsigned short rp, wp; /* read/write pointers */
371 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
372 u32 res[AZX_MAX_CODECS]; /* last read value */
376 struct snd_card *card;
380 /* chip type specific */
382 int playback_streams;
383 int playback_index_offset;
385 int capture_index_offset;
390 void __iomem *remap_addr;
395 struct mutex open_mutex;
397 /* streams (x num_streams) */
398 struct azx_dev *azx_dev;
401 struct snd_pcm *pcm[AZX_MAX_PCMS];
404 unsigned short codec_mask;
405 int codec_probe_mask; /* copied from probe_mask option */
412 /* CORB/RIRB and position buffers */
413 struct snd_dma_buffer rb;
414 struct snd_dma_buffer posbuf;
418 unsigned int running :1;
419 unsigned int initialized :1;
420 unsigned int single_cmd :1;
421 unsigned int polling_mode :1;
423 unsigned int irq_pending_warned :1;
424 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
425 unsigned int probing :1; /* codec probing phase */
428 unsigned int last_cmd[AZX_MAX_CODECS];
430 /* for pending irqs */
431 struct work_struct irq_pending_work;
433 /* reboot notifier (for mysterious hangup problem at power-down) */
434 struct notifier_block reboot_notifier;
449 AZX_NUM_DRIVERS, /* keep this as last entry */
452 static char *driver_short_names[] __devinitdata = {
453 [AZX_DRIVER_ICH] = "HDA Intel",
454 [AZX_DRIVER_SCH] = "HDA Intel MID",
455 [AZX_DRIVER_ATI] = "HDA ATI SB",
456 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
457 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
458 [AZX_DRIVER_SIS] = "HDA SIS966",
459 [AZX_DRIVER_ULI] = "HDA ULI M5461",
460 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
461 [AZX_DRIVER_TERA] = "HDA Teradici",
462 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
466 * macros for easy use
468 #define azx_writel(chip,reg,value) \
469 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
470 #define azx_readl(chip,reg) \
471 readl((chip)->remap_addr + ICH6_REG_##reg)
472 #define azx_writew(chip,reg,value) \
473 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
474 #define azx_readw(chip,reg) \
475 readw((chip)->remap_addr + ICH6_REG_##reg)
476 #define azx_writeb(chip,reg,value) \
477 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
478 #define azx_readb(chip,reg) \
479 readb((chip)->remap_addr + ICH6_REG_##reg)
481 #define azx_sd_writel(dev,reg,value) \
482 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
483 #define azx_sd_readl(dev,reg) \
484 readl((dev)->sd_addr + ICH6_REG_##reg)
485 #define azx_sd_writew(dev,reg,value) \
486 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
487 #define azx_sd_readw(dev,reg) \
488 readw((dev)->sd_addr + ICH6_REG_##reg)
489 #define azx_sd_writeb(dev,reg,value) \
490 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
491 #define azx_sd_readb(dev,reg) \
492 readb((dev)->sd_addr + ICH6_REG_##reg)
494 /* for pcm support */
495 #define get_azx_dev(substream) (substream->runtime->private_data)
497 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
500 * Interface for HD codec
504 * CORB / RIRB interface
506 static int azx_alloc_cmd_io(struct azx *chip)
510 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
511 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
512 snd_dma_pci_data(chip->pci),
513 PAGE_SIZE, &chip->rb);
515 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
521 static void azx_init_cmd_io(struct azx *chip)
523 spin_lock_irq(&chip->reg_lock);
525 chip->corb.addr = chip->rb.addr;
526 chip->corb.buf = (u32 *)chip->rb.area;
527 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
528 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
530 /* set the corb size to 256 entries (ULI requires explicitly) */
531 azx_writeb(chip, CORBSIZE, 0x02);
532 /* set the corb write pointer to 0 */
533 azx_writew(chip, CORBWP, 0);
534 /* reset the corb hw read pointer */
535 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
536 /* enable corb dma */
537 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
540 chip->rirb.addr = chip->rb.addr + 2048;
541 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
542 chip->rirb.wp = chip->rirb.rp = 0;
543 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
544 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
545 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
547 /* set the rirb size to 256 entries (ULI requires explicitly) */
548 azx_writeb(chip, RIRBSIZE, 0x02);
549 /* reset the rirb hw write pointer */
550 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
551 /* set N=1, get RIRB response interrupt for new entry */
552 azx_writew(chip, RINTCNT, 1);
553 /* enable rirb dma and response irq */
554 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
555 spin_unlock_irq(&chip->reg_lock);
558 static void azx_free_cmd_io(struct azx *chip)
560 spin_lock_irq(&chip->reg_lock);
561 /* disable ringbuffer DMAs */
562 azx_writeb(chip, RIRBCTL, 0);
563 azx_writeb(chip, CORBCTL, 0);
564 spin_unlock_irq(&chip->reg_lock);
567 static unsigned int azx_command_addr(u32 cmd)
569 unsigned int addr = cmd >> 28;
571 if (addr >= AZX_MAX_CODECS) {
579 static unsigned int azx_response_addr(u32 res)
581 unsigned int addr = res & 0xf;
583 if (addr >= AZX_MAX_CODECS) {
592 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
594 struct azx *chip = bus->private_data;
595 unsigned int addr = azx_command_addr(val);
598 spin_lock_irq(&chip->reg_lock);
600 /* add command to corb */
601 wp = azx_readb(chip, CORBWP);
603 wp %= ICH6_MAX_CORB_ENTRIES;
605 chip->rirb.cmds[addr]++;
606 chip->corb.buf[wp] = cpu_to_le32(val);
607 azx_writel(chip, CORBWP, wp);
609 spin_unlock_irq(&chip->reg_lock);
614 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
616 /* retrieve RIRB entry - called from interrupt handler */
617 static void azx_update_rirb(struct azx *chip)
623 wp = azx_readb(chip, RIRBWP);
624 if (wp == chip->rirb.wp)
628 while (chip->rirb.rp != wp) {
630 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
632 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
633 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
634 res = le32_to_cpu(chip->rirb.buf[rp]);
635 addr = azx_response_addr(res_ex);
636 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
637 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
638 else if (chip->rirb.cmds[addr]) {
639 chip->rirb.res[addr] = res;
641 chip->rirb.cmds[addr]--;
643 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
646 chip->last_cmd[addr]);
650 /* receive a response */
651 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
654 struct azx *chip = bus->private_data;
655 unsigned long timeout;
658 timeout = jiffies + msecs_to_jiffies(1000);
660 if (chip->polling_mode) {
661 spin_lock_irq(&chip->reg_lock);
662 azx_update_rirb(chip);
663 spin_unlock_irq(&chip->reg_lock);
665 if (!chip->rirb.cmds[addr]) {
668 return chip->rirb.res[addr]; /* the last value */
670 if (time_after(jiffies, timeout))
672 if (bus->needs_damn_long_delay)
673 msleep(2); /* temporary workaround */
681 snd_printk(KERN_WARNING SFX "No response from codec, "
682 "disabling MSI: last cmd=0x%08x\n",
683 chip->last_cmd[addr]);
684 free_irq(chip->irq, chip);
686 pci_disable_msi(chip->pci);
688 if (azx_acquire_irq(chip, 1) < 0) {
695 if (!chip->polling_mode) {
696 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
697 "switching to polling mode: last cmd=0x%08x\n",
698 chip->last_cmd[addr]);
699 chip->polling_mode = 1;
704 /* If this critical timeout happens during the codec probing
705 * phase, this is likely an access to a non-existing codec
706 * slot. Better to return an error and reset the system.
711 /* a fatal communication error; need either to reset or to fallback
712 * to the single_cmd mode
715 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
716 bus->response_reset = 1;
717 return -1; /* give a chance to retry */
720 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
721 "switching to single_cmd mode: last cmd=0x%08x\n",
722 chip->last_cmd[addr]);
723 chip->single_cmd = 1;
724 bus->response_reset = 0;
725 /* re-initialize CORB/RIRB */
726 azx_free_cmd_io(chip);
727 azx_init_cmd_io(chip);
732 * Use the single immediate command instead of CORB/RIRB for simplicity
734 * Note: according to Intel, this is not preferred use. The command was
735 * intended for the BIOS only, and may get confused with unsolicited
736 * responses. So, we shouldn't use it for normal operation from the
738 * I left the codes, however, for debugging/testing purposes.
741 /* receive a response */
742 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
747 /* check IRV busy bit */
748 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
749 /* reuse rirb.res as the response return value */
750 chip->rirb.res[addr] = azx_readl(chip, IR);
755 if (printk_ratelimit())
756 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
757 azx_readw(chip, IRS));
758 chip->rirb.res[addr] = -1;
763 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
765 struct azx *chip = bus->private_data;
766 unsigned int addr = azx_command_addr(val);
771 /* check ICB busy bit */
772 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
773 /* Clear IRV valid bit */
774 azx_writew(chip, IRS, azx_readw(chip, IRS) |
776 azx_writel(chip, IC, val);
777 azx_writew(chip, IRS, azx_readw(chip, IRS) |
779 return azx_single_wait_for_response(chip, addr);
783 if (printk_ratelimit())
784 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
785 azx_readw(chip, IRS), val);
789 /* receive a response */
790 static unsigned int azx_single_get_response(struct hda_bus *bus,
793 struct azx *chip = bus->private_data;
794 return chip->rirb.res[addr];
798 * The below are the main callbacks from hda_codec.
800 * They are just the skeleton to call sub-callbacks according to the
801 * current setting of chip->single_cmd.
805 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
807 struct azx *chip = bus->private_data;
809 chip->last_cmd[azx_command_addr(val)] = val;
810 if (chip->single_cmd)
811 return azx_single_send_cmd(bus, val);
813 return azx_corb_send_cmd(bus, val);
817 static unsigned int azx_get_response(struct hda_bus *bus,
820 struct azx *chip = bus->private_data;
821 if (chip->single_cmd)
822 return azx_single_get_response(bus, addr);
824 return azx_rirb_get_response(bus, addr);
827 #ifdef CONFIG_SND_HDA_POWER_SAVE
828 static void azx_power_notify(struct hda_bus *bus);
831 /* reset codec link */
832 static int azx_reset(struct azx *chip)
837 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
839 /* reset controller */
840 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
843 while (azx_readb(chip, GCTL) && --count)
846 /* delay for >= 100us for codec PLL to settle per spec
847 * Rev 0.9 section 5.5.1
851 /* Bring controller out of reset */
852 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
855 while (!azx_readb(chip, GCTL) && --count)
858 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
861 /* check to see if controller is ready */
862 if (!azx_readb(chip, GCTL)) {
863 snd_printd(SFX "azx_reset: controller not ready!\n");
867 /* Accept unsolicited responses */
868 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
871 if (!chip->codec_mask) {
872 chip->codec_mask = azx_readw(chip, STATESTS);
873 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
884 /* enable interrupts */
885 static void azx_int_enable(struct azx *chip)
887 /* enable controller CIE and GIE */
888 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
889 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
892 /* disable interrupts */
893 static void azx_int_disable(struct azx *chip)
897 /* disable interrupts in stream descriptor */
898 for (i = 0; i < chip->num_streams; i++) {
899 struct azx_dev *azx_dev = &chip->azx_dev[i];
900 azx_sd_writeb(azx_dev, SD_CTL,
901 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
904 /* disable SIE for all streams */
905 azx_writeb(chip, INTCTL, 0);
907 /* disable controller CIE and GIE */
908 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
909 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
912 /* clear interrupts */
913 static void azx_int_clear(struct azx *chip)
917 /* clear stream status */
918 for (i = 0; i < chip->num_streams; i++) {
919 struct azx_dev *azx_dev = &chip->azx_dev[i];
920 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
924 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
926 /* clear rirb status */
927 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
929 /* clear int status */
930 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
934 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
937 * Before stream start, initialize parameter
939 azx_dev->insufficient = 1;
942 azx_writeb(chip, INTCTL,
943 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
944 /* set DMA start and interrupt mask */
945 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
946 SD_CTL_DMA_START | SD_INT_MASK);
950 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
952 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
953 ~(SD_CTL_DMA_START | SD_INT_MASK));
954 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
958 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
960 azx_stream_clear(chip, azx_dev);
962 azx_writeb(chip, INTCTL,
963 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
968 * reset and start the controller registers
970 static void azx_init_chip(struct azx *chip)
972 if (chip->initialized)
975 /* reset controller */
978 /* initialize interrupts */
980 azx_int_enable(chip);
982 /* initialize the codec command I/O */
983 azx_init_cmd_io(chip);
985 /* program the position buffer */
986 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
987 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
989 chip->initialized = 1;
993 * initialize the PCI registers
995 /* update bits in a PCI register byte */
996 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
997 unsigned char mask, unsigned char val)
1001 pci_read_config_byte(pci, reg, &data);
1003 data |= (val & mask);
1004 pci_write_config_byte(pci, reg, data);
1007 static void azx_init_pci(struct azx *chip)
1009 unsigned short snoop;
1011 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1012 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1013 * Ensuring these bits are 0 clears playback static on some HD Audio
1016 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1018 switch (chip->driver_type) {
1019 case AZX_DRIVER_ATI:
1020 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1021 update_pci_byte(chip->pci,
1022 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1023 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1025 case AZX_DRIVER_NVIDIA:
1026 /* For NVIDIA HDA, enable snoop */
1027 update_pci_byte(chip->pci,
1028 NVIDIA_HDA_TRANSREG_ADDR,
1029 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1030 update_pci_byte(chip->pci,
1031 NVIDIA_HDA_ISTRM_COH,
1032 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1033 update_pci_byte(chip->pci,
1034 NVIDIA_HDA_OSTRM_COH,
1035 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1037 case AZX_DRIVER_SCH:
1038 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1039 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1040 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1041 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1042 pci_read_config_word(chip->pci,
1043 INTEL_SCH_HDA_DEVC, &snoop);
1044 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1045 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1054 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1059 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1061 struct azx *chip = dev_id;
1062 struct azx_dev *azx_dev;
1066 spin_lock(&chip->reg_lock);
1068 status = azx_readl(chip, INTSTS);
1070 spin_unlock(&chip->reg_lock);
1074 for (i = 0; i < chip->num_streams; i++) {
1075 azx_dev = &chip->azx_dev[i];
1076 if (status & azx_dev->sd_int_sta_mask) {
1077 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1078 if (!azx_dev->substream || !azx_dev->running)
1080 /* check whether this IRQ is really acceptable */
1081 ok = azx_position_ok(chip, azx_dev);
1083 azx_dev->irq_pending = 0;
1084 spin_unlock(&chip->reg_lock);
1085 snd_pcm_period_elapsed(azx_dev->substream);
1086 spin_lock(&chip->reg_lock);
1087 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1088 /* bogus IRQ, process it later */
1089 azx_dev->irq_pending = 1;
1090 queue_work(chip->bus->workq,
1091 &chip->irq_pending_work);
1096 /* clear rirb int */
1097 status = azx_readb(chip, RIRBSTS);
1098 if (status & RIRB_INT_MASK) {
1099 if (status & RIRB_INT_RESPONSE)
1100 azx_update_rirb(chip);
1101 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1105 /* clear state status int */
1106 if (azx_readb(chip, STATESTS) & 0x04)
1107 azx_writeb(chip, STATESTS, 0x04);
1109 spin_unlock(&chip->reg_lock);
1116 * set up a BDL entry
1118 static int setup_bdle(struct snd_pcm_substream *substream,
1119 struct azx_dev *azx_dev, u32 **bdlp,
1120 int ofs, int size, int with_ioc)
1128 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1131 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1132 /* program the address field of the BDL entry */
1133 bdl[0] = cpu_to_le32((u32)addr);
1134 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1135 /* program the size field of the BDL entry */
1136 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1137 bdl[2] = cpu_to_le32(chunk);
1138 /* program the IOC to enable interrupt
1139 * only when the whole fragment is processed
1142 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1152 * set up BDL entries
1154 static int azx_setup_periods(struct azx *chip,
1155 struct snd_pcm_substream *substream,
1156 struct azx_dev *azx_dev)
1159 int i, ofs, periods, period_bytes;
1162 /* reset BDL address */
1163 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1164 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1166 period_bytes = azx_dev->period_bytes;
1167 periods = azx_dev->bufsize / period_bytes;
1169 /* program the initial BDL entries */
1170 bdl = (u32 *)azx_dev->bdl.area;
1173 pos_adj = bdl_pos_adj[chip->dev_index];
1175 struct snd_pcm_runtime *runtime = substream->runtime;
1176 int pos_align = pos_adj;
1177 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1179 pos_adj = pos_align;
1181 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1183 pos_adj = frames_to_bytes(runtime, pos_adj);
1184 if (pos_adj >= period_bytes) {
1185 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1186 bdl_pos_adj[chip->dev_index]);
1189 ofs = setup_bdle(substream, azx_dev,
1190 &bdl, ofs, pos_adj, 1);
1196 for (i = 0; i < periods; i++) {
1197 if (i == periods - 1 && pos_adj)
1198 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1199 period_bytes - pos_adj, 0);
1201 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1209 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1210 azx_dev->bufsize, period_bytes);
1215 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1220 azx_stream_clear(chip, azx_dev);
1222 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1223 SD_CTL_STREAM_RESET);
1226 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1229 val &= ~SD_CTL_STREAM_RESET;
1230 azx_sd_writeb(azx_dev, SD_CTL, val);
1234 /* waiting for hardware to report that the stream is out of reset */
1235 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1239 /* reset first position - may not be synced with hw at this time */
1240 *azx_dev->posbuf = 0;
1244 * set up the SD for streaming
1246 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1248 /* make sure the run bit is zero for SD */
1249 azx_stream_clear(chip, azx_dev);
1250 /* program the stream_tag */
1251 azx_sd_writel(azx_dev, SD_CTL,
1252 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1253 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1255 /* program the length of samples in cyclic buffer */
1256 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1258 /* program the stream format */
1259 /* this value needs to be the same as the one programmed */
1260 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1262 /* program the stream LVI (last valid index) of the BDL */
1263 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1265 /* program the BDL address */
1266 /* lower BDL address */
1267 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1268 /* upper BDL address */
1269 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1271 /* enable the position buffer */
1272 if (chip->position_fix == POS_FIX_POSBUF ||
1273 chip->position_fix == POS_FIX_AUTO ||
1274 chip->via_dmapos_patch) {
1275 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1276 azx_writel(chip, DPLBASE,
1277 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1280 /* set the interrupt enable bits in the descriptor control register */
1281 azx_sd_writel(azx_dev, SD_CTL,
1282 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1288 * Probe the given codec address
1290 static int probe_codec(struct azx *chip, int addr)
1292 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1293 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1296 mutex_lock(&chip->bus->cmd_mutex);
1298 azx_send_cmd(chip->bus, cmd);
1299 res = azx_get_response(chip->bus, addr);
1301 mutex_unlock(&chip->bus->cmd_mutex);
1304 snd_printdd(SFX "codec #%d probed OK\n", addr);
1308 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1309 struct hda_pcm *cpcm);
1310 static void azx_stop_chip(struct azx *chip);
1312 static void azx_bus_reset(struct hda_bus *bus)
1314 struct azx *chip = bus->private_data;
1317 azx_stop_chip(chip);
1318 azx_init_chip(chip);
1320 if (chip->initialized) {
1323 for (i = 0; i < AZX_MAX_PCMS; i++)
1324 snd_pcm_suspend_all(chip->pcm[i]);
1325 snd_hda_suspend(chip->bus);
1326 snd_hda_resume(chip->bus);
1333 * Codec initialization
1336 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1337 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1338 [AZX_DRIVER_TERA] = 1,
1341 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1343 struct hda_bus_template bus_temp;
1347 memset(&bus_temp, 0, sizeof(bus_temp));
1348 bus_temp.private_data = chip;
1349 bus_temp.modelname = model;
1350 bus_temp.pci = chip->pci;
1351 bus_temp.ops.command = azx_send_cmd;
1352 bus_temp.ops.get_response = azx_get_response;
1353 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1354 bus_temp.ops.bus_reset = azx_bus_reset;
1355 #ifdef CONFIG_SND_HDA_POWER_SAVE
1356 bus_temp.power_save = &power_save;
1357 bus_temp.ops.pm_notify = azx_power_notify;
1360 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1364 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1365 chip->bus->needs_damn_long_delay = 1;
1368 max_slots = azx_max_codecs[chip->driver_type];
1370 max_slots = AZX_MAX_CODECS;
1372 /* First try to probe all given codec slots */
1373 for (c = 0; c < max_slots; c++) {
1374 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1375 if (probe_codec(chip, c) < 0) {
1376 /* Some BIOSen give you wrong codec addresses
1379 snd_printk(KERN_WARNING SFX
1380 "Codec #%d probe error; "
1381 "disabling it...\n", c);
1382 chip->codec_mask &= ~(1 << c);
1383 /* More badly, accessing to a non-existing
1384 * codec often screws up the controller chip,
1385 * and distrubs the further communications.
1386 * Thus if an error occurs during probing,
1387 * better to reset the controller chip to
1388 * get back to the sanity state.
1390 azx_stop_chip(chip);
1391 azx_init_chip(chip);
1396 /* Then create codec instances */
1397 for (c = 0; c < max_slots; c++) {
1398 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1399 struct hda_codec *codec;
1400 err = snd_hda_codec_new(chip->bus, c, &codec);
1407 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1413 /* configure each codec instance */
1414 static int __devinit azx_codec_configure(struct azx *chip)
1416 struct hda_codec *codec;
1417 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1418 snd_hda_codec_configure(codec);
1428 /* assign a stream for the PCM */
1429 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1432 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1433 dev = chip->playback_index_offset;
1434 nums = chip->playback_streams;
1436 dev = chip->capture_index_offset;
1437 nums = chip->capture_streams;
1439 for (i = 0; i < nums; i++, dev++)
1440 if (!chip->azx_dev[dev].opened) {
1441 chip->azx_dev[dev].opened = 1;
1442 return &chip->azx_dev[dev];
1447 /* release the assigned stream */
1448 static inline void azx_release_device(struct azx_dev *azx_dev)
1450 azx_dev->opened = 0;
1453 static struct snd_pcm_hardware azx_pcm_hw = {
1454 .info = (SNDRV_PCM_INFO_MMAP |
1455 SNDRV_PCM_INFO_INTERLEAVED |
1456 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1457 SNDRV_PCM_INFO_MMAP_VALID |
1458 /* No full-resume yet implemented */
1459 /* SNDRV_PCM_INFO_RESUME |*/
1460 SNDRV_PCM_INFO_PAUSE |
1461 SNDRV_PCM_INFO_SYNC_START),
1462 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1463 .rates = SNDRV_PCM_RATE_48000,
1468 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1469 .period_bytes_min = 128,
1470 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1472 .periods_max = AZX_MAX_FRAG,
1478 struct hda_codec *codec;
1479 struct hda_pcm_stream *hinfo[2];
1482 static int azx_pcm_open(struct snd_pcm_substream *substream)
1484 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1485 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1486 struct azx *chip = apcm->chip;
1487 struct azx_dev *azx_dev;
1488 struct snd_pcm_runtime *runtime = substream->runtime;
1489 unsigned long flags;
1492 mutex_lock(&chip->open_mutex);
1493 azx_dev = azx_assign_device(chip, substream->stream);
1494 if (azx_dev == NULL) {
1495 mutex_unlock(&chip->open_mutex);
1498 runtime->hw = azx_pcm_hw;
1499 runtime->hw.channels_min = hinfo->channels_min;
1500 runtime->hw.channels_max = hinfo->channels_max;
1501 runtime->hw.formats = hinfo->formats;
1502 runtime->hw.rates = hinfo->rates;
1503 snd_pcm_limit_hw_rates(runtime);
1504 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1505 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1507 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1509 snd_hda_power_up(apcm->codec);
1510 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1512 azx_release_device(azx_dev);
1513 snd_hda_power_down(apcm->codec);
1514 mutex_unlock(&chip->open_mutex);
1517 snd_pcm_limit_hw_rates(runtime);
1519 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1520 snd_BUG_ON(!runtime->hw.channels_max) ||
1521 snd_BUG_ON(!runtime->hw.formats) ||
1522 snd_BUG_ON(!runtime->hw.rates)) {
1523 azx_release_device(azx_dev);
1524 hinfo->ops.close(hinfo, apcm->codec, substream);
1525 snd_hda_power_down(apcm->codec);
1526 mutex_unlock(&chip->open_mutex);
1529 spin_lock_irqsave(&chip->reg_lock, flags);
1530 azx_dev->substream = substream;
1531 azx_dev->running = 0;
1532 spin_unlock_irqrestore(&chip->reg_lock, flags);
1534 runtime->private_data = azx_dev;
1535 snd_pcm_set_sync(substream);
1536 mutex_unlock(&chip->open_mutex);
1540 static int azx_pcm_close(struct snd_pcm_substream *substream)
1542 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1543 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1544 struct azx *chip = apcm->chip;
1545 struct azx_dev *azx_dev = get_azx_dev(substream);
1546 unsigned long flags;
1548 mutex_lock(&chip->open_mutex);
1549 spin_lock_irqsave(&chip->reg_lock, flags);
1550 azx_dev->substream = NULL;
1551 azx_dev->running = 0;
1552 spin_unlock_irqrestore(&chip->reg_lock, flags);
1553 azx_release_device(azx_dev);
1554 hinfo->ops.close(hinfo, apcm->codec, substream);
1555 snd_hda_power_down(apcm->codec);
1556 mutex_unlock(&chip->open_mutex);
1560 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1561 struct snd_pcm_hw_params *hw_params)
1563 struct azx_dev *azx_dev = get_azx_dev(substream);
1565 azx_dev->bufsize = 0;
1566 azx_dev->period_bytes = 0;
1567 azx_dev->format_val = 0;
1568 return snd_pcm_lib_malloc_pages(substream,
1569 params_buffer_bytes(hw_params));
1572 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1574 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1575 struct azx_dev *azx_dev = get_azx_dev(substream);
1576 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1578 /* reset BDL address */
1579 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1580 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1581 azx_sd_writel(azx_dev, SD_CTL, 0);
1582 azx_dev->bufsize = 0;
1583 azx_dev->period_bytes = 0;
1584 azx_dev->format_val = 0;
1586 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1588 return snd_pcm_lib_free_pages(substream);
1591 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1593 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1594 struct azx *chip = apcm->chip;
1595 struct azx_dev *azx_dev = get_azx_dev(substream);
1596 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1597 struct snd_pcm_runtime *runtime = substream->runtime;
1598 unsigned int bufsize, period_bytes, format_val;
1601 azx_stream_reset(chip, azx_dev);
1602 format_val = snd_hda_calc_stream_format(runtime->rate,
1607 snd_printk(KERN_ERR SFX
1608 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1609 runtime->rate, runtime->channels, runtime->format);
1613 bufsize = snd_pcm_lib_buffer_bytes(substream);
1614 period_bytes = snd_pcm_lib_period_bytes(substream);
1616 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1617 bufsize, format_val);
1619 if (bufsize != azx_dev->bufsize ||
1620 period_bytes != azx_dev->period_bytes ||
1621 format_val != azx_dev->format_val) {
1622 azx_dev->bufsize = bufsize;
1623 azx_dev->period_bytes = period_bytes;
1624 azx_dev->format_val = format_val;
1625 err = azx_setup_periods(chip, substream, azx_dev);
1630 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1631 (runtime->rate * 2);
1632 azx_setup_controller(chip, azx_dev);
1633 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1634 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1636 azx_dev->fifo_size = 0;
1638 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1639 azx_dev->format_val, substream);
1642 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1644 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1645 struct azx *chip = apcm->chip;
1646 struct azx_dev *azx_dev;
1647 struct snd_pcm_substream *s;
1648 int rstart = 0, start, nsync = 0, sbits = 0;
1652 case SNDRV_PCM_TRIGGER_START:
1654 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1655 case SNDRV_PCM_TRIGGER_RESUME:
1658 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1659 case SNDRV_PCM_TRIGGER_SUSPEND:
1660 case SNDRV_PCM_TRIGGER_STOP:
1667 snd_pcm_group_for_each_entry(s, substream) {
1668 if (s->pcm->card != substream->pcm->card)
1670 azx_dev = get_azx_dev(s);
1671 sbits |= 1 << azx_dev->index;
1673 snd_pcm_trigger_done(s, substream);
1676 spin_lock(&chip->reg_lock);
1678 /* first, set SYNC bits of corresponding streams */
1679 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1681 snd_pcm_group_for_each_entry(s, substream) {
1682 if (s->pcm->card != substream->pcm->card)
1684 azx_dev = get_azx_dev(s);
1686 azx_dev->start_flag = 1;
1687 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1690 azx_stream_start(chip, azx_dev);
1692 azx_stream_stop(chip, azx_dev);
1693 azx_dev->running = start;
1695 spin_unlock(&chip->reg_lock);
1699 /* wait until all FIFOs get ready */
1700 for (timeout = 5000; timeout; timeout--) {
1702 snd_pcm_group_for_each_entry(s, substream) {
1703 if (s->pcm->card != substream->pcm->card)
1705 azx_dev = get_azx_dev(s);
1706 if (!(azx_sd_readb(azx_dev, SD_STS) &
1715 /* wait until all RUN bits are cleared */
1716 for (timeout = 5000; timeout; timeout--) {
1718 snd_pcm_group_for_each_entry(s, substream) {
1719 if (s->pcm->card != substream->pcm->card)
1721 azx_dev = get_azx_dev(s);
1722 if (azx_sd_readb(azx_dev, SD_CTL) &
1732 spin_lock(&chip->reg_lock);
1733 /* reset SYNC bits */
1734 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1735 spin_unlock(&chip->reg_lock);
1740 /* get the current DMA position with correction on VIA chips */
1741 static unsigned int azx_via_get_position(struct azx *chip,
1742 struct azx_dev *azx_dev)
1744 unsigned int link_pos, mini_pos, bound_pos;
1745 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1746 unsigned int fifo_size;
1748 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1749 if (azx_dev->index >= 4) {
1750 /* Playback, no problem using link position */
1756 * use mod to get the DMA position just like old chipset
1758 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1759 mod_dma_pos %= azx_dev->period_bytes;
1761 /* azx_dev->fifo_size can't get FIFO size of in stream.
1762 * Get from base address + offset.
1764 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1766 if (azx_dev->insufficient) {
1767 /* Link position never gather than FIFO size */
1768 if (link_pos <= fifo_size)
1771 azx_dev->insufficient = 0;
1774 if (link_pos <= fifo_size)
1775 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1777 mini_pos = link_pos - fifo_size;
1779 /* Find nearest previous boudary */
1780 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1781 mod_link_pos = link_pos % azx_dev->period_bytes;
1782 if (mod_link_pos >= fifo_size)
1783 bound_pos = link_pos - mod_link_pos;
1784 else if (mod_dma_pos >= mod_mini_pos)
1785 bound_pos = mini_pos - mod_mini_pos;
1787 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1788 if (bound_pos >= azx_dev->bufsize)
1792 /* Calculate real DMA position we want */
1793 return bound_pos + mod_dma_pos;
1796 static unsigned int azx_get_position(struct azx *chip,
1797 struct azx_dev *azx_dev)
1801 if (chip->via_dmapos_patch)
1802 pos = azx_via_get_position(chip, azx_dev);
1803 else if (chip->position_fix == POS_FIX_POSBUF ||
1804 chip->position_fix == POS_FIX_AUTO) {
1805 /* use the position buffer */
1806 pos = le32_to_cpu(*azx_dev->posbuf);
1809 pos = azx_sd_readl(azx_dev, SD_LPIB);
1811 if (pos >= azx_dev->bufsize)
1816 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1818 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1819 struct azx *chip = apcm->chip;
1820 struct azx_dev *azx_dev = get_azx_dev(substream);
1821 return bytes_to_frames(substream->runtime,
1822 azx_get_position(chip, azx_dev));
1826 * Check whether the current DMA position is acceptable for updating
1827 * periods. Returns non-zero if it's OK.
1829 * Many HD-audio controllers appear pretty inaccurate about
1830 * the update-IRQ timing. The IRQ is issued before actually the
1831 * data is processed. So, we need to process it afterwords in a
1834 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1838 if (azx_dev->start_flag &&
1839 time_before_eq(jiffies, azx_dev->start_jiffies))
1840 return -1; /* bogus (too early) interrupt */
1841 azx_dev->start_flag = 0;
1843 pos = azx_get_position(chip, azx_dev);
1844 if (chip->position_fix == POS_FIX_AUTO) {
1847 "hda-intel: Invalid position buffer, "
1848 "using LPIB read method instead.\n");
1849 chip->position_fix = POS_FIX_LPIB;
1850 pos = azx_get_position(chip, azx_dev);
1852 chip->position_fix = POS_FIX_POSBUF;
1855 if (!bdl_pos_adj[chip->dev_index])
1856 return 1; /* no delayed ack */
1857 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1858 return 0; /* NG - it's below the period boundary */
1859 return 1; /* OK, it's fine */
1863 * The work for pending PCM period updates.
1865 static void azx_irq_pending_work(struct work_struct *work)
1867 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1870 if (!chip->irq_pending_warned) {
1872 "hda-intel: IRQ timing workaround is activated "
1873 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1874 chip->card->number);
1875 chip->irq_pending_warned = 1;
1880 spin_lock_irq(&chip->reg_lock);
1881 for (i = 0; i < chip->num_streams; i++) {
1882 struct azx_dev *azx_dev = &chip->azx_dev[i];
1883 if (!azx_dev->irq_pending ||
1884 !azx_dev->substream ||
1887 if (azx_position_ok(chip, azx_dev)) {
1888 azx_dev->irq_pending = 0;
1889 spin_unlock(&chip->reg_lock);
1890 snd_pcm_period_elapsed(azx_dev->substream);
1891 spin_lock(&chip->reg_lock);
1895 spin_unlock_irq(&chip->reg_lock);
1902 /* clear irq_pending flags and assure no on-going workq */
1903 static void azx_clear_irq_pending(struct azx *chip)
1907 spin_lock_irq(&chip->reg_lock);
1908 for (i = 0; i < chip->num_streams; i++)
1909 chip->azx_dev[i].irq_pending = 0;
1910 spin_unlock_irq(&chip->reg_lock);
1913 static struct snd_pcm_ops azx_pcm_ops = {
1914 .open = azx_pcm_open,
1915 .close = azx_pcm_close,
1916 .ioctl = snd_pcm_lib_ioctl,
1917 .hw_params = azx_pcm_hw_params,
1918 .hw_free = azx_pcm_hw_free,
1919 .prepare = azx_pcm_prepare,
1920 .trigger = azx_pcm_trigger,
1921 .pointer = azx_pcm_pointer,
1922 .page = snd_pcm_sgbuf_ops_page,
1925 static void azx_pcm_free(struct snd_pcm *pcm)
1927 struct azx_pcm *apcm = pcm->private_data;
1929 apcm->chip->pcm[pcm->device] = NULL;
1935 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1936 struct hda_pcm *cpcm)
1938 struct azx *chip = bus->private_data;
1939 struct snd_pcm *pcm;
1940 struct azx_pcm *apcm;
1941 int pcm_dev = cpcm->device;
1944 if (pcm_dev >= AZX_MAX_PCMS) {
1945 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1949 if (chip->pcm[pcm_dev]) {
1950 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1953 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1954 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1955 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1959 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1960 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1964 apcm->codec = codec;
1965 pcm->private_data = apcm;
1966 pcm->private_free = azx_pcm_free;
1967 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1968 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1969 chip->pcm[pcm_dev] = pcm;
1971 for (s = 0; s < 2; s++) {
1972 apcm->hinfo[s] = &cpcm->stream[s];
1973 if (cpcm->stream[s].substreams)
1974 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1976 /* buffer pre-allocation */
1977 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1978 snd_dma_pci_data(chip->pci),
1979 1024 * 64, 32 * 1024 * 1024);
1984 * mixer creation - all stuff is implemented in hda module
1986 static int __devinit azx_mixer_create(struct azx *chip)
1988 return snd_hda_build_controls(chip->bus);
1993 * initialize SD streams
1995 static int __devinit azx_init_stream(struct azx *chip)
1999 /* initialize each stream (aka device)
2000 * assign the starting bdl address to each stream (device)
2003 for (i = 0; i < chip->num_streams; i++) {
2004 struct azx_dev *azx_dev = &chip->azx_dev[i];
2005 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2006 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2007 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2008 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2009 azx_dev->sd_int_sta_mask = 1 << i;
2010 /* stream tag: must be non-zero and unique */
2012 azx_dev->stream_tag = i + 1;
2018 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2020 if (request_irq(chip->pci->irq, azx_interrupt,
2021 chip->msi ? 0 : IRQF_SHARED,
2022 "HDA Intel", chip)) {
2023 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2024 "disabling device\n", chip->pci->irq);
2026 snd_card_disconnect(chip->card);
2029 chip->irq = chip->pci->irq;
2030 pci_intx(chip->pci, !chip->msi);
2035 static void azx_stop_chip(struct azx *chip)
2037 if (!chip->initialized)
2040 /* disable interrupts */
2041 azx_int_disable(chip);
2042 azx_int_clear(chip);
2044 /* disable CORB/RIRB */
2045 azx_free_cmd_io(chip);
2047 /* disable position buffer */
2048 azx_writel(chip, DPLBASE, 0);
2049 azx_writel(chip, DPUBASE, 0);
2051 chip->initialized = 0;
2054 #ifdef CONFIG_SND_HDA_POWER_SAVE
2055 /* power-up/down the controller */
2056 static void azx_power_notify(struct hda_bus *bus)
2058 struct azx *chip = bus->private_data;
2059 struct hda_codec *c;
2062 list_for_each_entry(c, &bus->codec_list, list) {
2069 azx_init_chip(chip);
2070 else if (chip->running && power_save_controller)
2071 azx_stop_chip(chip);
2073 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2080 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2082 struct hda_codec *codec;
2084 list_for_each_entry(codec, &bus->codec_list, list) {
2085 if (snd_hda_codec_needs_resume(codec))
2091 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2093 struct snd_card *card = pci_get_drvdata(pci);
2094 struct azx *chip = card->private_data;
2097 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2098 azx_clear_irq_pending(chip);
2099 for (i = 0; i < AZX_MAX_PCMS; i++)
2100 snd_pcm_suspend_all(chip->pcm[i]);
2101 if (chip->initialized)
2102 snd_hda_suspend(chip->bus);
2103 azx_stop_chip(chip);
2104 if (chip->irq >= 0) {
2105 free_irq(chip->irq, chip);
2109 pci_disable_msi(chip->pci);
2110 pci_disable_device(pci);
2111 pci_save_state(pci);
2112 pci_set_power_state(pci, pci_choose_state(pci, state));
2116 static int azx_resume(struct pci_dev *pci)
2118 struct snd_card *card = pci_get_drvdata(pci);
2119 struct azx *chip = card->private_data;
2121 pci_set_power_state(pci, PCI_D0);
2122 pci_restore_state(pci);
2123 if (pci_enable_device(pci) < 0) {
2124 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2125 "disabling device\n");
2126 snd_card_disconnect(card);
2129 pci_set_master(pci);
2131 if (pci_enable_msi(pci) < 0)
2133 if (azx_acquire_irq(chip, 1) < 0)
2137 if (snd_hda_codecs_inuse(chip->bus))
2138 azx_init_chip(chip);
2140 snd_hda_resume(chip->bus);
2141 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2144 #endif /* CONFIG_PM */
2148 * reboot notifier for hang-up problem at power-down
2150 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2152 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2153 azx_stop_chip(chip);
2157 static void azx_notifier_register(struct azx *chip)
2159 chip->reboot_notifier.notifier_call = azx_halt;
2160 register_reboot_notifier(&chip->reboot_notifier);
2163 static void azx_notifier_unregister(struct azx *chip)
2165 if (chip->reboot_notifier.notifier_call)
2166 unregister_reboot_notifier(&chip->reboot_notifier);
2172 static int azx_free(struct azx *chip)
2176 azx_notifier_unregister(chip);
2178 if (chip->initialized) {
2179 azx_clear_irq_pending(chip);
2180 for (i = 0; i < chip->num_streams; i++)
2181 azx_stream_stop(chip, &chip->azx_dev[i]);
2182 azx_stop_chip(chip);
2186 free_irq(chip->irq, (void*)chip);
2188 pci_disable_msi(chip->pci);
2189 if (chip->remap_addr)
2190 iounmap(chip->remap_addr);
2192 if (chip->azx_dev) {
2193 for (i = 0; i < chip->num_streams; i++)
2194 if (chip->azx_dev[i].bdl.area)
2195 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2198 snd_dma_free_pages(&chip->rb);
2199 if (chip->posbuf.area)
2200 snd_dma_free_pages(&chip->posbuf);
2201 pci_release_regions(chip->pci);
2202 pci_disable_device(chip->pci);
2203 kfree(chip->azx_dev);
2209 static int azx_dev_free(struct snd_device *device)
2211 return azx_free(device->device_data);
2215 * white/black-listing for position_fix
2217 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2218 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2219 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2220 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2224 static int __devinit check_position_fix(struct azx *chip, int fix)
2226 const struct snd_pci_quirk *q;
2230 case POS_FIX_POSBUF:
2234 /* Check VIA/ATI HD Audio Controller exist */
2235 switch (chip->driver_type) {
2236 case AZX_DRIVER_VIA:
2237 case AZX_DRIVER_ATI:
2238 chip->via_dmapos_patch = 1;
2239 /* Use link position directly, avoid any transfer problem. */
2240 return POS_FIX_LPIB;
2242 chip->via_dmapos_patch = 0;
2244 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2247 "hda_intel: position_fix set to %d "
2248 "for device %04x:%04x\n",
2249 q->value, q->subvendor, q->subdevice);
2252 return POS_FIX_AUTO;
2256 * black-lists for probe_mask
2258 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2259 /* Thinkpad often breaks the controller communication when accessing
2260 * to the non-working (or non-existing) modem codec slot.
2262 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2263 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2264 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2266 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2267 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2268 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2269 /* forced codec slots */
2270 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2271 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2275 #define AZX_FORCE_CODEC_MASK 0x100
2277 static void __devinit check_probe_mask(struct azx *chip, int dev)
2279 const struct snd_pci_quirk *q;
2281 chip->codec_probe_mask = probe_mask[dev];
2282 if (chip->codec_probe_mask == -1) {
2283 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2286 "hda_intel: probe_mask set to 0x%x "
2287 "for device %04x:%04x\n",
2288 q->value, q->subvendor, q->subdevice);
2289 chip->codec_probe_mask = q->value;
2293 /* check forced option */
2294 if (chip->codec_probe_mask != -1 &&
2295 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2296 chip->codec_mask = chip->codec_probe_mask & 0xff;
2297 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2303 * white-list for enable_msi
2305 static struct snd_pci_quirk msi_white_list[] __devinitdata = {
2306 SND_PCI_QUIRK(0x103c, 0x3607, "HP Compa CQ40", 1),
2310 static void __devinit check_msi(struct azx *chip)
2312 const struct snd_pci_quirk *q;
2314 chip->msi = enable_msi;
2317 q = snd_pci_quirk_lookup(chip->pci, msi_white_list);
2320 "hda_intel: msi for device %04x:%04x set to %d\n",
2321 q->subvendor, q->subdevice, q->value);
2322 chip->msi = q->value;
2330 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2331 int dev, int driver_type,
2336 unsigned short gcap;
2337 static struct snd_device_ops ops = {
2338 .dev_free = azx_dev_free,
2343 err = pci_enable_device(pci);
2347 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2349 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2350 pci_disable_device(pci);
2354 spin_lock_init(&chip->reg_lock);
2355 mutex_init(&chip->open_mutex);
2359 chip->driver_type = driver_type;
2361 chip->dev_index = dev;
2362 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2364 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2365 check_probe_mask(chip, dev);
2367 chip->single_cmd = single_cmd;
2369 if (bdl_pos_adj[dev] < 0) {
2370 switch (chip->driver_type) {
2371 case AZX_DRIVER_ICH:
2372 bdl_pos_adj[dev] = 1;
2375 bdl_pos_adj[dev] = 32;
2380 #if BITS_PER_LONG != 64
2381 /* Fix up base address on ULI M5461 */
2382 if (chip->driver_type == AZX_DRIVER_ULI) {
2384 pci_read_config_word(pci, 0x40, &tmp3);
2385 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2386 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2390 err = pci_request_regions(pci, "ICH HD audio");
2393 pci_disable_device(pci);
2397 chip->addr = pci_resource_start(pci, 0);
2398 chip->remap_addr = pci_ioremap_bar(pci, 0);
2399 if (chip->remap_addr == NULL) {
2400 snd_printk(KERN_ERR SFX "ioremap error\n");
2406 if (pci_enable_msi(pci) < 0)
2409 if (azx_acquire_irq(chip, 0) < 0) {
2414 pci_set_master(pci);
2415 synchronize_irq(chip->irq);
2417 gcap = azx_readw(chip, GCAP);
2418 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2420 /* disable SB600 64bit support for safety */
2421 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2422 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2423 struct pci_dev *p_smbus;
2424 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2425 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2428 if (p_smbus->revision < 0x30)
2429 gcap &= ~ICH6_GCAP_64OK;
2430 pci_dev_put(p_smbus);
2434 /* allow 64bit DMA address if supported by H/W */
2435 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2436 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2438 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2439 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2442 /* read number of streams from GCAP register instead of using
2445 chip->capture_streams = (gcap >> 8) & 0x0f;
2446 chip->playback_streams = (gcap >> 12) & 0x0f;
2447 if (!chip->playback_streams && !chip->capture_streams) {
2448 /* gcap didn't give any info, switching to old method */
2450 switch (chip->driver_type) {
2451 case AZX_DRIVER_ULI:
2452 chip->playback_streams = ULI_NUM_PLAYBACK;
2453 chip->capture_streams = ULI_NUM_CAPTURE;
2455 case AZX_DRIVER_ATIHDMI:
2456 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2457 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2459 case AZX_DRIVER_GENERIC:
2461 chip->playback_streams = ICH6_NUM_PLAYBACK;
2462 chip->capture_streams = ICH6_NUM_CAPTURE;
2466 chip->capture_index_offset = 0;
2467 chip->playback_index_offset = chip->capture_streams;
2468 chip->num_streams = chip->playback_streams + chip->capture_streams;
2469 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2471 if (!chip->azx_dev) {
2472 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2476 for (i = 0; i < chip->num_streams; i++) {
2477 /* allocate memory for the BDL for each stream */
2478 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2479 snd_dma_pci_data(chip->pci),
2480 BDL_SIZE, &chip->azx_dev[i].bdl);
2482 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2486 /* allocate memory for the position buffer */
2487 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2488 snd_dma_pci_data(chip->pci),
2489 chip->num_streams * 8, &chip->posbuf);
2491 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2494 /* allocate CORB/RIRB */
2495 err = azx_alloc_cmd_io(chip);
2499 /* initialize streams */
2500 azx_init_stream(chip);
2502 /* initialize chip */
2504 azx_init_chip(chip);
2506 /* codec detection */
2507 if (!chip->codec_mask) {
2508 snd_printk(KERN_ERR SFX "no codecs found!\n");
2513 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2515 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2519 strcpy(card->driver, "HDA-Intel");
2520 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2521 sizeof(card->shortname));
2522 snprintf(card->longname, sizeof(card->longname),
2523 "%s at 0x%lx irq %i",
2524 card->shortname, chip->addr, chip->irq);
2534 static void power_down_all_codecs(struct azx *chip)
2536 #ifdef CONFIG_SND_HDA_POWER_SAVE
2537 /* The codecs were powered up in snd_hda_codec_new().
2538 * Now all initialization done, so turn them down if possible
2540 struct hda_codec *codec;
2541 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2542 snd_hda_power_down(codec);
2547 static int __devinit azx_probe(struct pci_dev *pci,
2548 const struct pci_device_id *pci_id)
2551 struct snd_card *card;
2555 if (dev >= SNDRV_CARDS)
2562 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2564 snd_printk(KERN_ERR SFX "Error creating card!\n");
2568 /* set this here since it's referred in snd_hda_load_patch() */
2569 snd_card_set_dev(card, &pci->dev);
2571 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2574 card->private_data = chip;
2576 /* create codec instances */
2577 err = azx_codec_create(chip, model[dev]);
2580 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2582 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2584 err = snd_hda_load_patch(chip->bus, patch[dev]);
2589 if (!probe_only[dev]) {
2590 err = azx_codec_configure(chip);
2595 /* create PCM streams */
2596 err = snd_hda_build_pcms(chip->bus);
2600 /* create mixer controls */
2601 err = azx_mixer_create(chip);
2605 err = snd_card_register(card);
2609 pci_set_drvdata(pci, card);
2611 power_down_all_codecs(chip);
2612 azx_notifier_register(chip);
2617 snd_card_free(card);
2621 static void __devexit azx_remove(struct pci_dev *pci)
2623 snd_card_free(pci_get_drvdata(pci));
2624 pci_set_drvdata(pci, NULL);
2628 static struct pci_device_id azx_ids[] = {
2630 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2631 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2632 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2633 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2634 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2635 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2636 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2637 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2638 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2640 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2642 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2643 /* ATI SB 450/600 */
2644 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2645 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2647 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2648 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2649 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2650 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2651 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2652 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2653 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2654 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2655 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2656 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2657 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2658 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2659 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2660 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2661 /* VIA VT8251/VT8237A */
2662 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2664 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2666 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2668 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2669 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2670 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2671 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2672 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2673 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2674 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2675 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2676 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2677 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2678 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2679 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2680 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2681 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2682 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2683 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2684 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2685 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2686 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2687 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2688 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2689 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2691 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2692 /* Creative X-Fi (CA0110-IBG) */
2693 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2694 /* the following entry conflicts with snd-ctxfi driver,
2695 * as ctxfi driver mutates from HD-audio to native mode with
2696 * a special command sequence.
2698 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2699 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2700 .class_mask = 0xffffff,
2701 .driver_data = AZX_DRIVER_GENERIC },
2703 /* this entry seems still valid -- i.e. without emu20kx chip */
2704 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2706 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2707 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2708 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2709 .class_mask = 0xffffff,
2710 .driver_data = AZX_DRIVER_GENERIC },
2711 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2712 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2713 .class_mask = 0xffffff,
2714 .driver_data = AZX_DRIVER_GENERIC },
2717 MODULE_DEVICE_TABLE(pci, azx_ids);
2719 /* pci_driver definition */
2720 static struct pci_driver driver = {
2721 .name = "HDA Intel",
2722 .id_table = azx_ids,
2724 .remove = __devexit_p(azx_remove),
2726 .suspend = azx_suspend,
2727 .resume = azx_resume,
2731 static int __init alsa_card_azx_init(void)
2733 return pci_register_driver(&driver);
2736 static void __exit alsa_card_azx_exit(void)
2738 pci_unregister_driver(&driver);
2741 module_init(alsa_card_azx_init)
2742 module_exit(alsa_card_azx_exit)