drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <plat/sram.h>
  40 #include <plat/clock.h>
  41
  42 #include <video/omapdss.h>
  43
  44 #include "dss.h"
  45 #include "dss_features.h"
  46 #include "dispc.h"
  47
  48 /* DISPC */
  49 #define DISPC_SZ_REGS                   SZ_4K
  50
  51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_OCP_ERR | \
  53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_SYNC_LOST | \
  56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  57
  58 #define DISPC_MAX_NR_ISRS               8
  59
  60 struct omap_dispc_isr_data {
  61         omap_dispc_isr_t        isr;
  62         void                    *arg;
  63         u32                     mask;
  64 };
  65
  66 struct dispc_h_coef {
  67         s8 hc4;
  68         s8 hc3;
  69         u8 hc2;
  70         s8 hc1;
  71         s8 hc0;
  72 };
  73
  74 struct dispc_v_coef {
  75         s8 vc22;
  76         s8 vc2;
  77         u8 vc1;
  78         s8 vc0;
  79         s8 vc00;
  80 };
  81
  82 enum omap_burst_size {
  83         BURST_SIZE_X2 = 0,
  84         BURST_SIZE_X4 = 1,
  85         BURST_SIZE_X8 = 2,
  86 };
  87
  88 #define REG_GET(idx, start, end) \
  89         FLD_GET(dispc_read_reg(idx), start, end)
  90
  91 #define REG_FLD_MOD(idx, val, start, end)                               \
  92         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  93
  94 struct dispc_irq_stats {
  95         unsigned long last_reset;
  96         unsigned irq_count;
  97         unsigned irqs[32];
  98 };
  99
 100 static struct {
 101         struct platform_device *pdev;
 102         void __iomem    *base;
 103
 104         int             ctx_loss_cnt;
 105
 106         int irq;
 107         struct clk *dss_clk;
 108
 109         u32     fifo_size[MAX_DSS_OVERLAYS];
 110
 111         spinlock_t irq_lock;
 112         u32 irq_error_mask;
 113         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 114         u32 error_irqs;
 115         struct work_struct error_work;
 116
 117         bool            ctx_valid;
 118         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 119
 120 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 121         spinlock_t irq_stats_lock;
 122         struct dispc_irq_stats irq_stats;
 123 #endif
 124 } dispc;
 125
 126 enum omap_color_component {
 127         /* used for all color formats for OMAP3 and earlier
 128          * and for RGB and Y color component on OMAP4
 129          */
 130         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 131         /* used for UV component for
 132          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 133          * color formats on OMAP4
 134          */
 135         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 136 };
 137
 138 static void _omap_dispc_set_irqs(void);
 139
 140 static inline void dispc_write_reg(const u16 idx, u32 val)
 141 {
 142         __raw_writel(val, dispc.base + idx);
 143 }
 144
 145 static inline u32 dispc_read_reg(const u16 idx)
 146 {
 147         return __raw_readl(dispc.base + idx);
 148 }
 149
 150 static int dispc_get_ctx_loss_count(void)
 151 {
 152         struct device *dev = &dispc.pdev->dev;
 153         struct omap_display_platform_data *pdata = dev->platform_data;
 154         struct omap_dss_board_info *board_data = pdata->board_data;
 155         int cnt;
 156
 157         if (!board_data->get_context_loss_count)
 158                 return -ENOENT;
 159
 160         cnt = board_data->get_context_loss_count(dev);
 161
 162         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 163
 164         return cnt;
 165 }
 166
 167 #define SR(reg) \
 168         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 169 #define RR(reg) \
 170         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 171
 172 static void dispc_save_context(void)
 173 {
 174         int i, j;
 175
 176         DSSDBG("dispc_save_context\n");
 177
 178         SR(IRQENABLE);
 179         SR(CONTROL);
 180         SR(CONFIG);
 181         SR(LINE_NUMBER);
 182         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 183                 SR(GLOBAL_ALPHA);
 184         if (dss_has_feature(FEAT_MGR_LCD2)) {
 185                 SR(CONTROL2);
 186                 SR(CONFIG2);
 187         }
 188
 189         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 190                 SR(DEFAULT_COLOR(i));
 191                 SR(TRANS_COLOR(i));
 192                 SR(SIZE_MGR(i));
 193                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 194                         continue;
 195                 SR(TIMING_H(i));
 196                 SR(TIMING_V(i));
 197                 SR(POL_FREQ(i));
 198                 SR(DIVISORo(i));
 199
 200                 SR(DATA_CYCLE1(i));
 201                 SR(DATA_CYCLE2(i));
 202                 SR(DATA_CYCLE3(i));
 203
 204                 if (dss_has_feature(FEAT_CPR)) {
 205                         SR(CPR_COEF_R(i));
 206                         SR(CPR_COEF_G(i));
 207                         SR(CPR_COEF_B(i));
 208                 }
 209         }
 210
 211         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 212                 SR(OVL_BA0(i));
 213                 SR(OVL_BA1(i));
 214                 SR(OVL_POSITION(i));
 215                 SR(OVL_SIZE(i));
 216                 SR(OVL_ATTRIBUTES(i));
 217                 SR(OVL_FIFO_THRESHOLD(i));
 218                 SR(OVL_ROW_INC(i));
 219                 SR(OVL_PIXEL_INC(i));
 220                 if (dss_has_feature(FEAT_PRELOAD))
 221                         SR(OVL_PRELOAD(i));
 222                 if (i == OMAP_DSS_GFX) {
 223                         SR(OVL_WINDOW_SKIP(i));
 224                         SR(OVL_TABLE_BA(i));
 225                         continue;
 226                 }
 227                 SR(OVL_FIR(i));
 228                 SR(OVL_PICTURE_SIZE(i));
 229                 SR(OVL_ACCU0(i));
 230                 SR(OVL_ACCU1(i));
 231
 232                 for (j = 0; j < 8; j++)
 233                         SR(OVL_FIR_COEF_H(i, j));
 234
 235                 for (j = 0; j < 8; j++)
 236                         SR(OVL_FIR_COEF_HV(i, j));
 237
 238                 for (j = 0; j < 5; j++)
 239                         SR(OVL_CONV_COEF(i, j));
 240
 241                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 242                         for (j = 0; j < 8; j++)
 243                                 SR(OVL_FIR_COEF_V(i, j));
 244                 }
 245
 246                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 247                         SR(OVL_BA0_UV(i));
 248                         SR(OVL_BA1_UV(i));
 249                         SR(OVL_FIR2(i));
 250                         SR(OVL_ACCU2_0(i));
 251                         SR(OVL_ACCU2_1(i));
 252
 253                         for (j = 0; j < 8; j++)
 254                                 SR(OVL_FIR_COEF_H2(i, j));
 255
 256                         for (j = 0; j < 8; j++)
 257                                 SR(OVL_FIR_COEF_HV2(i, j));
 258
 259                         for (j = 0; j < 8; j++)
 260                                 SR(OVL_FIR_COEF_V2(i, j));
 261                 }
 262                 if (dss_has_feature(FEAT_ATTR2))
 263                         SR(OVL_ATTRIBUTES2(i));
 264         }
 265
 266         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 267                 SR(DIVISOR);
 268
 269         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 270         dispc.ctx_valid = true;
 271
 272         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 273 }
 274
 275 static void dispc_restore_context(void)
 276 {
 277         int i, j, ctx;
 278
 279         DSSDBG("dispc_restore_context\n");
 280
 281         if (!dispc.ctx_valid)
 282                 return;
 283
 284         ctx = dispc_get_ctx_loss_count();
 285
 286         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 287                 return;
 288
 289         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 290                         dispc.ctx_loss_cnt, ctx);
 291
 292         /*RR(IRQENABLE);*/
 293         /*RR(CONTROL);*/
 294         RR(CONFIG);
 295         RR(LINE_NUMBER);
 296         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 297                 RR(GLOBAL_ALPHA);
 298         if (dss_has_feature(FEAT_MGR_LCD2))
 299                 RR(CONFIG2);
 300
 301         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 302                 RR(DEFAULT_COLOR(i));
 303                 RR(TRANS_COLOR(i));
 304                 RR(SIZE_MGR(i));
 305                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 306                         continue;
 307                 RR(TIMING_H(i));
 308                 RR(TIMING_V(i));
 309                 RR(POL_FREQ(i));
 310                 RR(DIVISORo(i));
 311
 312                 RR(DATA_CYCLE1(i));
 313                 RR(DATA_CYCLE2(i));
 314                 RR(DATA_CYCLE3(i));
 315
 316                 if (dss_has_feature(FEAT_CPR)) {
 317                         RR(CPR_COEF_R(i));
 318                         RR(CPR_COEF_G(i));
 319                         RR(CPR_COEF_B(i));
 320                 }
 321         }
 322
 323         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 324                 RR(OVL_BA0(i));
 325                 RR(OVL_BA1(i));
 326                 RR(OVL_POSITION(i));
 327                 RR(OVL_SIZE(i));
 328                 RR(OVL_ATTRIBUTES(i));
 329                 RR(OVL_FIFO_THRESHOLD(i));
 330                 RR(OVL_ROW_INC(i));
 331                 RR(OVL_PIXEL_INC(i));
 332                 if (dss_has_feature(FEAT_PRELOAD))
 333                         RR(OVL_PRELOAD(i));
 334                 if (i == OMAP_DSS_GFX) {
 335                         RR(OVL_WINDOW_SKIP(i));
 336                         RR(OVL_TABLE_BA(i));
 337                         continue;
 338                 }
 339                 RR(OVL_FIR(i));
 340                 RR(OVL_PICTURE_SIZE(i));
 341                 RR(OVL_ACCU0(i));
 342                 RR(OVL_ACCU1(i));
 343
 344                 for (j = 0; j < 8; j++)
 345                         RR(OVL_FIR_COEF_H(i, j));
 346
 347                 for (j = 0; j < 8; j++)
 348                         RR(OVL_FIR_COEF_HV(i, j));
 349
 350                 for (j = 0; j < 5; j++)
 351                         RR(OVL_CONV_COEF(i, j));
 352
 353                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 354                         for (j = 0; j < 8; j++)
 355                                 RR(OVL_FIR_COEF_V(i, j));
 356                 }
 357
 358                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 359                         RR(OVL_BA0_UV(i));
 360                         RR(OVL_BA1_UV(i));
 361                         RR(OVL_FIR2(i));
 362                         RR(OVL_ACCU2_0(i));
 363                         RR(OVL_ACCU2_1(i));
 364
 365                         for (j = 0; j < 8; j++)
 366                                 RR(OVL_FIR_COEF_H2(i, j));
 367
 368                         for (j = 0; j < 8; j++)
 369                                 RR(OVL_FIR_COEF_HV2(i, j));
 370
 371                         for (j = 0; j < 8; j++)
 372                                 RR(OVL_FIR_COEF_V2(i, j));
 373                 }
 374                 if (dss_has_feature(FEAT_ATTR2))
 375                         RR(OVL_ATTRIBUTES2(i));
 376         }
 377
 378         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 379                 RR(DIVISOR);
 380
 381         /* enable last, because LCD & DIGIT enable are here */
 382         RR(CONTROL);
 383         if (dss_has_feature(FEAT_MGR_LCD2))
 384                 RR(CONTROL2);
 385         /* clear spurious SYNC_LOST_DIGIT interrupts */
 386         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 387
 388         /*
 389          * enable last so IRQs won't trigger before
 390          * the context is fully restored
 391          */
 392         RR(IRQENABLE);
 393
 394         DSSDBG("context restored\n");
 395 }
 396
 397 #undef SR
 398 #undef RR
 399
 400 int dispc_runtime_get(void)
 401 {
 402         int r;
 403
 404         DSSDBG("dispc_runtime_get\n");
 405
 406         r = pm_runtime_get_sync(&dispc.pdev->dev);
 407         WARN_ON(r < 0);
 408         return r < 0 ? r : 0;
 409 }
 410
 411 void dispc_runtime_put(void)
 412 {
 413         int r;
 414
 415         DSSDBG("dispc_runtime_put\n");
 416
 417         r = pm_runtime_put(&dispc.pdev->dev);
 418         WARN_ON(r < 0);
 419 }
 420
 421 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
 422 {
 423         if (channel == OMAP_DSS_CHANNEL_LCD ||
 424                         channel == OMAP_DSS_CHANNEL_LCD2)
 425                 return true;
 426         else
 427                 return false;
 428 }
 429
 430 bool dispc_mgr_go_busy(enum omap_channel channel)
 431 {
 432         int bit;
 433
 434         if (dispc_mgr_is_lcd(channel))
 435                 bit = 5; /* GOLCD */
 436         else
 437                 bit = 6; /* GODIGIT */
 438
 439         if (channel == OMAP_DSS_CHANNEL_LCD2)
 440                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 441         else
 442                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 443 }
 444
 445 void dispc_mgr_go(enum omap_channel channel)
 446 {
 447         int bit;
 448         bool enable_bit, go_bit;
 449
 450         if (dispc_mgr_is_lcd(channel))
 451                 bit = 0; /* LCDENABLE */
 452         else
 453                 bit = 1; /* DIGITALENABLE */
 454
 455         /* if the channel is not enabled, we don't need GO */
 456         if (channel == OMAP_DSS_CHANNEL_LCD2)
 457                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 458         else
 459                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 460
 461         if (!enable_bit)
 462                 return;
 463
 464         if (dispc_mgr_is_lcd(channel))
 465                 bit = 5; /* GOLCD */
 466         else
 467                 bit = 6; /* GODIGIT */
 468
 469         if (channel == OMAP_DSS_CHANNEL_LCD2)
 470                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 471         else
 472                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 473
 474         if (go_bit) {
 475                 DSSERR("GO bit not down for channel %d\n", channel);
 476                 return;
 477         }
 478
 479         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 480                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 481
 482         if (channel == OMAP_DSS_CHANNEL_LCD2)
 483                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 484         else
 485                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 486 }
 487
 488 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 489 {
 490         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 491 }
 492
 493 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 494 {
 495         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 496 }
 497
 498 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 499 {
 500         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 501 }
 502
 503 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 504 {
 505         BUG_ON(plane == OMAP_DSS_GFX);
 506
 507         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 508 }
 509
 510 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 511                 u32 value)
 512 {
 513         BUG_ON(plane == OMAP_DSS_GFX);
 514
 515         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 516 }
 517
 518 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 519 {
 520         BUG_ON(plane == OMAP_DSS_GFX);
 521
 522         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 523 }
 524
 525 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
 526                                   int vscaleup, int five_taps,
 527                                   enum omap_color_component color_comp)
 528 {
 529         /* Coefficients for horizontal up-sampling */
 530         static const struct dispc_h_coef coef_hup[8] = {
 531                 {  0,   0, 128,   0,  0 },
 532                 { -1,  13, 124,  -8,  0 },
 533                 { -2,  30, 112, -11, -1 },
 534                 { -5,  51,  95, -11, -2 },
 535                 {  0,  -9,  73,  73, -9 },
 536                 { -2, -11,  95,  51, -5 },
 537                 { -1, -11, 112,  30, -2 },
 538                 {  0,  -8, 124,  13, -1 },
 539         };
 540
 541         /* Coefficients for vertical up-sampling */
 542         static const struct dispc_v_coef coef_vup_3tap[8] = {
 543                 { 0,  0, 128,  0, 0 },
 544                 { 0,  3, 123,  2, 0 },
 545                 { 0, 12, 111,  5, 0 },
 546                 { 0, 32,  89,  7, 0 },
 547                 { 0,  0,  64, 64, 0 },
 548                 { 0,  7,  89, 32, 0 },
 549                 { 0,  5, 111, 12, 0 },
 550                 { 0,  2, 123,  3, 0 },
 551         };
 552
 553         static const struct dispc_v_coef coef_vup_5tap[8] = {
 554                 {  0,   0, 128,   0,  0 },
 555                 { -1,  13, 124,  -8,  0 },
 556                 { -2,  30, 112, -11, -1 },
 557                 { -5,  51,  95, -11, -2 },
 558                 {  0,  -9,  73,  73, -9 },
 559                 { -2, -11,  95,  51, -5 },
 560                 { -1, -11, 112,  30, -2 },
 561                 {  0,  -8, 124,  13, -1 },
 562         };
 563
 564         /* Coefficients for horizontal down-sampling */
 565         static const struct dispc_h_coef coef_hdown[8] = {
 566                 {   0, 36, 56, 36,  0 },
 567                 {   4, 40, 55, 31, -2 },
 568                 {   8, 44, 54, 27, -5 },
 569                 {  12, 48, 53, 22, -7 },
 570                 {  -9, 17, 52, 51, 17 },
 571                 {  -7, 22, 53, 48, 12 },
 572                 {  -5, 27, 54, 44,  8 },
 573                 {  -2, 31, 55, 40,  4 },
 574         };
 575
 576         /* Coefficients for vertical down-sampling */
 577         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 578                 { 0, 36, 56, 36, 0 },
 579                 { 0, 40, 57, 31, 0 },
 580                 { 0, 45, 56, 27, 0 },
 581                 { 0, 50, 55, 23, 0 },
 582                 { 0, 18, 55, 55, 0 },
 583                 { 0, 23, 55, 50, 0 },
 584                 { 0, 27, 56, 45, 0 },
 585                 { 0, 31, 57, 40, 0 },
 586         };
 587
 588         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 589                 {   0, 36, 56, 36,  0 },
 590                 {   4, 40, 55, 31, -2 },
 591                 {   8, 44, 54, 27, -5 },
 592                 {  12, 48, 53, 22, -7 },
 593                 {  -9, 17, 52, 51, 17 },
 594                 {  -7, 22, 53, 48, 12 },
 595                 {  -5, 27, 54, 44,  8 },
 596                 {  -2, 31, 55, 40,  4 },
 597         };
 598
 599         const struct dispc_h_coef *h_coef;
 600         const struct dispc_v_coef *v_coef;
 601         int i;
 602
 603         if (hscaleup)
 604                 h_coef = coef_hup;
 605         else
 606                 h_coef = coef_hdown;
 607
 608         if (vscaleup)
 609                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 610         else
 611                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 612
 613         for (i = 0; i < 8; i++) {
 614                 u32 h, hv;
 615
 616                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 617                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 618                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 619                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 620                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 621                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 622                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 623                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 624
 625                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 626                         dispc_ovl_write_firh_reg(plane, i, h);
 627                         dispc_ovl_write_firhv_reg(plane, i, hv);
 628                 } else {
 629                         dispc_ovl_write_firh2_reg(plane, i, h);
 630                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 631                 }
 632
 633         }
 634
 635         if (five_taps) {
 636                 for (i = 0; i < 8; i++) {
 637                         u32 v;
 638                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 639                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 640                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 641                                 dispc_ovl_write_firv_reg(plane, i, v);
 642                         else
 643                                 dispc_ovl_write_firv2_reg(plane, i, v);
 644                 }
 645         }
 646 }
 647
 648 static void _dispc_setup_color_conv_coef(void)
 649 {
 650         int i;
 651         const struct color_conv_coef {
 652                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 653                 int  full_range;
 654         }  ctbl_bt601_5 = {
 655                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 656         };
 657
 658         const struct color_conv_coef *ct;
 659
 660 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 661
 662         ct = &ctbl_bt601_5;
 663
 664         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 665                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 666                         CVAL(ct->rcr, ct->ry));
 667                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 668                         CVAL(ct->gy,  ct->rcb));
 669                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 670                         CVAL(ct->gcb, ct->gcr));
 671                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 672                         CVAL(ct->bcr, ct->by));
 673                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 674                         CVAL(0, ct->bcb));
 675
 676                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 677                         11, 11);
 678         }
 679
 680 #undef CVAL
 681 }
 682
 683
 684 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 685 {
 686         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 687 }
 688
 689 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 690 {
 691         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 692 }
 693
 694 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 695 {
 696         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 697 }
 698
 699 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 700 {
 701         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 702 }
 703
 704 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 705 {
 706         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 707
 708         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 709 }
 710
 711 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 712 {
 713         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 714
 715         if (plane == OMAP_DSS_GFX)
 716                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 717         else
 718                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 719 }
 720
 721 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 722 {
 723         u32 val;
 724
 725         BUG_ON(plane == OMAP_DSS_GFX);
 726
 727         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 728
 729         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 730 }
 731
 732 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 733 {
 734         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 735
 736         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 737                 return;
 738
 739         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 740 }
 741
 742 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 743 {
 744         static const unsigned shifts[] = { 0, 8, 16, };
 745         int shift;
 746         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 747
 748         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 749                 return;
 750
 751         shift = shifts[plane];
 752         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 753 }
 754
 755 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 756 {
 757         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 758 }
 759
 760 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 761 {
 762         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 763 }
 764
 765 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 766                 enum omap_color_mode color_mode)
 767 {
 768         u32 m = 0;
 769         if (plane != OMAP_DSS_GFX) {
 770                 switch (color_mode) {
 771                 case OMAP_DSS_COLOR_NV12:
 772                         m = 0x0; break;
 773                 case OMAP_DSS_COLOR_RGB12U:
 774                         m = 0x1; break;
 775                 case OMAP_DSS_COLOR_RGBA16:
 776                         m = 0x2; break;
 777                 case OMAP_DSS_COLOR_RGBX16:
 778                         m = 0x4; break;
 779                 case OMAP_DSS_COLOR_ARGB16:
 780                         m = 0x5; break;
 781                 case OMAP_DSS_COLOR_RGB16:
 782                         m = 0x6; break;
 783                 case OMAP_DSS_COLOR_ARGB16_1555:
 784                         m = 0x7; break;
 785                 case OMAP_DSS_COLOR_RGB24U:
 786                         m = 0x8; break;
 787                 case OMAP_DSS_COLOR_RGB24P:
 788                         m = 0x9; break;
 789                 case OMAP_DSS_COLOR_YUV2:
 790                         m = 0xa; break;
 791                 case OMAP_DSS_COLOR_UYVY:
 792                         m = 0xb; break;
 793                 case OMAP_DSS_COLOR_ARGB32:
 794                         m = 0xc; break;
 795                 case OMAP_DSS_COLOR_RGBA32:
 796                         m = 0xd; break;
 797                 case OMAP_DSS_COLOR_RGBX32:
 798                         m = 0xe; break;
 799                 case OMAP_DSS_COLOR_XRGB16_1555:
 800                         m = 0xf; break;
 801                 default:
 802                         BUG(); break;
 803                 }
 804         } else {
 805                 switch (color_mode) {
 806                 case OMAP_DSS_COLOR_CLUT1:
 807                         m = 0x0; break;
 808                 case OMAP_DSS_COLOR_CLUT2:
 809                         m = 0x1; break;
 810                 case OMAP_DSS_COLOR_CLUT4:
 811                         m = 0x2; break;
 812                 case OMAP_DSS_COLOR_CLUT8:
 813                         m = 0x3; break;
 814                 case OMAP_DSS_COLOR_RGB12U:
 815                         m = 0x4; break;
 816                 case OMAP_DSS_COLOR_ARGB16:
 817                         m = 0x5; break;
 818                 case OMAP_DSS_COLOR_RGB16:
 819                         m = 0x6; break;
 820                 case OMAP_DSS_COLOR_ARGB16_1555:
 821                         m = 0x7; break;
 822                 case OMAP_DSS_COLOR_RGB24U:
 823                         m = 0x8; break;
 824                 case OMAP_DSS_COLOR_RGB24P:
 825                         m = 0x9; break;
 826                 case OMAP_DSS_COLOR_YUV2:
 827                         m = 0xa; break;
 828                 case OMAP_DSS_COLOR_UYVY:
 829                         m = 0xb; break;
 830                 case OMAP_DSS_COLOR_ARGB32:
 831                         m = 0xc; break;
 832                 case OMAP_DSS_COLOR_RGBA32:
 833                         m = 0xd; break;
 834                 case OMAP_DSS_COLOR_RGBX32:
 835                         m = 0xe; break;
 836                 case OMAP_DSS_COLOR_XRGB16_1555:
 837                         m = 0xf; break;
 838                 default:
 839                         BUG(); break;
 840                 }
 841         }
 842
 843         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 844 }
 845
 846 static void dispc_ovl_set_channel_out(enum omap_plane plane,
 847                 enum omap_channel channel)
 848 {
 849         int shift;
 850         u32 val;
 851         int chan = 0, chan2 = 0;
 852
 853         switch (plane) {
 854         case OMAP_DSS_GFX:
 855                 shift = 8;
 856                 break;
 857         case OMAP_DSS_VIDEO1:
 858         case OMAP_DSS_VIDEO2:
 859                 shift = 16;
 860                 break;
 861         default:
 862                 BUG();
 863                 return;
 864         }
 865
 866         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 867         if (dss_has_feature(FEAT_MGR_LCD2)) {
 868                 switch (channel) {
 869                 case OMAP_DSS_CHANNEL_LCD:
 870                         chan = 0;
 871                         chan2 = 0;
 872                         break;
 873                 case OMAP_DSS_CHANNEL_DIGIT:
 874                         chan = 1;
 875                         chan2 = 0;
 876                         break;
 877                 case OMAP_DSS_CHANNEL_LCD2:
 878                         chan = 0;
 879                         chan2 = 1;
 880                         break;
 881                 default:
 882                         BUG();
 883                 }
 884
 885                 val = FLD_MOD(val, chan, shift, shift);
 886                 val = FLD_MOD(val, chan2, 31, 30);
 887         } else {
 888                 val = FLD_MOD(val, channel, shift, shift);
 889         }
 890         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 891 }
 892
 893 static void dispc_ovl_set_burst_size(enum omap_plane plane,
 894                 enum omap_burst_size burst_size)
 895 {
 896         static const unsigned shifts[] = { 6, 14, 14, };
 897         int shift;
 898
 899         shift = shifts[plane];
 900         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 901 }
 902
 903 static void dispc_configure_burst_sizes(void)
 904 {
 905         int i;
 906         const int burst_size = BURST_SIZE_X8;
 907
 908         /* Configure burst size always to maximum size */
 909         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 910                 dispc_ovl_set_burst_size(i, burst_size);
 911 }
 912
 913 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
 914 {
 915         unsigned unit = dss_feat_get_burst_size_unit();
 916         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 917         return unit * 8;
 918 }
 919
 920 void dispc_enable_gamma_table(bool enable)
 921 {
 922         /*
 923          * This is partially implemented to support only disabling of
 924          * the gamma table.
 925          */
 926         if (enable) {
 927                 DSSWARN("Gamma table enabling for TV not yet supported");
 928                 return;
 929         }
 930
 931         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
 932 }
 933
 934 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
 935 {
 936         u16 reg;
 937
 938         if (channel == OMAP_DSS_CHANNEL_LCD)
 939                 reg = DISPC_CONFIG;
 940         else if (channel == OMAP_DSS_CHANNEL_LCD2)
 941                 reg = DISPC_CONFIG2;
 942         else
 943                 return;
 944
 945         REG_FLD_MOD(reg, enable, 15, 15);
 946 }
 947
 948 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 949                 struct omap_dss_cpr_coefs *coefs)
 950 {
 951         u32 coef_r, coef_g, coef_b;
 952
 953         if (!dispc_mgr_is_lcd(channel))
 954                 return;
 955
 956         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
 957                 FLD_VAL(coefs->rb, 9, 0);
 958         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
 959                 FLD_VAL(coefs->gb, 9, 0);
 960         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
 961                 FLD_VAL(coefs->bb, 9, 0);
 962
 963         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
 964         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
 965         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 966 }
 967
 968 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
 969 {
 970         u32 val;
 971
 972         BUG_ON(plane == OMAP_DSS_GFX);
 973
 974         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 975         val = FLD_MOD(val, enable, 9, 9);
 976         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 977 }
 978
 979 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
 980 {
 981         static const unsigned shifts[] = { 5, 10, 10 };
 982         int shift;
 983
 984         shift = shifts[plane];
 985         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
 986 }
 987
 988 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 989 {
 990         u32 val;
 991         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 992         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 993         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
 994 }
 995
 996 void dispc_set_digit_size(u16 width, u16 height)
 997 {
 998         u32 val;
 999         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1000         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1001         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1002 }
1003
1004 static void dispc_read_plane_fifo_sizes(void)
1005 {
1006         u32 size;
1007         int plane;
1008         u8 start, end;
1009         u32 unit;
1010
1011         unit = dss_feat_get_buffer_size_unit();
1012
1013         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1014
1015         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1016                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1017                 size *= unit;
1018                 dispc.fifo_size[plane] = size;
1019         }
1020 }
1021
1022 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1023 {
1024         return dispc.fifo_size[plane];
1025 }
1026
1027 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1028                 u32 high)
1029 {
1030         u8 hi_start, hi_end, lo_start, lo_end;
1031         u32 unit;
1032
1033         unit = dss_feat_get_buffer_size_unit();
1034
1035         WARN_ON(low % unit != 0);
1036         WARN_ON(high % unit != 0);
1037
1038         low /= unit;
1039         high /= unit;
1040
1041         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1042         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1043
1044         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1045                         plane,
1046                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1047                                 lo_start, lo_end),
1048                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1049                                 hi_start, hi_end),
1050                         low, high);
1051
1052         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1053                         FLD_VAL(high, hi_start, hi_end) |
1054                         FLD_VAL(low, lo_start, lo_end));
1055 }
1056
1057 void dispc_enable_fifomerge(bool enable)
1058 {
1059         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1060         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1061 }
1062
1063 static void dispc_ovl_set_fir(enum omap_plane plane,
1064                                 int hinc, int vinc,
1065                                 enum omap_color_component color_comp)
1066 {
1067         u32 val;
1068
1069         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1070                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1071
1072                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1073                                         &hinc_start, &hinc_end);
1074                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1075                                         &vinc_start, &vinc_end);
1076                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1077                                 FLD_VAL(hinc, hinc_start, hinc_end);
1078
1079                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1080         } else {
1081                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1082                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1083         }
1084 }
1085
1086 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1087 {
1088         u32 val;
1089         u8 hor_start, hor_end, vert_start, vert_end;
1090
1091         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1092         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1093
1094         val = FLD_VAL(vaccu, vert_start, vert_end) |
1095                         FLD_VAL(haccu, hor_start, hor_end);
1096
1097         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1098 }
1099
1100 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1101 {
1102         u32 val;
1103         u8 hor_start, hor_end, vert_start, vert_end;
1104
1105         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1106         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1107
1108         val = FLD_VAL(vaccu, vert_start, vert_end) |
1109                         FLD_VAL(haccu, hor_start, hor_end);
1110
1111         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1112 }
1113
1114 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1115                 int vaccu)
1116 {
1117         u32 val;
1118
1119         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1120         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1121 }
1122
1123 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1124                 int vaccu)
1125 {
1126         u32 val;
1127
1128         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1129         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1130 }
1131
1132 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1133                 u16 orig_width, u16 orig_height,
1134                 u16 out_width, u16 out_height,
1135                 bool five_taps, u8 rotation,
1136                 enum omap_color_component color_comp)
1137 {
1138         int fir_hinc, fir_vinc;
1139         int hscaleup, vscaleup;
1140
1141         hscaleup = orig_width <= out_width;
1142         vscaleup = orig_height <= out_height;
1143
1144         dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1145                         color_comp);
1146
1147         fir_hinc = 1024 * orig_width / out_width;
1148         fir_vinc = 1024 * orig_height / out_height;
1149
1150         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1151 }
1152
1153 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1154                 u16 orig_width, u16 orig_height,
1155                 u16 out_width, u16 out_height,
1156                 bool ilace, bool five_taps,
1157                 bool fieldmode, enum omap_color_mode color_mode,
1158                 u8 rotation)
1159 {
1160         int accu0 = 0;
1161         int accu1 = 0;
1162         u32 l;
1163
1164         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1165                                 out_width, out_height, five_taps,
1166                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1167         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1168
1169         /* RESIZEENABLE and VERTICALTAPS */
1170         l &= ~((0x3 << 5) | (0x1 << 21));
1171         l |= (orig_width != out_width) ? (1 << 5) : 0;
1172         l |= (orig_height != out_height) ? (1 << 6) : 0;
1173         l |= five_taps ? (1 << 21) : 0;
1174
1175         /* VRESIZECONF and HRESIZECONF */
1176         if (dss_has_feature(FEAT_RESIZECONF)) {
1177                 l &= ~(0x3 << 7);
1178                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1179                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1180         }
1181
1182         /* LINEBUFFERSPLIT */
1183         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1184                 l &= ~(0x1 << 22);
1185                 l |= five_taps ? (1 << 22) : 0;
1186         }
1187
1188         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1189
1190         /*
1191          * field 0 = even field = bottom field
1192          * field 1 = odd field = top field
1193          */
1194         if (ilace && !fieldmode) {
1195                 accu1 = 0;
1196                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1197                 if (accu0 >= 1024/2) {
1198                         accu1 = 1024/2;
1199                         accu0 -= accu1;
1200                 }
1201         }
1202
1203         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1204         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1205 }
1206
1207 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1208                 u16 orig_width, u16 orig_height,
1209                 u16 out_width, u16 out_height,
1210                 bool ilace, bool five_taps,
1211                 bool fieldmode, enum omap_color_mode color_mode,
1212                 u8 rotation)
1213 {
1214         int scale_x = out_width != orig_width;
1215         int scale_y = out_height != orig_height;
1216
1217         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1218                 return;
1219         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1220                         color_mode != OMAP_DSS_COLOR_UYVY &&
1221                         color_mode != OMAP_DSS_COLOR_NV12)) {
1222                 /* reset chroma resampling for RGB formats  */
1223                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1224                 return;
1225         }
1226         switch (color_mode) {
1227         case OMAP_DSS_COLOR_NV12:
1228                 /* UV is subsampled by 2 vertically*/
1229                 orig_height >>= 1;
1230                 /* UV is subsampled by 2 horz.*/
1231                 orig_width >>= 1;
1232                 break;
1233         case OMAP_DSS_COLOR_YUV2:
1234         case OMAP_DSS_COLOR_UYVY:
1235                 /*For YUV422 with 90/270 rotation,
1236                  *we don't upsample chroma
1237                  */
1238                 if (rotation == OMAP_DSS_ROT_0 ||
1239                         rotation == OMAP_DSS_ROT_180)
1240                         /* UV is subsampled by 2 hrz*/
1241                         orig_width >>= 1;
1242                 /* must use FIR for YUV422 if rotated */
1243                 if (rotation != OMAP_DSS_ROT_0)
1244                         scale_x = scale_y = true;
1245                 break;
1246         default:
1247                 BUG();
1248         }
1249
1250         if (out_width != orig_width)
1251                 scale_x = true;
1252         if (out_height != orig_height)
1253                 scale_y = true;
1254
1255         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1256                         out_width, out_height, five_taps,
1257                                 rotation, DISPC_COLOR_COMPONENT_UV);
1258
1259         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1260                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1261         /* set H scaling */
1262         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1263         /* set V scaling */
1264         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1265
1266         dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1267         dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1268 }
1269
1270 static void dispc_ovl_set_scaling(enum omap_plane plane,
1271                 u16 orig_width, u16 orig_height,
1272                 u16 out_width, u16 out_height,
1273                 bool ilace, bool five_taps,
1274                 bool fieldmode, enum omap_color_mode color_mode,
1275                 u8 rotation)
1276 {
1277         BUG_ON(plane == OMAP_DSS_GFX);
1278
1279         dispc_ovl_set_scaling_common(plane,
1280                         orig_width, orig_height,
1281                         out_width, out_height,
1282                         ilace, five_taps,
1283                         fieldmode, color_mode,
1284                         rotation);
1285
1286         dispc_ovl_set_scaling_uv(plane,
1287                 orig_width, orig_height,
1288                 out_width, out_height,
1289                 ilace, five_taps,
1290                 fieldmode, color_mode,
1291                 rotation);
1292 }
1293
1294 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1295                 bool mirroring, enum omap_color_mode color_mode)
1296 {
1297         bool row_repeat = false;
1298         int vidrot = 0;
1299
1300         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1301                         color_mode == OMAP_DSS_COLOR_UYVY) {
1302
1303                 if (mirroring) {
1304                         switch (rotation) {
1305                         case OMAP_DSS_ROT_0:
1306                                 vidrot = 2;
1307                                 break;
1308                         case OMAP_DSS_ROT_90:
1309                                 vidrot = 1;
1310                                 break;
1311                         case OMAP_DSS_ROT_180:
1312                                 vidrot = 0;
1313                                 break;
1314                         case OMAP_DSS_ROT_270:
1315                                 vidrot = 3;
1316                                 break;
1317                         }
1318                 } else {
1319                         switch (rotation) {
1320                         case OMAP_DSS_ROT_0:
1321                                 vidrot = 0;
1322                                 break;
1323                         case OMAP_DSS_ROT_90:
1324                                 vidrot = 1;
1325                                 break;
1326                         case OMAP_DSS_ROT_180:
1327                                 vidrot = 2;
1328                                 break;
1329                         case OMAP_DSS_ROT_270:
1330                                 vidrot = 3;
1331                                 break;
1332                         }
1333                 }
1334
1335                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1336                         row_repeat = true;
1337                 else
1338                         row_repeat = false;
1339         }
1340
1341         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1342         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1343                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1344                         row_repeat ? 1 : 0, 18, 18);
1345 }
1346
1347 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1348 {
1349         switch (color_mode) {
1350         case OMAP_DSS_COLOR_CLUT1:
1351                 return 1;
1352         case OMAP_DSS_COLOR_CLUT2:
1353                 return 2;
1354         case OMAP_DSS_COLOR_CLUT4:
1355                 return 4;
1356         case OMAP_DSS_COLOR_CLUT8:
1357         case OMAP_DSS_COLOR_NV12:
1358                 return 8;
1359         case OMAP_DSS_COLOR_RGB12U:
1360         case OMAP_DSS_COLOR_RGB16:
1361         case OMAP_DSS_COLOR_ARGB16:
1362         case OMAP_DSS_COLOR_YUV2:
1363         case OMAP_DSS_COLOR_UYVY:
1364         case OMAP_DSS_COLOR_RGBA16:
1365         case OMAP_DSS_COLOR_RGBX16:
1366         case OMAP_DSS_COLOR_ARGB16_1555:
1367         case OMAP_DSS_COLOR_XRGB16_1555:
1368                 return 16;
1369         case OMAP_DSS_COLOR_RGB24P:
1370                 return 24;
1371         case OMAP_DSS_COLOR_RGB24U:
1372         case OMAP_DSS_COLOR_ARGB32:
1373         case OMAP_DSS_COLOR_RGBA32:
1374         case OMAP_DSS_COLOR_RGBX32:
1375                 return 32;
1376         default:
1377                 BUG();
1378         }
1379 }
1380
1381 static s32 pixinc(int pixels, u8 ps)
1382 {
1383         if (pixels == 1)
1384                 return 1;
1385         else if (pixels > 1)
1386                 return 1 + (pixels - 1) * ps;
1387         else if (pixels < 0)
1388                 return 1 - (-pixels + 1) * ps;
1389         else
1390                 BUG();
1391 }
1392
1393 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1394                 u16 screen_width,
1395                 u16 width, u16 height,
1396                 enum omap_color_mode color_mode, bool fieldmode,
1397                 unsigned int field_offset,
1398                 unsigned *offset0, unsigned *offset1,
1399                 s32 *row_inc, s32 *pix_inc)
1400 {
1401         u8 ps;
1402
1403         /* FIXME CLUT formats */
1404         switch (color_mode) {
1405         case OMAP_DSS_COLOR_CLUT1:
1406         case OMAP_DSS_COLOR_CLUT2:
1407         case OMAP_DSS_COLOR_CLUT4:
1408         case OMAP_DSS_COLOR_CLUT8:
1409                 BUG();
1410                 return;
1411         case OMAP_DSS_COLOR_YUV2:
1412         case OMAP_DSS_COLOR_UYVY:
1413                 ps = 4;
1414                 break;
1415         default:
1416                 ps = color_mode_to_bpp(color_mode) / 8;
1417                 break;
1418         }
1419
1420         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1421                         width, height);
1422
1423         /*
1424          * field 0 = even field = bottom field
1425          * field 1 = odd field = top field
1426          */
1427         switch (rotation + mirror * 4) {
1428         case OMAP_DSS_ROT_0:
1429         case OMAP_DSS_ROT_180:
1430                 /*
1431                  * If the pixel format is YUV or UYVY divide the width
1432                  * of the image by 2 for 0 and 180 degree rotation.
1433                  */
1434                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1435                         color_mode == OMAP_DSS_COLOR_UYVY)
1436                         width = width >> 1;
1437         case OMAP_DSS_ROT_90:
1438         case OMAP_DSS_ROT_270:
1439                 *offset1 = 0;
1440                 if (field_offset)
1441                         *offset0 = field_offset * screen_width * ps;
1442                 else
1443                         *offset0 = 0;
1444
1445                 *row_inc = pixinc(1 + (screen_width - width) +
1446                                 (fieldmode ? screen_width : 0),
1447                                 ps);
1448                 *pix_inc = pixinc(1, ps);
1449                 break;
1450
1451         case OMAP_DSS_ROT_0 + 4:
1452         case OMAP_DSS_ROT_180 + 4:
1453                 /* If the pixel format is YUV or UYVY divide the width
1454                  * of the image by 2  for 0 degree and 180 degree
1455                  */
1456                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1457                         color_mode == OMAP_DSS_COLOR_UYVY)
1458                         width = width >> 1;
1459         case OMAP_DSS_ROT_90 + 4:
1460         case OMAP_DSS_ROT_270 + 4:
1461                 *offset1 = 0;
1462                 if (field_offset)
1463                         *offset0 = field_offset * screen_width * ps;
1464                 else
1465                         *offset0 = 0;
1466                 *row_inc = pixinc(1 - (screen_width + width) -
1467                                 (fieldmode ? screen_width : 0),
1468                                 ps);
1469                 *pix_inc = pixinc(1, ps);
1470                 break;
1471
1472         default:
1473                 BUG();
1474         }
1475 }
1476
1477 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1478                 u16 screen_width,
1479                 u16 width, u16 height,
1480                 enum omap_color_mode color_mode, bool fieldmode,
1481                 unsigned int field_offset,
1482                 unsigned *offset0, unsigned *offset1,
1483                 s32 *row_inc, s32 *pix_inc)
1484 {
1485         u8 ps;
1486         u16 fbw, fbh;
1487
1488         /* FIXME CLUT formats */
1489         switch (color_mode) {
1490         case OMAP_DSS_COLOR_CLUT1:
1491         case OMAP_DSS_COLOR_CLUT2:
1492         case OMAP_DSS_COLOR_CLUT4:
1493         case OMAP_DSS_COLOR_CLUT8:
1494                 BUG();
1495                 return;
1496         default:
1497                 ps = color_mode_to_bpp(color_mode) / 8;
1498                 break;
1499         }
1500
1501         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1502                         width, height);
1503
1504         /* width & height are overlay sizes, convert to fb sizes */
1505
1506         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1507                 fbw = width;
1508                 fbh = height;
1509         } else {
1510                 fbw = height;
1511                 fbh = width;
1512         }
1513
1514         /*
1515          * field 0 = even field = bottom field
1516          * field 1 = odd field = top field
1517          */
1518         switch (rotation + mirror * 4) {
1519         case OMAP_DSS_ROT_0:
1520                 *offset1 = 0;
1521                 if (field_offset)
1522                         *offset0 = *offset1 + field_offset * screen_width * ps;
1523                 else
1524                         *offset0 = *offset1;
1525                 *row_inc = pixinc(1 + (screen_width - fbw) +
1526                                 (fieldmode ? screen_width : 0),
1527                                 ps);
1528                 *pix_inc = pixinc(1, ps);
1529                 break;
1530         case OMAP_DSS_ROT_90:
1531                 *offset1 = screen_width * (fbh - 1) * ps;
1532                 if (field_offset)
1533                         *offset0 = *offset1 + field_offset * ps;
1534                 else
1535                         *offset0 = *offset1;
1536                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1537                                 (fieldmode ? 1 : 0), ps);
1538                 *pix_inc = pixinc(-screen_width, ps);
1539                 break;
1540         case OMAP_DSS_ROT_180:
1541                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1542                 if (field_offset)
1543                         *offset0 = *offset1 - field_offset * screen_width * ps;
1544                 else
1545                         *offset0 = *offset1;
1546                 *row_inc = pixinc(-1 -
1547                                 (screen_width - fbw) -
1548                                 (fieldmode ? screen_width : 0),
1549                                 ps);
1550                 *pix_inc = pixinc(-1, ps);
1551                 break;
1552         case OMAP_DSS_ROT_270:
1553                 *offset1 = (fbw - 1) * ps;
1554                 if (field_offset)
1555                         *offset0 = *offset1 - field_offset * ps;
1556                 else
1557                         *offset0 = *offset1;
1558                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1559                                 (fieldmode ? 1 : 0), ps);
1560                 *pix_inc = pixinc(screen_width, ps);
1561                 break;
1562
1563         /* mirroring */
1564         case OMAP_DSS_ROT_0 + 4:
1565                 *offset1 = (fbw - 1) * ps;
1566                 if (field_offset)
1567                         *offset0 = *offset1 + field_offset * screen_width * ps;
1568                 else
1569                         *offset0 = *offset1;
1570                 *row_inc = pixinc(screen_width * 2 - 1 +
1571                                 (fieldmode ? screen_width : 0),
1572                                 ps);
1573                 *pix_inc = pixinc(-1, ps);
1574                 break;
1575
1576         case OMAP_DSS_ROT_90 + 4:
1577                 *offset1 = 0;
1578                 if (field_offset)
1579                         *offset0 = *offset1 + field_offset * ps;
1580                 else
1581                         *offset0 = *offset1;
1582                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1583                                 (fieldmode ? 1 : 0),
1584                                 ps);
1585                 *pix_inc = pixinc(screen_width, ps);
1586                 break;
1587
1588         case OMAP_DSS_ROT_180 + 4:
1589                 *offset1 = screen_width * (fbh - 1) * ps;
1590                 if (field_offset)
1591                         *offset0 = *offset1 - field_offset * screen_width * ps;
1592                 else
1593                         *offset0 = *offset1;
1594                 *row_inc = pixinc(1 - screen_width * 2 -
1595                                 (fieldmode ? screen_width : 0),
1596                                 ps);
1597                 *pix_inc = pixinc(1, ps);
1598                 break;
1599
1600         case OMAP_DSS_ROT_270 + 4:
1601                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1602                 if (field_offset)
1603                         *offset0 = *offset1 - field_offset * ps;
1604                 else
1605                         *offset0 = *offset1;
1606                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1607                                 (fieldmode ? 1 : 0),
1608                                 ps);
1609                 *pix_inc = pixinc(-screen_width, ps);
1610                 break;
1611
1612         default:
1613                 BUG();
1614         }
1615 }
1616
1617 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1618                 u16 height, u16 out_width, u16 out_height,
1619                 enum omap_color_mode color_mode)
1620 {
1621         u32 fclk = 0;
1622         /* FIXME venc pclk? */
1623         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1624
1625         if (height > out_height) {
1626                 /* FIXME get real display PPL */
1627                 unsigned int ppl = 800;
1628
1629                 tmp = pclk * height * out_width;
1630                 do_div(tmp, 2 * out_height * ppl);
1631                 fclk = tmp;
1632
1633                 if (height > 2 * out_height) {
1634                         if (ppl == out_width)
1635                                 return 0;
1636
1637                         tmp = pclk * (height - 2 * out_height) * out_width;
1638                         do_div(tmp, 2 * out_height * (ppl - out_width));
1639                         fclk = max(fclk, (u32) tmp);
1640                 }
1641         }
1642
1643         if (width > out_width) {
1644                 tmp = pclk * width;
1645                 do_div(tmp, out_width);
1646                 fclk = max(fclk, (u32) tmp);
1647
1648                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1649                         fclk <<= 1;
1650         }
1651
1652         return fclk;
1653 }
1654
1655 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1656                 u16 height, u16 out_width, u16 out_height)
1657 {
1658         unsigned int hf, vf;
1659
1660         /*
1661          * FIXME how to determine the 'A' factor
1662          * for the no downscaling case ?
1663          */
1664
1665         if (width > 3 * out_width)
1666                 hf = 4;
1667         else if (width > 2 * out_width)
1668                 hf = 3;
1669         else if (width > out_width)
1670                 hf = 2;
1671         else
1672                 hf = 1;
1673
1674         if (height > out_height)
1675                 vf = 2;
1676         else
1677                 vf = 1;
1678
1679         /* FIXME venc pclk? */
1680         return dispc_mgr_pclk_rate(channel) * vf * hf;
1681 }
1682
1683 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1684                 bool ilace, enum omap_channel channel, bool replication,
1685                 u32 fifo_low, u32 fifo_high)
1686 {
1687         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1688         bool five_taps = 0;
1689         bool fieldmode = 0;
1690         int cconv = 0;
1691         unsigned offset0, offset1;
1692         s32 row_inc;
1693         s32 pix_inc;
1694         u16 frame_height = oi->height;
1695         unsigned int field_offset = 0;
1696
1697         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1698                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1699                 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1700                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1701                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1702                 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1703
1704         if (oi->paddr == 0)
1705                 return -EINVAL;
1706
1707         if (ilace && oi->height == oi->out_height)
1708                 fieldmode = 1;
1709
1710         if (ilace) {
1711                 if (fieldmode)
1712                         oi->height /= 2;
1713                 oi->pos_y /= 2;
1714                 oi->out_height /= 2;
1715
1716                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1717                                 "out_height %d\n",
1718                                 oi->height, oi->pos_y, oi->out_height);
1719         }
1720
1721         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1722                 return -EINVAL;
1723
1724         if (plane == OMAP_DSS_GFX) {
1725                 if (oi->width != oi->out_width || oi->height != oi->out_height)
1726                         return -EINVAL;
1727         } else {
1728                 /* video plane */
1729
1730                 unsigned long fclk = 0;
1731
1732                 if (oi->out_width < oi->width / maxdownscale ||
1733                    oi->out_width > oi->width * 8)
1734                         return -EINVAL;
1735
1736                 if (oi->out_height < oi->height / maxdownscale ||
1737                    oi->out_height > oi->height * 8)
1738                         return -EINVAL;
1739
1740                 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1741                                 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1742                                 oi->color_mode == OMAP_DSS_COLOR_NV12)
1743                         cconv = 1;
1744
1745                 /* Must use 5-tap filter? */
1746                 five_taps = oi->height > oi->out_height * 2;
1747
1748                 if (!five_taps) {
1749                         fclk = calc_fclk(channel, oi->width, oi->height,
1750                                         oi->out_width, oi->out_height);
1751
1752                         /* Try 5-tap filter if 3-tap fclk is too high */
1753                         if (cpu_is_omap34xx() && oi->height > oi->out_height &&
1754                                         fclk > dispc_fclk_rate())
1755                                 five_taps = true;
1756                 }
1757
1758                 if (oi->width > (2048 >> five_taps)) {
1759                         DSSERR("failed to set up scaling, fclk too low\n");
1760                         return -EINVAL;
1761                 }
1762
1763                 if (five_taps)
1764                         fclk = calc_fclk_five_taps(channel, oi->width,
1765                                         oi->height, oi->out_width,
1766                                         oi->out_height, oi->color_mode);
1767
1768                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1769                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1770
1771                 if (!fclk || fclk > dispc_fclk_rate()) {
1772                         DSSERR("failed to set up scaling, "
1773                                         "required fclk rate = %lu Hz, "
1774                                         "current fclk rate = %lu Hz\n",
1775                                         fclk, dispc_fclk_rate());
1776                         return -EINVAL;
1777                 }
1778         }
1779
1780         if (ilace && !fieldmode) {
1781                 /*
1782                  * when downscaling the bottom field may have to start several
1783                  * source lines below the top field. Unfortunately ACCUI
1784                  * registers will only hold the fractional part of the offset
1785                  * so the integer part must be added to the base address of the
1786                  * bottom field.
1787                  */
1788                 if (!oi->height || oi->height == oi->out_height)
1789                         field_offset = 0;
1790                 else
1791                         field_offset = oi->height / oi->out_height / 2;
1792         }
1793
1794         /* Fields are independent but interleaved in memory. */
1795         if (fieldmode)
1796                 field_offset = 1;
1797
1798         if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1799                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1800                                 oi->screen_width, oi->width, frame_height,
1801                                 oi->color_mode, fieldmode, field_offset,
1802                                 &offset0, &offset1, &row_inc, &pix_inc);
1803         else
1804                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1805                                 oi->screen_width, oi->width, frame_height,
1806                                 oi->color_mode, fieldmode, field_offset,
1807                                 &offset0, &offset1, &row_inc, &pix_inc);
1808
1809         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1810                         offset0, offset1, row_inc, pix_inc);
1811
1812         dispc_ovl_set_color_mode(plane, oi->color_mode);
1813
1814         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1815         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1816
1817         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1818                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1819                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1820         }
1821
1822
1823         dispc_ovl_set_row_inc(plane, row_inc);
1824         dispc_ovl_set_pix_inc(plane, pix_inc);
1825
1826         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1827                         oi->height, oi->out_width, oi->out_height);
1828
1829         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1830
1831         dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1832
1833         if (plane != OMAP_DSS_GFX) {
1834                 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1835                                    oi->out_width, oi->out_height,
1836                                    ilace, five_taps, fieldmode,
1837                                    oi->color_mode, oi->rotation);
1838                 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1839                 dispc_ovl_set_vid_color_conv(plane, cconv);
1840         }
1841
1842         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1843                         oi->color_mode);
1844
1845         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1846         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1847
1848         dispc_ovl_set_channel_out(plane, channel);
1849
1850         dispc_ovl_enable_replication(plane, replication);
1851         dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1852
1853         return 0;
1854 }
1855
1856 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1857 {
1858         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1859
1860         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1861
1862         return 0;
1863 }
1864
1865 static void dispc_disable_isr(void *data, u32 mask)
1866 {
1867         struct completion *compl = data;
1868         complete(compl);
1869 }
1870
1871 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1872 {
1873         if (channel == OMAP_DSS_CHANNEL_LCD2)
1874                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1875         else
1876                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1877 }
1878
1879 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1880 {
1881         struct completion frame_done_completion;
1882         bool is_on;
1883         int r;
1884         u32 irq;
1885
1886         /* When we disable LCD output, we need to wait until frame is done.
1887          * Otherwise the DSS is still working, and turning off the clocks
1888          * prevents DSS from going to OFF mode */
1889         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1890                         REG_GET(DISPC_CONTROL2, 0, 0) :
1891                         REG_GET(DISPC_CONTROL, 0, 0);
1892
1893         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1894                         DISPC_IRQ_FRAMEDONE;
1895
1896         if (!enable && is_on) {
1897                 init_completion(&frame_done_completion);
1898
1899                 r = omap_dispc_register_isr(dispc_disable_isr,
1900                                 &frame_done_completion, irq);
1901
1902                 if (r)
1903                         DSSERR("failed to register FRAMEDONE isr\n");
1904         }
1905
1906         _enable_lcd_out(channel, enable);
1907
1908         if (!enable && is_on) {
1909                 if (!wait_for_completion_timeout(&frame_done_completion,
1910                                         msecs_to_jiffies(100)))
1911                         DSSERR("timeout waiting for FRAME DONE\n");
1912
1913                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1914                                 &frame_done_completion, irq);
1915
1916                 if (r)
1917                         DSSERR("failed to unregister FRAMEDONE isr\n");
1918         }
1919 }
1920
1921 static void _enable_digit_out(bool enable)
1922 {
1923         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1924 }
1925
1926 static void dispc_mgr_enable_digit_out(bool enable)
1927 {
1928         struct completion frame_done_completion;
1929         enum dss_hdmi_venc_clk_source_select src;
1930         int r, i;
1931         u32 irq_mask;
1932         int num_irqs;
1933
1934         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1935                 return;
1936
1937         src = dss_get_hdmi_venc_clk_source();
1938
1939         if (enable) {
1940                 unsigned long flags;
1941                 /* When we enable digit output, we'll get an extra digit
1942                  * sync lost interrupt, that we need to ignore */
1943                 spin_lock_irqsave(&dispc.irq_lock, flags);
1944                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1945                 _omap_dispc_set_irqs();
1946                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1947         }
1948
1949         /* When we disable digit output, we need to wait until fields are done.
1950          * Otherwise the DSS is still working, and turning off the clocks
1951          * prevents DSS from going to OFF mode. And when enabling, we need to
1952          * wait for the extra sync losts */
1953         init_completion(&frame_done_completion);
1954
1955         if (src == DSS_HDMI_M_PCLK && enable == false) {
1956                 irq_mask = DISPC_IRQ_FRAMEDONETV;
1957                 num_irqs = 1;
1958         } else {
1959                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
1960                 /* XXX I understand from TRM that we should only wait for the
1961                  * current field to complete. But it seems we have to wait for
1962                  * both fields */
1963                 num_irqs = 2;
1964         }
1965
1966         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1967                         irq_mask);
1968         if (r)
1969                 DSSERR("failed to register %x isr\n", irq_mask);
1970
1971         _enable_digit_out(enable);
1972
1973         for (i = 0; i < num_irqs; ++i) {
1974                 if (!wait_for_completion_timeout(&frame_done_completion,
1975                                         msecs_to_jiffies(100)))
1976                         DSSERR("timeout waiting for digit out to %s\n",
1977                                         enable ? "start" : "stop");
1978         }
1979
1980         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
1981                         irq_mask);
1982         if (r)
1983                 DSSERR("failed to unregister %x isr\n", irq_mask);
1984
1985         if (enable) {
1986                 unsigned long flags;
1987                 spin_lock_irqsave(&dispc.irq_lock, flags);
1988                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
1989                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1990                 _omap_dispc_set_irqs();
1991                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1992         }
1993 }
1994
1995 bool dispc_mgr_is_enabled(enum omap_channel channel)
1996 {
1997         if (channel == OMAP_DSS_CHANNEL_LCD)
1998                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1999         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2000                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2001         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2002                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2003         else
2004                 BUG();
2005 }
2006
2007 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2008 {
2009         if (dispc_mgr_is_lcd(channel))
2010                 dispc_mgr_enable_lcd_out(channel, enable);
2011         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2012                 dispc_mgr_enable_digit_out(enable);
2013         else
2014                 BUG();
2015 }
2016
2017 void dispc_lcd_enable_signal_polarity(bool act_high)
2018 {
2019         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2020                 return;
2021
2022         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2023 }
2024
2025 void dispc_lcd_enable_signal(bool enable)
2026 {
2027         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2028                 return;
2029
2030         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2031 }
2032
2033 void dispc_pck_free_enable(bool enable)
2034 {
2035         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2036                 return;
2037
2038         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2039 }
2040
2041 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2042 {
2043         if (channel == OMAP_DSS_CHANNEL_LCD2)
2044                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2045         else
2046                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2047 }
2048
2049
2050 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2051                 enum omap_lcd_display_type type)
2052 {
2053         int mode;
2054
2055         switch (type) {
2056         case OMAP_DSS_LCD_DISPLAY_STN:
2057                 mode = 0;
2058                 break;
2059
2060         case OMAP_DSS_LCD_DISPLAY_TFT:
2061                 mode = 1;
2062                 break;
2063
2064         default:
2065                 BUG();
2066                 return;
2067         }
2068
2069         if (channel == OMAP_DSS_CHANNEL_LCD2)
2070                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2071         else
2072                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2073 }
2074
2075 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2076 {
2077         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2078 }
2079
2080
2081 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2082 {
2083         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2084 }
2085
2086 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2087 {
2088         u32 l;
2089
2090         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2091                 channel != OMAP_DSS_CHANNEL_LCD &&
2092                 channel != OMAP_DSS_CHANNEL_LCD2);
2093
2094         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2095
2096         return l;
2097 }
2098
2099 void dispc_mgr_set_trans_key(enum omap_channel ch,
2100                 enum omap_dss_trans_key_type type,
2101                 u32 trans_key)
2102 {
2103         if (ch == OMAP_DSS_CHANNEL_LCD)
2104                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2105         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2106                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2107         else /* OMAP_DSS_CHANNEL_LCD2 */
2108                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2109
2110         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2111 }
2112
2113 void dispc_mgr_get_trans_key(enum omap_channel ch,
2114                 enum omap_dss_trans_key_type *type,
2115                 u32 *trans_key)
2116 {
2117         if (type) {
2118                 if (ch == OMAP_DSS_CHANNEL_LCD)
2119                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2120                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2121                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2122                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2123                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2124                 else
2125                         BUG();
2126         }
2127
2128         if (trans_key)
2129                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2130 }
2131
2132 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2133 {
2134         if (ch == OMAP_DSS_CHANNEL_LCD)
2135                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2136         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2137                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2138         else /* OMAP_DSS_CHANNEL_LCD2 */
2139                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2140 }
2141 void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable)
2142 {
2143         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2144                 return;
2145
2146         if (ch == OMAP_DSS_CHANNEL_LCD)
2147                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2148         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2149                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2150         else /* OMAP_DSS_CHANNEL_LCD2 */
2151                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2152 }
2153 bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch)
2154 {
2155         bool enabled;
2156
2157         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2158                 return false;
2159
2160         if (ch == OMAP_DSS_CHANNEL_LCD)
2161                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2162         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2163                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2164         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2165                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2166         else
2167                 BUG();
2168
2169         return enabled;
2170 }
2171
2172
2173 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2174 {
2175         bool enabled;
2176
2177         if (ch == OMAP_DSS_CHANNEL_LCD)
2178                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2179         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2180                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2181         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2182                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2183         else
2184                 BUG();
2185
2186         return enabled;
2187 }
2188
2189
2190 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2191 {
2192         int code;
2193
2194         switch (data_lines) {
2195         case 12:
2196                 code = 0;
2197                 break;
2198         case 16:
2199                 code = 1;
2200                 break;
2201         case 18:
2202                 code = 2;
2203                 break;
2204         case 24:
2205                 code = 3;
2206                 break;
2207         default:
2208                 BUG();
2209                 return;
2210         }
2211
2212         if (channel == OMAP_DSS_CHANNEL_LCD2)
2213                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2214         else
2215                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2216 }
2217
2218 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2219 {
2220         u32 l;
2221         int gpout0, gpout1;
2222
2223         switch (mode) {
2224         case DSS_IO_PAD_MODE_RESET:
2225                 gpout0 = 0;
2226                 gpout1 = 0;
2227                 break;
2228         case DSS_IO_PAD_MODE_RFBI:
2229                 gpout0 = 1;
2230                 gpout1 = 0;
2231                 break;
2232         case DSS_IO_PAD_MODE_BYPASS:
2233                 gpout0 = 1;
2234                 gpout1 = 1;
2235                 break;
2236         default:
2237                 BUG();
2238                 return;
2239         }
2240
2241         l = dispc_read_reg(DISPC_CONTROL);
2242         l = FLD_MOD(l, gpout0, 15, 15);
2243         l = FLD_MOD(l, gpout1, 16, 16);
2244         dispc_write_reg(DISPC_CONTROL, l);
2245 }
2246
2247 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2248 {
2249         if (channel == OMAP_DSS_CHANNEL_LCD2)
2250                 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2251         else
2252                 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2253 }
2254
2255 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2256                 int vsw, int vfp, int vbp)
2257 {
2258         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2259                 if (hsw < 1 || hsw > 64 ||
2260                                 hfp < 1 || hfp > 256 ||
2261                                 hbp < 1 || hbp > 256 ||
2262                                 vsw < 1 || vsw > 64 ||
2263                                 vfp < 0 || vfp > 255 ||
2264                                 vbp < 0 || vbp > 255)
2265                         return false;
2266         } else {
2267                 if (hsw < 1 || hsw > 256 ||
2268                                 hfp < 1 || hfp > 4096 ||
2269                                 hbp < 1 || hbp > 4096 ||
2270                                 vsw < 1 || vsw > 256 ||
2271                                 vfp < 0 || vfp > 4095 ||
2272                                 vbp < 0 || vbp > 4095)
2273                         return false;
2274         }
2275
2276         return true;
2277 }
2278
2279 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2280 {
2281         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2282                         timings->hbp, timings->vsw,
2283                         timings->vfp, timings->vbp);
2284 }
2285
2286 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2287                 int hfp, int hbp, int vsw, int vfp, int vbp)
2288 {
2289         u32 timing_h, timing_v;
2290
2291         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2292                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2293                         FLD_VAL(hbp-1, 27, 20);
2294
2295                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2296                         FLD_VAL(vbp, 27, 20);
2297         } else {
2298                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2299                         FLD_VAL(hbp-1, 31, 20);
2300
2301                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2302                         FLD_VAL(vbp, 31, 20);
2303         }
2304
2305         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2306         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2307 }
2308
2309 /* change name to mode? */
2310 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2311                 struct omap_video_timings *timings)
2312 {
2313         unsigned xtot, ytot;
2314         unsigned long ht, vt;
2315
2316         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2317                                 timings->hbp, timings->vsw,
2318                                 timings->vfp, timings->vbp))
2319                 BUG();
2320
2321         _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2322                         timings->hbp, timings->vsw, timings->vfp,
2323                         timings->vbp);
2324
2325         dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2326
2327         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2328         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2329
2330         ht = (timings->pixel_clock * 1000) / xtot;
2331         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2332
2333         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2334                         timings->y_res);
2335         DSSDBG("pck %u\n", timings->pixel_clock);
2336         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2337                         timings->hsw, timings->hfp, timings->hbp,
2338                         timings->vsw, timings->vfp, timings->vbp);
2339
2340         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2341 }
2342
2343 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2344                 u16 pck_div)
2345 {
2346         BUG_ON(lck_div < 1);
2347         BUG_ON(pck_div < 1);
2348
2349         dispc_write_reg(DISPC_DIVISORo(channel),
2350                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2351 }
2352
2353 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2354                 int *pck_div)
2355 {
2356         u32 l;
2357         l = dispc_read_reg(DISPC_DIVISORo(channel));
2358         *lck_div = FLD_GET(l, 23, 16);
2359         *pck_div = FLD_GET(l, 7, 0);
2360 }
2361
2362 unsigned long dispc_fclk_rate(void)
2363 {
2364         struct platform_device *dsidev;
2365         unsigned long r = 0;
2366
2367         switch (dss_get_dispc_clk_source()) {
2368         case OMAP_DSS_CLK_SRC_FCK:
2369                 r = clk_get_rate(dispc.dss_clk);
2370                 break;
2371         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2372                 dsidev = dsi_get_dsidev_from_id(0);
2373                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2374                 break;
2375         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2376                 dsidev = dsi_get_dsidev_from_id(1);
2377                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2378                 break;
2379         default:
2380                 BUG();
2381         }
2382
2383         return r;
2384 }
2385
2386 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2387 {
2388         struct platform_device *dsidev;
2389         int lcd;
2390         unsigned long r;
2391         u32 l;
2392
2393         l = dispc_read_reg(DISPC_DIVISORo(channel));
2394
2395         lcd = FLD_GET(l, 23, 16);
2396
2397         switch (dss_get_lcd_clk_source(channel)) {
2398         case OMAP_DSS_CLK_SRC_FCK:
2399                 r = clk_get_rate(dispc.dss_clk);
2400                 break;
2401         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2402                 dsidev = dsi_get_dsidev_from_id(0);
2403                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2404                 break;
2405         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2406                 dsidev = dsi_get_dsidev_from_id(1);
2407                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2408                 break;
2409         default:
2410                 BUG();
2411         }
2412
2413         return r / lcd;
2414 }
2415
2416 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2417 {
2418         int pcd;
2419         unsigned long r;
2420         u32 l;
2421
2422         l = dispc_read_reg(DISPC_DIVISORo(channel));
2423
2424         pcd = FLD_GET(l, 7, 0);
2425
2426         r = dispc_mgr_lclk_rate(channel);
2427
2428         return r / pcd;
2429 }
2430
2431 void dispc_dump_clocks(struct seq_file *s)
2432 {
2433         int lcd, pcd;
2434         u32 l;
2435         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2436         enum omap_dss_clk_source lcd_clk_src;
2437
2438         if (dispc_runtime_get())
2439                 return;
2440
2441         seq_printf(s, "- DISPC -\n");
2442
2443         seq_printf(s, "dispc fclk source = %s (%s)\n",
2444                         dss_get_generic_clk_source_name(dispc_clk_src),
2445                         dss_feat_get_clk_source_name(dispc_clk_src));
2446
2447         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2448
2449         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2450                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2451                 l = dispc_read_reg(DISPC_DIVISOR);
2452                 lcd = FLD_GET(l, 23, 16);
2453
2454                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2455                                 (dispc_fclk_rate()/lcd), lcd);
2456         }
2457         seq_printf(s, "- LCD1 -\n");
2458
2459         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2460
2461         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2462                 dss_get_generic_clk_source_name(lcd_clk_src),
2463                 dss_feat_get_clk_source_name(lcd_clk_src));
2464
2465         dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2466
2467         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2468                         dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2469         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2470                         dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2471         if (dss_has_feature(FEAT_MGR_LCD2)) {
2472                 seq_printf(s, "- LCD2 -\n");
2473
2474                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2475
2476                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2477                         dss_get_generic_clk_source_name(lcd_clk_src),
2478                         dss_feat_get_clk_source_name(lcd_clk_src));
2479
2480                 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2481
2482                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2483                                 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2484                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2485                                 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2486         }
2487
2488         dispc_runtime_put();
2489 }
2490
2491 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2492 void dispc_dump_irqs(struct seq_file *s)
2493 {
2494         unsigned long flags;
2495         struct dispc_irq_stats stats;
2496
2497         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2498
2499         stats = dispc.irq_stats;
2500         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2501         dispc.irq_stats.last_reset = jiffies;
2502
2503         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2504
2505         seq_printf(s, "period %u ms\n",
2506                         jiffies_to_msecs(jiffies - stats.last_reset));
2507
2508         seq_printf(s, "irqs %d\n", stats.irq_count);
2509 #define PIS(x) \
2510         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2511
2512         PIS(FRAMEDONE);
2513         PIS(VSYNC);
2514         PIS(EVSYNC_EVEN);
2515         PIS(EVSYNC_ODD);
2516         PIS(ACBIAS_COUNT_STAT);
2517         PIS(PROG_LINE_NUM);
2518         PIS(GFX_FIFO_UNDERFLOW);
2519         PIS(GFX_END_WIN);
2520         PIS(PAL_GAMMA_MASK);
2521         PIS(OCP_ERR);
2522         PIS(VID1_FIFO_UNDERFLOW);
2523         PIS(VID1_END_WIN);
2524         PIS(VID2_FIFO_UNDERFLOW);
2525         PIS(VID2_END_WIN);
2526         PIS(SYNC_LOST);
2527         PIS(SYNC_LOST_DIGIT);
2528         PIS(WAKEUP);
2529         if (dss_has_feature(FEAT_MGR_LCD2)) {
2530                 PIS(FRAMEDONE2);
2531                 PIS(VSYNC2);
2532                 PIS(ACBIAS_COUNT_STAT2);
2533                 PIS(SYNC_LOST2);
2534         }
2535 #undef PIS
2536 }
2537 #endif
2538
2539 void dispc_dump_regs(struct seq_file *s)
2540 {
2541         int i, j;
2542         const char *mgr_names[] = {
2543                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2544                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2545                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2546         };
2547         const char *ovl_names[] = {
2548                 [OMAP_DSS_GFX]          = "GFX",
2549                 [OMAP_DSS_VIDEO1]       = "VID1",
2550                 [OMAP_DSS_VIDEO2]       = "VID2",
2551         };
2552         const char **p_names;
2553
2554 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2555
2556         if (dispc_runtime_get())
2557                 return;
2558
2559         /* DISPC common registers */
2560         DUMPREG(DISPC_REVISION);
2561         DUMPREG(DISPC_SYSCONFIG);
2562         DUMPREG(DISPC_SYSSTATUS);
2563         DUMPREG(DISPC_IRQSTATUS);
2564         DUMPREG(DISPC_IRQENABLE);
2565         DUMPREG(DISPC_CONTROL);
2566         DUMPREG(DISPC_CONFIG);
2567         DUMPREG(DISPC_CAPABLE);
2568         DUMPREG(DISPC_LINE_STATUS);
2569         DUMPREG(DISPC_LINE_NUMBER);
2570         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2571                 DUMPREG(DISPC_GLOBAL_ALPHA);
2572         if (dss_has_feature(FEAT_MGR_LCD2)) {
2573                 DUMPREG(DISPC_CONTROL2);
2574                 DUMPREG(DISPC_CONFIG2);
2575         }
2576
2577 #undef DUMPREG
2578
2579 #define DISPC_REG(i, name) name(i)
2580 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2581         48 - strlen(#r) - strlen(p_names[i]), " ", \
2582         dispc_read_reg(DISPC_REG(i, r)))
2583
2584         p_names = mgr_names;
2585
2586         /* DISPC channel specific registers */
2587         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2588                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2589                 DUMPREG(i, DISPC_TRANS_COLOR);
2590                 DUMPREG(i, DISPC_SIZE_MGR);
2591
2592                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2593                         continue;
2594
2595                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2596                 DUMPREG(i, DISPC_TRANS_COLOR);
2597                 DUMPREG(i, DISPC_TIMING_H);
2598                 DUMPREG(i, DISPC_TIMING_V);
2599                 DUMPREG(i, DISPC_POL_FREQ);
2600                 DUMPREG(i, DISPC_DIVISORo);
2601                 DUMPREG(i, DISPC_SIZE_MGR);
2602
2603                 DUMPREG(i, DISPC_DATA_CYCLE1);
2604                 DUMPREG(i, DISPC_DATA_CYCLE2);
2605                 DUMPREG(i, DISPC_DATA_CYCLE3);
2606
2607                 if (dss_has_feature(FEAT_CPR)) {
2608                         DUMPREG(i, DISPC_CPR_COEF_R);
2609                         DUMPREG(i, DISPC_CPR_COEF_G);
2610                         DUMPREG(i, DISPC_CPR_COEF_B);
2611                 }
2612         }
2613
2614         p_names = ovl_names;
2615
2616         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2617                 DUMPREG(i, DISPC_OVL_BA0);
2618                 DUMPREG(i, DISPC_OVL_BA1);
2619                 DUMPREG(i, DISPC_OVL_POSITION);
2620                 DUMPREG(i, DISPC_OVL_SIZE);
2621                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2622                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2623                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2624                 DUMPREG(i, DISPC_OVL_ROW_INC);
2625                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2626                 if (dss_has_feature(FEAT_PRELOAD))
2627                         DUMPREG(i, DISPC_OVL_PRELOAD);
2628
2629                 if (i == OMAP_DSS_GFX) {
2630                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2631                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2632                         continue;
2633                 }
2634
2635                 DUMPREG(i, DISPC_OVL_FIR);
2636                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2637                 DUMPREG(i, DISPC_OVL_ACCU0);
2638                 DUMPREG(i, DISPC_OVL_ACCU1);
2639                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2640                         DUMPREG(i, DISPC_OVL_BA0_UV);
2641                         DUMPREG(i, DISPC_OVL_BA1_UV);
2642                         DUMPREG(i, DISPC_OVL_FIR2);
2643                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2644                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2645                 }
2646                 if (dss_has_feature(FEAT_ATTR2))
2647                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2648                 if (dss_has_feature(FEAT_PRELOAD))
2649                         DUMPREG(i, DISPC_OVL_PRELOAD);
2650         }
2651
2652 #undef DISPC_REG
2653 #undef DUMPREG
2654
2655 #define DISPC_REG(plane, name, i) name(plane, i)
2656 #define DUMPREG(plane, name, i) \
2657         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2658         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2659         dispc_read_reg(DISPC_REG(plane, name, i)))
2660
2661         /* Video pipeline coefficient registers */
2662
2663         /* start from OMAP_DSS_VIDEO1 */
2664         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2665                 for (j = 0; j < 8; j++)
2666                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2667
2668                 for (j = 0; j < 8; j++)
2669                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2670
2671                 for (j = 0; j < 5; j++)
2672                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2673
2674                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2675                         for (j = 0; j < 8; j++)
2676                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2677                 }
2678
2679                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2680                         for (j = 0; j < 8; j++)
2681                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2682
2683                         for (j = 0; j < 8; j++)
2684                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2685
2686                         for (j = 0; j < 8; j++)
2687                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2688                 }
2689         }
2690
2691         dispc_runtime_put();
2692
2693 #undef DISPC_REG
2694 #undef DUMPREG
2695 }
2696
2697 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2698                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2699                 u8 acb)
2700 {
2701         u32 l = 0;
2702
2703         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2704                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2705
2706         l |= FLD_VAL(onoff, 17, 17);
2707         l |= FLD_VAL(rf, 16, 16);
2708         l |= FLD_VAL(ieo, 15, 15);
2709         l |= FLD_VAL(ipc, 14, 14);
2710         l |= FLD_VAL(ihs, 13, 13);
2711         l |= FLD_VAL(ivs, 12, 12);
2712         l |= FLD_VAL(acbi, 11, 8);
2713         l |= FLD_VAL(acb, 7, 0);
2714
2715         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2716 }
2717
2718 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2719                 enum omap_panel_config config, u8 acbi, u8 acb)
2720 {
2721         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2722                         (config & OMAP_DSS_LCD_RF) != 0,
2723                         (config & OMAP_DSS_LCD_IEO) != 0,
2724                         (config & OMAP_DSS_LCD_IPC) != 0,
2725                         (config & OMAP_DSS_LCD_IHS) != 0,
2726                         (config & OMAP_DSS_LCD_IVS) != 0,
2727                         acbi, acb);
2728 }
2729
2730 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2731 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2732                 struct dispc_clock_info *cinfo)
2733 {
2734         u16 pcd_min, pcd_max;
2735         unsigned long best_pck;
2736         u16 best_ld, cur_ld;
2737         u16 best_pd, cur_pd;
2738
2739         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2740         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2741
2742         if (!is_tft)
2743                 pcd_min = 3;
2744
2745         best_pck = 0;
2746         best_ld = 0;
2747         best_pd = 0;
2748
2749         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2750                 unsigned long lck = fck / cur_ld;
2751
2752                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2753                         unsigned long pck = lck / cur_pd;
2754                         long old_delta = abs(best_pck - req_pck);
2755                         long new_delta = abs(pck - req_pck);
2756
2757                         if (best_pck == 0 || new_delta < old_delta) {
2758                                 best_pck = pck;
2759                                 best_ld = cur_ld;
2760                                 best_pd = cur_pd;
2761
2762                                 if (pck == req_pck)
2763                                         goto found;
2764                         }
2765
2766                         if (pck < req_pck)
2767                                 break;
2768                 }
2769
2770                 if (lck / pcd_min < req_pck)
2771                         break;
2772         }
2773
2774 found:
2775         cinfo->lck_div = best_ld;
2776         cinfo->pck_div = best_pd;
2777         cinfo->lck = fck / cinfo->lck_div;
2778         cinfo->pck = cinfo->lck / cinfo->pck_div;
2779 }
2780
2781 /* calculate clock rates using dividers in cinfo */
2782 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2783                 struct dispc_clock_info *cinfo)
2784 {
2785         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2786                 return -EINVAL;
2787         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2788                 return -EINVAL;
2789
2790         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2791         cinfo->pck = cinfo->lck / cinfo->pck_div;
2792
2793         return 0;
2794 }
2795
2796 int dispc_mgr_set_clock_div(enum omap_channel channel,
2797                 struct dispc_clock_info *cinfo)
2798 {
2799         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2800         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2801
2802         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2803
2804         return 0;
2805 }
2806
2807 int dispc_mgr_get_clock_div(enum omap_channel channel,
2808                 struct dispc_clock_info *cinfo)
2809 {
2810         unsigned long fck;
2811
2812         fck = dispc_fclk_rate();
2813
2814         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2815         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2816
2817         cinfo->lck = fck / cinfo->lck_div;
2818         cinfo->pck = cinfo->lck / cinfo->pck_div;
2819
2820         return 0;
2821 }
2822
2823 /* dispc.irq_lock has to be locked by the caller */
2824 static void _omap_dispc_set_irqs(void)
2825 {
2826         u32 mask;
2827         u32 old_mask;
2828         int i;
2829         struct omap_dispc_isr_data *isr_data;
2830
2831         mask = dispc.irq_error_mask;
2832
2833         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2834                 isr_data = &dispc.registered_isr[i];
2835
2836                 if (isr_data->isr == NULL)
2837                         continue;
2838
2839                 mask |= isr_data->mask;
2840         }
2841
2842         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2843         /* clear the irqstatus for newly enabled irqs */
2844         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2845
2846         dispc_write_reg(DISPC_IRQENABLE, mask);
2847 }
2848
2849 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2850 {
2851         int i;
2852         int ret;
2853         unsigned long flags;
2854         struct omap_dispc_isr_data *isr_data;
2855
2856         if (isr == NULL)
2857                 return -EINVAL;
2858
2859         spin_lock_irqsave(&dispc.irq_lock, flags);
2860
2861         /* check for duplicate entry */
2862         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2863                 isr_data = &dispc.registered_isr[i];
2864                 if (isr_data->isr == isr && isr_data->arg == arg &&
2865                                 isr_data->mask == mask) {
2866                         ret = -EINVAL;
2867                         goto err;
2868                 }
2869         }
2870
2871         isr_data = NULL;
2872         ret = -EBUSY;
2873
2874         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2875                 isr_data = &dispc.registered_isr[i];
2876
2877                 if (isr_data->isr != NULL)
2878                         continue;
2879
2880                 isr_data->isr = isr;
2881                 isr_data->arg = arg;
2882                 isr_data->mask = mask;
2883                 ret = 0;
2884
2885                 break;
2886         }
2887
2888         if (ret)
2889                 goto err;
2890
2891         _omap_dispc_set_irqs();
2892
2893         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2894
2895         return 0;
2896 err:
2897         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2898
2899         return ret;
2900 }
2901 EXPORT_SYMBOL(omap_dispc_register_isr);
2902
2903 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2904 {
2905         int i;
2906         unsigned long flags;
2907         int ret = -EINVAL;
2908         struct omap_dispc_isr_data *isr_data;
2909
2910         spin_lock_irqsave(&dispc.irq_lock, flags);
2911
2912         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2913                 isr_data = &dispc.registered_isr[i];
2914                 if (isr_data->isr != isr || isr_data->arg != arg ||
2915                                 isr_data->mask != mask)
2916                         continue;
2917
2918                 /* found the correct isr */
2919
2920                 isr_data->isr = NULL;
2921                 isr_data->arg = NULL;
2922                 isr_data->mask = 0;
2923
2924                 ret = 0;
2925                 break;
2926         }
2927
2928         if (ret == 0)
2929                 _omap_dispc_set_irqs();
2930
2931         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2932
2933         return ret;
2934 }
2935 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2936
2937 #ifdef DEBUG
2938 static void print_irq_status(u32 status)
2939 {
2940         if ((status & dispc.irq_error_mask) == 0)
2941                 return;
2942
2943         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2944
2945 #define PIS(x) \
2946         if (status & DISPC_IRQ_##x) \
2947                 printk(#x " ");
2948         PIS(GFX_FIFO_UNDERFLOW);
2949         PIS(OCP_ERR);
2950         PIS(VID1_FIFO_UNDERFLOW);
2951         PIS(VID2_FIFO_UNDERFLOW);
2952         PIS(SYNC_LOST);
2953         PIS(SYNC_LOST_DIGIT);
2954         if (dss_has_feature(FEAT_MGR_LCD2))
2955                 PIS(SYNC_LOST2);
2956 #undef PIS
2957
2958         printk("\n");
2959 }
2960 #endif
2961
2962 /* Called from dss.c. Note that we don't touch clocks here,
2963  * but we presume they are on because we got an IRQ. However,
2964  * an irq handler may turn the clocks off, so we may not have
2965  * clock later in the function. */
2966 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2967 {
2968         int i;
2969         u32 irqstatus, irqenable;
2970         u32 handledirqs = 0;
2971         u32 unhandled_errors;
2972         struct omap_dispc_isr_data *isr_data;
2973         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2974
2975         spin_lock(&dispc.irq_lock);
2976
2977         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2978         irqenable = dispc_read_reg(DISPC_IRQENABLE);
2979
2980         /* IRQ is not for us */
2981         if (!(irqstatus & irqenable)) {
2982                 spin_unlock(&dispc.irq_lock);
2983                 return IRQ_NONE;
2984         }
2985
2986 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2987         spin_lock(&dispc.irq_stats_lock);
2988         dispc.irq_stats.irq_count++;
2989         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2990         spin_unlock(&dispc.irq_stats_lock);
2991 #endif
2992
2993 #ifdef DEBUG
2994         if (dss_debug)
2995                 print_irq_status(irqstatus);
2996 #endif
2997         /* Ack the interrupt. Do it here before clocks are possibly turned
2998          * off */
2999         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3000         /* flush posted write */
3001         dispc_read_reg(DISPC_IRQSTATUS);
3002
3003         /* make a copy and unlock, so that isrs can unregister
3004          * themselves */
3005         memcpy(registered_isr, dispc.registered_isr,
3006                         sizeof(registered_isr));
3007
3008         spin_unlock(&dispc.irq_lock);
3009
3010         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3011                 isr_data = &registered_isr[i];
3012
3013                 if (!isr_data->isr)
3014                         continue;
3015
3016                 if (isr_data->mask & irqstatus) {
3017                         isr_data->isr(isr_data->arg, irqstatus);
3018                         handledirqs |= isr_data->mask;
3019                 }
3020         }
3021
3022         spin_lock(&dispc.irq_lock);
3023
3024         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3025
3026         if (unhandled_errors) {
3027                 dispc.error_irqs |= unhandled_errors;
3028
3029                 dispc.irq_error_mask &= ~unhandled_errors;
3030                 _omap_dispc_set_irqs();
3031
3032                 schedule_work(&dispc.error_work);
3033         }
3034
3035         spin_unlock(&dispc.irq_lock);
3036
3037         return IRQ_HANDLED;
3038 }
3039
3040 static void dispc_error_worker(struct work_struct *work)
3041 {
3042         int i;
3043         u32 errors;
3044         unsigned long flags;
3045         static const unsigned fifo_underflow_bits[] = {
3046                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3047                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3048                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3049         };
3050
3051         static const unsigned sync_lost_bits[] = {
3052                 DISPC_IRQ_SYNC_LOST,
3053                 DISPC_IRQ_SYNC_LOST_DIGIT,
3054                 DISPC_IRQ_SYNC_LOST2,
3055         };
3056
3057         spin_lock_irqsave(&dispc.irq_lock, flags);
3058         errors = dispc.error_irqs;
3059         dispc.error_irqs = 0;
3060         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3061
3062         dispc_runtime_get();
3063
3064         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3065                 struct omap_overlay *ovl;
3066                 unsigned bit;
3067
3068                 ovl = omap_dss_get_overlay(i);
3069                 bit = fifo_underflow_bits[i];
3070
3071                 if (bit & errors) {
3072                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3073                                         ovl->name);
3074                         dispc_ovl_enable(ovl->id, false);
3075                         dispc_mgr_go(ovl->manager->id);
3076                         mdelay(50);
3077                 }
3078         }
3079
3080         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3081                 struct omap_overlay_manager *mgr;
3082                 unsigned bit;
3083
3084                 mgr = omap_dss_get_overlay_manager(i);
3085                 bit = sync_lost_bits[i];
3086
3087                 if (bit & errors) {
3088                         struct omap_dss_device *dssdev = mgr->device;
3089                         bool enable;
3090
3091                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3092                                         "with video overlays disabled\n",
3093                                         mgr->name);
3094
3095                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3096                         dssdev->driver->disable(dssdev);
3097
3098                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3099                                 struct omap_overlay *ovl;
3100                                 ovl = omap_dss_get_overlay(i);
3101
3102                                 if (ovl->id != OMAP_DSS_GFX &&
3103                                                 ovl->manager == mgr)
3104                                         dispc_ovl_enable(ovl->id, false);
3105                         }
3106
3107                         dispc_mgr_go(mgr->id);
3108                         mdelay(50);
3109
3110                         if (enable)
3111                                 dssdev->driver->enable(dssdev);
3112                 }
3113         }
3114
3115         if (errors & DISPC_IRQ_OCP_ERR) {
3116                 DSSERR("OCP_ERR\n");
3117                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3118                         struct omap_overlay_manager *mgr;
3119                         mgr = omap_dss_get_overlay_manager(i);
3120                         mgr->device->driver->disable(mgr->device);
3121                 }
3122         }
3123
3124         spin_lock_irqsave(&dispc.irq_lock, flags);
3125         dispc.irq_error_mask |= errors;
3126         _omap_dispc_set_irqs();
3127         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3128
3129         dispc_runtime_put();
3130 }
3131
3132 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3133 {
3134         void dispc_irq_wait_handler(void *data, u32 mask)
3135         {
3136                 complete((struct completion *)data);
3137         }
3138
3139         int r;
3140         DECLARE_COMPLETION_ONSTACK(completion);
3141
3142         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3143                         irqmask);
3144
3145         if (r)
3146                 return r;
3147
3148         timeout = wait_for_completion_timeout(&completion, timeout);
3149
3150         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3151
3152         if (timeout == 0)
3153                 return -ETIMEDOUT;
3154
3155         if (timeout == -ERESTARTSYS)
3156                 return -ERESTARTSYS;
3157
3158         return 0;
3159 }
3160
3161 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3162                 unsigned long timeout)
3163 {
3164         void dispc_irq_wait_handler(void *data, u32 mask)
3165         {
3166                 complete((struct completion *)data);
3167         }
3168
3169         int r;
3170         DECLARE_COMPLETION_ONSTACK(completion);
3171
3172         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3173                         irqmask);
3174
3175         if (r)
3176                 return r;
3177
3178         timeout = wait_for_completion_interruptible_timeout(&completion,
3179                         timeout);
3180
3181         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3182
3183         if (timeout == 0)
3184                 return -ETIMEDOUT;
3185
3186         if (timeout == -ERESTARTSYS)
3187                 return -ERESTARTSYS;
3188
3189         return 0;
3190 }
3191
3192 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3193 void dispc_fake_vsync_irq(void)
3194 {
3195         u32 irqstatus = DISPC_IRQ_VSYNC;
3196         int i;
3197
3198         WARN_ON(!in_interrupt());
3199
3200         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3201                 struct omap_dispc_isr_data *isr_data;
3202                 isr_data = &dispc.registered_isr[i];
3203
3204                 if (!isr_data->isr)
3205                         continue;
3206
3207                 if (isr_data->mask & irqstatus)
3208                         isr_data->isr(isr_data->arg, irqstatus);
3209         }
3210 }
3211 #endif
3212
3213 static void _omap_dispc_initialize_irq(void)
3214 {
3215         unsigned long flags;
3216
3217         spin_lock_irqsave(&dispc.irq_lock, flags);
3218
3219         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3220
3221         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3222         if (dss_has_feature(FEAT_MGR_LCD2))
3223                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3224
3225         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3226          * so clear it */
3227         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3228
3229         _omap_dispc_set_irqs();
3230
3231         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3232 }
3233
3234 void dispc_enable_sidle(void)
3235 {
3236         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3237 }
3238
3239 void dispc_disable_sidle(void)
3240 {
3241         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3242 }
3243
3244 static void _omap_dispc_initial_config(void)
3245 {
3246         u32 l;
3247
3248         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3249         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3250                 l = dispc_read_reg(DISPC_DIVISOR);
3251                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3252                 l = FLD_MOD(l, 1, 0, 0);
3253                 l = FLD_MOD(l, 1, 23, 16);
3254                 dispc_write_reg(DISPC_DIVISOR, l);
3255         }
3256
3257         /* FUNCGATED */
3258         if (dss_has_feature(FEAT_FUNCGATED))
3259                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3260
3261         /* L3 firewall setting: enable access to OCM RAM */
3262         /* XXX this should be somewhere in plat-omap */
3263         if (cpu_is_omap24xx())
3264                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3265
3266         _dispc_setup_color_conv_coef();
3267
3268         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3269
3270         dispc_read_plane_fifo_sizes();
3271
3272         dispc_configure_burst_sizes();
3273 }
3274
3275 /* DISPC HW IP initialisation */
3276 static int omap_dispchw_probe(struct platform_device *pdev)
3277 {
3278         u32 rev;
3279         int r = 0;
3280         struct resource *dispc_mem;
3281         struct clk *clk;
3282
3283         dispc.pdev = pdev;
3284
3285         clk = clk_get(&pdev->dev, "fck");
3286         if (IS_ERR(clk)) {
3287                 DSSERR("can't get fck\n");
3288                 r = PTR_ERR(clk);
3289                 goto err_get_clk;
3290         }
3291
3292         dispc.dss_clk = clk;
3293
3294         spin_lock_init(&dispc.irq_lock);
3295
3296 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3297         spin_lock_init(&dispc.irq_stats_lock);
3298         dispc.irq_stats.last_reset = jiffies;
3299 #endif
3300
3301         INIT_WORK(&dispc.error_work, dispc_error_worker);
3302
3303         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3304         if (!dispc_mem) {
3305                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3306                 r = -EINVAL;
3307                 goto err_ioremap;
3308         }
3309         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3310         if (!dispc.base) {
3311                 DSSERR("can't ioremap DISPC\n");
3312                 r = -ENOMEM;
3313                 goto err_ioremap;
3314         }
3315         dispc.irq = platform_get_irq(dispc.pdev, 0);
3316         if (dispc.irq < 0) {
3317                 DSSERR("platform_get_irq failed\n");
3318                 r = -ENODEV;
3319                 goto err_irq;
3320         }
3321
3322         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3323                 "OMAP DISPC", dispc.pdev);
3324         if (r < 0) {
3325                 DSSERR("request_irq failed\n");
3326                 goto err_irq;
3327         }
3328
3329         pm_runtime_enable(&pdev->dev);
3330
3331         r = dispc_runtime_get();
3332         if (r)
3333                 goto err_runtime_get;
3334
3335         _omap_dispc_initial_config();
3336
3337         _omap_dispc_initialize_irq();
3338
3339         rev = dispc_read_reg(DISPC_REVISION);
3340         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3341                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3342
3343         dispc_runtime_put();
3344
3345         return 0;
3346
3347 err_runtime_get:
3348         pm_runtime_disable(&pdev->dev);
3349         free_irq(dispc.irq, dispc.pdev);
3350 err_irq:
3351         iounmap(dispc.base);
3352 err_ioremap:
3353         clk_put(dispc.dss_clk);
3354 err_get_clk:
3355         return r;
3356 }
3357
3358 static int omap_dispchw_remove(struct platform_device *pdev)
3359 {
3360         pm_runtime_disable(&pdev->dev);
3361
3362         clk_put(dispc.dss_clk);
3363
3364         free_irq(dispc.irq, dispc.pdev);
3365         iounmap(dispc.base);
3366         return 0;
3367 }
3368
3369 static int dispc_runtime_suspend(struct device *dev)
3370 {
3371         dispc_save_context();
3372         dss_runtime_put();
3373
3374         return 0;
3375 }
3376
3377 static int dispc_runtime_resume(struct device *dev)
3378 {
3379         int r;
3380
3381         r = dss_runtime_get();
3382         if (r < 0)
3383                 return r;
3384
3385         dispc_restore_context();
3386
3387         return 0;
3388 }
3389
3390 static const struct dev_pm_ops dispc_pm_ops = {
3391         .runtime_suspend = dispc_runtime_suspend,
3392         .runtime_resume = dispc_runtime_resume,
3393 };
3394
3395 static struct platform_driver omap_dispchw_driver = {
3396         .probe          = omap_dispchw_probe,
3397         .remove         = omap_dispchw_remove,
3398         .driver         = {
3399                 .name   = "omapdss_dispc",
3400                 .owner  = THIS_MODULE,
3401                 .pm     = &dispc_pm_ops,
3402         },
3403 };
3404
3405 int dispc_init_platform_driver(void)
3406 {
3407         return platform_driver_register(&omap_dispchw_driver);
3408 }
3409
3410 void dispc_uninit_platform_driver(void)
3411 {
3412         return platform_driver_unregister(&omap_dispchw_driver);
3413 }