drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <plat/sram.h>
  38 #include <plat/clock.h>
  39
  40 #include <plat/display.h>
  41
  42 #include "dss.h"
  43 #include "dss_features.h"
  44
  45 /* DISPC */
  46 #define DISPC_SZ_REGS                   SZ_4K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /*
  53  * DISPC common registers and
  54  * DISPC channel registers , ch = 0 for LCD, ch = 1 for
  55  * DIGIT, and ch = 2 for LCD2
  56  */
  57 #define DISPC_REVISION                  DISPC_REG(0x0000)
  58 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  59 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  60 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  61 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  62 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  63 #define DISPC_CONTROL2                  DISPC_REG(0x0238)
  64 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  65 #define DISPC_CONFIG2                   DISPC_REG(0x0620)
  66 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  67 #define DISPC_DEFAULT_COLOR(ch)         DISPC_REG(ch == 0 ? 0x004C : \
  68                                         (ch == 1 ? 0x0050 : 0x03AC))
  69 #define DISPC_TRANS_COLOR(ch)           DISPC_REG(ch == 0 ? 0x0054 : \
  70                                         (ch == 1 ? 0x0058 : 0x03B0))
  71 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  72 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  73 #define DISPC_TIMING_H(ch)              DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
  74 #define DISPC_TIMING_V(ch)              DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
  75 #define DISPC_POL_FREQ(ch)              DISPC_REG(ch != 2 ? 0x006C : 0x0408)
  76 #define DISPC_DIVISOR(ch)               DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
  77 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  78 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  79 #define DISPC_SIZE_LCD(ch)              DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
  80
  81 /* DISPC GFX plane */
  82 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  83 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  84 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  85 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  86 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  87 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  88 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  89 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  90 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  91 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  92 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  93
  94 #define DISPC_DATA_CYCLE1(ch)           DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
  95 #define DISPC_DATA_CYCLE2(ch)           DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
  96 #define DISPC_DATA_CYCLE3(ch)           DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
  97 #define DISPC_CPR_COEF_R(ch)            DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
  98 #define DISPC_CPR_COEF_G(ch)            DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
  99 #define DISPC_CPR_COEF_B(ch)            DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
 100
 101 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
 102
 103 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
 104 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 105
 106 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 107 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 108 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 109 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 110 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 111 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 112 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 113 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 114 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 115 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 116 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 117 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 118 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 119
 120 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 121 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 122 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 123 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 124 /* coef index i = {0, 1, 2, 3, 4} */
 125 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 126 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 127 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 128
 129 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 130
 131
 132 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 133                                          DISPC_IRQ_OCP_ERR | \
 134                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 135                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 136                                          DISPC_IRQ_SYNC_LOST | \
 137                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 138
 139 #define DISPC_MAX_NR_ISRS               8
 140
 141 struct omap_dispc_isr_data {
 142         omap_dispc_isr_t        isr;
 143         void                    *arg;
 144         u32                     mask;
 145 };
 146
 147 struct dispc_h_coef {
 148         s8 hc4;
 149         s8 hc3;
 150         u8 hc2;
 151         s8 hc1;
 152         s8 hc0;
 153 };
 154
 155 struct dispc_v_coef {
 156         s8 vc22;
 157         s8 vc2;
 158         u8 vc1;
 159         s8 vc0;
 160         s8 vc00;
 161 };
 162
 163 #define REG_GET(idx, start, end) \
 164         FLD_GET(dispc_read_reg(idx), start, end)
 165
 166 #define REG_FLD_MOD(idx, val, start, end)                               \
 167         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 168
 169 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 170         DISPC_VID_ATTRIBUTES(0),
 171         DISPC_VID_ATTRIBUTES(1) };
 172
 173 struct dispc_irq_stats {
 174         unsigned long last_reset;
 175         unsigned irq_count;
 176         unsigned irqs[32];
 177 };
 178
 179 static struct {
 180         struct platform_device *pdev;
 181         void __iomem    *base;
 182         int irq;
 183
 184         u32     fifo_size[3];
 185
 186         spinlock_t irq_lock;
 187         u32 irq_error_mask;
 188         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 189         u32 error_irqs;
 190         struct work_struct error_work;
 191
 192         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 193
 194 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 195         spinlock_t irq_stats_lock;
 196         struct dispc_irq_stats irq_stats;
 197 #endif
 198 } dispc;
 199
 200 static void _omap_dispc_set_irqs(void);
 201
 202 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 203 {
 204         __raw_writel(val, dispc.base + idx.idx);
 205 }
 206
 207 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 208 {
 209         return __raw_readl(dispc.base + idx.idx);
 210 }
 211
 212 #define SR(reg) \
 213         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 214 #define RR(reg) \
 215         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 216
 217 void dispc_save_context(void)
 218 {
 219         if (cpu_is_omap24xx())
 220                 return;
 221
 222         SR(SYSCONFIG);
 223         SR(IRQENABLE);
 224         SR(CONTROL);
 225         SR(CONFIG);
 226         SR(DEFAULT_COLOR(0));
 227         SR(DEFAULT_COLOR(1));
 228         SR(TRANS_COLOR(0));
 229         SR(TRANS_COLOR(1));
 230         SR(LINE_NUMBER);
 231         SR(TIMING_H(0));
 232         SR(TIMING_V(0));
 233         SR(POL_FREQ(0));
 234         SR(DIVISOR(0));
 235         SR(GLOBAL_ALPHA);
 236         SR(SIZE_DIG);
 237         SR(SIZE_LCD(0));
 238         if (dss_has_feature(FEAT_MGR_LCD2)) {
 239                 SR(CONTROL2);
 240                 SR(DEFAULT_COLOR(2));
 241                 SR(TRANS_COLOR(2));
 242                 SR(SIZE_LCD(2));
 243                 SR(TIMING_H(2));
 244                 SR(TIMING_V(2));
 245                 SR(POL_FREQ(2));
 246                 SR(DIVISOR(2));
 247                 SR(CONFIG2);
 248         }
 249
 250         SR(GFX_BA0);
 251         SR(GFX_BA1);
 252         SR(GFX_POSITION);
 253         SR(GFX_SIZE);
 254         SR(GFX_ATTRIBUTES);
 255         SR(GFX_FIFO_THRESHOLD);
 256         SR(GFX_ROW_INC);
 257         SR(GFX_PIXEL_INC);
 258         SR(GFX_WINDOW_SKIP);
 259         SR(GFX_TABLE_BA);
 260
 261         SR(DATA_CYCLE1(0));
 262         SR(DATA_CYCLE2(0));
 263         SR(DATA_CYCLE3(0));
 264
 265         SR(CPR_COEF_R(0));
 266         SR(CPR_COEF_G(0));
 267         SR(CPR_COEF_B(0));
 268         if (dss_has_feature(FEAT_MGR_LCD2)) {
 269                 SR(CPR_COEF_B(2));
 270                 SR(CPR_COEF_G(2));
 271                 SR(CPR_COEF_R(2));
 272
 273                 SR(DATA_CYCLE1(2));
 274                 SR(DATA_CYCLE2(2));
 275                 SR(DATA_CYCLE3(2));
 276         }
 277
 278         SR(GFX_PRELOAD);
 279
 280         /* VID1 */
 281         SR(VID_BA0(0));
 282         SR(VID_BA1(0));
 283         SR(VID_POSITION(0));
 284         SR(VID_SIZE(0));
 285         SR(VID_ATTRIBUTES(0));
 286         SR(VID_FIFO_THRESHOLD(0));
 287         SR(VID_ROW_INC(0));
 288         SR(VID_PIXEL_INC(0));
 289         SR(VID_FIR(0));
 290         SR(VID_PICTURE_SIZE(0));
 291         SR(VID_ACCU0(0));
 292         SR(VID_ACCU1(0));
 293
 294         SR(VID_FIR_COEF_H(0, 0));
 295         SR(VID_FIR_COEF_H(0, 1));
 296         SR(VID_FIR_COEF_H(0, 2));
 297         SR(VID_FIR_COEF_H(0, 3));
 298         SR(VID_FIR_COEF_H(0, 4));
 299         SR(VID_FIR_COEF_H(0, 5));
 300         SR(VID_FIR_COEF_H(0, 6));
 301         SR(VID_FIR_COEF_H(0, 7));
 302
 303         SR(VID_FIR_COEF_HV(0, 0));
 304         SR(VID_FIR_COEF_HV(0, 1));
 305         SR(VID_FIR_COEF_HV(0, 2));
 306         SR(VID_FIR_COEF_HV(0, 3));
 307         SR(VID_FIR_COEF_HV(0, 4));
 308         SR(VID_FIR_COEF_HV(0, 5));
 309         SR(VID_FIR_COEF_HV(0, 6));
 310         SR(VID_FIR_COEF_HV(0, 7));
 311
 312         SR(VID_CONV_COEF(0, 0));
 313         SR(VID_CONV_COEF(0, 1));
 314         SR(VID_CONV_COEF(0, 2));
 315         SR(VID_CONV_COEF(0, 3));
 316         SR(VID_CONV_COEF(0, 4));
 317
 318         SR(VID_FIR_COEF_V(0, 0));
 319         SR(VID_FIR_COEF_V(0, 1));
 320         SR(VID_FIR_COEF_V(0, 2));
 321         SR(VID_FIR_COEF_V(0, 3));
 322         SR(VID_FIR_COEF_V(0, 4));
 323         SR(VID_FIR_COEF_V(0, 5));
 324         SR(VID_FIR_COEF_V(0, 6));
 325         SR(VID_FIR_COEF_V(0, 7));
 326
 327         SR(VID_PRELOAD(0));
 328
 329         /* VID2 */
 330         SR(VID_BA0(1));
 331         SR(VID_BA1(1));
 332         SR(VID_POSITION(1));
 333         SR(VID_SIZE(1));
 334         SR(VID_ATTRIBUTES(1));
 335         SR(VID_FIFO_THRESHOLD(1));
 336         SR(VID_ROW_INC(1));
 337         SR(VID_PIXEL_INC(1));
 338         SR(VID_FIR(1));
 339         SR(VID_PICTURE_SIZE(1));
 340         SR(VID_ACCU0(1));
 341         SR(VID_ACCU1(1));
 342
 343         SR(VID_FIR_COEF_H(1, 0));
 344         SR(VID_FIR_COEF_H(1, 1));
 345         SR(VID_FIR_COEF_H(1, 2));
 346         SR(VID_FIR_COEF_H(1, 3));
 347         SR(VID_FIR_COEF_H(1, 4));
 348         SR(VID_FIR_COEF_H(1, 5));
 349         SR(VID_FIR_COEF_H(1, 6));
 350         SR(VID_FIR_COEF_H(1, 7));
 351
 352         SR(VID_FIR_COEF_HV(1, 0));
 353         SR(VID_FIR_COEF_HV(1, 1));
 354         SR(VID_FIR_COEF_HV(1, 2));
 355         SR(VID_FIR_COEF_HV(1, 3));
 356         SR(VID_FIR_COEF_HV(1, 4));
 357         SR(VID_FIR_COEF_HV(1, 5));
 358         SR(VID_FIR_COEF_HV(1, 6));
 359         SR(VID_FIR_COEF_HV(1, 7));
 360
 361         SR(VID_CONV_COEF(1, 0));
 362         SR(VID_CONV_COEF(1, 1));
 363         SR(VID_CONV_COEF(1, 2));
 364         SR(VID_CONV_COEF(1, 3));
 365         SR(VID_CONV_COEF(1, 4));
 366
 367         SR(VID_FIR_COEF_V(1, 0));
 368         SR(VID_FIR_COEF_V(1, 1));
 369         SR(VID_FIR_COEF_V(1, 2));
 370         SR(VID_FIR_COEF_V(1, 3));
 371         SR(VID_FIR_COEF_V(1, 4));
 372         SR(VID_FIR_COEF_V(1, 5));
 373         SR(VID_FIR_COEF_V(1, 6));
 374         SR(VID_FIR_COEF_V(1, 7));
 375
 376         SR(VID_PRELOAD(1));
 377 }
 378
 379 void dispc_restore_context(void)
 380 {
 381         RR(SYSCONFIG);
 382         /*RR(IRQENABLE);*/
 383         /*RR(CONTROL);*/
 384         RR(CONFIG);
 385         RR(DEFAULT_COLOR(0));
 386         RR(DEFAULT_COLOR(1));
 387         RR(TRANS_COLOR(0));
 388         RR(TRANS_COLOR(1));
 389         RR(LINE_NUMBER);
 390         RR(TIMING_H(0));
 391         RR(TIMING_V(0));
 392         RR(POL_FREQ(0));
 393         RR(DIVISOR(0));
 394         RR(GLOBAL_ALPHA);
 395         RR(SIZE_DIG);
 396         RR(SIZE_LCD(0));
 397         if (dss_has_feature(FEAT_MGR_LCD2)) {
 398                 RR(DEFAULT_COLOR(2));
 399                 RR(TRANS_COLOR(2));
 400                 RR(SIZE_LCD(2));
 401                 RR(TIMING_H(2));
 402                 RR(TIMING_V(2));
 403                 RR(POL_FREQ(2));
 404                 RR(DIVISOR(2));
 405                 RR(CONFIG2);
 406         }
 407
 408         RR(GFX_BA0);
 409         RR(GFX_BA1);
 410         RR(GFX_POSITION);
 411         RR(GFX_SIZE);
 412         RR(GFX_ATTRIBUTES);
 413         RR(GFX_FIFO_THRESHOLD);
 414         RR(GFX_ROW_INC);
 415         RR(GFX_PIXEL_INC);
 416         RR(GFX_WINDOW_SKIP);
 417         RR(GFX_TABLE_BA);
 418
 419         RR(DATA_CYCLE1(0));
 420         RR(DATA_CYCLE2(0));
 421         RR(DATA_CYCLE3(0));
 422
 423         RR(CPR_COEF_R(0));
 424         RR(CPR_COEF_G(0));
 425         RR(CPR_COEF_B(0));
 426         if (dss_has_feature(FEAT_MGR_LCD2)) {
 427                 RR(DATA_CYCLE1(2));
 428                 RR(DATA_CYCLE2(2));
 429                 RR(DATA_CYCLE3(2));
 430
 431                 RR(CPR_COEF_B(2));
 432                 RR(CPR_COEF_G(2));
 433                 RR(CPR_COEF_R(2));
 434         }
 435
 436         RR(GFX_PRELOAD);
 437
 438         /* VID1 */
 439         RR(VID_BA0(0));
 440         RR(VID_BA1(0));
 441         RR(VID_POSITION(0));
 442         RR(VID_SIZE(0));
 443         RR(VID_ATTRIBUTES(0));
 444         RR(VID_FIFO_THRESHOLD(0));
 445         RR(VID_ROW_INC(0));
 446         RR(VID_PIXEL_INC(0));
 447         RR(VID_FIR(0));
 448         RR(VID_PICTURE_SIZE(0));
 449         RR(VID_ACCU0(0));
 450         RR(VID_ACCU1(0));
 451
 452         RR(VID_FIR_COEF_H(0, 0));
 453         RR(VID_FIR_COEF_H(0, 1));
 454         RR(VID_FIR_COEF_H(0, 2));
 455         RR(VID_FIR_COEF_H(0, 3));
 456         RR(VID_FIR_COEF_H(0, 4));
 457         RR(VID_FIR_COEF_H(0, 5));
 458         RR(VID_FIR_COEF_H(0, 6));
 459         RR(VID_FIR_COEF_H(0, 7));
 460
 461         RR(VID_FIR_COEF_HV(0, 0));
 462         RR(VID_FIR_COEF_HV(0, 1));
 463         RR(VID_FIR_COEF_HV(0, 2));
 464         RR(VID_FIR_COEF_HV(0, 3));
 465         RR(VID_FIR_COEF_HV(0, 4));
 466         RR(VID_FIR_COEF_HV(0, 5));
 467         RR(VID_FIR_COEF_HV(0, 6));
 468         RR(VID_FIR_COEF_HV(0, 7));
 469
 470         RR(VID_CONV_COEF(0, 0));
 471         RR(VID_CONV_COEF(0, 1));
 472         RR(VID_CONV_COEF(0, 2));
 473         RR(VID_CONV_COEF(0, 3));
 474         RR(VID_CONV_COEF(0, 4));
 475
 476         RR(VID_FIR_COEF_V(0, 0));
 477         RR(VID_FIR_COEF_V(0, 1));
 478         RR(VID_FIR_COEF_V(0, 2));
 479         RR(VID_FIR_COEF_V(0, 3));
 480         RR(VID_FIR_COEF_V(0, 4));
 481         RR(VID_FIR_COEF_V(0, 5));
 482         RR(VID_FIR_COEF_V(0, 6));
 483         RR(VID_FIR_COEF_V(0, 7));
 484
 485         RR(VID_PRELOAD(0));
 486
 487         /* VID2 */
 488         RR(VID_BA0(1));
 489         RR(VID_BA1(1));
 490         RR(VID_POSITION(1));
 491         RR(VID_SIZE(1));
 492         RR(VID_ATTRIBUTES(1));
 493         RR(VID_FIFO_THRESHOLD(1));
 494         RR(VID_ROW_INC(1));
 495         RR(VID_PIXEL_INC(1));
 496         RR(VID_FIR(1));
 497         RR(VID_PICTURE_SIZE(1));
 498         RR(VID_ACCU0(1));
 499         RR(VID_ACCU1(1));
 500
 501         RR(VID_FIR_COEF_H(1, 0));
 502         RR(VID_FIR_COEF_H(1, 1));
 503         RR(VID_FIR_COEF_H(1, 2));
 504         RR(VID_FIR_COEF_H(1, 3));
 505         RR(VID_FIR_COEF_H(1, 4));
 506         RR(VID_FIR_COEF_H(1, 5));
 507         RR(VID_FIR_COEF_H(1, 6));
 508         RR(VID_FIR_COEF_H(1, 7));
 509
 510         RR(VID_FIR_COEF_HV(1, 0));
 511         RR(VID_FIR_COEF_HV(1, 1));
 512         RR(VID_FIR_COEF_HV(1, 2));
 513         RR(VID_FIR_COEF_HV(1, 3));
 514         RR(VID_FIR_COEF_HV(1, 4));
 515         RR(VID_FIR_COEF_HV(1, 5));
 516         RR(VID_FIR_COEF_HV(1, 6));
 517         RR(VID_FIR_COEF_HV(1, 7));
 518
 519         RR(VID_CONV_COEF(1, 0));
 520         RR(VID_CONV_COEF(1, 1));
 521         RR(VID_CONV_COEF(1, 2));
 522         RR(VID_CONV_COEF(1, 3));
 523         RR(VID_CONV_COEF(1, 4));
 524
 525         RR(VID_FIR_COEF_V(1, 0));
 526         RR(VID_FIR_COEF_V(1, 1));
 527         RR(VID_FIR_COEF_V(1, 2));
 528         RR(VID_FIR_COEF_V(1, 3));
 529         RR(VID_FIR_COEF_V(1, 4));
 530         RR(VID_FIR_COEF_V(1, 5));
 531         RR(VID_FIR_COEF_V(1, 6));
 532         RR(VID_FIR_COEF_V(1, 7));
 533
 534         RR(VID_PRELOAD(1));
 535
 536         /* enable last, because LCD & DIGIT enable are here */
 537         RR(CONTROL);
 538         if (dss_has_feature(FEAT_MGR_LCD2))
 539                 RR(CONTROL2);
 540         /* clear spurious SYNC_LOST_DIGIT interrupts */
 541         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 542
 543         /*
 544          * enable last so IRQs won't trigger before
 545          * the context is fully restored
 546          */
 547         RR(IRQENABLE);
 548 }
 549
 550 #undef SR
 551 #undef RR
 552
 553 static inline void enable_clocks(bool enable)
 554 {
 555         if (enable)
 556                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 557         else
 558                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 559 }
 560
 561 bool dispc_go_busy(enum omap_channel channel)
 562 {
 563         int bit;
 564
 565         if (channel == OMAP_DSS_CHANNEL_LCD ||
 566                         channel == OMAP_DSS_CHANNEL_LCD2)
 567                 bit = 5; /* GOLCD */
 568         else
 569                 bit = 6; /* GODIGIT */
 570
 571         if (channel == OMAP_DSS_CHANNEL_LCD2)
 572                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 573         else
 574                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 575 }
 576
 577 void dispc_go(enum omap_channel channel)
 578 {
 579         int bit;
 580         bool enable_bit, go_bit;
 581
 582         enable_clocks(1);
 583
 584         if (channel == OMAP_DSS_CHANNEL_LCD ||
 585                         channel == OMAP_DSS_CHANNEL_LCD2)
 586                 bit = 0; /* LCDENABLE */
 587         else
 588                 bit = 1; /* DIGITALENABLE */
 589
 590         /* if the channel is not enabled, we don't need GO */
 591         if (channel == OMAP_DSS_CHANNEL_LCD2)
 592                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 593         else
 594                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 595
 596         if (!enable_bit)
 597                 goto end;
 598
 599         if (channel == OMAP_DSS_CHANNEL_LCD ||
 600                         channel == OMAP_DSS_CHANNEL_LCD2)
 601                 bit = 5; /* GOLCD */
 602         else
 603                 bit = 6; /* GODIGIT */
 604
 605         if (channel == OMAP_DSS_CHANNEL_LCD2)
 606                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 607         else
 608                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 609
 610         if (go_bit) {
 611                 DSSERR("GO bit not down for channel %d\n", channel);
 612                 goto end;
 613         }
 614
 615         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 616                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 617
 618         if (channel == OMAP_DSS_CHANNEL_LCD2)
 619                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 620         else
 621                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 622 end:
 623         enable_clocks(0);
 624 }
 625
 626 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 627 {
 628         BUG_ON(plane == OMAP_DSS_GFX);
 629
 630         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 631 }
 632
 633 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 634 {
 635         BUG_ON(plane == OMAP_DSS_GFX);
 636
 637         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 638 }
 639
 640 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 641 {
 642         BUG_ON(plane == OMAP_DSS_GFX);
 643
 644         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 645 }
 646
 647 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 648                 int vscaleup, int five_taps)
 649 {
 650         /* Coefficients for horizontal up-sampling */
 651         static const struct dispc_h_coef coef_hup[8] = {
 652                 {  0,   0, 128,   0,  0 },
 653                 { -1,  13, 124,  -8,  0 },
 654                 { -2,  30, 112, -11, -1 },
 655                 { -5,  51,  95, -11, -2 },
 656                 {  0,  -9,  73,  73, -9 },
 657                 { -2, -11,  95,  51, -5 },
 658                 { -1, -11, 112,  30, -2 },
 659                 {  0,  -8, 124,  13, -1 },
 660         };
 661
 662         /* Coefficients for vertical up-sampling */
 663         static const struct dispc_v_coef coef_vup_3tap[8] = {
 664                 { 0,  0, 128,  0, 0 },
 665                 { 0,  3, 123,  2, 0 },
 666                 { 0, 12, 111,  5, 0 },
 667                 { 0, 32,  89,  7, 0 },
 668                 { 0,  0,  64, 64, 0 },
 669                 { 0,  7,  89, 32, 0 },
 670                 { 0,  5, 111, 12, 0 },
 671                 { 0,  2, 123,  3, 0 },
 672         };
 673
 674         static const struct dispc_v_coef coef_vup_5tap[8] = {
 675                 {  0,   0, 128,   0,  0 },
 676                 { -1,  13, 124,  -8,  0 },
 677                 { -2,  30, 112, -11, -1 },
 678                 { -5,  51,  95, -11, -2 },
 679                 {  0,  -9,  73,  73, -9 },
 680                 { -2, -11,  95,  51, -5 },
 681                 { -1, -11, 112,  30, -2 },
 682                 {  0,  -8, 124,  13, -1 },
 683         };
 684
 685         /* Coefficients for horizontal down-sampling */
 686         static const struct dispc_h_coef coef_hdown[8] = {
 687                 {   0, 36, 56, 36,  0 },
 688                 {   4, 40, 55, 31, -2 },
 689                 {   8, 44, 54, 27, -5 },
 690                 {  12, 48, 53, 22, -7 },
 691                 {  -9, 17, 52, 51, 17 },
 692                 {  -7, 22, 53, 48, 12 },
 693                 {  -5, 27, 54, 44,  8 },
 694                 {  -2, 31, 55, 40,  4 },
 695         };
 696
 697         /* Coefficients for vertical down-sampling */
 698         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 699                 { 0, 36, 56, 36, 0 },
 700                 { 0, 40, 57, 31, 0 },
 701                 { 0, 45, 56, 27, 0 },
 702                 { 0, 50, 55, 23, 0 },
 703                 { 0, 18, 55, 55, 0 },
 704                 { 0, 23, 55, 50, 0 },
 705                 { 0, 27, 56, 45, 0 },
 706                 { 0, 31, 57, 40, 0 },
 707         };
 708
 709         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 710                 {   0, 36, 56, 36,  0 },
 711                 {   4, 40, 55, 31, -2 },
 712                 {   8, 44, 54, 27, -5 },
 713                 {  12, 48, 53, 22, -7 },
 714                 {  -9, 17, 52, 51, 17 },
 715                 {  -7, 22, 53, 48, 12 },
 716                 {  -5, 27, 54, 44,  8 },
 717                 {  -2, 31, 55, 40,  4 },
 718         };
 719
 720         const struct dispc_h_coef *h_coef;
 721         const struct dispc_v_coef *v_coef;
 722         int i;
 723
 724         if (hscaleup)
 725                 h_coef = coef_hup;
 726         else
 727                 h_coef = coef_hdown;
 728
 729         if (vscaleup)
 730                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 731         else
 732                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 733
 734         for (i = 0; i < 8; i++) {
 735                 u32 h, hv;
 736
 737                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 738                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 739                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 740                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 741                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 742                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 743                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 744                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 745
 746                 _dispc_write_firh_reg(plane, i, h);
 747                 _dispc_write_firhv_reg(plane, i, hv);
 748         }
 749
 750         if (five_taps) {
 751                 for (i = 0; i < 8; i++) {
 752                         u32 v;
 753                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 754                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 755                         _dispc_write_firv_reg(plane, i, v);
 756                 }
 757         }
 758 }
 759
 760 static void _dispc_setup_color_conv_coef(void)
 761 {
 762         const struct color_conv_coef {
 763                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 764                 int  full_range;
 765         }  ctbl_bt601_5 = {
 766                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 767         };
 768
 769         const struct color_conv_coef *ct;
 770
 771 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 772
 773         ct = &ctbl_bt601_5;
 774
 775         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 776         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 777         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 778         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 779         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 780
 781         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 782         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 783         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 784         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 785         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 786
 787 #undef CVAL
 788
 789         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 790         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 791 }
 792
 793
 794 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 795 {
 796         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 797                 DISPC_VID_BA0(0),
 798                 DISPC_VID_BA0(1) };
 799
 800         dispc_write_reg(ba0_reg[plane], paddr);
 801 }
 802
 803 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 804 {
 805         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 806                                       DISPC_VID_BA1(0),
 807                                       DISPC_VID_BA1(1) };
 808
 809         dispc_write_reg(ba1_reg[plane], paddr);
 810 }
 811
 812 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 813 {
 814         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 815                                       DISPC_VID_POSITION(0),
 816                                       DISPC_VID_POSITION(1) };
 817
 818         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 819         dispc_write_reg(pos_reg[plane], val);
 820 }
 821
 822 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 823 {
 824         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 825                                       DISPC_VID_PICTURE_SIZE(0),
 826                                       DISPC_VID_PICTURE_SIZE(1) };
 827         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 828         dispc_write_reg(siz_reg[plane], val);
 829 }
 830
 831 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 832 {
 833         u32 val;
 834         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 835                                       DISPC_VID_SIZE(1) };
 836
 837         BUG_ON(plane == OMAP_DSS_GFX);
 838
 839         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 840         dispc_write_reg(vsi_reg[plane-1], val);
 841 }
 842
 843 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 844 {
 845         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 846                 return;
 847
 848         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 849                 plane == OMAP_DSS_VIDEO1)
 850                 return;
 851
 852         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
 853 }
 854
 855 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 856 {
 857         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 858                 return;
 859
 860         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 861                 plane == OMAP_DSS_VIDEO1)
 862                 return;
 863
 864         if (plane == OMAP_DSS_GFX)
 865                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 866         else if (plane == OMAP_DSS_VIDEO2)
 867                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 868 }
 869
 870 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 871 {
 872         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 873                                      DISPC_VID_PIXEL_INC(0),
 874                                      DISPC_VID_PIXEL_INC(1) };
 875
 876         dispc_write_reg(ri_reg[plane], inc);
 877 }
 878
 879 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 880 {
 881         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 882                                      DISPC_VID_ROW_INC(0),
 883                                      DISPC_VID_ROW_INC(1) };
 884
 885         dispc_write_reg(ri_reg[plane], inc);
 886 }
 887
 888 static void _dispc_set_color_mode(enum omap_plane plane,
 889                 enum omap_color_mode color_mode)
 890 {
 891         u32 m = 0;
 892
 893         switch (color_mode) {
 894         case OMAP_DSS_COLOR_CLUT1:
 895                 m = 0x0; break;
 896         case OMAP_DSS_COLOR_CLUT2:
 897                 m = 0x1; break;
 898         case OMAP_DSS_COLOR_CLUT4:
 899                 m = 0x2; break;
 900         case OMAP_DSS_COLOR_CLUT8:
 901                 m = 0x3; break;
 902         case OMAP_DSS_COLOR_RGB12U:
 903                 m = 0x4; break;
 904         case OMAP_DSS_COLOR_ARGB16:
 905                 m = 0x5; break;
 906         case OMAP_DSS_COLOR_RGB16:
 907                 m = 0x6; break;
 908         case OMAP_DSS_COLOR_RGB24U:
 909                 m = 0x8; break;
 910         case OMAP_DSS_COLOR_RGB24P:
 911                 m = 0x9; break;
 912         case OMAP_DSS_COLOR_YUV2:
 913                 m = 0xa; break;
 914         case OMAP_DSS_COLOR_UYVY:
 915                 m = 0xb; break;
 916         case OMAP_DSS_COLOR_ARGB32:
 917                 m = 0xc; break;
 918         case OMAP_DSS_COLOR_RGBA32:
 919                 m = 0xd; break;
 920         case OMAP_DSS_COLOR_RGBX32:
 921                 m = 0xe; break;
 922         default:
 923                 BUG(); break;
 924         }
 925
 926         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 927 }
 928
 929 static void _dispc_set_channel_out(enum omap_plane plane,
 930                 enum omap_channel channel)
 931 {
 932         int shift;
 933         u32 val;
 934         int chan = 0, chan2 = 0;
 935
 936         switch (plane) {
 937         case OMAP_DSS_GFX:
 938                 shift = 8;
 939                 break;
 940         case OMAP_DSS_VIDEO1:
 941         case OMAP_DSS_VIDEO2:
 942                 shift = 16;
 943                 break;
 944         default:
 945                 BUG();
 946                 return;
 947         }
 948
 949         val = dispc_read_reg(dispc_reg_att[plane]);
 950         if (dss_has_feature(FEAT_MGR_LCD2)) {
 951                 switch (channel) {
 952                 case OMAP_DSS_CHANNEL_LCD:
 953                         chan = 0;
 954                         chan2 = 0;
 955                         break;
 956                 case OMAP_DSS_CHANNEL_DIGIT:
 957                         chan = 1;
 958                         chan2 = 0;
 959                         break;
 960                 case OMAP_DSS_CHANNEL_LCD2:
 961                         chan = 0;
 962                         chan2 = 1;
 963                         break;
 964                 default:
 965                         BUG();
 966                 }
 967
 968                 val = FLD_MOD(val, chan, shift, shift);
 969                 val = FLD_MOD(val, chan2, 31, 30);
 970         } else {
 971                 val = FLD_MOD(val, channel, shift, shift);
 972         }
 973         dispc_write_reg(dispc_reg_att[plane], val);
 974 }
 975
 976 void dispc_set_burst_size(enum omap_plane plane,
 977                 enum omap_burst_size burst_size)
 978 {
 979         int shift;
 980         u32 val;
 981
 982         enable_clocks(1);
 983
 984         switch (plane) {
 985         case OMAP_DSS_GFX:
 986                 shift = 6;
 987                 break;
 988         case OMAP_DSS_VIDEO1:
 989         case OMAP_DSS_VIDEO2:
 990                 shift = 14;
 991                 break;
 992         default:
 993                 BUG();
 994                 return;
 995         }
 996
 997         val = dispc_read_reg(dispc_reg_att[plane]);
 998         val = FLD_MOD(val, burst_size, shift+1, shift);
 999         dispc_write_reg(dispc_reg_att[plane], val);
1000
1001         enable_clocks(0);
1002 }
1003
1004 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1005 {
1006         u32 val;
1007
1008         BUG_ON(plane == OMAP_DSS_GFX);
1009
1010         val = dispc_read_reg(dispc_reg_att[plane]);
1011         val = FLD_MOD(val, enable, 9, 9);
1012         dispc_write_reg(dispc_reg_att[plane], val);
1013 }
1014
1015 void dispc_enable_replication(enum omap_plane plane, bool enable)
1016 {
1017         int bit;
1018
1019         if (plane == OMAP_DSS_GFX)
1020                 bit = 5;
1021         else
1022                 bit = 10;
1023
1024         enable_clocks(1);
1025         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1026         enable_clocks(0);
1027 }
1028
1029 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1030 {
1031         u32 val;
1032         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1033         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1034         enable_clocks(1);
1035         dispc_write_reg(DISPC_SIZE_LCD(channel), val);
1036         enable_clocks(0);
1037 }
1038
1039 void dispc_set_digit_size(u16 width, u16 height)
1040 {
1041         u32 val;
1042         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1043         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1044         enable_clocks(1);
1045         dispc_write_reg(DISPC_SIZE_DIG, val);
1046         enable_clocks(0);
1047 }
1048
1049 static void dispc_read_plane_fifo_sizes(void)
1050 {
1051         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1052                                       DISPC_VID_FIFO_SIZE_STATUS(0),
1053                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
1054         u32 size;
1055         int plane;
1056         u8 start, end;
1057
1058         enable_clocks(1);
1059
1060         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1061
1062         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1063                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
1064                 dispc.fifo_size[plane] = size;
1065         }
1066
1067         enable_clocks(0);
1068 }
1069
1070 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1071 {
1072         return dispc.fifo_size[plane];
1073 }
1074
1075 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1076 {
1077         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1078                                        DISPC_VID_FIFO_THRESHOLD(0),
1079                                        DISPC_VID_FIFO_THRESHOLD(1) };
1080         u8 hi_start, hi_end, lo_start, lo_end;
1081
1082         enable_clocks(1);
1083
1084         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1085                         plane,
1086                         REG_GET(ftrs_reg[plane], 11, 0),
1087                         REG_GET(ftrs_reg[plane], 27, 16),
1088                         low, high);
1089
1090         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1091         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1092
1093         dispc_write_reg(ftrs_reg[plane],
1094                         FLD_VAL(high, hi_start, hi_end) |
1095                         FLD_VAL(low, lo_start, lo_end));
1096
1097         enable_clocks(0);
1098 }
1099
1100 void dispc_enable_fifomerge(bool enable)
1101 {
1102         enable_clocks(1);
1103
1104         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1105         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1106
1107         enable_clocks(0);
1108 }
1109
1110 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1111 {
1112         u32 val;
1113         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1114                                       DISPC_VID_FIR(1) };
1115         u8 hinc_start, hinc_end, vinc_start, vinc_end;
1116
1117         BUG_ON(plane == OMAP_DSS_GFX);
1118
1119         dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1120         dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1121
1122         val = FLD_VAL(vinc, vinc_start, vinc_end) |
1123                         FLD_VAL(hinc, hinc_start, hinc_end);
1124
1125         dispc_write_reg(fir_reg[plane-1], val);
1126 }
1127
1128 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1129 {
1130         u32 val;
1131         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1132                                       DISPC_VID_ACCU0(1) };
1133         u8 hor_start, hor_end, vert_start, vert_end;
1134
1135         BUG_ON(plane == OMAP_DSS_GFX);
1136
1137         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1138         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1139
1140         val = FLD_VAL(vaccu, vert_start, vert_end) |
1141                         FLD_VAL(haccu, hor_start, hor_end);
1142
1143         dispc_write_reg(ac0_reg[plane-1], val);
1144 }
1145
1146 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1147 {
1148         u32 val;
1149         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1150                                       DISPC_VID_ACCU1(1) };
1151         u8 hor_start, hor_end, vert_start, vert_end;
1152
1153         BUG_ON(plane == OMAP_DSS_GFX);
1154
1155         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1156         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1157
1158         val = FLD_VAL(vaccu, vert_start, vert_end) |
1159                         FLD_VAL(haccu, hor_start, hor_end);
1160
1161         dispc_write_reg(ac1_reg[plane-1], val);
1162 }
1163
1164
1165 static void _dispc_set_scaling(enum omap_plane plane,
1166                 u16 orig_width, u16 orig_height,
1167                 u16 out_width, u16 out_height,
1168                 bool ilace, bool five_taps,
1169                 bool fieldmode)
1170 {
1171         int fir_hinc;
1172         int fir_vinc;
1173         int hscaleup, vscaleup;
1174         int accu0 = 0;
1175         int accu1 = 0;
1176         u32 l;
1177
1178         BUG_ON(plane == OMAP_DSS_GFX);
1179
1180         hscaleup = orig_width <= out_width;
1181         vscaleup = orig_height <= out_height;
1182
1183         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1184
1185         if (!orig_width || orig_width == out_width)
1186                 fir_hinc = 0;
1187         else
1188                 fir_hinc = 1024 * orig_width / out_width;
1189
1190         if (!orig_height || orig_height == out_height)
1191                 fir_vinc = 0;
1192         else
1193                 fir_vinc = 1024 * orig_height / out_height;
1194
1195         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1196
1197         l = dispc_read_reg(dispc_reg_att[plane]);
1198
1199         /* RESIZEENABLE and VERTICALTAPS */
1200         l &= ~((0x3 << 5) | (0x1 << 21));
1201         l |= fir_hinc ? (1 << 5) : 0;
1202         l |= fir_vinc ? (1 << 6) : 0;
1203         l |= five_taps ? (1 << 21) : 0;
1204
1205         /* VRESIZECONF and HRESIZECONF */
1206         if (dss_has_feature(FEAT_RESIZECONF)) {
1207                 l &= ~(0x3 << 7);
1208                 l |= hscaleup ? 0 : (1 << 7);
1209                 l |= vscaleup ? 0 : (1 << 8);
1210         }
1211
1212         /* LINEBUFFERSPLIT */
1213         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1214                 l &= ~(0x1 << 22);
1215                 l |= five_taps ? (1 << 22) : 0;
1216         }
1217
1218         dispc_write_reg(dispc_reg_att[plane], l);
1219
1220         /*
1221          * field 0 = even field = bottom field
1222          * field 1 = odd field = top field
1223          */
1224         if (ilace && !fieldmode) {
1225                 accu1 = 0;
1226                 accu0 = (fir_vinc / 2) & 0x3ff;
1227                 if (accu0 >= 1024/2) {
1228                         accu1 = 1024/2;
1229                         accu0 -= accu1;
1230                 }
1231         }
1232
1233         _dispc_set_vid_accu0(plane, 0, accu0);
1234         _dispc_set_vid_accu1(plane, 0, accu1);
1235 }
1236
1237 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1238                 bool mirroring, enum omap_color_mode color_mode)
1239 {
1240         bool row_repeat = false;
1241         int vidrot = 0;
1242
1243         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1244                         color_mode == OMAP_DSS_COLOR_UYVY) {
1245
1246                 if (mirroring) {
1247                         switch (rotation) {
1248                         case OMAP_DSS_ROT_0:
1249                                 vidrot = 2;
1250                                 break;
1251                         case OMAP_DSS_ROT_90:
1252                                 vidrot = 1;
1253                                 break;
1254                         case OMAP_DSS_ROT_180:
1255                                 vidrot = 0;
1256                                 break;
1257                         case OMAP_DSS_ROT_270:
1258                                 vidrot = 3;
1259                                 break;
1260                         }
1261                 } else {
1262                         switch (rotation) {
1263                         case OMAP_DSS_ROT_0:
1264                                 vidrot = 0;
1265                                 break;
1266                         case OMAP_DSS_ROT_90:
1267                                 vidrot = 1;
1268                                 break;
1269                         case OMAP_DSS_ROT_180:
1270                                 vidrot = 2;
1271                                 break;
1272                         case OMAP_DSS_ROT_270:
1273                                 vidrot = 3;
1274                                 break;
1275                         }
1276                 }
1277
1278                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1279                         row_repeat = true;
1280                 else
1281                         row_repeat = false;
1282         }
1283
1284         REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1285         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1286                 REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
1287 }
1288
1289 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1290 {
1291         switch (color_mode) {
1292         case OMAP_DSS_COLOR_CLUT1:
1293                 return 1;
1294         case OMAP_DSS_COLOR_CLUT2:
1295                 return 2;
1296         case OMAP_DSS_COLOR_CLUT4:
1297                 return 4;
1298         case OMAP_DSS_COLOR_CLUT8:
1299                 return 8;
1300         case OMAP_DSS_COLOR_RGB12U:
1301         case OMAP_DSS_COLOR_RGB16:
1302         case OMAP_DSS_COLOR_ARGB16:
1303         case OMAP_DSS_COLOR_YUV2:
1304         case OMAP_DSS_COLOR_UYVY:
1305                 return 16;
1306         case OMAP_DSS_COLOR_RGB24P:
1307                 return 24;
1308         case OMAP_DSS_COLOR_RGB24U:
1309         case OMAP_DSS_COLOR_ARGB32:
1310         case OMAP_DSS_COLOR_RGBA32:
1311         case OMAP_DSS_COLOR_RGBX32:
1312                 return 32;
1313         default:
1314                 BUG();
1315         }
1316 }
1317
1318 static s32 pixinc(int pixels, u8 ps)
1319 {
1320         if (pixels == 1)
1321                 return 1;
1322         else if (pixels > 1)
1323                 return 1 + (pixels - 1) * ps;
1324         else if (pixels < 0)
1325                 return 1 - (-pixels + 1) * ps;
1326         else
1327                 BUG();
1328 }
1329
1330 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1331                 u16 screen_width,
1332                 u16 width, u16 height,
1333                 enum omap_color_mode color_mode, bool fieldmode,
1334                 unsigned int field_offset,
1335                 unsigned *offset0, unsigned *offset1,
1336                 s32 *row_inc, s32 *pix_inc)
1337 {
1338         u8 ps;
1339
1340         /* FIXME CLUT formats */
1341         switch (color_mode) {
1342         case OMAP_DSS_COLOR_CLUT1:
1343         case OMAP_DSS_COLOR_CLUT2:
1344         case OMAP_DSS_COLOR_CLUT4:
1345         case OMAP_DSS_COLOR_CLUT8:
1346                 BUG();
1347                 return;
1348         case OMAP_DSS_COLOR_YUV2:
1349         case OMAP_DSS_COLOR_UYVY:
1350                 ps = 4;
1351                 break;
1352         default:
1353                 ps = color_mode_to_bpp(color_mode) / 8;
1354                 break;
1355         }
1356
1357         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1358                         width, height);
1359
1360         /*
1361          * field 0 = even field = bottom field
1362          * field 1 = odd field = top field
1363          */
1364         switch (rotation + mirror * 4) {
1365         case OMAP_DSS_ROT_0:
1366         case OMAP_DSS_ROT_180:
1367                 /*
1368                  * If the pixel format is YUV or UYVY divide the width
1369                  * of the image by 2 for 0 and 180 degree rotation.
1370                  */
1371                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1372                         color_mode == OMAP_DSS_COLOR_UYVY)
1373                         width = width >> 1;
1374         case OMAP_DSS_ROT_90:
1375         case OMAP_DSS_ROT_270:
1376                 *offset1 = 0;
1377                 if (field_offset)
1378                         *offset0 = field_offset * screen_width * ps;
1379                 else
1380                         *offset0 = 0;
1381
1382                 *row_inc = pixinc(1 + (screen_width - width) +
1383                                 (fieldmode ? screen_width : 0),
1384                                 ps);
1385                 *pix_inc = pixinc(1, ps);
1386                 break;
1387
1388         case OMAP_DSS_ROT_0 + 4:
1389         case OMAP_DSS_ROT_180 + 4:
1390                 /* If the pixel format is YUV or UYVY divide the width
1391                  * of the image by 2  for 0 degree and 180 degree
1392                  */
1393                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1394                         color_mode == OMAP_DSS_COLOR_UYVY)
1395                         width = width >> 1;
1396         case OMAP_DSS_ROT_90 + 4:
1397         case OMAP_DSS_ROT_270 + 4:
1398                 *offset1 = 0;
1399                 if (field_offset)
1400                         *offset0 = field_offset * screen_width * ps;
1401                 else
1402                         *offset0 = 0;
1403                 *row_inc = pixinc(1 - (screen_width + width) -
1404                                 (fieldmode ? screen_width : 0),
1405                                 ps);
1406                 *pix_inc = pixinc(1, ps);
1407                 break;
1408
1409         default:
1410                 BUG();
1411         }
1412 }
1413
1414 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1415                 u16 screen_width,
1416                 u16 width, u16 height,
1417                 enum omap_color_mode color_mode, bool fieldmode,
1418                 unsigned int field_offset,
1419                 unsigned *offset0, unsigned *offset1,
1420                 s32 *row_inc, s32 *pix_inc)
1421 {
1422         u8 ps;
1423         u16 fbw, fbh;
1424
1425         /* FIXME CLUT formats */
1426         switch (color_mode) {
1427         case OMAP_DSS_COLOR_CLUT1:
1428         case OMAP_DSS_COLOR_CLUT2:
1429         case OMAP_DSS_COLOR_CLUT4:
1430         case OMAP_DSS_COLOR_CLUT8:
1431                 BUG();
1432                 return;
1433         default:
1434                 ps = color_mode_to_bpp(color_mode) / 8;
1435                 break;
1436         }
1437
1438         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1439                         width, height);
1440
1441         /* width & height are overlay sizes, convert to fb sizes */
1442
1443         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1444                 fbw = width;
1445                 fbh = height;
1446         } else {
1447                 fbw = height;
1448                 fbh = width;
1449         }
1450
1451         /*
1452          * field 0 = even field = bottom field
1453          * field 1 = odd field = top field
1454          */
1455         switch (rotation + mirror * 4) {
1456         case OMAP_DSS_ROT_0:
1457                 *offset1 = 0;
1458                 if (field_offset)
1459                         *offset0 = *offset1 + field_offset * screen_width * ps;
1460                 else
1461                         *offset0 = *offset1;
1462                 *row_inc = pixinc(1 + (screen_width - fbw) +
1463                                 (fieldmode ? screen_width : 0),
1464                                 ps);
1465                 *pix_inc = pixinc(1, ps);
1466                 break;
1467         case OMAP_DSS_ROT_90:
1468                 *offset1 = screen_width * (fbh - 1) * ps;
1469                 if (field_offset)
1470                         *offset0 = *offset1 + field_offset * ps;
1471                 else
1472                         *offset0 = *offset1;
1473                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1474                                 (fieldmode ? 1 : 0), ps);
1475                 *pix_inc = pixinc(-screen_width, ps);
1476                 break;
1477         case OMAP_DSS_ROT_180:
1478                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1479                 if (field_offset)
1480                         *offset0 = *offset1 - field_offset * screen_width * ps;
1481                 else
1482                         *offset0 = *offset1;
1483                 *row_inc = pixinc(-1 -
1484                                 (screen_width - fbw) -
1485                                 (fieldmode ? screen_width : 0),
1486                                 ps);
1487                 *pix_inc = pixinc(-1, ps);
1488                 break;
1489         case OMAP_DSS_ROT_270:
1490                 *offset1 = (fbw - 1) * ps;
1491                 if (field_offset)
1492                         *offset0 = *offset1 - field_offset * ps;
1493                 else
1494                         *offset0 = *offset1;
1495                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1496                                 (fieldmode ? 1 : 0), ps);
1497                 *pix_inc = pixinc(screen_width, ps);
1498                 break;
1499
1500         /* mirroring */
1501         case OMAP_DSS_ROT_0 + 4:
1502                 *offset1 = (fbw - 1) * ps;
1503                 if (field_offset)
1504                         *offset0 = *offset1 + field_offset * screen_width * ps;
1505                 else
1506                         *offset0 = *offset1;
1507                 *row_inc = pixinc(screen_width * 2 - 1 +
1508                                 (fieldmode ? screen_width : 0),
1509                                 ps);
1510                 *pix_inc = pixinc(-1, ps);
1511                 break;
1512
1513         case OMAP_DSS_ROT_90 + 4:
1514                 *offset1 = 0;
1515                 if (field_offset)
1516                         *offset0 = *offset1 + field_offset * ps;
1517                 else
1518                         *offset0 = *offset1;
1519                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1520                                 (fieldmode ? 1 : 0),
1521                                 ps);
1522                 *pix_inc = pixinc(screen_width, ps);
1523                 break;
1524
1525         case OMAP_DSS_ROT_180 + 4:
1526                 *offset1 = screen_width * (fbh - 1) * ps;
1527                 if (field_offset)
1528                         *offset0 = *offset1 - field_offset * screen_width * ps;
1529                 else
1530                         *offset0 = *offset1;
1531                 *row_inc = pixinc(1 - screen_width * 2 -
1532                                 (fieldmode ? screen_width : 0),
1533                                 ps);
1534                 *pix_inc = pixinc(1, ps);
1535                 break;
1536
1537         case OMAP_DSS_ROT_270 + 4:
1538                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1539                 if (field_offset)
1540                         *offset0 = *offset1 - field_offset * ps;
1541                 else
1542                         *offset0 = *offset1;
1543                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1544                                 (fieldmode ? 1 : 0),
1545                                 ps);
1546                 *pix_inc = pixinc(-screen_width, ps);
1547                 break;
1548
1549         default:
1550                 BUG();
1551         }
1552 }
1553
1554 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1555                 u16 height, u16 out_width, u16 out_height,
1556                 enum omap_color_mode color_mode)
1557 {
1558         u32 fclk = 0;
1559         /* FIXME venc pclk? */
1560         u64 tmp, pclk = dispc_pclk_rate(channel);
1561
1562         if (height > out_height) {
1563                 /* FIXME get real display PPL */
1564                 unsigned int ppl = 800;
1565
1566                 tmp = pclk * height * out_width;
1567                 do_div(tmp, 2 * out_height * ppl);
1568                 fclk = tmp;
1569
1570                 if (height > 2 * out_height) {
1571                         if (ppl == out_width)
1572                                 return 0;
1573
1574                         tmp = pclk * (height - 2 * out_height) * out_width;
1575                         do_div(tmp, 2 * out_height * (ppl - out_width));
1576                         fclk = max(fclk, (u32) tmp);
1577                 }
1578         }
1579
1580         if (width > out_width) {
1581                 tmp = pclk * width;
1582                 do_div(tmp, out_width);
1583                 fclk = max(fclk, (u32) tmp);
1584
1585                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1586                         fclk <<= 1;
1587         }
1588
1589         return fclk;
1590 }
1591
1592 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1593                 u16 height, u16 out_width, u16 out_height)
1594 {
1595         unsigned int hf, vf;
1596
1597         /*
1598          * FIXME how to determine the 'A' factor
1599          * for the no downscaling case ?
1600          */
1601
1602         if (width > 3 * out_width)
1603                 hf = 4;
1604         else if (width > 2 * out_width)
1605                 hf = 3;
1606         else if (width > out_width)
1607                 hf = 2;
1608         else
1609                 hf = 1;
1610
1611         if (height > out_height)
1612                 vf = 2;
1613         else
1614                 vf = 1;
1615
1616         /* FIXME venc pclk? */
1617         return dispc_pclk_rate(channel) * vf * hf;
1618 }
1619
1620 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1621 {
1622         enable_clocks(1);
1623         _dispc_set_channel_out(plane, channel_out);
1624         enable_clocks(0);
1625 }
1626
1627 static int _dispc_setup_plane(enum omap_plane plane,
1628                 u32 paddr, u16 screen_width,
1629                 u16 pos_x, u16 pos_y,
1630                 u16 width, u16 height,
1631                 u16 out_width, u16 out_height,
1632                 enum omap_color_mode color_mode,
1633                 bool ilace,
1634                 enum omap_dss_rotation_type rotation_type,
1635                 u8 rotation, int mirror,
1636                 u8 global_alpha, u8 pre_mult_alpha,
1637                 enum omap_channel channel)
1638 {
1639         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1640         bool five_taps = 0;
1641         bool fieldmode = 0;
1642         int cconv = 0;
1643         unsigned offset0, offset1;
1644         s32 row_inc;
1645         s32 pix_inc;
1646         u16 frame_height = height;
1647         unsigned int field_offset = 0;
1648
1649         if (paddr == 0)
1650                 return -EINVAL;
1651
1652         if (ilace && height == out_height)
1653                 fieldmode = 1;
1654
1655         if (ilace) {
1656                 if (fieldmode)
1657                         height /= 2;
1658                 pos_y /= 2;
1659                 out_height /= 2;
1660
1661                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1662                                 "out_height %d\n",
1663                                 height, pos_y, out_height);
1664         }
1665
1666         if (!dss_feat_color_mode_supported(plane, color_mode))
1667                 return -EINVAL;
1668
1669         if (plane == OMAP_DSS_GFX) {
1670                 if (width != out_width || height != out_height)
1671                         return -EINVAL;
1672         } else {
1673                 /* video plane */
1674
1675                 unsigned long fclk = 0;
1676
1677                 if (out_width < width / maxdownscale ||
1678                    out_width > width * 8)
1679                         return -EINVAL;
1680
1681                 if (out_height < height / maxdownscale ||
1682                    out_height > height * 8)
1683                         return -EINVAL;
1684
1685                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1686                         color_mode == OMAP_DSS_COLOR_UYVY)
1687                         cconv = 1;
1688
1689                 /* Must use 5-tap filter? */
1690                 five_taps = height > out_height * 2;
1691
1692                 if (!five_taps) {
1693                         fclk = calc_fclk(channel, width, height, out_width,
1694                                         out_height);
1695
1696                         /* Try 5-tap filter if 3-tap fclk is too high */
1697                         if (cpu_is_omap34xx() && height > out_height &&
1698                                         fclk > dispc_fclk_rate())
1699                                 five_taps = true;
1700                 }
1701
1702                 if (width > (2048 >> five_taps)) {
1703                         DSSERR("failed to set up scaling, fclk too low\n");
1704                         return -EINVAL;
1705                 }
1706
1707                 if (five_taps)
1708                         fclk = calc_fclk_five_taps(channel, width, height,
1709                                         out_width, out_height, color_mode);
1710
1711                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1712                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1713
1714                 if (!fclk || fclk > dispc_fclk_rate()) {
1715                         DSSERR("failed to set up scaling, "
1716                                         "required fclk rate = %lu Hz, "
1717                                         "current fclk rate = %lu Hz\n",
1718                                         fclk, dispc_fclk_rate());
1719                         return -EINVAL;
1720                 }
1721         }
1722
1723         if (ilace && !fieldmode) {
1724                 /*
1725                  * when downscaling the bottom field may have to start several
1726                  * source lines below the top field. Unfortunately ACCUI
1727                  * registers will only hold the fractional part of the offset
1728                  * so the integer part must be added to the base address of the
1729                  * bottom field.
1730                  */
1731                 if (!height || height == out_height)
1732                         field_offset = 0;
1733                 else
1734                         field_offset = height / out_height / 2;
1735         }
1736
1737         /* Fields are independent but interleaved in memory. */
1738         if (fieldmode)
1739                 field_offset = 1;
1740
1741         if (rotation_type == OMAP_DSS_ROT_DMA)
1742                 calc_dma_rotation_offset(rotation, mirror,
1743                                 screen_width, width, frame_height, color_mode,
1744                                 fieldmode, field_offset,
1745                                 &offset0, &offset1, &row_inc, &pix_inc);
1746         else
1747                 calc_vrfb_rotation_offset(rotation, mirror,
1748                                 screen_width, width, frame_height, color_mode,
1749                                 fieldmode, field_offset,
1750                                 &offset0, &offset1, &row_inc, &pix_inc);
1751
1752         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1753                         offset0, offset1, row_inc, pix_inc);
1754
1755         _dispc_set_color_mode(plane, color_mode);
1756
1757         _dispc_set_plane_ba0(plane, paddr + offset0);
1758         _dispc_set_plane_ba1(plane, paddr + offset1);
1759
1760         _dispc_set_row_inc(plane, row_inc);
1761         _dispc_set_pix_inc(plane, pix_inc);
1762
1763         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1764                         out_width, out_height);
1765
1766         _dispc_set_plane_pos(plane, pos_x, pos_y);
1767
1768         _dispc_set_pic_size(plane, width, height);
1769
1770         if (plane != OMAP_DSS_GFX) {
1771                 _dispc_set_scaling(plane, width, height,
1772                                    out_width, out_height,
1773                                    ilace, five_taps, fieldmode);
1774                 _dispc_set_vid_size(plane, out_width, out_height);
1775                 _dispc_set_vid_color_conv(plane, cconv);
1776         }
1777
1778         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1779
1780         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1781         _dispc_setup_global_alpha(plane, global_alpha);
1782
1783         return 0;
1784 }
1785
1786 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1787 {
1788         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1789 }
1790
1791 static void dispc_disable_isr(void *data, u32 mask)
1792 {
1793         struct completion *compl = data;
1794         complete(compl);
1795 }
1796
1797 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1798 {
1799         if (channel == OMAP_DSS_CHANNEL_LCD2)
1800                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1801         else
1802                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1803 }
1804
1805 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1806 {
1807         struct completion frame_done_completion;
1808         bool is_on;
1809         int r;
1810         u32 irq;
1811
1812         enable_clocks(1);
1813
1814         /* When we disable LCD output, we need to wait until frame is done.
1815          * Otherwise the DSS is still working, and turning off the clocks
1816          * prevents DSS from going to OFF mode */
1817         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1818                         REG_GET(DISPC_CONTROL2, 0, 0) :
1819                         REG_GET(DISPC_CONTROL, 0, 0);
1820
1821         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1822                         DISPC_IRQ_FRAMEDONE;
1823
1824         if (!enable && is_on) {
1825                 init_completion(&frame_done_completion);
1826
1827                 r = omap_dispc_register_isr(dispc_disable_isr,
1828                                 &frame_done_completion, irq);
1829
1830                 if (r)
1831                         DSSERR("failed to register FRAMEDONE isr\n");
1832         }
1833
1834         _enable_lcd_out(channel, enable);
1835
1836         if (!enable && is_on) {
1837                 if (!wait_for_completion_timeout(&frame_done_completion,
1838                                         msecs_to_jiffies(100)))
1839                         DSSERR("timeout waiting for FRAME DONE\n");
1840
1841                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1842                                 &frame_done_completion, irq);
1843
1844                 if (r)
1845                         DSSERR("failed to unregister FRAMEDONE isr\n");
1846         }
1847
1848         enable_clocks(0);
1849 }
1850
1851 static void _enable_digit_out(bool enable)
1852 {
1853         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1854 }
1855
1856 static void dispc_enable_digit_out(bool enable)
1857 {
1858         struct completion frame_done_completion;
1859         int r;
1860
1861         enable_clocks(1);
1862
1863         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1864                 enable_clocks(0);
1865                 return;
1866         }
1867
1868         if (enable) {
1869                 unsigned long flags;
1870                 /* When we enable digit output, we'll get an extra digit
1871                  * sync lost interrupt, that we need to ignore */
1872                 spin_lock_irqsave(&dispc.irq_lock, flags);
1873                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1874                 _omap_dispc_set_irqs();
1875                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1876         }
1877
1878         /* When we disable digit output, we need to wait until fields are done.
1879          * Otherwise the DSS is still working, and turning off the clocks
1880          * prevents DSS from going to OFF mode. And when enabling, we need to
1881          * wait for the extra sync losts */
1882         init_completion(&frame_done_completion);
1883
1884         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1885                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1886         if (r)
1887                 DSSERR("failed to register EVSYNC isr\n");
1888
1889         _enable_digit_out(enable);
1890
1891         /* XXX I understand from TRM that we should only wait for the
1892          * current field to complete. But it seems we have to wait
1893          * for both fields */
1894         if (!wait_for_completion_timeout(&frame_done_completion,
1895                                 msecs_to_jiffies(100)))
1896                 DSSERR("timeout waiting for EVSYNC\n");
1897
1898         if (!wait_for_completion_timeout(&frame_done_completion,
1899                                 msecs_to_jiffies(100)))
1900                 DSSERR("timeout waiting for EVSYNC\n");
1901
1902         r = omap_dispc_unregister_isr(dispc_disable_isr,
1903                         &frame_done_completion,
1904                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1905         if (r)
1906                 DSSERR("failed to unregister EVSYNC isr\n");
1907
1908         if (enable) {
1909                 unsigned long flags;
1910                 spin_lock_irqsave(&dispc.irq_lock, flags);
1911                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1912                 if (dss_has_feature(FEAT_MGR_LCD2))
1913                         dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
1914                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1915                 _omap_dispc_set_irqs();
1916                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1917         }
1918
1919         enable_clocks(0);
1920 }
1921
1922 bool dispc_is_channel_enabled(enum omap_channel channel)
1923 {
1924         if (channel == OMAP_DSS_CHANNEL_LCD)
1925                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1926         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1927                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1928         else if (channel == OMAP_DSS_CHANNEL_LCD2)
1929                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
1930         else
1931                 BUG();
1932 }
1933
1934 void dispc_enable_channel(enum omap_channel channel, bool enable)
1935 {
1936         if (channel == OMAP_DSS_CHANNEL_LCD ||
1937                         channel == OMAP_DSS_CHANNEL_LCD2)
1938                 dispc_enable_lcd_out(channel, enable);
1939         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1940                 dispc_enable_digit_out(enable);
1941         else
1942                 BUG();
1943 }
1944
1945 void dispc_lcd_enable_signal_polarity(bool act_high)
1946 {
1947         if (!dss_has_feature(FEAT_LCDENABLEPOL))
1948                 return;
1949
1950         enable_clocks(1);
1951         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1952         enable_clocks(0);
1953 }
1954
1955 void dispc_lcd_enable_signal(bool enable)
1956 {
1957         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1958                 return;
1959
1960         enable_clocks(1);
1961         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1962         enable_clocks(0);
1963 }
1964
1965 void dispc_pck_free_enable(bool enable)
1966 {
1967         if (!dss_has_feature(FEAT_PCKFREEENABLE))
1968                 return;
1969
1970         enable_clocks(1);
1971         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1972         enable_clocks(0);
1973 }
1974
1975 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
1976 {
1977         enable_clocks(1);
1978         if (channel == OMAP_DSS_CHANNEL_LCD2)
1979                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1980         else
1981                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1982         enable_clocks(0);
1983 }
1984
1985
1986 void dispc_set_lcd_display_type(enum omap_channel channel,
1987                 enum omap_lcd_display_type type)
1988 {
1989         int mode;
1990
1991         switch (type) {
1992         case OMAP_DSS_LCD_DISPLAY_STN:
1993                 mode = 0;
1994                 break;
1995
1996         case OMAP_DSS_LCD_DISPLAY_TFT:
1997                 mode = 1;
1998                 break;
1999
2000         default:
2001                 BUG();
2002                 return;
2003         }
2004
2005         enable_clocks(1);
2006         if (channel == OMAP_DSS_CHANNEL_LCD2)
2007                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2008         else
2009                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2010         enable_clocks(0);
2011 }
2012
2013 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2014 {
2015         enable_clocks(1);
2016         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2017         enable_clocks(0);
2018 }
2019
2020
2021 void dispc_set_default_color(enum omap_channel channel, u32 color)
2022 {
2023         enable_clocks(1);
2024         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2025         enable_clocks(0);
2026 }
2027
2028 u32 dispc_get_default_color(enum omap_channel channel)
2029 {
2030         u32 l;
2031
2032         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2033                 channel != OMAP_DSS_CHANNEL_LCD &&
2034                 channel != OMAP_DSS_CHANNEL_LCD2);
2035
2036         enable_clocks(1);
2037         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2038         enable_clocks(0);
2039
2040         return l;
2041 }
2042
2043 void dispc_set_trans_key(enum omap_channel ch,
2044                 enum omap_dss_trans_key_type type,
2045                 u32 trans_key)
2046 {
2047         enable_clocks(1);
2048         if (ch == OMAP_DSS_CHANNEL_LCD)
2049                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2050         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2051                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2052         else /* OMAP_DSS_CHANNEL_LCD2 */
2053                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2054
2055         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2056         enable_clocks(0);
2057 }
2058
2059 void dispc_get_trans_key(enum omap_channel ch,
2060                 enum omap_dss_trans_key_type *type,
2061                 u32 *trans_key)
2062 {
2063         enable_clocks(1);
2064         if (type) {
2065                 if (ch == OMAP_DSS_CHANNEL_LCD)
2066                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2067                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2068                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2069                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2070                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2071                 else
2072                         BUG();
2073         }
2074
2075         if (trans_key)
2076                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2077         enable_clocks(0);
2078 }
2079
2080 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2081 {
2082         enable_clocks(1);
2083         if (ch == OMAP_DSS_CHANNEL_LCD)
2084                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2085         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2086                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2087         else /* OMAP_DSS_CHANNEL_LCD2 */
2088                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2089         enable_clocks(0);
2090 }
2091 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2092 {
2093         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2094                 return;
2095
2096         enable_clocks(1);
2097         if (ch == OMAP_DSS_CHANNEL_LCD)
2098                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2099         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2100                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2101         else /* OMAP_DSS_CHANNEL_LCD2 */
2102                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2103         enable_clocks(0);
2104 }
2105 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2106 {
2107         bool enabled;
2108
2109         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2110                 return false;
2111
2112         enable_clocks(1);
2113         if (ch == OMAP_DSS_CHANNEL_LCD)
2114                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2115         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2116                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2117         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2118                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2119         else
2120                 BUG();
2121         enable_clocks(0);
2122
2123         return enabled;
2124 }
2125
2126
2127 bool dispc_trans_key_enabled(enum omap_channel ch)
2128 {
2129         bool enabled;
2130
2131         enable_clocks(1);
2132         if (ch == OMAP_DSS_CHANNEL_LCD)
2133                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2134         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2135                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2136         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2137                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2138         else
2139                 BUG();
2140         enable_clocks(0);
2141
2142         return enabled;
2143 }
2144
2145
2146 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2147 {
2148         int code;
2149
2150         switch (data_lines) {
2151         case 12:
2152                 code = 0;
2153                 break;
2154         case 16:
2155                 code = 1;
2156                 break;
2157         case 18:
2158                 code = 2;
2159                 break;
2160         case 24:
2161                 code = 3;
2162                 break;
2163         default:
2164                 BUG();
2165                 return;
2166         }
2167
2168         enable_clocks(1);
2169         if (channel == OMAP_DSS_CHANNEL_LCD2)
2170                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2171         else
2172                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2173         enable_clocks(0);
2174 }
2175
2176 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2177                 enum omap_parallel_interface_mode mode)
2178 {
2179         u32 l;
2180         int stallmode;
2181         int gpout0 = 1;
2182         int gpout1;
2183
2184         switch (mode) {
2185         case OMAP_DSS_PARALLELMODE_BYPASS:
2186                 stallmode = 0;
2187                 gpout1 = 1;
2188                 break;
2189
2190         case OMAP_DSS_PARALLELMODE_RFBI:
2191                 stallmode = 1;
2192                 gpout1 = 0;
2193                 break;
2194
2195         case OMAP_DSS_PARALLELMODE_DSI:
2196                 stallmode = 1;
2197                 gpout1 = 1;
2198                 break;
2199
2200         default:
2201                 BUG();
2202                 return;
2203         }
2204
2205         enable_clocks(1);
2206
2207         if (channel == OMAP_DSS_CHANNEL_LCD2) {
2208                 l = dispc_read_reg(DISPC_CONTROL2);
2209                 l = FLD_MOD(l, stallmode, 11, 11);
2210                 dispc_write_reg(DISPC_CONTROL2, l);
2211         } else {
2212                 l = dispc_read_reg(DISPC_CONTROL);
2213                 l = FLD_MOD(l, stallmode, 11, 11);
2214                 l = FLD_MOD(l, gpout0, 15, 15);
2215                 l = FLD_MOD(l, gpout1, 16, 16);
2216                 dispc_write_reg(DISPC_CONTROL, l);
2217         }
2218
2219         enable_clocks(0);
2220 }
2221
2222 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2223                 int vsw, int vfp, int vbp)
2224 {
2225         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2226                 if (hsw < 1 || hsw > 64 ||
2227                                 hfp < 1 || hfp > 256 ||
2228                                 hbp < 1 || hbp > 256 ||
2229                                 vsw < 1 || vsw > 64 ||
2230                                 vfp < 0 || vfp > 255 ||
2231                                 vbp < 0 || vbp > 255)
2232                         return false;
2233         } else {
2234                 if (hsw < 1 || hsw > 256 ||
2235                                 hfp < 1 || hfp > 4096 ||
2236                                 hbp < 1 || hbp > 4096 ||
2237                                 vsw < 1 || vsw > 256 ||
2238                                 vfp < 0 || vfp > 4095 ||
2239                                 vbp < 0 || vbp > 4095)
2240                         return false;
2241         }
2242
2243         return true;
2244 }
2245
2246 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2247 {
2248         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2249                         timings->hbp, timings->vsw,
2250                         timings->vfp, timings->vbp);
2251 }
2252
2253 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2254                 int hfp, int hbp, int vsw, int vfp, int vbp)
2255 {
2256         u32 timing_h, timing_v;
2257
2258         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2259                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2260                         FLD_VAL(hbp-1, 27, 20);
2261
2262                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2263                         FLD_VAL(vbp, 27, 20);
2264         } else {
2265                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2266                         FLD_VAL(hbp-1, 31, 20);
2267
2268                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2269                         FLD_VAL(vbp, 31, 20);
2270         }
2271
2272         enable_clocks(1);
2273         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2274         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2275         enable_clocks(0);
2276 }
2277
2278 /* change name to mode? */
2279 void dispc_set_lcd_timings(enum omap_channel channel,
2280                 struct omap_video_timings *timings)
2281 {
2282         unsigned xtot, ytot;
2283         unsigned long ht, vt;
2284
2285         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2286                                 timings->hbp, timings->vsw,
2287                                 timings->vfp, timings->vbp))
2288                 BUG();
2289
2290         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2291                         timings->hbp, timings->vsw, timings->vfp,
2292                         timings->vbp);
2293
2294         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2295
2296         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2297         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2298
2299         ht = (timings->pixel_clock * 1000) / xtot;
2300         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2301
2302         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2303                         timings->y_res);
2304         DSSDBG("pck %u\n", timings->pixel_clock);
2305         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2306                         timings->hsw, timings->hfp, timings->hbp,
2307                         timings->vsw, timings->vfp, timings->vbp);
2308
2309         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2310 }
2311
2312 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2313                 u16 pck_div)
2314 {
2315         BUG_ON(lck_div < 1);
2316         BUG_ON(pck_div < 2);
2317
2318         enable_clocks(1);
2319         dispc_write_reg(DISPC_DIVISOR(channel),
2320                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2321         enable_clocks(0);
2322 }
2323
2324 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2325                 int *pck_div)
2326 {
2327         u32 l;
2328         l = dispc_read_reg(DISPC_DIVISOR(channel));
2329         *lck_div = FLD_GET(l, 23, 16);
2330         *pck_div = FLD_GET(l, 7, 0);
2331 }
2332
2333 unsigned long dispc_fclk_rate(void)
2334 {
2335         unsigned long r = 0;
2336
2337         if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK)
2338                 r = dss_clk_get_rate(DSS_CLK_FCK);
2339         else
2340 #ifdef CONFIG_OMAP2_DSS_DSI
2341                 r = dsi_get_dsi1_pll_rate();
2342 #else
2343         BUG();
2344 #endif
2345         return r;
2346 }
2347
2348 unsigned long dispc_lclk_rate(enum omap_channel channel)
2349 {
2350         int lcd;
2351         unsigned long r;
2352         u32 l;
2353
2354         l = dispc_read_reg(DISPC_DIVISOR(channel));
2355
2356         lcd = FLD_GET(l, 23, 16);
2357
2358         r = dispc_fclk_rate();
2359
2360         return r / lcd;
2361 }
2362
2363 unsigned long dispc_pclk_rate(enum omap_channel channel)
2364 {
2365         int lcd, pcd;
2366         unsigned long r;
2367         u32 l;
2368
2369         l = dispc_read_reg(DISPC_DIVISOR(channel));
2370
2371         lcd = FLD_GET(l, 23, 16);
2372         pcd = FLD_GET(l, 7, 0);
2373
2374         r = dispc_fclk_rate();
2375
2376         return r / lcd / pcd;
2377 }
2378
2379 void dispc_dump_clocks(struct seq_file *s)
2380 {
2381         int lcd, pcd;
2382         enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2383
2384         enable_clocks(1);
2385
2386         seq_printf(s, "- DISPC -\n");
2387
2388         seq_printf(s, "dispc fclk source = %s (%s)\n",
2389                         dss_get_generic_clk_source_name(dispc_clk_src),
2390                         dss_feat_get_clk_source_name(dispc_clk_src));
2391
2392         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2393
2394         seq_printf(s, "- LCD1 -\n");
2395
2396         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2397
2398         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2399                         dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2400         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2401                         dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2402         if (dss_has_feature(FEAT_MGR_LCD2)) {
2403                 seq_printf(s, "- LCD2 -\n");
2404
2405                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2406
2407                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2408                                 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2409                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2410                                 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2411         }
2412         enable_clocks(0);
2413 }
2414
2415 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2416 void dispc_dump_irqs(struct seq_file *s)
2417 {
2418         unsigned long flags;
2419         struct dispc_irq_stats stats;
2420
2421         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2422
2423         stats = dispc.irq_stats;
2424         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2425         dispc.irq_stats.last_reset = jiffies;
2426
2427         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2428
2429         seq_printf(s, "period %u ms\n",
2430                         jiffies_to_msecs(jiffies - stats.last_reset));
2431
2432         seq_printf(s, "irqs %d\n", stats.irq_count);
2433 #define PIS(x) \
2434         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2435
2436         PIS(FRAMEDONE);
2437         PIS(VSYNC);
2438         PIS(EVSYNC_EVEN);
2439         PIS(EVSYNC_ODD);
2440         PIS(ACBIAS_COUNT_STAT);
2441         PIS(PROG_LINE_NUM);
2442         PIS(GFX_FIFO_UNDERFLOW);
2443         PIS(GFX_END_WIN);
2444         PIS(PAL_GAMMA_MASK);
2445         PIS(OCP_ERR);
2446         PIS(VID1_FIFO_UNDERFLOW);
2447         PIS(VID1_END_WIN);
2448         PIS(VID2_FIFO_UNDERFLOW);
2449         PIS(VID2_END_WIN);
2450         PIS(SYNC_LOST);
2451         PIS(SYNC_LOST_DIGIT);
2452         PIS(WAKEUP);
2453         if (dss_has_feature(FEAT_MGR_LCD2)) {
2454                 PIS(FRAMEDONE2);
2455                 PIS(VSYNC2);
2456                 PIS(ACBIAS_COUNT_STAT2);
2457                 PIS(SYNC_LOST2);
2458         }
2459 #undef PIS
2460 }
2461 #endif
2462
2463 void dispc_dump_regs(struct seq_file *s)
2464 {
2465 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2466
2467         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
2468
2469         DUMPREG(DISPC_REVISION);
2470         DUMPREG(DISPC_SYSCONFIG);
2471         DUMPREG(DISPC_SYSSTATUS);
2472         DUMPREG(DISPC_IRQSTATUS);
2473         DUMPREG(DISPC_IRQENABLE);
2474         DUMPREG(DISPC_CONTROL);
2475         DUMPREG(DISPC_CONFIG);
2476         DUMPREG(DISPC_CAPABLE);
2477         DUMPREG(DISPC_DEFAULT_COLOR(0));
2478         DUMPREG(DISPC_DEFAULT_COLOR(1));
2479         DUMPREG(DISPC_TRANS_COLOR(0));
2480         DUMPREG(DISPC_TRANS_COLOR(1));
2481         DUMPREG(DISPC_LINE_STATUS);
2482         DUMPREG(DISPC_LINE_NUMBER);
2483         DUMPREG(DISPC_TIMING_H(0));
2484         DUMPREG(DISPC_TIMING_V(0));
2485         DUMPREG(DISPC_POL_FREQ(0));
2486         DUMPREG(DISPC_DIVISOR(0));
2487         DUMPREG(DISPC_GLOBAL_ALPHA);
2488         DUMPREG(DISPC_SIZE_DIG);
2489         DUMPREG(DISPC_SIZE_LCD(0));
2490         if (dss_has_feature(FEAT_MGR_LCD2)) {
2491                 DUMPREG(DISPC_CONTROL2);
2492                 DUMPREG(DISPC_CONFIG2);
2493                 DUMPREG(DISPC_DEFAULT_COLOR(2));
2494                 DUMPREG(DISPC_TRANS_COLOR(2));
2495                 DUMPREG(DISPC_TIMING_H(2));
2496                 DUMPREG(DISPC_TIMING_V(2));
2497                 DUMPREG(DISPC_POL_FREQ(2));
2498                 DUMPREG(DISPC_DIVISOR(2));
2499                 DUMPREG(DISPC_SIZE_LCD(2));
2500         }
2501
2502         DUMPREG(DISPC_GFX_BA0);
2503         DUMPREG(DISPC_GFX_BA1);
2504         DUMPREG(DISPC_GFX_POSITION);
2505         DUMPREG(DISPC_GFX_SIZE);
2506         DUMPREG(DISPC_GFX_ATTRIBUTES);
2507         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2508         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2509         DUMPREG(DISPC_GFX_ROW_INC);
2510         DUMPREG(DISPC_GFX_PIXEL_INC);
2511         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2512         DUMPREG(DISPC_GFX_TABLE_BA);
2513
2514         DUMPREG(DISPC_DATA_CYCLE1(0));
2515         DUMPREG(DISPC_DATA_CYCLE2(0));
2516         DUMPREG(DISPC_DATA_CYCLE3(0));
2517
2518         DUMPREG(DISPC_CPR_COEF_R(0));
2519         DUMPREG(DISPC_CPR_COEF_G(0));
2520         DUMPREG(DISPC_CPR_COEF_B(0));
2521         if (dss_has_feature(FEAT_MGR_LCD2)) {
2522                 DUMPREG(DISPC_DATA_CYCLE1(2));
2523                 DUMPREG(DISPC_DATA_CYCLE2(2));
2524                 DUMPREG(DISPC_DATA_CYCLE3(2));
2525
2526                 DUMPREG(DISPC_CPR_COEF_R(2));
2527                 DUMPREG(DISPC_CPR_COEF_G(2));
2528                 DUMPREG(DISPC_CPR_COEF_B(2));
2529         }
2530
2531         DUMPREG(DISPC_GFX_PRELOAD);
2532
2533         DUMPREG(DISPC_VID_BA0(0));
2534         DUMPREG(DISPC_VID_BA1(0));
2535         DUMPREG(DISPC_VID_POSITION(0));
2536         DUMPREG(DISPC_VID_SIZE(0));
2537         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2538         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2539         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2540         DUMPREG(DISPC_VID_ROW_INC(0));
2541         DUMPREG(DISPC_VID_PIXEL_INC(0));
2542         DUMPREG(DISPC_VID_FIR(0));
2543         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2544         DUMPREG(DISPC_VID_ACCU0(0));
2545         DUMPREG(DISPC_VID_ACCU1(0));
2546
2547         DUMPREG(DISPC_VID_BA0(1));
2548         DUMPREG(DISPC_VID_BA1(1));
2549         DUMPREG(DISPC_VID_POSITION(1));
2550         DUMPREG(DISPC_VID_SIZE(1));
2551         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2552         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2553         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2554         DUMPREG(DISPC_VID_ROW_INC(1));
2555         DUMPREG(DISPC_VID_PIXEL_INC(1));
2556         DUMPREG(DISPC_VID_FIR(1));
2557         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2558         DUMPREG(DISPC_VID_ACCU0(1));
2559         DUMPREG(DISPC_VID_ACCU1(1));
2560
2561         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2562         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2563         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2564         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2565         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2566         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2567         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2568         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2569         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2570         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2571         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2572         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2573         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2574         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2575         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2576         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2577         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2578         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2579         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2580         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2581         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2582         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2583         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2584         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2585         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2586         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2587         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2588         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2589         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2590
2591         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2592         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2593         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2594         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2595         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2596         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2597         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2598         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2599         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2600         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2601         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2602         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2603         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2604         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2605         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2606         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2607         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2608         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2609         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2610         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2611         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2612         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2613         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2614         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2615         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2616         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2617         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2618         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2619         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2620
2621         DUMPREG(DISPC_VID_PRELOAD(0));
2622         DUMPREG(DISPC_VID_PRELOAD(1));
2623
2624         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
2625 #undef DUMPREG
2626 }
2627
2628 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2629                 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2630 {
2631         u32 l = 0;
2632
2633         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2634                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2635
2636         l |= FLD_VAL(onoff, 17, 17);
2637         l |= FLD_VAL(rf, 16, 16);
2638         l |= FLD_VAL(ieo, 15, 15);
2639         l |= FLD_VAL(ipc, 14, 14);
2640         l |= FLD_VAL(ihs, 13, 13);
2641         l |= FLD_VAL(ivs, 12, 12);
2642         l |= FLD_VAL(acbi, 11, 8);
2643         l |= FLD_VAL(acb, 7, 0);
2644
2645         enable_clocks(1);
2646         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2647         enable_clocks(0);
2648 }
2649
2650 void dispc_set_pol_freq(enum omap_channel channel,
2651                 enum omap_panel_config config, u8 acbi, u8 acb)
2652 {
2653         _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2654                         (config & OMAP_DSS_LCD_RF) != 0,
2655                         (config & OMAP_DSS_LCD_IEO) != 0,
2656                         (config & OMAP_DSS_LCD_IPC) != 0,
2657                         (config & OMAP_DSS_LCD_IHS) != 0,
2658                         (config & OMAP_DSS_LCD_IVS) != 0,
2659                         acbi, acb);
2660 }
2661
2662 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2663 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2664                 struct dispc_clock_info *cinfo)
2665 {
2666         u16 pcd_min = is_tft ? 2 : 3;
2667         unsigned long best_pck;
2668         u16 best_ld, cur_ld;
2669         u16 best_pd, cur_pd;
2670
2671         best_pck = 0;
2672         best_ld = 0;
2673         best_pd = 0;
2674
2675         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2676                 unsigned long lck = fck / cur_ld;
2677
2678                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2679                         unsigned long pck = lck / cur_pd;
2680                         long old_delta = abs(best_pck - req_pck);
2681                         long new_delta = abs(pck - req_pck);
2682
2683                         if (best_pck == 0 || new_delta < old_delta) {
2684                                 best_pck = pck;
2685                                 best_ld = cur_ld;
2686                                 best_pd = cur_pd;
2687
2688                                 if (pck == req_pck)
2689                                         goto found;
2690                         }
2691
2692                         if (pck < req_pck)
2693                                 break;
2694                 }
2695
2696                 if (lck / pcd_min < req_pck)
2697                         break;
2698         }
2699
2700 found:
2701         cinfo->lck_div = best_ld;
2702         cinfo->pck_div = best_pd;
2703         cinfo->lck = fck / cinfo->lck_div;
2704         cinfo->pck = cinfo->lck / cinfo->pck_div;
2705 }
2706
2707 /* calculate clock rates using dividers in cinfo */
2708 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2709                 struct dispc_clock_info *cinfo)
2710 {
2711         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2712                 return -EINVAL;
2713         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2714                 return -EINVAL;
2715
2716         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2717         cinfo->pck = cinfo->lck / cinfo->pck_div;
2718
2719         return 0;
2720 }
2721
2722 int dispc_set_clock_div(enum omap_channel channel,
2723                 struct dispc_clock_info *cinfo)
2724 {
2725         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2726         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2727
2728         dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2729
2730         return 0;
2731 }
2732
2733 int dispc_get_clock_div(enum omap_channel channel,
2734                 struct dispc_clock_info *cinfo)
2735 {
2736         unsigned long fck;
2737
2738         fck = dispc_fclk_rate();
2739
2740         cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
2741         cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
2742
2743         cinfo->lck = fck / cinfo->lck_div;
2744         cinfo->pck = cinfo->lck / cinfo->pck_div;
2745
2746         return 0;
2747 }
2748
2749 /* dispc.irq_lock has to be locked by the caller */
2750 static void _omap_dispc_set_irqs(void)
2751 {
2752         u32 mask;
2753         u32 old_mask;
2754         int i;
2755         struct omap_dispc_isr_data *isr_data;
2756
2757         mask = dispc.irq_error_mask;
2758
2759         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2760                 isr_data = &dispc.registered_isr[i];
2761
2762                 if (isr_data->isr == NULL)
2763                         continue;
2764
2765                 mask |= isr_data->mask;
2766         }
2767
2768         enable_clocks(1);
2769
2770         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2771         /* clear the irqstatus for newly enabled irqs */
2772         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2773
2774         dispc_write_reg(DISPC_IRQENABLE, mask);
2775
2776         enable_clocks(0);
2777 }
2778
2779 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2780 {
2781         int i;
2782         int ret;
2783         unsigned long flags;
2784         struct omap_dispc_isr_data *isr_data;
2785
2786         if (isr == NULL)
2787                 return -EINVAL;
2788
2789         spin_lock_irqsave(&dispc.irq_lock, flags);
2790
2791         /* check for duplicate entry */
2792         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2793                 isr_data = &dispc.registered_isr[i];
2794                 if (isr_data->isr == isr && isr_data->arg == arg &&
2795                                 isr_data->mask == mask) {
2796                         ret = -EINVAL;
2797                         goto err;
2798                 }
2799         }
2800
2801         isr_data = NULL;
2802         ret = -EBUSY;
2803
2804         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2805                 isr_data = &dispc.registered_isr[i];
2806
2807                 if (isr_data->isr != NULL)
2808                         continue;
2809
2810                 isr_data->isr = isr;
2811                 isr_data->arg = arg;
2812                 isr_data->mask = mask;
2813                 ret = 0;
2814
2815                 break;
2816         }
2817
2818         _omap_dispc_set_irqs();
2819
2820         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2821
2822         return 0;
2823 err:
2824         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2825
2826         return ret;
2827 }
2828 EXPORT_SYMBOL(omap_dispc_register_isr);
2829
2830 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2831 {
2832         int i;
2833         unsigned long flags;
2834         int ret = -EINVAL;
2835         struct omap_dispc_isr_data *isr_data;
2836
2837         spin_lock_irqsave(&dispc.irq_lock, flags);
2838
2839         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2840                 isr_data = &dispc.registered_isr[i];
2841                 if (isr_data->isr != isr || isr_data->arg != arg ||
2842                                 isr_data->mask != mask)
2843                         continue;
2844
2845                 /* found the correct isr */
2846
2847                 isr_data->isr = NULL;
2848                 isr_data->arg = NULL;
2849                 isr_data->mask = 0;
2850
2851                 ret = 0;
2852                 break;
2853         }
2854
2855         if (ret == 0)
2856                 _omap_dispc_set_irqs();
2857
2858         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2859
2860         return ret;
2861 }
2862 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2863
2864 #ifdef DEBUG
2865 static void print_irq_status(u32 status)
2866 {
2867         if ((status & dispc.irq_error_mask) == 0)
2868                 return;
2869
2870         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2871
2872 #define PIS(x) \
2873         if (status & DISPC_IRQ_##x) \
2874                 printk(#x " ");
2875         PIS(GFX_FIFO_UNDERFLOW);
2876         PIS(OCP_ERR);
2877         PIS(VID1_FIFO_UNDERFLOW);
2878         PIS(VID2_FIFO_UNDERFLOW);
2879         PIS(SYNC_LOST);
2880         PIS(SYNC_LOST_DIGIT);
2881         if (dss_has_feature(FEAT_MGR_LCD2))
2882                 PIS(SYNC_LOST2);
2883 #undef PIS
2884
2885         printk("\n");
2886 }
2887 #endif
2888
2889 /* Called from dss.c. Note that we don't touch clocks here,
2890  * but we presume they are on because we got an IRQ. However,
2891  * an irq handler may turn the clocks off, so we may not have
2892  * clock later in the function. */
2893 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2894 {
2895         int i;
2896         u32 irqstatus, irqenable;
2897         u32 handledirqs = 0;
2898         u32 unhandled_errors;
2899         struct omap_dispc_isr_data *isr_data;
2900         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2901
2902         spin_lock(&dispc.irq_lock);
2903
2904         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2905         irqenable = dispc_read_reg(DISPC_IRQENABLE);
2906
2907         /* IRQ is not for us */
2908         if (!(irqstatus & irqenable)) {
2909                 spin_unlock(&dispc.irq_lock);
2910                 return IRQ_NONE;
2911         }
2912
2913 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2914         spin_lock(&dispc.irq_stats_lock);
2915         dispc.irq_stats.irq_count++;
2916         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2917         spin_unlock(&dispc.irq_stats_lock);
2918 #endif
2919
2920 #ifdef DEBUG
2921         if (dss_debug)
2922                 print_irq_status(irqstatus);
2923 #endif
2924         /* Ack the interrupt. Do it here before clocks are possibly turned
2925          * off */
2926         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2927         /* flush posted write */
2928         dispc_read_reg(DISPC_IRQSTATUS);
2929
2930         /* make a copy and unlock, so that isrs can unregister
2931          * themselves */
2932         memcpy(registered_isr, dispc.registered_isr,
2933                         sizeof(registered_isr));
2934
2935         spin_unlock(&dispc.irq_lock);
2936
2937         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2938                 isr_data = &registered_isr[i];
2939
2940                 if (!isr_data->isr)
2941                         continue;
2942
2943                 if (isr_data->mask & irqstatus) {
2944                         isr_data->isr(isr_data->arg, irqstatus);
2945                         handledirqs |= isr_data->mask;
2946                 }
2947         }
2948
2949         spin_lock(&dispc.irq_lock);
2950
2951         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2952
2953         if (unhandled_errors) {
2954                 dispc.error_irqs |= unhandled_errors;
2955
2956                 dispc.irq_error_mask &= ~unhandled_errors;
2957                 _omap_dispc_set_irqs();
2958
2959                 schedule_work(&dispc.error_work);
2960         }
2961
2962         spin_unlock(&dispc.irq_lock);
2963
2964         return IRQ_HANDLED;
2965 }
2966
2967 static void dispc_error_worker(struct work_struct *work)
2968 {
2969         int i;
2970         u32 errors;
2971         unsigned long flags;
2972
2973         spin_lock_irqsave(&dispc.irq_lock, flags);
2974         errors = dispc.error_irqs;
2975         dispc.error_irqs = 0;
2976         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2977
2978         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2979                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2980                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2981                         struct omap_overlay *ovl;
2982                         ovl = omap_dss_get_overlay(i);
2983
2984                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2985                                 continue;
2986
2987                         if (ovl->id == 0) {
2988                                 dispc_enable_plane(ovl->id, 0);
2989                                 dispc_go(ovl->manager->id);
2990                                 mdelay(50);
2991                                 break;
2992                         }
2993                 }
2994         }
2995
2996         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2997                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2998                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2999                         struct omap_overlay *ovl;
3000                         ovl = omap_dss_get_overlay(i);
3001
3002                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3003                                 continue;
3004
3005                         if (ovl->id == 1) {
3006                                 dispc_enable_plane(ovl->id, 0);
3007                                 dispc_go(ovl->manager->id);
3008                                 mdelay(50);
3009                                 break;
3010                         }
3011                 }
3012         }
3013
3014         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3015                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3016                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3017                         struct omap_overlay *ovl;
3018                         ovl = omap_dss_get_overlay(i);
3019
3020                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3021                                 continue;
3022
3023                         if (ovl->id == 2) {
3024                                 dispc_enable_plane(ovl->id, 0);
3025                                 dispc_go(ovl->manager->id);
3026                                 mdelay(50);
3027                                 break;
3028                         }
3029                 }
3030         }
3031
3032         if (errors & DISPC_IRQ_SYNC_LOST) {
3033                 struct omap_overlay_manager *manager = NULL;
3034                 bool enable = false;
3035
3036                 DSSERR("SYNC_LOST, disabling LCD\n");
3037
3038                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3039                         struct omap_overlay_manager *mgr;
3040                         mgr = omap_dss_get_overlay_manager(i);
3041
3042                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3043                                 manager = mgr;
3044                                 enable = mgr->device->state ==
3045                                                 OMAP_DSS_DISPLAY_ACTIVE;
3046                                 mgr->device->driver->disable(mgr->device);
3047                                 break;
3048                         }
3049                 }
3050
3051                 if (manager) {
3052                         struct omap_dss_device *dssdev = manager->device;
3053                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3054                                 struct omap_overlay *ovl;
3055                                 ovl = omap_dss_get_overlay(i);
3056
3057                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3058                                         continue;
3059
3060                                 if (ovl->id != 0 && ovl->manager == manager)
3061                                         dispc_enable_plane(ovl->id, 0);
3062                         }
3063
3064                         dispc_go(manager->id);
3065                         mdelay(50);
3066                         if (enable)
3067                                 dssdev->driver->enable(dssdev);
3068                 }
3069         }
3070
3071         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3072                 struct omap_overlay_manager *manager = NULL;
3073                 bool enable = false;
3074
3075                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3076
3077                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3078                         struct omap_overlay_manager *mgr;
3079                         mgr = omap_dss_get_overlay_manager(i);
3080
3081                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3082                                 manager = mgr;
3083                                 enable = mgr->device->state ==
3084                                                 OMAP_DSS_DISPLAY_ACTIVE;
3085                                 mgr->device->driver->disable(mgr->device);
3086                                 break;
3087                         }
3088                 }
3089
3090                 if (manager) {
3091                         struct omap_dss_device *dssdev = manager->device;
3092                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3093                                 struct omap_overlay *ovl;
3094                                 ovl = omap_dss_get_overlay(i);
3095
3096                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3097                                         continue;
3098
3099                                 if (ovl->id != 0 && ovl->manager == manager)
3100                                         dispc_enable_plane(ovl->id, 0);
3101                         }
3102
3103                         dispc_go(manager->id);
3104                         mdelay(50);
3105                         if (enable)
3106                                 dssdev->driver->enable(dssdev);
3107                 }
3108         }
3109
3110         if (errors & DISPC_IRQ_SYNC_LOST2) {
3111                 struct omap_overlay_manager *manager = NULL;
3112                 bool enable = false;
3113
3114                 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3115
3116                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3117                         struct omap_overlay_manager *mgr;
3118                         mgr = omap_dss_get_overlay_manager(i);
3119
3120                         if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3121                                 manager = mgr;
3122                                 enable = mgr->device->state ==
3123                                                 OMAP_DSS_DISPLAY_ACTIVE;
3124                                 mgr->device->driver->disable(mgr->device);
3125                                 break;
3126                         }
3127                 }
3128
3129                 if (manager) {
3130                         struct omap_dss_device *dssdev = manager->device;
3131                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3132                                 struct omap_overlay *ovl;
3133                                 ovl = omap_dss_get_overlay(i);
3134
3135                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3136                                         continue;
3137
3138                                 if (ovl->id != 0 && ovl->manager == manager)
3139                                         dispc_enable_plane(ovl->id, 0);
3140                         }
3141
3142                         dispc_go(manager->id);
3143                         mdelay(50);
3144                         if (enable)
3145                                 dssdev->driver->enable(dssdev);
3146                 }
3147         }
3148
3149         if (errors & DISPC_IRQ_OCP_ERR) {
3150                 DSSERR("OCP_ERR\n");
3151                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3152                         struct omap_overlay_manager *mgr;
3153                         mgr = omap_dss_get_overlay_manager(i);
3154
3155                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
3156                                 mgr->device->driver->disable(mgr->device);
3157                 }
3158         }
3159
3160         spin_lock_irqsave(&dispc.irq_lock, flags);
3161         dispc.irq_error_mask |= errors;
3162         _omap_dispc_set_irqs();
3163         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3164 }
3165
3166 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3167 {
3168         void dispc_irq_wait_handler(void *data, u32 mask)
3169         {
3170                 complete((struct completion *)data);
3171         }
3172
3173         int r;
3174         DECLARE_COMPLETION_ONSTACK(completion);
3175
3176         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3177                         irqmask);
3178
3179         if (r)
3180                 return r;
3181
3182         timeout = wait_for_completion_timeout(&completion, timeout);
3183
3184         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3185
3186         if (timeout == 0)
3187                 return -ETIMEDOUT;
3188
3189         if (timeout == -ERESTARTSYS)
3190                 return -ERESTARTSYS;
3191
3192         return 0;
3193 }
3194
3195 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3196                 unsigned long timeout)
3197 {
3198         void dispc_irq_wait_handler(void *data, u32 mask)
3199         {
3200                 complete((struct completion *)data);
3201         }
3202
3203         int r;
3204         DECLARE_COMPLETION_ONSTACK(completion);
3205
3206         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3207                         irqmask);
3208
3209         if (r)
3210                 return r;
3211
3212         timeout = wait_for_completion_interruptible_timeout(&completion,
3213                         timeout);
3214
3215         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3216
3217         if (timeout == 0)
3218                 return -ETIMEDOUT;
3219
3220         if (timeout == -ERESTARTSYS)
3221                 return -ERESTARTSYS;
3222
3223         return 0;
3224 }
3225
3226 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3227 void dispc_fake_vsync_irq(void)
3228 {
3229         u32 irqstatus = DISPC_IRQ_VSYNC;
3230         int i;
3231
3232         WARN_ON(!in_interrupt());
3233
3234         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3235                 struct omap_dispc_isr_data *isr_data;
3236                 isr_data = &dispc.registered_isr[i];
3237
3238                 if (!isr_data->isr)
3239                         continue;
3240
3241                 if (isr_data->mask & irqstatus)
3242                         isr_data->isr(isr_data->arg, irqstatus);
3243         }
3244 }
3245 #endif
3246
3247 static void _omap_dispc_initialize_irq(void)
3248 {
3249         unsigned long flags;
3250
3251         spin_lock_irqsave(&dispc.irq_lock, flags);
3252
3253         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3254
3255         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3256         if (dss_has_feature(FEAT_MGR_LCD2))
3257                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3258
3259         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3260          * so clear it */
3261         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3262
3263         _omap_dispc_set_irqs();
3264
3265         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3266 }
3267
3268 void dispc_enable_sidle(void)
3269 {
3270         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3271 }
3272
3273 void dispc_disable_sidle(void)
3274 {
3275         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3276 }
3277
3278 static void _omap_dispc_initial_config(void)
3279 {
3280         u32 l;
3281
3282         l = dispc_read_reg(DISPC_SYSCONFIG);
3283         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3284         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3285         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3286         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3287         dispc_write_reg(DISPC_SYSCONFIG, l);
3288
3289         /* FUNCGATED */
3290         if (dss_has_feature(FEAT_FUNCGATED))
3291                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3292
3293         /* L3 firewall setting: enable access to OCM RAM */
3294         /* XXX this should be somewhere in plat-omap */
3295         if (cpu_is_omap24xx())
3296                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3297
3298         _dispc_setup_color_conv_coef();
3299
3300         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3301
3302         dispc_read_plane_fifo_sizes();
3303 }
3304
3305 int dispc_enable_plane(enum omap_plane plane, bool enable)
3306 {
3307         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3308
3309         enable_clocks(1);
3310         _dispc_enable_plane(plane, enable);
3311         enable_clocks(0);
3312
3313         return 0;
3314 }
3315
3316 int dispc_setup_plane(enum omap_plane plane,
3317                        u32 paddr, u16 screen_width,
3318                        u16 pos_x, u16 pos_y,
3319                        u16 width, u16 height,
3320                        u16 out_width, u16 out_height,
3321                        enum omap_color_mode color_mode,
3322                        bool ilace,
3323                        enum omap_dss_rotation_type rotation_type,
3324                        u8 rotation, bool mirror, u8 global_alpha,
3325                        u8 pre_mult_alpha, enum omap_channel channel)
3326 {
3327         int r = 0;
3328
3329         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3330                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
3331                plane, paddr, screen_width, pos_x, pos_y,
3332                width, height,
3333                out_width, out_height,
3334                ilace, color_mode,
3335                rotation, mirror, channel);
3336
3337         enable_clocks(1);
3338
3339         r = _dispc_setup_plane(plane,
3340                            paddr, screen_width,
3341                            pos_x, pos_y,
3342                            width, height,
3343                            out_width, out_height,
3344                            color_mode, ilace,
3345                            rotation_type,
3346                            rotation, mirror,
3347                            global_alpha,
3348                            pre_mult_alpha, channel);
3349
3350         enable_clocks(0);
3351
3352         return r;
3353 }
3354
3355 /* DISPC HW IP initialisation */
3356 static int omap_dispchw_probe(struct platform_device *pdev)
3357 {
3358         u32 rev;
3359         int r = 0;
3360         struct resource *dispc_mem;
3361
3362         dispc.pdev = pdev;
3363
3364         spin_lock_init(&dispc.irq_lock);
3365
3366 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3367         spin_lock_init(&dispc.irq_stats_lock);
3368         dispc.irq_stats.last_reset = jiffies;
3369 #endif
3370
3371         INIT_WORK(&dispc.error_work, dispc_error_worker);
3372
3373         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3374         if (!dispc_mem) {
3375                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3376                 r = -EINVAL;
3377                 goto fail0;
3378         }
3379         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3380         if (!dispc.base) {
3381                 DSSERR("can't ioremap DISPC\n");
3382                 r = -ENOMEM;
3383                 goto fail0;
3384         }
3385         dispc.irq = platform_get_irq(dispc.pdev, 0);
3386         if (dispc.irq < 0) {
3387                 DSSERR("platform_get_irq failed\n");
3388                 r = -ENODEV;
3389                 goto fail1;
3390         }
3391
3392         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3393                 "OMAP DISPC", dispc.pdev);
3394         if (r < 0) {
3395                 DSSERR("request_irq failed\n");
3396                 goto fail1;
3397         }
3398
3399         enable_clocks(1);
3400
3401         _omap_dispc_initial_config();
3402
3403         _omap_dispc_initialize_irq();
3404
3405         dispc_save_context();
3406
3407         rev = dispc_read_reg(DISPC_REVISION);
3408         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3409                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3410
3411         enable_clocks(0);
3412
3413         return 0;
3414 fail1:
3415         iounmap(dispc.base);
3416 fail0:
3417         return r;
3418 }
3419
3420 static int omap_dispchw_remove(struct platform_device *pdev)
3421 {
3422         free_irq(dispc.irq, dispc.pdev);
3423         iounmap(dispc.base);
3424         return 0;
3425 }
3426
3427 static struct platform_driver omap_dispchw_driver = {
3428         .probe          = omap_dispchw_probe,
3429         .remove         = omap_dispchw_remove,
3430         .driver         = {
3431                 .name   = "omapdss_dispc",
3432                 .owner  = THIS_MODULE,
3433         },
3434 };
3435
3436 int dispc_init_platform_driver(void)
3437 {
3438         return platform_driver_register(&omap_dispchw_driver);
3439 }
3440
3441 void dispc_uninit_platform_driver(void)
3442 {
3443         return platform_driver_unregister(&omap_dispchw_driver);
3444 }