2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
35 #include <mach/sram.h>
36 #include <mach/board.h>
37 #include <mach/clock.h>
39 #include <mach/display.h>
44 #define DISPC_BASE 0x48050400
46 #define DISPC_SZ_REGS SZ_1K
48 struct dispc_reg { u16 idx; };
50 #define DISPC_REG(idx) ((const struct dispc_reg) { idx })
53 #define DISPC_REVISION DISPC_REG(0x0000)
54 #define DISPC_SYSCONFIG DISPC_REG(0x0010)
55 #define DISPC_SYSSTATUS DISPC_REG(0x0014)
56 #define DISPC_IRQSTATUS DISPC_REG(0x0018)
57 #define DISPC_IRQENABLE DISPC_REG(0x001C)
58 #define DISPC_CONTROL DISPC_REG(0x0040)
59 #define DISPC_CONFIG DISPC_REG(0x0044)
60 #define DISPC_CAPABLE DISPC_REG(0x0048)
61 #define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
62 #define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
63 #define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
64 #define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
65 #define DISPC_LINE_STATUS DISPC_REG(0x005C)
66 #define DISPC_LINE_NUMBER DISPC_REG(0x0060)
67 #define DISPC_TIMING_H DISPC_REG(0x0064)
68 #define DISPC_TIMING_V DISPC_REG(0x0068)
69 #define DISPC_POL_FREQ DISPC_REG(0x006C)
70 #define DISPC_DIVISOR DISPC_REG(0x0070)
71 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
72 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
73 #define DISPC_SIZE_LCD DISPC_REG(0x007C)
76 #define DISPC_GFX_BA0 DISPC_REG(0x0080)
77 #define DISPC_GFX_BA1 DISPC_REG(0x0084)
78 #define DISPC_GFX_POSITION DISPC_REG(0x0088)
79 #define DISPC_GFX_SIZE DISPC_REG(0x008C)
80 #define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
81 #define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
82 #define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
83 #define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
84 #define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
85 #define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
86 #define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
88 #define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
89 #define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
90 #define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
92 #define DISPC_CPR_COEF_R DISPC_REG(0x0220)
93 #define DISPC_CPR_COEF_G DISPC_REG(0x0224)
94 #define DISPC_CPR_COEF_B DISPC_REG(0x0228)
96 #define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
99 #define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
101 #define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
102 #define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
103 #define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
104 #define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
105 #define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
106 #define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
107 #define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
108 #define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
109 #define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
110 #define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
111 #define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
112 #define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
113 #define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
116 #define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
118 #define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
119 /* coef index i = {0, 1, 2, 3, 4} */
120 #define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122 #define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
124 #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
127 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
128 DISPC_IRQ_OCP_ERR | \
129 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
130 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
131 DISPC_IRQ_SYNC_LOST | \
132 DISPC_IRQ_SYNC_LOST_DIGIT)
134 #define DISPC_MAX_NR_ISRS 8
136 struct omap_dispc_isr_data {
137 omap_dispc_isr_t isr;
142 #define REG_GET(idx, start, end) \
143 FLD_GET(dispc_read_reg(idx), start, end)
145 #define REG_FLD_MOD(idx, val, start, end) \
146 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
149 DISPC_VID_ATTRIBUTES(0),
150 DISPC_VID_ATTRIBUTES(1) };
155 struct clk *dpll4_m4_ck;
159 unsigned long cache_req_pck;
160 unsigned long cache_prate;
161 struct dispc_clock_info cache_cinfo;
164 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
166 spinlock_t error_lock;
168 struct work_struct error_work;
170 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
173 static void omap_dispc_set_irqs(void);
175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
177 __raw_writel(val, dispc.base + idx.idx);
180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
182 return __raw_readl(dispc.base + idx.idx);
186 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
188 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
190 void dispc_save_context(void)
192 if (cpu_is_omap24xx())
217 SR(GFX_FIFO_THRESHOLD);
238 SR(VID_ATTRIBUTES(0));
239 SR(VID_FIFO_THRESHOLD(0));
241 SR(VID_PIXEL_INC(0));
243 SR(VID_PICTURE_SIZE(0));
247 SR(VID_FIR_COEF_H(0, 0));
248 SR(VID_FIR_COEF_H(0, 1));
249 SR(VID_FIR_COEF_H(0, 2));
250 SR(VID_FIR_COEF_H(0, 3));
251 SR(VID_FIR_COEF_H(0, 4));
252 SR(VID_FIR_COEF_H(0, 5));
253 SR(VID_FIR_COEF_H(0, 6));
254 SR(VID_FIR_COEF_H(0, 7));
256 SR(VID_FIR_COEF_HV(0, 0));
257 SR(VID_FIR_COEF_HV(0, 1));
258 SR(VID_FIR_COEF_HV(0, 2));
259 SR(VID_FIR_COEF_HV(0, 3));
260 SR(VID_FIR_COEF_HV(0, 4));
261 SR(VID_FIR_COEF_HV(0, 5));
262 SR(VID_FIR_COEF_HV(0, 6));
263 SR(VID_FIR_COEF_HV(0, 7));
265 SR(VID_CONV_COEF(0, 0));
266 SR(VID_CONV_COEF(0, 1));
267 SR(VID_CONV_COEF(0, 2));
268 SR(VID_CONV_COEF(0, 3));
269 SR(VID_CONV_COEF(0, 4));
271 SR(VID_FIR_COEF_V(0, 0));
272 SR(VID_FIR_COEF_V(0, 1));
273 SR(VID_FIR_COEF_V(0, 2));
274 SR(VID_FIR_COEF_V(0, 3));
275 SR(VID_FIR_COEF_V(0, 4));
276 SR(VID_FIR_COEF_V(0, 5));
277 SR(VID_FIR_COEF_V(0, 6));
278 SR(VID_FIR_COEF_V(0, 7));
287 SR(VID_ATTRIBUTES(1));
288 SR(VID_FIFO_THRESHOLD(1));
290 SR(VID_PIXEL_INC(1));
292 SR(VID_PICTURE_SIZE(1));
296 SR(VID_FIR_COEF_H(1, 0));
297 SR(VID_FIR_COEF_H(1, 1));
298 SR(VID_FIR_COEF_H(1, 2));
299 SR(VID_FIR_COEF_H(1, 3));
300 SR(VID_FIR_COEF_H(1, 4));
301 SR(VID_FIR_COEF_H(1, 5));
302 SR(VID_FIR_COEF_H(1, 6));
303 SR(VID_FIR_COEF_H(1, 7));
305 SR(VID_FIR_COEF_HV(1, 0));
306 SR(VID_FIR_COEF_HV(1, 1));
307 SR(VID_FIR_COEF_HV(1, 2));
308 SR(VID_FIR_COEF_HV(1, 3));
309 SR(VID_FIR_COEF_HV(1, 4));
310 SR(VID_FIR_COEF_HV(1, 5));
311 SR(VID_FIR_COEF_HV(1, 6));
312 SR(VID_FIR_COEF_HV(1, 7));
314 SR(VID_CONV_COEF(1, 0));
315 SR(VID_CONV_COEF(1, 1));
316 SR(VID_CONV_COEF(1, 2));
317 SR(VID_CONV_COEF(1, 3));
318 SR(VID_CONV_COEF(1, 4));
320 SR(VID_FIR_COEF_V(1, 0));
321 SR(VID_FIR_COEF_V(1, 1));
322 SR(VID_FIR_COEF_V(1, 2));
323 SR(VID_FIR_COEF_V(1, 3));
324 SR(VID_FIR_COEF_V(1, 4));
325 SR(VID_FIR_COEF_V(1, 5));
326 SR(VID_FIR_COEF_V(1, 6));
327 SR(VID_FIR_COEF_V(1, 7));
332 void dispc_restore_context(void)
356 RR(GFX_FIFO_THRESHOLD);
377 RR(VID_ATTRIBUTES(0));
378 RR(VID_FIFO_THRESHOLD(0));
380 RR(VID_PIXEL_INC(0));
382 RR(VID_PICTURE_SIZE(0));
386 RR(VID_FIR_COEF_H(0, 0));
387 RR(VID_FIR_COEF_H(0, 1));
388 RR(VID_FIR_COEF_H(0, 2));
389 RR(VID_FIR_COEF_H(0, 3));
390 RR(VID_FIR_COEF_H(0, 4));
391 RR(VID_FIR_COEF_H(0, 5));
392 RR(VID_FIR_COEF_H(0, 6));
393 RR(VID_FIR_COEF_H(0, 7));
395 RR(VID_FIR_COEF_HV(0, 0));
396 RR(VID_FIR_COEF_HV(0, 1));
397 RR(VID_FIR_COEF_HV(0, 2));
398 RR(VID_FIR_COEF_HV(0, 3));
399 RR(VID_FIR_COEF_HV(0, 4));
400 RR(VID_FIR_COEF_HV(0, 5));
401 RR(VID_FIR_COEF_HV(0, 6));
402 RR(VID_FIR_COEF_HV(0, 7));
404 RR(VID_CONV_COEF(0, 0));
405 RR(VID_CONV_COEF(0, 1));
406 RR(VID_CONV_COEF(0, 2));
407 RR(VID_CONV_COEF(0, 3));
408 RR(VID_CONV_COEF(0, 4));
410 RR(VID_FIR_COEF_V(0, 0));
411 RR(VID_FIR_COEF_V(0, 1));
412 RR(VID_FIR_COEF_V(0, 2));
413 RR(VID_FIR_COEF_V(0, 3));
414 RR(VID_FIR_COEF_V(0, 4));
415 RR(VID_FIR_COEF_V(0, 5));
416 RR(VID_FIR_COEF_V(0, 6));
417 RR(VID_FIR_COEF_V(0, 7));
426 RR(VID_ATTRIBUTES(1));
427 RR(VID_FIFO_THRESHOLD(1));
429 RR(VID_PIXEL_INC(1));
431 RR(VID_PICTURE_SIZE(1));
435 RR(VID_FIR_COEF_H(1, 0));
436 RR(VID_FIR_COEF_H(1, 1));
437 RR(VID_FIR_COEF_H(1, 2));
438 RR(VID_FIR_COEF_H(1, 3));
439 RR(VID_FIR_COEF_H(1, 4));
440 RR(VID_FIR_COEF_H(1, 5));
441 RR(VID_FIR_COEF_H(1, 6));
442 RR(VID_FIR_COEF_H(1, 7));
444 RR(VID_FIR_COEF_HV(1, 0));
445 RR(VID_FIR_COEF_HV(1, 1));
446 RR(VID_FIR_COEF_HV(1, 2));
447 RR(VID_FIR_COEF_HV(1, 3));
448 RR(VID_FIR_COEF_HV(1, 4));
449 RR(VID_FIR_COEF_HV(1, 5));
450 RR(VID_FIR_COEF_HV(1, 6));
451 RR(VID_FIR_COEF_HV(1, 7));
453 RR(VID_CONV_COEF(1, 0));
454 RR(VID_CONV_COEF(1, 1));
455 RR(VID_CONV_COEF(1, 2));
456 RR(VID_CONV_COEF(1, 3));
457 RR(VID_CONV_COEF(1, 4));
459 RR(VID_FIR_COEF_V(1, 0));
460 RR(VID_FIR_COEF_V(1, 1));
461 RR(VID_FIR_COEF_V(1, 2));
462 RR(VID_FIR_COEF_V(1, 3));
463 RR(VID_FIR_COEF_V(1, 4));
464 RR(VID_FIR_COEF_V(1, 5));
465 RR(VID_FIR_COEF_V(1, 6));
466 RR(VID_FIR_COEF_V(1, 7));
470 /* enable last, because LCD & DIGIT enable are here */
477 static inline void enable_clocks(bool enable)
480 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
482 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
485 void dispc_go(enum omap_channel channel)
492 if (channel == OMAP_DSS_CHANNEL_LCD)
493 bit = 0; /* LCDENABLE */
495 bit = 1; /* DIGITALENABLE */
497 /* if the channel is not enabled, we don't need GO */
498 if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
501 if (channel == OMAP_DSS_CHANNEL_LCD)
504 bit = 6; /* GODIGIT */
506 tmo = jiffies + msecs_to_jiffies(200);
507 while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
508 if (time_after(jiffies, tmo)) {
509 DSSERR("timeout waiting GO flag\n");
515 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
517 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
524 BUG_ON(plane == OMAP_DSS_GFX);
526 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
531 BUG_ON(plane == OMAP_DSS_GFX);
533 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
538 BUG_ON(plane == OMAP_DSS_GFX);
540 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
544 int vscaleup, int five_taps)
546 /* Coefficients for horizontal up-sampling */
547 static const u32 coef_hup[8] = {
558 /* Coefficients for horizontal down-sampling */
559 static const u32 coef_hdown[8] = {
570 /* Coefficients for horizontal and vertical up-sampling */
571 static const u32 coef_hvup[2][8] = {
594 /* Coefficients for horizontal and vertical down-sampling */
595 static const u32 coef_hvdown[2][8] = {
618 /* Coefficients for vertical up-sampling */
619 static const u32 coef_vup[8] = {
631 /* Coefficients for vertical down-sampling */
632 static const u32 coef_vdown[8] = {
645 const u32 *hv_coef_mod;
655 hv_coef = coef_hvup[five_taps];
661 hv_coef_mod = coef_hvdown[five_taps];
663 hv_coef = coef_hvdown[five_taps];
667 hv_coef_mod = coef_hvup[five_taps];
672 for (i = 0; i < 8; i++) {
681 hv |= (hv_coef_mod[i] & 0xff);
684 _dispc_write_firh_reg(plane, i, h);
685 _dispc_write_firhv_reg(plane, i, hv);
691 for (i = 0; i < 8; i++) {
694 _dispc_write_firv_reg(plane, i, v);
698 static void _dispc_setup_color_conv_coef(void)
700 const struct color_conv_coef {
701 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
704 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
707 const struct color_conv_coef *ct;
709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
713 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
714 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
715 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
716 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
717 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
719 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
720 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
721 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
722 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
723 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
727 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
728 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
734 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
738 dispc_write_reg(ba0_reg[plane], paddr);
741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
743 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
747 dispc_write_reg(ba1_reg[plane], paddr);
750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
752 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
753 DISPC_VID_POSITION(0),
754 DISPC_VID_POSITION(1) };
756 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
757 dispc_write_reg(pos_reg[plane], val);
760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
762 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
763 DISPC_VID_PICTURE_SIZE(0),
764 DISPC_VID_PICTURE_SIZE(1) };
765 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
766 dispc_write_reg(siz_reg[plane], val);
769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
772 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
775 BUG_ON(plane == OMAP_DSS_GFX);
777 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
778 dispc_write_reg(vsi_reg[plane-1], val);
781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
783 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
784 DISPC_VID_PIXEL_INC(0),
785 DISPC_VID_PIXEL_INC(1) };
787 dispc_write_reg(ri_reg[plane], inc);
790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
792 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
793 DISPC_VID_ROW_INC(0),
794 DISPC_VID_ROW_INC(1) };
796 dispc_write_reg(ri_reg[plane], inc);
799 static void _dispc_set_color_mode(enum omap_plane plane,
800 enum omap_color_mode color_mode)
804 switch (color_mode) {
805 case OMAP_DSS_COLOR_CLUT1:
807 case OMAP_DSS_COLOR_CLUT2:
809 case OMAP_DSS_COLOR_CLUT4:
811 case OMAP_DSS_COLOR_CLUT8:
813 case OMAP_DSS_COLOR_RGB12U:
815 case OMAP_DSS_COLOR_ARGB16:
817 case OMAP_DSS_COLOR_RGB16:
819 case OMAP_DSS_COLOR_RGB24U:
821 case OMAP_DSS_COLOR_RGB24P:
823 case OMAP_DSS_COLOR_YUV2:
825 case OMAP_DSS_COLOR_UYVY:
827 case OMAP_DSS_COLOR_ARGB32:
829 case OMAP_DSS_COLOR_RGBA32:
831 case OMAP_DSS_COLOR_RGBX32:
837 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
840 static void _dispc_set_channel_out(enum omap_plane plane,
841 enum omap_channel channel)
850 case OMAP_DSS_VIDEO1:
851 case OMAP_DSS_VIDEO2:
859 val = dispc_read_reg(dispc_reg_att[plane]);
860 val = FLD_MOD(val, channel, shift, shift);
861 dispc_write_reg(dispc_reg_att[plane], val);
864 void dispc_set_burst_size(enum omap_plane plane,
865 enum omap_burst_size burst_size)
876 case OMAP_DSS_VIDEO1:
877 case OMAP_DSS_VIDEO2:
885 val = dispc_read_reg(dispc_reg_att[plane]);
886 val = FLD_MOD(val, burst_size, shift+1, shift);
887 dispc_write_reg(dispc_reg_att[plane], val);
892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
896 BUG_ON(plane == OMAP_DSS_GFX);
898 val = dispc_read_reg(dispc_reg_att[plane]);
899 val = FLD_MOD(val, enable, 9, 9);
900 dispc_write_reg(dispc_reg_att[plane], val);
903 void dispc_set_lcd_size(u16 width, u16 height)
906 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
907 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
909 dispc_write_reg(DISPC_SIZE_LCD, val);
913 void dispc_set_digit_size(u16 width, u16 height)
916 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
917 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
919 dispc_write_reg(DISPC_SIZE_DIG, val);
923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
925 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
926 DISPC_VID_FIFO_SIZE_STATUS(0),
927 DISPC_VID_FIFO_SIZE_STATUS(1) };
932 if (cpu_is_omap24xx())
933 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
934 else if (cpu_is_omap34xx())
935 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
939 if (cpu_is_omap34xx()) {
941 if (REG_GET(DISPC_CONFIG, 14, 14))
950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
952 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
953 DISPC_VID_FIFO_THRESHOLD(0),
954 DISPC_VID_FIFO_THRESHOLD(1) };
959 size = dispc_get_plane_fifo_size(plane);
961 BUG_ON(low > size || high > size);
963 DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
965 REG_GET(ftrs_reg[plane], 11, 0),
966 REG_GET(ftrs_reg[plane], 27, 16),
969 if (cpu_is_omap24xx())
970 dispc_write_reg(ftrs_reg[plane],
971 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
973 dispc_write_reg(ftrs_reg[plane],
974 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
979 void dispc_enable_fifomerge(bool enable)
983 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
984 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
992 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
995 BUG_ON(plane == OMAP_DSS_GFX);
997 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
998 dispc_write_reg(fir_reg[plane-1], val);
1001 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1004 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1005 DISPC_VID_ACCU0(1) };
1007 BUG_ON(plane == OMAP_DSS_GFX);
1009 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1010 dispc_write_reg(ac0_reg[plane-1], val);
1013 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1016 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1017 DISPC_VID_ACCU1(1) };
1019 BUG_ON(plane == OMAP_DSS_GFX);
1021 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1022 dispc_write_reg(ac1_reg[plane-1], val);
1026 static void _dispc_set_scaling(enum omap_plane plane,
1027 u16 orig_width, u16 orig_height,
1028 u16 out_width, u16 out_height,
1033 int hscaleup, vscaleup, five_taps;
1039 BUG_ON(plane == OMAP_DSS_GFX);
1041 hscaleup = orig_width <= out_width;
1042 vscaleup = orig_height <= out_height;
1043 five_taps = orig_height > out_height * 2;
1045 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1047 if (!orig_width || orig_width == out_width)
1050 fir_hinc = 1024 * orig_width / out_width;
1052 if (!orig_height || orig_height == out_height)
1055 fir_vinc = 1024 * orig_height / out_height;
1057 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1059 l = dispc_read_reg(dispc_reg_att[plane]);
1060 l &= ~((0x0f << 5) | (0x3 << 21));
1062 l |= fir_hinc ? (1 << 5) : 0;
1063 l |= fir_vinc ? (1 << 6) : 0;
1065 l |= hscaleup ? 0 : (1 << 7);
1066 l |= vscaleup ? 0 : (1 << 8);
1068 l |= five_taps ? (1 << 21) : 0;
1069 l |= five_taps ? (1 << 22) : 0;
1071 dispc_write_reg(dispc_reg_att[plane], l);
1075 accu0 = fir_vinc / 2;
1079 accu1 = fir_vinc / 2;
1080 if (accu1 >= 1024/2) {
1087 _dispc_set_vid_accu0(plane, 0, accu0);
1088 _dispc_set_vid_accu1(plane, 0, accu1);
1091 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1092 bool mirroring, enum omap_color_mode color_mode)
1094 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1095 color_mode == OMAP_DSS_COLOR_UYVY) {
1100 case 0: vidrot = 2; break;
1101 case 1: vidrot = 3; break;
1102 case 2: vidrot = 0; break;
1103 case 3: vidrot = 1; break;
1107 case 0: vidrot = 0; break;
1108 case 1: vidrot = 1; break;
1109 case 2: vidrot = 2; break;
1110 case 3: vidrot = 1; break;
1114 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1116 if (rotation == 1 || rotation == 3)
1117 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1119 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1121 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1122 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1126 static s32 pixinc(int pixels, u8 ps)
1130 else if (pixels > 1)
1131 return 1 + (pixels - 1) * ps;
1132 else if (pixels < 0)
1133 return 1 - (-pixels + 1) * ps;
1138 static void calc_rotation_offset(u8 rotation, bool mirror,
1140 u16 width, u16 height,
1141 enum omap_color_mode color_mode, bool fieldmode,
1142 unsigned *offset0, unsigned *offset1,
1143 s32 *row_inc, s32 *pix_inc)
1148 switch (color_mode) {
1149 case OMAP_DSS_COLOR_RGB16:
1150 case OMAP_DSS_COLOR_ARGB16:
1154 case OMAP_DSS_COLOR_RGB24P:
1158 case OMAP_DSS_COLOR_RGB24U:
1159 case OMAP_DSS_COLOR_ARGB32:
1160 case OMAP_DSS_COLOR_RGBA32:
1161 case OMAP_DSS_COLOR_RGBX32:
1165 case OMAP_DSS_COLOR_YUV2:
1166 case OMAP_DSS_COLOR_UYVY:
1174 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1177 /* width & height are overlay sizes, convert to fb sizes */
1179 if (rotation == 0 || rotation == 2) {
1187 switch (rotation + mirror * 4) {
1191 *offset1 = screen_width * ps;
1194 *row_inc = pixinc(1 + (screen_width - fbw) +
1195 (fieldmode ? screen_width : 0),
1197 *pix_inc = pixinc(1, ps);
1200 *offset0 = screen_width * (fbh - 1) * ps;
1202 *offset1 = *offset0 + ps;
1204 *offset1 = *offset0;
1205 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1206 (fieldmode ? 1 : 0), ps);
1207 *pix_inc = pixinc(-screen_width, ps);
1210 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1212 *offset1 = *offset0 - screen_width * ps;
1214 *offset1 = *offset0;
1215 *row_inc = pixinc(-1 -
1216 (screen_width - fbw) -
1217 (fieldmode ? screen_width : 0),
1219 *pix_inc = pixinc(-1, ps);
1222 *offset0 = (fbw - 1) * ps;
1224 *offset1 = *offset0 - ps;
1226 *offset1 = *offset0;
1227 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1228 (fieldmode ? 1 : 0), ps);
1229 *pix_inc = pixinc(screen_width, ps);
1234 *offset0 = (fbw - 1) * ps;
1236 *offset1 = *offset0 + screen_width * ps;
1238 *offset1 = *offset0;
1239 *row_inc = pixinc(screen_width * 2 - 1 +
1240 (fieldmode ? screen_width : 0),
1242 *pix_inc = pixinc(-1, ps);
1248 *offset1 = *offset0 + screen_width * ps;
1250 *offset1 = *offset0;
1251 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1252 (fieldmode ? 1 : 0),
1254 *pix_inc = pixinc(screen_width, ps);
1258 *offset0 = screen_width * (fbh - 1) * ps;
1260 *offset1 = *offset0 + screen_width * ps;
1262 *offset1 = *offset0;
1263 *row_inc = pixinc(1 - screen_width * 2 -
1264 (fieldmode ? screen_width : 0),
1266 *pix_inc = pixinc(1, ps);
1270 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1272 *offset1 = *offset0 + screen_width * ps;
1274 *offset1 = *offset0;
1275 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1276 (fieldmode ? 1 : 0),
1278 *pix_inc = pixinc(-screen_width, ps);
1286 static int _dispc_setup_plane(enum omap_plane plane,
1287 enum omap_channel channel_out,
1288 u32 paddr, u16 screen_width,
1289 u16 pos_x, u16 pos_y,
1290 u16 width, u16 height,
1291 u16 out_width, u16 out_height,
1292 enum omap_color_mode color_mode,
1294 u8 rotation, int mirror)
1296 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1297 bool five_taps = height > out_height * 2;
1300 unsigned offset0, offset1;
1307 if (plane == OMAP_DSS_GFX) {
1308 if (width != out_width || height != out_height)
1311 switch (color_mode) {
1312 case OMAP_DSS_COLOR_ARGB16:
1313 case OMAP_DSS_COLOR_RGB16:
1314 case OMAP_DSS_COLOR_RGB24P:
1315 case OMAP_DSS_COLOR_RGB24U:
1316 case OMAP_DSS_COLOR_ARGB32:
1317 case OMAP_DSS_COLOR_RGBA32:
1318 case OMAP_DSS_COLOR_RGBX32:
1326 if (width > (2048 >> five_taps))
1329 if (out_width < width / maxdownscale ||
1330 out_width > width * 8)
1333 if (out_height < height / maxdownscale ||
1334 out_height > height * 8)
1337 switch (color_mode) {
1338 case OMAP_DSS_COLOR_RGB16:
1339 case OMAP_DSS_COLOR_RGB24P:
1340 case OMAP_DSS_COLOR_RGB24U:
1341 case OMAP_DSS_COLOR_RGBX32:
1344 case OMAP_DSS_COLOR_ARGB16:
1345 case OMAP_DSS_COLOR_ARGB32:
1346 case OMAP_DSS_COLOR_RGBA32:
1347 if (plane == OMAP_DSS_VIDEO1)
1351 case OMAP_DSS_COLOR_YUV2:
1352 case OMAP_DSS_COLOR_UYVY:
1361 if (ilace && height >= out_height)
1364 calc_rotation_offset(rotation, mirror,
1365 screen_width, width, height, color_mode,
1367 &offset0, &offset1, &row_inc, &pix_inc);
1369 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1370 offset0, offset1, row_inc, pix_inc);
1378 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1380 height, pos_y, out_height);
1383 _dispc_set_channel_out(plane, channel_out);
1384 _dispc_set_color_mode(plane, color_mode);
1386 _dispc_set_plane_ba0(plane, paddr + offset0);
1387 _dispc_set_plane_ba1(plane, paddr + offset1);
1389 _dispc_set_row_inc(plane, row_inc);
1390 _dispc_set_pix_inc(plane, pix_inc);
1392 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1393 out_width, out_height);
1395 _dispc_set_plane_pos(plane, pos_x, pos_y);
1397 _dispc_set_pic_size(plane, width, height);
1399 if (plane != OMAP_DSS_GFX) {
1400 _dispc_set_scaling(plane, width, height,
1401 out_width, out_height,
1403 _dispc_set_vid_size(plane, out_width, out_height);
1404 _dispc_set_vid_color_conv(plane, cconv);
1407 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1412 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1414 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1417 static void dispc_disable_isr(void *data, u32 mask)
1419 struct completion *compl = data;
1423 static void _enable_lcd_out(bool enable)
1425 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1428 void dispc_enable_lcd_out(bool enable)
1430 struct completion frame_done_completion;
1436 /* When we disable LCD output, we need to wait until frame is done.
1437 * Otherwise the DSS is still working, and turning off the clocks
1438 * prevents DSS from going to OFF mode */
1439 is_on = REG_GET(DISPC_CONTROL, 0, 0);
1441 if (!enable && is_on) {
1442 init_completion(&frame_done_completion);
1444 r = omap_dispc_register_isr(dispc_disable_isr,
1445 &frame_done_completion,
1446 DISPC_IRQ_FRAMEDONE);
1449 DSSERR("failed to register FRAMEDONE isr\n");
1452 _enable_lcd_out(enable);
1454 if (!enable && is_on) {
1455 if (!wait_for_completion_timeout(&frame_done_completion,
1456 msecs_to_jiffies(100)))
1457 DSSERR("timeout waiting for FRAME DONE\n");
1459 r = omap_dispc_unregister_isr(dispc_disable_isr,
1460 &frame_done_completion,
1461 DISPC_IRQ_FRAMEDONE);
1464 DSSERR("failed to unregister FRAMEDONE isr\n");
1470 static void _enable_digit_out(bool enable)
1472 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1475 void dispc_enable_digit_out(bool enable)
1477 struct completion frame_done_completion;
1482 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1488 /* When we enable digit output, we'll get an extra digit
1489 * sync lost interrupt, that we need to ignore */
1490 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1491 omap_dispc_set_irqs();
1494 /* When we disable digit output, we need to wait until fields are done.
1495 * Otherwise the DSS is still working, and turning off the clocks
1496 * prevents DSS from going to OFF mode. And when enabling, we need to
1497 * wait for the extra sync losts */
1498 init_completion(&frame_done_completion);
1500 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1501 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1503 DSSERR("failed to register EVSYNC isr\n");
1505 _enable_digit_out(enable);
1507 /* XXX I understand from TRM that we should only wait for the
1508 * current field to complete. But it seems we have to wait
1509 * for both fields */
1510 if (!wait_for_completion_timeout(&frame_done_completion,
1511 msecs_to_jiffies(100)))
1512 DSSERR("timeout waiting for EVSYNC\n");
1514 if (!wait_for_completion_timeout(&frame_done_completion,
1515 msecs_to_jiffies(100)))
1516 DSSERR("timeout waiting for EVSYNC\n");
1518 r = omap_dispc_unregister_isr(dispc_disable_isr,
1519 &frame_done_completion,
1520 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1522 DSSERR("failed to unregister EVSYNC isr\n");
1525 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1526 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1527 omap_dispc_set_irqs();
1533 void dispc_lcd_enable_signal_polarity(bool act_high)
1536 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1540 void dispc_lcd_enable_signal(bool enable)
1543 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1547 void dispc_pck_free_enable(bool enable)
1550 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1554 void dispc_enable_fifohandcheck(bool enable)
1557 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1562 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1567 case OMAP_DSS_LCD_DISPLAY_STN:
1571 case OMAP_DSS_LCD_DISPLAY_TFT:
1581 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1585 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1588 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1593 void dispc_set_default_color(enum omap_channel channel, u32 color)
1595 const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1596 DISPC_DEFAULT_COLOR1 };
1599 dispc_write_reg(def_reg[channel], color);
1603 u32 dispc_get_default_color(enum omap_channel channel)
1605 const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1606 DISPC_DEFAULT_COLOR1 };
1609 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1610 channel != OMAP_DSS_CHANNEL_LCD);
1613 l = dispc_read_reg(def_reg[channel]);
1619 void dispc_set_trans_key(enum omap_channel ch,
1620 enum omap_dss_color_key_type type,
1623 const struct dispc_reg tr_reg[] = {
1624 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1627 if (ch == OMAP_DSS_CHANNEL_LCD)
1628 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1629 else /* OMAP_DSS_CHANNEL_DIGIT */
1630 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1632 dispc_write_reg(tr_reg[ch], trans_key);
1636 void dispc_get_trans_key(enum omap_channel ch,
1637 enum omap_dss_color_key_type *type,
1640 const struct dispc_reg tr_reg[] = {
1641 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1645 if (ch == OMAP_DSS_CHANNEL_LCD)
1646 *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
1647 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1648 *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
1654 *trans_key = dispc_read_reg(tr_reg[ch]);
1658 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1661 if (ch == OMAP_DSS_CHANNEL_LCD)
1662 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1663 else /* OMAP_DSS_CHANNEL_DIGIT */
1664 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1668 bool dispc_trans_key_enabled(enum omap_channel ch)
1673 if (ch == OMAP_DSS_CHANNEL_LCD)
1674 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1675 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1676 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1684 void dispc_set_tft_data_lines(u8 data_lines)
1688 switch (data_lines) {
1707 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1711 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1719 case OMAP_DSS_PARALLELMODE_BYPASS:
1724 case OMAP_DSS_PARALLELMODE_RFBI:
1729 case OMAP_DSS_PARALLELMODE_DSI:
1741 l = dispc_read_reg(DISPC_CONTROL);
1743 l = FLD_MOD(l, stallmode, 11, 11);
1744 l = FLD_MOD(l, gpout0, 15, 15);
1745 l = FLD_MOD(l, gpout1, 16, 16);
1747 dispc_write_reg(DISPC_CONTROL, l);
1752 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1753 int vsw, int vfp, int vbp)
1755 u32 timing_h, timing_v;
1757 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1758 BUG_ON(hsw < 1 || hsw > 64);
1759 BUG_ON(hfp < 1 || hfp > 256);
1760 BUG_ON(hbp < 1 || hbp > 256);
1762 BUG_ON(vsw < 1 || vsw > 64);
1763 BUG_ON(vfp < 0 || vfp > 255);
1764 BUG_ON(vbp < 0 || vbp > 255);
1766 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1767 FLD_VAL(hbp-1, 27, 20);
1769 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1770 FLD_VAL(vbp, 27, 20);
1772 BUG_ON(hsw < 1 || hsw > 256);
1773 BUG_ON(hfp < 1 || hfp > 4096);
1774 BUG_ON(hbp < 1 || hbp > 4096);
1776 BUG_ON(vsw < 1 || vsw > 256);
1777 BUG_ON(vfp < 0 || vfp > 4095);
1778 BUG_ON(vbp < 0 || vbp > 4095);
1780 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1781 FLD_VAL(hbp-1, 31, 20);
1783 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1784 FLD_VAL(vbp, 31, 20);
1788 dispc_write_reg(DISPC_TIMING_H, timing_h);
1789 dispc_write_reg(DISPC_TIMING_V, timing_v);
1793 /* change name to mode? */
1794 void dispc_set_lcd_timings(struct omap_video_timings *timings)
1796 unsigned xtot, ytot;
1797 unsigned long ht, vt;
1799 _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
1800 timings->vsw, timings->vfp, timings->vbp);
1802 dispc_set_lcd_size(timings->x_res, timings->y_res);
1804 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
1805 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
1807 ht = (timings->pixel_clock * 1000) / xtot;
1808 vt = (timings->pixel_clock * 1000) / xtot / ytot;
1810 DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
1811 DSSDBG("pck %u\n", timings->pixel_clock);
1812 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
1813 timings->hsw, timings->hfp, timings->hbp,
1814 timings->vsw, timings->vfp, timings->vbp);
1816 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
1819 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
1821 BUG_ON(lck_div < 1);
1822 BUG_ON(pck_div < 2);
1825 dispc_write_reg(DISPC_DIVISOR,
1826 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
1830 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
1833 l = dispc_read_reg(DISPC_DIVISOR);
1834 *lck_div = FLD_GET(l, 23, 16);
1835 *pck_div = FLD_GET(l, 7, 0);
1838 unsigned long dispc_fclk_rate(void)
1840 unsigned long r = 0;
1842 if (dss_get_dispc_clk_source() == 0)
1843 r = dss_clk_get_rate(DSS_CLK_FCK1);
1845 #ifdef CONFIG_OMAP2_DSS_DSI
1846 r = dsi_get_dsi1_pll_rate();
1853 unsigned long dispc_pclk_rate(void)
1859 l = dispc_read_reg(DISPC_DIVISOR);
1861 lcd = FLD_GET(l, 23, 16);
1862 pcd = FLD_GET(l, 7, 0);
1864 r = dispc_fclk_rate();
1866 return r / lcd / pcd;
1869 void dispc_dump_clocks(struct seq_file *s)
1875 dispc_get_lcd_divisor(&lcd, &pcd);
1877 seq_printf(s, "- dispc -\n");
1879 seq_printf(s, "dispc fclk source = %s\n",
1880 dss_get_dispc_clk_source() == 0 ?
1881 "dss1_alwon_fclk" : "dsi1_pll_fclk");
1883 seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
1891 void dispc_dump_regs(struct seq_file *s)
1893 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
1895 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1897 DUMPREG(DISPC_REVISION);
1898 DUMPREG(DISPC_SYSCONFIG);
1899 DUMPREG(DISPC_SYSSTATUS);
1900 DUMPREG(DISPC_IRQSTATUS);
1901 DUMPREG(DISPC_IRQENABLE);
1902 DUMPREG(DISPC_CONTROL);
1903 DUMPREG(DISPC_CONFIG);
1904 DUMPREG(DISPC_CAPABLE);
1905 DUMPREG(DISPC_DEFAULT_COLOR0);
1906 DUMPREG(DISPC_DEFAULT_COLOR1);
1907 DUMPREG(DISPC_TRANS_COLOR0);
1908 DUMPREG(DISPC_TRANS_COLOR1);
1909 DUMPREG(DISPC_LINE_STATUS);
1910 DUMPREG(DISPC_LINE_NUMBER);
1911 DUMPREG(DISPC_TIMING_H);
1912 DUMPREG(DISPC_TIMING_V);
1913 DUMPREG(DISPC_POL_FREQ);
1914 DUMPREG(DISPC_DIVISOR);
1915 DUMPREG(DISPC_GLOBAL_ALPHA);
1916 DUMPREG(DISPC_SIZE_DIG);
1917 DUMPREG(DISPC_SIZE_LCD);
1919 DUMPREG(DISPC_GFX_BA0);
1920 DUMPREG(DISPC_GFX_BA1);
1921 DUMPREG(DISPC_GFX_POSITION);
1922 DUMPREG(DISPC_GFX_SIZE);
1923 DUMPREG(DISPC_GFX_ATTRIBUTES);
1924 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
1925 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
1926 DUMPREG(DISPC_GFX_ROW_INC);
1927 DUMPREG(DISPC_GFX_PIXEL_INC);
1928 DUMPREG(DISPC_GFX_WINDOW_SKIP);
1929 DUMPREG(DISPC_GFX_TABLE_BA);
1931 DUMPREG(DISPC_DATA_CYCLE1);
1932 DUMPREG(DISPC_DATA_CYCLE2);
1933 DUMPREG(DISPC_DATA_CYCLE3);
1935 DUMPREG(DISPC_CPR_COEF_R);
1936 DUMPREG(DISPC_CPR_COEF_G);
1937 DUMPREG(DISPC_CPR_COEF_B);
1939 DUMPREG(DISPC_GFX_PRELOAD);
1941 DUMPREG(DISPC_VID_BA0(0));
1942 DUMPREG(DISPC_VID_BA1(0));
1943 DUMPREG(DISPC_VID_POSITION(0));
1944 DUMPREG(DISPC_VID_SIZE(0));
1945 DUMPREG(DISPC_VID_ATTRIBUTES(0));
1946 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
1947 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
1948 DUMPREG(DISPC_VID_ROW_INC(0));
1949 DUMPREG(DISPC_VID_PIXEL_INC(0));
1950 DUMPREG(DISPC_VID_FIR(0));
1951 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
1952 DUMPREG(DISPC_VID_ACCU0(0));
1953 DUMPREG(DISPC_VID_ACCU1(0));
1955 DUMPREG(DISPC_VID_BA0(1));
1956 DUMPREG(DISPC_VID_BA1(1));
1957 DUMPREG(DISPC_VID_POSITION(1));
1958 DUMPREG(DISPC_VID_SIZE(1));
1959 DUMPREG(DISPC_VID_ATTRIBUTES(1));
1960 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
1961 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
1962 DUMPREG(DISPC_VID_ROW_INC(1));
1963 DUMPREG(DISPC_VID_PIXEL_INC(1));
1964 DUMPREG(DISPC_VID_FIR(1));
1965 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
1966 DUMPREG(DISPC_VID_ACCU0(1));
1967 DUMPREG(DISPC_VID_ACCU1(1));
1969 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
1970 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
1971 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
1972 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
1973 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
1974 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
1975 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
1976 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
1977 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
1978 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
1979 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
1980 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
1981 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
1982 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
1983 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
1984 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
1985 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
1986 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
1987 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
1988 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
1989 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
1990 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
1991 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
1992 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
1993 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
1994 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
1995 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
1996 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
1997 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
1999 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2000 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2001 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2002 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2003 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2004 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2005 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2006 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2007 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2008 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2009 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2010 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2011 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2012 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2013 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2014 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2015 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2016 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2017 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2018 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2019 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2020 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2021 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2022 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2023 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2024 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2025 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2026 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2027 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2029 DUMPREG(DISPC_VID_PRELOAD(0));
2030 DUMPREG(DISPC_VID_PRELOAD(1));
2032 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2036 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2037 bool ihs, bool ivs, u8 acbi, u8 acb)
2041 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2042 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2044 l |= FLD_VAL(onoff, 17, 17);
2045 l |= FLD_VAL(rf, 16, 16);
2046 l |= FLD_VAL(ieo, 15, 15);
2047 l |= FLD_VAL(ipc, 14, 14);
2048 l |= FLD_VAL(ihs, 13, 13);
2049 l |= FLD_VAL(ivs, 12, 12);
2050 l |= FLD_VAL(acbi, 11, 8);
2051 l |= FLD_VAL(acb, 7, 0);
2054 dispc_write_reg(DISPC_POL_FREQ, l);
2058 void dispc_set_pol_freq(struct omap_panel *panel)
2060 _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2061 (panel->config & OMAP_DSS_LCD_RF) != 0,
2062 (panel->config & OMAP_DSS_LCD_IEO) != 0,
2063 (panel->config & OMAP_DSS_LCD_IPC) != 0,
2064 (panel->config & OMAP_DSS_LCD_IHS) != 0,
2065 (panel->config & OMAP_DSS_LCD_IVS) != 0,
2066 panel->acbi, panel->acb);
2069 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2070 u16 *lck_div, u16 *pck_div)
2072 u16 pcd_min = is_tft ? 2 : 3;
2073 unsigned long best_pck;
2074 u16 best_ld, cur_ld;
2075 u16 best_pd, cur_pd;
2081 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2082 unsigned long lck = fck / cur_ld;
2084 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2085 unsigned long pck = lck / cur_pd;
2086 long old_delta = abs(best_pck - req_pck);
2087 long new_delta = abs(pck - req_pck);
2089 if (best_pck == 0 || new_delta < old_delta) {
2102 if (lck / pcd_min < req_pck)
2111 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2112 struct dispc_clock_info *cinfo)
2114 unsigned long prate;
2115 struct dispc_clock_info cur, best;
2117 int min_fck_per_pck;
2118 unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2120 if (cpu_is_omap34xx())
2121 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2125 if (req_pck == dispc.cache_req_pck &&
2126 ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2127 dispc.cache_cinfo.fck == fck_rate)) {
2128 DSSDBG("dispc clock info found from cache.\n");
2129 *cinfo = dispc.cache_cinfo;
2133 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2135 if (min_fck_per_pck &&
2136 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2137 DSSERR("Requested pixel clock not possible with the current "
2138 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2139 "the constraint off.\n");
2140 min_fck_per_pck = 0;
2144 memset(&cur, 0, sizeof(cur));
2145 memset(&best, 0, sizeof(best));
2147 if (cpu_is_omap24xx()) {
2148 /* XXX can we change the clock on omap2? */
2149 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2154 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2155 &cur.lck_div, &cur.pck_div);
2157 cur.lck = cur.fck / cur.lck_div;
2158 cur.pck = cur.lck / cur.pck_div;
2163 } else if (cpu_is_omap34xx()) {
2164 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2165 cur.fck = prate / cur.fck_div * 2;
2167 if (cur.fck > DISPC_MAX_FCK)
2170 if (min_fck_per_pck &&
2171 cur.fck < req_pck * min_fck_per_pck)
2176 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2177 &cur.lck_div, &cur.pck_div);
2179 cur.lck = cur.fck / cur.lck_div;
2180 cur.pck = cur.lck / cur.pck_div;
2182 if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2185 if (cur.pck == req_pck)
2195 if (min_fck_per_pck) {
2196 DSSERR("Could not find suitable clock settings.\n"
2197 "Turning FCK/PCK constraint off and"
2199 min_fck_per_pck = 0;
2203 DSSERR("Could not find suitable clock settings.\n");
2211 dispc.cache_req_pck = req_pck;
2212 dispc.cache_prate = prate;
2213 dispc.cache_cinfo = best;
2218 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2220 unsigned long prate;
2223 if (cpu_is_omap34xx()) {
2224 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2225 DSSDBG("dpll4_m4 = %ld\n", prate);
2228 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2229 DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2230 DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2232 if (cpu_is_omap34xx()) {
2233 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2238 dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2243 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2245 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2247 if (cpu_is_omap34xx()) {
2248 unsigned long prate;
2249 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2250 cinfo->fck_div = prate / (cinfo->fck / 2);
2255 cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2256 cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2258 cinfo->lck = cinfo->fck / cinfo->lck_div;
2259 cinfo->pck = cinfo->lck / cinfo->pck_div;
2264 static void omap_dispc_set_irqs(void)
2266 unsigned long flags;
2267 u32 mask = dispc.irq_error_mask;
2269 struct omap_dispc_isr_data *isr_data;
2271 spin_lock_irqsave(&dispc.irq_lock, flags);
2273 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2274 isr_data = &dispc.registered_isr[i];
2276 if (isr_data->isr == NULL)
2279 mask |= isr_data->mask;
2283 dispc_write_reg(DISPC_IRQENABLE, mask);
2286 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2289 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2293 unsigned long flags;
2294 struct omap_dispc_isr_data *isr_data;
2299 spin_lock_irqsave(&dispc.irq_lock, flags);
2301 /* check for duplicate entry */
2302 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2303 isr_data = &dispc.registered_isr[i];
2304 if (isr_data->isr == isr && isr_data->arg == arg &&
2305 isr_data->mask == mask) {
2314 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2315 isr_data = &dispc.registered_isr[i];
2317 if (isr_data->isr != NULL)
2320 isr_data->isr = isr;
2321 isr_data->arg = arg;
2322 isr_data->mask = mask;
2328 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2331 omap_dispc_set_irqs();
2335 EXPORT_SYMBOL(omap_dispc_register_isr);
2337 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2340 unsigned long flags;
2342 struct omap_dispc_isr_data *isr_data;
2344 spin_lock_irqsave(&dispc.irq_lock, flags);
2346 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2347 isr_data = &dispc.registered_isr[i];
2348 if (isr_data->isr != isr || isr_data->arg != arg ||
2349 isr_data->mask != mask)
2352 /* found the correct isr */
2354 isr_data->isr = NULL;
2355 isr_data->arg = NULL;
2362 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2365 omap_dispc_set_irqs();
2369 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2372 static void print_irq_status(u32 status)
2374 if ((status & dispc.irq_error_mask) == 0)
2377 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2380 if (status & DISPC_IRQ_##x) \
2382 PIS(GFX_FIFO_UNDERFLOW);
2384 PIS(VID1_FIFO_UNDERFLOW);
2385 PIS(VID2_FIFO_UNDERFLOW);
2387 PIS(SYNC_LOST_DIGIT);
2394 /* Called from dss.c. Note that we don't touch clocks here,
2395 * but we presume they are on because we got an IRQ. However,
2396 * an irq handler may turn the clocks off, so we may not have
2397 * clock later in the function. */
2398 void dispc_irq_handler(void)
2401 u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2402 u32 handledirqs = 0;
2403 u32 unhandled_errors;
2404 struct omap_dispc_isr_data *isr_data;
2408 print_irq_status(irqstatus);
2410 /* Ack the interrupt. Do it here before clocks are possibly turned
2412 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2414 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2415 isr_data = &dispc.registered_isr[i];
2420 if (isr_data->mask & irqstatus) {
2421 isr_data->isr(isr_data->arg, irqstatus);
2422 handledirqs |= isr_data->mask;
2426 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2428 if (unhandled_errors) {
2429 spin_lock(&dispc.error_lock);
2430 dispc.error_irqs |= unhandled_errors;
2431 spin_unlock(&dispc.error_lock);
2433 dispc.irq_error_mask &= ~unhandled_errors;
2434 omap_dispc_set_irqs();
2436 schedule_work(&dispc.error_work);
2440 static void dispc_error_worker(struct work_struct *work)
2444 unsigned long flags;
2446 spin_lock_irqsave(&dispc.error_lock, flags);
2447 errors = dispc.error_irqs;
2448 dispc.error_irqs = 0;
2449 spin_unlock_irqrestore(&dispc.error_lock, flags);
2451 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2452 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2453 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2454 struct omap_overlay *ovl;
2455 ovl = omap_dss_get_overlay(i);
2457 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2461 dispc_enable_plane(ovl->id, 0);
2462 dispc_go(ovl->manager->id);
2469 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2470 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2471 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2472 struct omap_overlay *ovl;
2473 ovl = omap_dss_get_overlay(i);
2475 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2479 dispc_enable_plane(ovl->id, 0);
2480 dispc_go(ovl->manager->id);
2487 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2488 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2489 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2490 struct omap_overlay *ovl;
2491 ovl = omap_dss_get_overlay(i);
2493 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2497 dispc_enable_plane(ovl->id, 0);
2498 dispc_go(ovl->manager->id);
2505 if (errors & DISPC_IRQ_SYNC_LOST) {
2506 DSSERR("SYNC_LOST, disabling LCD\n");
2507 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2508 struct omap_overlay_manager *mgr;
2509 mgr = omap_dss_get_overlay_manager(i);
2511 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2512 mgr->display->disable(mgr->display);
2518 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2519 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2520 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2521 struct omap_overlay_manager *mgr;
2522 mgr = omap_dss_get_overlay_manager(i);
2524 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2525 mgr->display->disable(mgr->display);
2531 if (errors & DISPC_IRQ_OCP_ERR) {
2532 DSSERR("OCP_ERR\n");
2533 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2534 struct omap_overlay_manager *mgr;
2535 mgr = omap_dss_get_overlay_manager(i);
2537 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2538 mgr->display->disable(mgr->display);
2542 dispc.irq_error_mask |= errors;
2543 omap_dispc_set_irqs();
2546 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2548 void dispc_irq_wait_handler(void *data, u32 mask)
2550 complete((struct completion *)data);
2554 DECLARE_COMPLETION_ONSTACK(completion);
2556 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2562 timeout = wait_for_completion_timeout(&completion, timeout);
2564 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2569 if (timeout == -ERESTARTSYS)
2570 return -ERESTARTSYS;
2575 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2576 unsigned long timeout)
2578 void dispc_irq_wait_handler(void *data, u32 mask)
2580 complete((struct completion *)data);
2584 DECLARE_COMPLETION_ONSTACK(completion);
2586 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2592 timeout = wait_for_completion_interruptible_timeout(&completion,
2595 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2600 if (timeout == -ERESTARTSYS)
2601 return -ERESTARTSYS;
2606 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2607 void dispc_fake_vsync_irq(void)
2609 u32 irqstatus = DISPC_IRQ_VSYNC;
2612 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2613 struct omap_dispc_isr_data *isr_data;
2614 isr_data = &dispc.registered_isr[i];
2619 if (isr_data->mask & irqstatus)
2620 isr_data->isr(isr_data->arg, irqstatus);
2625 static void _omap_dispc_initialize_irq(void)
2627 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2629 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2631 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2633 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2635 omap_dispc_set_irqs();
2638 static void _omap_dispc_initial_config(void)
2642 l = dispc_read_reg(DISPC_SYSCONFIG);
2643 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
2644 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
2645 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
2646 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
2647 dispc_write_reg(DISPC_SYSCONFIG, l);
2650 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2652 /* L3 firewall setting: enable access to OCM RAM */
2653 if (cpu_is_omap24xx())
2654 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2656 _dispc_setup_color_conv_coef();
2658 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2661 int dispc_init(void)
2665 spin_lock_init(&dispc.irq_lock);
2666 spin_lock_init(&dispc.error_lock);
2668 INIT_WORK(&dispc.error_work, dispc_error_worker);
2670 dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2672 DSSERR("can't ioremap DISPC\n");
2676 if (cpu_is_omap34xx()) {
2677 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2678 if (IS_ERR(dispc.dpll4_m4_ck)) {
2679 DSSERR("Failed to get dpll4_m4_ck\n");
2686 _omap_dispc_initial_config();
2688 _omap_dispc_initialize_irq();
2690 dispc_save_context();
2692 rev = dispc_read_reg(DISPC_REVISION);
2693 printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2694 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2701 void dispc_exit(void)
2703 if (cpu_is_omap34xx())
2704 clk_put(dispc.dpll4_m4_ck);
2705 iounmap(dispc.base);
2708 int dispc_enable_plane(enum omap_plane plane, bool enable)
2710 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2713 _dispc_enable_plane(plane, enable);
2719 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
2720 u32 paddr, u16 screen_width,
2721 u16 pos_x, u16 pos_y,
2722 u16 width, u16 height,
2723 u16 out_width, u16 out_height,
2724 enum omap_color_mode color_mode,
2726 u8 rotation, bool mirror)
2730 DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
2731 "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
2732 plane, channel_out, paddr, screen_width, pos_x, pos_y,
2734 out_width, out_height,
2740 r = _dispc_setup_plane(plane, channel_out,
2741 paddr, screen_width,
2744 out_width, out_height,
2753 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
2754 int x2, int y2, int w2, int h2)
2771 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
2773 if (pi->width != pi->out_width)
2776 if (pi->height != pi->out_height)
2782 /* returns the area that needs updating */
2783 void dispc_setup_partial_planes(struct omap_display *display,
2784 u16 *xi, u16 *yi, u16 *wi, u16 *hi)
2786 struct omap_overlay_manager *mgr;
2796 DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
2797 *xi, *yi, *wi, *hi);
2800 mgr = display->manager;
2803 DSSDBG("no manager\n");
2807 for (i = 0; i < mgr->num_overlays; i++) {
2808 struct omap_overlay *ovl;
2809 struct omap_overlay_info *pi;
2810 ovl = mgr->overlays[i];
2812 if (ovl->manager != mgr)
2815 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2823 * If the plane is intersecting and scaled, we
2824 * enlarge the update region to accomodate the
2828 if (dispc_is_intersecting(x, y, w, h,
2829 pi->pos_x, pi->pos_y,
2830 pi->out_width, pi->out_height)) {
2831 if (dispc_is_overlay_scaled(pi)) {
2845 if ((x + w) < (pi->pos_x + pi->out_width))
2846 x2 = pi->pos_x + pi->out_width;
2850 if ((y + h) < (pi->pos_y + pi->out_height))
2851 y2 = pi->pos_y + pi->out_height;
2860 DSSDBG("Update area after enlarge due to "
2861 "scaling %d, %d %dx%d\n",
2867 for (i = 0; i < mgr->num_overlays; i++) {
2868 struct omap_overlay *ovl = mgr->overlays[i];
2869 struct omap_overlay_info *pi = &ovl->info;
2874 int ph = pi->height;
2875 int pow = pi->out_width;
2876 int poh = pi->out_height;
2878 int psw = pi->screen_width;
2881 if (ovl->manager != mgr)
2885 * If plane is not enabled or the update region
2886 * does not intersect with the plane in question,
2887 * we really disable the plane from hardware
2891 !dispc_is_intersecting(x, y, w, h,
2892 px, py, pow, poh)) {
2893 dispc_enable_plane(ovl->id, 0);
2897 switch (pi->color_mode) {
2898 case OMAP_DSS_COLOR_RGB16:
2899 case OMAP_DSS_COLOR_ARGB16:
2900 case OMAP_DSS_COLOR_YUV2:
2901 case OMAP_DSS_COLOR_UYVY:
2905 case OMAP_DSS_COLOR_RGB24P:
2909 case OMAP_DSS_COLOR_RGB24U:
2910 case OMAP_DSS_COLOR_ARGB32:
2911 case OMAP_DSS_COLOR_RGBA32:
2912 case OMAP_DSS_COLOR_RGBX32:
2921 if (x > pi->pos_x) {
2923 pw -= (x - pi->pos_x);
2924 pa += (x - pi->pos_x) * bpp / 8;
2929 if (y > pi->pos_y) {
2931 ph -= (y - pi->pos_y);
2932 pa += (y - pi->pos_y) * psw * bpp / 8;
2938 pw -= (px+pw) - (w);
2941 ph -= (py+ph) - (h);
2943 /* Can't scale the GFX plane */
2944 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
2945 dispc_is_overlay_scaled(pi) == 0) {
2950 DSSDBG("calc plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
2951 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
2953 dispc_setup_plane(ovl->id, mgr->id,
2959 pi->rotation, // XXX rotation probably wrong
2962 dispc_enable_plane(ovl->id, 1);